1
FEATURES
DESCRIPTION
1
2
3
4
8
7
6
5
GND
IN
IN
EN†
OUT
OUT
OUT
OC
TPS2045A, TPS2055A
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
GND
IN
EN1†
EN2†
OC1
OUT1
OUT2
OC2
TPS2046A, TPS2056A
D PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GNDA
IN1
EN1†
EN2†
GNDB
IN2
EN3†
EN4†
OC1
OUT1
OUT2
OC2
OC3
OUT3
OUT4
OC4
TPS2048A, TPS2058A
D PACKAGE
(TOP VIEW)
†All enable inputs are active high for the TPS205xA series.
NC – No connect
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GNDA
IN1
EN1†
EN2†
GNDB
IN2
EN3†
NC
OC1
OUT1
OUT2
OC2
OC3
OUT3
NC
NC
TPS2047A, TPS2057A
D PACKAGE
(TOP VIEW)
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008www.ti.com
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
•80-m ΩHigh-Side MOSFET Switch•250 mA Continuous Current Per Channel•Independent Thermal and Short-CircuitProtection With Overcurrent Logic Output•Operating Range: 2.7-V to 5.5-V•CMOS- and TTL-Compatible Enable Inputs•2.5-ms Typical Rise Time•Undervoltage Lockout•10 µA Maximum Standby Supply Currentfor Single and Dual(20 µA for Triple and Quad)•Bidirectional Switch•Ambient Temperature Range, 0 °C to 85 °C•ESD Protection
The TPS2045A through TPS2048A and TPS2055Athrough TPS2058A power-distribution switches areintended for applications where heavy capacitiveloads and short circuits are likely to be encountered.
These devices incorporate 80-m ΩN-channel MOSFET high-side power switches for power-distribution systemsthat require multiple power switches in a single package. Each switch is controlled by an independent logicenable input. Gate drive is provided by an internal charge pump designed to control the power-switch rise timesand fall times to minimize current surges during switching. The charge pump requires no external componentsand allows operation from supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, these devices limit the outputcurrent to a safe level by switching into a constant-current mode, pulling the overcurrent ( OCx) logic output low.When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing thejunction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from athermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switchremains off until valid input voltage is present. These power-distribution switches are designed to current limit at0.5 A.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
(1)
RECOMMENDED PACKAGED DEVICESTYPICAL SHORT-CIRCUITMAXIMUM CONTINUOUS NUMBER OFT
A
ENABLE CURRENT LIMIT AT 25 °CLOAD CURRENT SWITCHES
SOIC (D)
(2)(A)(A)
Active low TPS2045ADSingleActive high TPS2055ADActive low TPS2046ADDualActive high TPS2056AD0°C to 85 °C 0.25 0.5Active low TPS2047ADTripleActive high TPS2057ADActive low TPS2048ADQuadActive high TPS2058AD
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2045ADR)
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Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
TPS2045A
OUT
OC
IN
EN‡
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Power Switch
†
‡Active high for TPS205xA series
†Current sense
TPS2046A
Thermal
Sense
Driver Current
Limit
Charge
Pump
UVLO
CS †
Driver Current
Limit
CS †
Thermal
Sense
Charge
Pump
Power Switch
GND
EN1‡
IN
EN2‡
OC1
OUT1
OUT2
OC2
‡Active high for TPS205xA series
†Current sense
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
www.ti.com
TPS2047A
Thermal
Sense
Driver Current
Limit
Charge
Pump
UVLO
CS †
Driver Current
Limit
CS †
Thermal
Sense
Charge
Pump
Power Switch
GNDA
EN1‡
IN1
EN2‡
OC1
OUT1
OUT2
OC2
OUT3
OC3
IN2
EN3‡
GNDB
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Power Switch
†
‡Active high for TPS205xA series
†Current sense
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
4Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
www.ti.com
Thermal
Sense
Driver Current
Limit
Charge
Pump
UVLO CS †
Driver Current
Limit
CS †
Thermal
Sense
Charge
Pump
Power Switch
GNDA
EN1‡
IN1
EN2‡
OC1
OUT
1
OUT
2
OC2
Thermal
Sense
Driver Current
Limit
Charge
Pump
UVLO CS †
Driver Current
Limit
CS †
Thermal
Sense
Charge
Pump
Power Switch
GNDB
EN3‡
IN2
EN4‡
OC3
OUT3
OUT4
OC4
TPS2048A
‡Active high for TPS205xA series
†Current sense
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
www.ti.com
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Terminal Functions
TPS2045A AND TPS2055A
TERMINAL
NO. I/O DESCRIPTIONNAME
TPS2045A TPS2055A
EN 4 - I Enable input. Logic low turns on power switch.EN - 4 I Enable input. Logic high turns on power switch.GND 1 1 I GroundIN 2, 3 2, 3 I Input voltageOC 5 5 O Overcurrent. Open drain output active lowOUT 6, 7, 8 6, 7, 8 O Power-switch output
TPS2046A AND TPS2056A
TERMINAL
NO. I/O DESCRIPTIONNAME
TPS2046A TPS2056A
EN1 3 - I Enable input. Logic low turns on power switch, IN-OUT1.EN2 4 - I Enable input. Logic low turns on power switch, IN-OUT2.EN1 - 3 I Enable input. Logic high turns on power switch, IN-OUT1.EN2 - 4 I Enable input. Logic high turns on power switch, IN-OUT2.GND 1 1 I GroundIN 2 2 I Input voltageOC1 8 8 O Overcurrent. Open drain output active low, for power switch, IN-OUT1OC2 5 5 O Overcurrent. Open drain output active low, for power switch, IN-OUT2OUT1 7 7 O Power-switch outputOUT2 6 6 O Power-switch output
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Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
www.ti.com
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Terminal Functions (continued)
TPS2047A AND TPS2057A
TERMINAL
NO. I/O DESCRIPTIONNAME
TPS2047A TPS2057A
EN1 3 - I Enable input, logic low turns on power switch, IN1-OUT1.EN2 4 - I Enable input, logic low turns on power switch, IN1-OUT2.EN3 7 - I Enable input, logic low turns on power switch, IN2-OUT3.EN1 - 3 I Enable input, logic high turns on power switch, IN1-OUT1.EN2 - 4 I Enable input, logic high turns on power switch, IN1-OUT2.EN3 - 7 I Enable input, logic high turns on power switch, IN2-OUT3.GNDA 1 1 Ground for IN1 switch and circuitry.GNDB 5 5 Ground for IN2 switch and circuitry.IN1 2 2 I Input voltageIN2 6 6 I Input voltageNC 8, 9, 10 8, 9, 10 No connectionOC1 16 16 O Overcurrent, open drain output active low, IN1-OUT1OC2 13 13 O Overcurrent, open drain output active low, IN1-OUT2OC3 12 12 O Overcurrent, open drain output active low, IN2-OUT3OUT1 15 15 O Power-switch output, IN1-OUT1OUT2 14 14 O Power-switch output, IN1-OUT2OUT3 11 11 O Power-switch output, IN2-OUT3
TPS2048A AND TPS2058A
TERMINAL
NO. I/O DESCRIPTIONNAME
TPS2048A TPS2058A
EN1 3 - I Enable input. logic low turns on power switch, IN1-OUT1.EN2 4 - I Enable input. Logic low turns on power switch, IN1-OUT2.EN3 7 - I Enable input. Logic low turns on power switch, IN2-OUT3.EN4 8 - I Enable input. Logic low turns on power switch, IN2-OUT4.EN1 - 3 I Enable input. Logic high turns on power switch, IN1-OUT1.EN2 - 4 I Enable input. Logic high turns on power switch, IN1-OUT2.EN3 - 7 I Enable input. Logic high turns on power switch, IN2-OUT3.EN4 - 8 I Enable input. Logic high turns on power switch, IN2-OUT4.GNDA 1 1 Ground for IN1 switch and circuitry.GNDB 5 5 Ground for IN2 switch and circuitry.IN1 2 2 I Input voltageIN2 6 6 I Input voltageOC1 16 16 O Overcurrent. Open drain output active low, IN1-OUT1OC2 13 13 O Overcurrent. Open drain output active low, IN1-OUT2OC3 12 12 O Overcurrent. Open drain output active low, IN2-OUT3OC4 9 9 O Overcurrent. Open drain output active low, IN2-OUT4OUT1 15 15 O Power-switch output, IN1-OUT1OUT2 14 14 O Power-switch output, IN1-OUT2OUT3 11 11 O Power-switch output, IN2-OUT3OUT4 10 10 O Power-switch output, IN2-OUT4
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
www.ti.com
DETAILED DESCRIPTION
POWER SWITCH
CHARGE PUMP
DRIVER
ENABLE ( ENx, ENx)
OVERCURRENT ( OCx)
CURRENT SENSE
THERMAL SENSE
UNDERVOLTAGE LOCKOUT
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 m Ω(V
I(IN)
= 5 V).Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT whendisabled. The power switch supplies a minimum of 250 mA per switch.
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gateof the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requiresvery little supply current.
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associatedelectromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and falltimes of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reducethe supply current. The supply current is reduced to less than 10 µA on the single and dual devices (20 µA onthe triple and quad devices) when a logic high is present on ENx (TPS204xA
1
) or a logic low is present on ENx(TPS205xA
1
). A logic zero input on ENx or a logic high on ENx restores bias to the drive and control circuits andturns the power on. The enable input is compatible with both TTL and CMOS logic levels.
The OCx open-drain output is asserted (active low) when an overcurrent or over temperature condition isencountered. The output will remain asserted until the overcurrent or over temperature condition is removed.
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently thanconventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitrysends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into itssaturation region, which switches the output into a constant-current mode and holds the current constant whilevarying the voltage on the load.
The TPS204xA and TPS205xA implement a dual-threshold thermal trip to allow fully independent operation ofthe power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. Whenthe die temperature rises to approximately 140 °C, the internal thermal sense circuitry checks to determine whichpower switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interruptingoperation of the adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooledapproximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault isremoved. The ( OCx) open-drain output is asserted (active low) when over temperature or overcurrent occurs.
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a controlsignal turns off the power switch.
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Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
www.ti.com
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
I(IN)
Input voltage range
(2)
0.3 V to 6 VV
O(OUT)
Output voltage range
(2)
– 0.3 V to V
I(IN)
+ 0.3 VV
I( ENx)
or V
I(ENx)
Input voltage range – 0.3 V to 6 VI
O(OUT)
Continuous output current internally limitedContinuous total power dissipation See Dissipation Rating TableT
J
Operating virtual junction temperature range 0 °C to 125 °CT
stg
Storage temperature range – 65 °C to 150 °CLead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260 °CHuman body model MIL-STD-883C 2 kVESD Electrostatic discharge protection
Machine model 0.2 kV
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to GND.
T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °CPACKAGE
POWER RATING ABOVE T
A
= 25 °C POWER RATING POWER RATING
D-8 725 mW 5.9 mW/ °C 464 mW 377 mWD-16 1123 mW 9 mW/ °C 719 mW 584 mW
MIN MAX UNIT
V
I(IN)
Input voltage 2.7 5.5 VV
I( EN)
or V
I(EN)
Input voltage 0 5.5 VI
O(OUT)
Continuous output current (per switch) 0 250 mAT
J
Operating virtual junction temperature 0 125 °C
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
www.ti.com
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING JUNCTION
ENABLE INPUT ENx OR ENx
CURRENT LIMIT
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
TEMPERATURE RANGEV
I(IN)
= 5.5 V, I
O
= rated current, V
I( EN)
= V
I(IN)
(unless otherwise noted)
TPS204xA TPS205xAPARAMETER TEST CONDITIONS
(1)
UNITMIN TYP MAX MIN TYP MAX
V
I(IN)
= 5 V, T
J
= 25 °C,
80 100 80 100I
O
= 0.25 AStatic drain-source on-state resistance, V
I(IN)
= 5 V, T
J
= 85 °C,
90 120 90 1205-V operation I
O
= 0.25 AV
I(IN)
= 5 V, T
J
= 125 °C,
100 135 100 135I
O
= 0.25 Ar
DS(on)
mΩV
I(IN)
= 3.3 V, T
J
= 25 °C,
90 125 90 125I
O
= 0.25 AStatic drain-source on-state resistance, V
I(IN)
= 3.3 V, T
J
= 85 °C,
110 145 110 1453.3-V operation I
O
= 0.25 AV
I(IN)
= 3.3 V, T
J
= 125 °C,
120 160 120 160I
O
= 0.25 AV
I(IN)
= 5.5 V, T
J
= 25 °C,
2.5 2.5C
L
= 1 µF, R
L
= 20 Ωt
r
Rise time, output msV
I(IN)
= 2.7 V, T
J
= 25 °C,
3 3C
L
= 1 µF, R
L
= 20 Ω
V
I(IN)
= 5.5 V, T
J
= 25 °C,
4.4 4.4C
L
= 1 µF, R
L
= 20 Ωt
f
Fall time, output msV
I(IN)
= 2.7 V, T
J
= 25 °°C,
2.5 2.5C
L
= 1 µF, R
L
= 20 Ω
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into accountseparately.
TPS204xA TPS205xAPARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
V
IH
high-level input voltage 2.7 V ≤V
I(IN)
≤5.5 V 2 2 V4.5 V ≤V
I(IN)
≤5.5 V 0.8 0.8V
IL
Low-level input voltage V2.7 V ≤V
I(IN)
≤4.5 V 0.4 0.4TPS204xA V
I( ENx)
= 0 V or V
I( ENx)
= V
I(IN)
– 0.5 0.5I
I
Input current µATPS205xA V
I(ENx)
= V
I(IN)
or V
I(ENx)
= 0 V – 0.5 0.5t
on
Turnon time C
L
= 100 µF, R
L
= 20 Ω20 20
mst
off
Turnoff time C
L
= 100 µF, R
L
= 20 Ω40 40
TPS204xA TPS205xAPARAMETER TEST CONDITIONS
(1)
UNITMIN TYP MAX MIN TYP MAX
V
I(IN)
= 5 V, OUT connected to GND,I
OS
Short-circuit output current 0.3 0.5 0.7 0.3 0.5 0.7 ADevice enabled into short circuit
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into accountseparately.
10 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
www.ti.com
SUPPLY CURRENT (TPS2045A, TPS2055A)
SUPPLY CURRENT (TPS2046A, TPS2056A)
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
TPS2045A TPS2055APARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
T
J
= 25 °C 0.025 1V
I( EN)
= V
I(IN)
40 °C≤T
J
≤125 °C 10Supply current, No Load
µAlow-level output on OUT
T
J
= 25 °C 0.025 1V
I(EN)
= 0 V
40 °C≤T
J
≤125 °C 10T
J
= 25 °C 85 110V
I( EN)
= 0 V
40 °C≤T
J
≤125 °C 100Supply current, No Load
µAhigh-level output on OUT
T
J
= 25 °C 85 110V
I(EN)
= V
I(IN)
40 °C≤T
J
≤125 °C 100OUT V
I( EN)
= V
I(IN)
40 °C≤T
J
≤125 °C 100Leakage current connected µAV
I(EN)
= 0 V 40 °C≤T
J
≤125 °C 100to ground
V
I( EN)
= 0 V 0.3Reverse leakage IN = High
T
J
= 25 °CµAcurrent impedance
V
I(EN)
= V
I(IN)
0.3
TPS2046A TPS2056APARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
T
J
= 25 °C 0.025 1V
I( ENx)
= V
I(IN)
40 °C≤T
J
≤125 °C 10Supply current, No Load
µAlow-level output on OUT
T
J
= 25 °C 0.025 1V
I(ENx)
= 0 V
40 °C≤T
J
≤125 °C 10T
J
= 25 °C 85 110V
I( ENx)
= 0 V
40 °C≤T
J
≤125 °C 100Supply current, No Load
µAhigh-level output on OUT
T
J
= 25 °C 85 110V
I(ENx)
= V
I(IN)
40 °C≤T
J
≤125 °C 100OUT V
I( ENx)
= V
I(IN)
40 °C≤T
J
≤125 °C 100Leakage current connected µAV
I(ENx)
= 0 V 40 °C≤T
J
≤125 °C 100to ground
V
I( EN)
= 0 V 0.3Reverse leakage IN = high
T
J
= 25 °CµAcurrent impedance
V
I(EN)
= V
I(IN)
0.3
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SUPPLY CURRENT (TPS2047A, TPS2057A)
SUPPLY CURRENT (TPS2048A, TPS2058A)
UNDERVOLTAGE LOCKOUT
OVERCURRENT OC
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
TPS2047A TPS2057APARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
T
J
= 25 °C 0.05 2V
I( ENx)
= V
I(INx)
40 °C≤T
J
≤125 °C 20Supply current, No load on
µAlow-level output OUTx
T
J
= 25 °C 0.05 2V
I(ENx)
= 0 V
40 °C≤T
J
≤125 °C 20T
J
= 25 °C 160 200V
I(E Nx)
= 0 V
40 °C≤T
J
≤125 °C 200Supply current, No load on
µAhigh-level output OUTx
T
J
= 25 °C 160 200V
I(ENx)
= V
I(INx)
40 °C≤T
J
≤125 °C 200OUTx V
I( ENx)
= V
I(INx)
40 °C≤T
J
≤125 °C 200Leakage current connected µAV
I(ENx)
= 0 V 40 °C≤T
J
≤125 °C 200to ground
V
I( ENx)
= 0 V 0.3Reverse leakage IN = high
T
J
= 25 °CµAcurrent impedance
V
I(ENx)
= V
I(IN)
0.3
TPS2048A TPS2058APARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
T
J
= 25 °C 0.05 2V
I( ENx)
= V
I(INx)
40 °C≤T
J
≤125 °C 20Supply current, No Load on
µAlow-level output OUTx
T
J
= 25 °C 0.05 2V
I(ENx)
= 0 V
40 °C≤T
J
≤125 °C 20T
J
= 25 °C 170 220V
I( ENx)
= 0 V
40 °C≤T
J
≤125 °C 200Supply current, No Load on
µAhigh-level output OUTx
T
J
= 25 °C 170 220V
I(ENx)
= V
I(INx)
40 °C≤T
J
≤125 °C 200OUTx V
I( ENx)
= V
I(INx)
40 °C≤T
J
≤125 °C 200Leakage current connected µAV
I(ENx)
= 0 V 40 °C≤T
J
≤125 °C 200to ground
V
I( EN)
= 0 V 0.3Reverse leakage IN = high
T
J
= 25 °CµAcurrent impedance
V
I(EN)
= V
I(IN)
0.3
TPS204xA TPS205xAPARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
Low-level input voltage 2 2.5 2 2.5 VHysteresis T
J
= 25 °C 100 100 mV
TPS204xA TPS205xAPARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
Sink current
(1)
V
O
= 5 V 10 10 mAOutput low voltage I
O
= 5 V, V
OL( OC)
0.5 0.5 VOff-state current
(1)
V
O
= 5 V, V
O
= 3.3 V 1 1 µA
(1) Specified by design, not production tested.
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PARAMETER MEASUREMENT INFORMATION
RL CL
OUT
trtf
90% 90%
10%
10%
50% 50%
90%
10%
VO(OUT)
VI(EN)
VO(OUT)
VOLTAGE WAVEFORMS
TEST CIRCUIT
ton toff
50% 50%
90%
10%
VI(EN)
VO(OUT)
ton toff
VO(OUT)
(2 V/div)
0 1 2 3 4 5 6
t − Time − ms 7 8 9 10
VI(IN) = 5 V
TA = 25°C
CL = 0.1 µF
RL = 20 Ω
VI(EN)
(5 V/div)
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Figure 1. Test Circuit and Voltage Waveforms
Figure 2. Turnon Delay and Rise Time Figure 3. Turnoff Delay and Rise TimeWith 0.1- µF Load With 0.1- µF Load
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0 2 4 6 8 10 12
t − Time − ms 14 16 18 20
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
RL = 20 Ω
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
0 1 2 3 4 5 6
t − Time − ms 7 8 9 10
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
RL = 20 Ω
0 1 2 3 4 5 6
t − Time − ms 7 8 9 10
IO(OUTx)
(0.2 A/div)
VI(ENx)
(5 V/div)
VI(IN) = 5 V
TA = 25°C
0 10 20 30 40 50 60
t − Time − ms 70 80 90 100
IO(OUT)
(0.2 A/div)
VI(IN) = 5 V
TA = 25°C
RAMP: 1A/10ms
VO(OUT)
(2 V/div)
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Turnon Delay and Rise Time Figure 5. Turnoff Delay and Fall TimeWith 1- µF Load With 1- µF Load
Figure 6. TPS2055A, Short-Circuit Current, Figure 7. TPS2055A, Threshold Trip CurrentDevice Enabled Into Short With Ramped Load on Enabled Device
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VO(OC)
(5 V/div)
IO(OUT)
(0.2 A/div)
VI(IN) = 5 V
TA = 25°C
RAMP: 1A/100 ms
0 20 40 60 80 100 120
t − Time − ms 140 160 180 200
0 2 4 6 8 10 12
t − Time − ms 14 16 18 20
VI(EN)
(5 V/div)
IO(OUT)
(0.2 A/div)
47 µF
220 µF
VI(IN) = 5 V
TA = 25°C
RL = 20 Ω
100 µF
IO(OUT)
(0.5 A/div)
VI(IN) = 5 V
TA = 25°C
0 200 400 600 800 1000
VO(OC)
(5 V/div)
t − Time − µs
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. OC Response With Ramped Load Figure 9. Inrush Current With 47- µF, 100- µFon Enabled Device and 220- µF Load Capacitance
Figure 10. 4- ΩLoad Connected to Figure 11. 1- ΩLoad Connected toEnabled Device Enabled Device
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TYPICAL CHARACTERISTICS
2
4
6
8
10
2.5 3 3.5 4 4.5 5 5.5 6
Turnon Delay Time − ms
VI − Input Voltage − V
CL = 1 µF
RL = 20 Ω
TA = 25°C
3.3
3
2.7
2.42.5 3 3.5 4 4.5
Turnon Delay Time − ms
3.6
3.9
5 5.5 6
VI − Input Voltage − V
CL = 1 µF
RL = 20 Ω
TA = 25°C
1.3
1.4
1.5
1.6
1.8
1.9
2.5 3 3.5 4 4.5 5 5.5 6
− Fall Time − ms
ft
VI − Input Voltage − V
1.7
CL = 1 µF
RL = 20 Ω
TA = 25°C
2
2.1
2.3
2.5
2.7
2.5 3 3.5 4 4.5 5 5.5 6
− Rise Time − msrt
VI − Input Voltage − V
2.2
2.4
2.6
CL = 1 µF
RL = 20 Ω
TA = 25°C
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
TURNON DELAY TIME TURNOFF DELAY TIMEvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 12. Figure 13.
RISE TIME FALL TIMEvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 14. Figure 15.
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40
50
60
70
80
90
100
−40 0 25 85 125
VI(IN) = 5.5 V
VI(IN) = 5 V
VI(IN) = 4.5 V
VI(IN) = 3.3 V
VI(IN) = 2.7 V
− Supply Current, Output Enabled −
II(IN) Aµ
TJ − Junction Temperature − °C
VI(IN) = 4.5 V
0
20
40
60
80
100
120
140
160
−40 0 25 85 125
VI(IN) = 5.5 V
VI(IN) = 5 V
VI(IN) = 3.3 V
VI(IN) = 2.7 V
− Supply Current, Output Disabled − nA
II(IN)
TJ − Junction Temperature − °C
0
20
40
60
80
100
120
140
160
0 25 85 125
VI(IN) = 3 V
VI(IN) = 4.5 V
VI(IN) = 5 V
VI(IN) = 2.7 V VI(IN) = 3.3 V
− Static Drain-Source On-State Resistance − m Ω
rDS(on)
TJ − Junction Temperature − °C
0
10
20
30
40
50
60
70
100 200 300 400 500
TA = 25°C
VI(IN) = 2.7 V
VI(IN) = 3.3 V
VI(IN) = 4.5 V
VI(IN) = 5 V
− Input-to-Output Voltage − mVVI(IN) −VO(OUT)
IL − Load Current − A
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT DISABLEDvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 16. Figure 17.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE INPUT-TO-OUTPUT VOLTAGEvs vsJUNCTION TEMPERATURE LOAD CURRENT
Figure 18. Figure 19.
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Threshold Trip Current − A
VI − Input Voltage − V
0.57
0.59
0.61
0.63
0.65
0.67
2.5 3 3.5 4 4.5 5 5.5 6
TA = 25°C
Load Ramp = 1 A/10 ms
400
410
420
430
440
450
460
470
480
490
500
−40 0 25 85 125
TJ − Junction Temperature − °C
− Short-Circuit Output Current − mA
IOS
VI(IN) = 3.3 V
VI(IN) = 2.7 V
VI(IN) = 5 .5V VI(IN) = 4 .5V
VI(IN) = 5V
2.16
2.18
2.2
2.22
2.24
2.26
2.28
2.3
2.32
2.34
2.36
−40 0 25 85 125
UVLO − Undervoltage Lockout − V
TJ − Junction Temperature − °C
Start Threshold
Stop Threshold
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
TYPICAL CHARACTERISTICS (continued)
SHORT-CIRCUIT OUTPUT CURRENT THRESHOLD TRIP CURRENTvs vsJUNCTION TEMPERATURE INPUT VOLTAGE
Figure 20. Figure 21.
UNDERVOLTAGE LOCKOUT CURRENT-LIMIT RESPONSEvs vsJUNCTION TEMPERATURE PEAK CURRENT
Figure 22. Figure 23.
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APPLICATION INFORMATION
IN
OC
EN GND
0.1 µF
2,3
5
4
6,7,8
0.1 µF22 µF
Load
1
OUT
TPS2045A
Power Supply
2.7 V to 5.5 V
POWER-SUPPLY CONSIDERATIONS
OVERCURRENT
OC RESPONSE
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Figure 24. Typical Application (Example, TPS2045A)
A 0.01- µF to 0.1- µF ceramic bypass capacitor between INx and GND, close to the device, is recommended.Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing theoutput with a 0.01- µF to 0.1- µF ceramic capacitor improves the immunity of the device to short-circuit transients.
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do notincrease the series resistance of the current path. When an overcurrent condition is detected, the devicemaintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs onlyif the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before thedevice is enabled or before V
I(IN)
has been applied (see Figure 6). The TPS204xA and TPS205xA sense theshort and immediately switch into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overloadoccurs, very high currents may flow for a short time before the current-limit circuit can react. After thecurrent-limit circuit has tripped (reached the overcurrent trip threshold) the device switches into constant-currentmode.
In the third condition, the load has been gradually increased beyond the recommended operating current. Thecurrent is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device isexceeded (see Figure 7). The TPS204xA and TPS205xA are capable of delivering current up to the current-limitthreshold without damaging the device. Once the threshold has been reached, the device switches into itsconstant-current mode.
The OC open-drain output is asserted (active low) when an overcurrent or over temperature condition isencountered. The output will remain asserted until the overcurrent or over temperature condition is removed.Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting fromthe inrush current flowing through the device, charging the downstream capacitor. The TPS204xA andTPS205xA family of devices are designed to reduce false overcurrent reporting. An internal overcurrent transientfilter eliminates the need for external components to remove unwanted pulses. Using low-ESR electrolyticcapacitors on the output lowers the inrush current flow through the device during hot-plug events by providing alow-impedance energy source, also reducing erroneous overcurrent reporting.
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GND
IN
IN
EN
OUT
OC
OUT
OUT
TPS2045A
Rpullup
V+
POWER DISSIPATION AND JUNCTION TEMPERATURE
PD+rDS(on) I2
TJ+PD RqJA )TA
THERMAL PROTECTION
UNDERVOLTAGE LOCKOUT (UVLO)
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Figure 25. Typical Circuit for OC Pin (Example, TPS2045A)
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to passlarge currents. The thermal resistance of these packages is high compared to those of power packages; it isgood design practice to check power dissipation and junction temperature. Begin by determining the r
DS(on)
of theN-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use thehighest operating ambient temperature of interest and read r
DS(on)
from Figure 18. Using this value, the powerdissipation per switch can be calculated by:
Depending on which device is being used, multiply this number by the number of switches being used. This stepwill render the total power dissipation from the N-channel MOSFETs.
Finally, calculate the junction temperature:
Where: T
A
= Ambient temperature °C R
ΘJA
= Thermal resistance SOIC = 172 °C/W (for 8 pin), 111 °C/W (for 16pin) P
D
= Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generallysufficient to get a reasonable answer.
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present forextended periods of time. The faults force the TPS204xA and TPS205xA into constant-current mode, whichcauses the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across theswitch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to highlevels. The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built intothe thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on.The switch continues to cycle in this manner until the load fault or input power is removed.
The TPS204xA and TPS205xA implement a dual thermal trip to allow fully independent operation of the powerdistribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the dietemperature rises to approximately 140 °C, the internal thermal sense circuitry checks which power switch is in anovercurrent condition and turns that power switch off, thus isolating the fault without interrupting operation of theadjacent power switch. Should the die temperature exceed the first thermal trip point of 140 °C and reach 160 °C,both switches turn off. The OC open-drain output is asserted (active low) when overtemperature or overcurrentoccurs.
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the inputvoltage falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design ofhot-insertion systems where it is not possible to turn off the power switch before input power is removed. TheUVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if theswitch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce EMIand voltage overshoots.
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UNIVERSAL SERIAL BUS (USB) APPLICATIONS
HOST/SELF-POWERED AND BUS-POWERED HUBS
LOW-POWER BUS-POWERED FUNCTIONS AND HIGH-POWER BUS-POWERED FUNCTIONS
IN
OC
EN
GND
0.1 µF2,3
5
4
6, 7, 8
0.1 µF10 µF
GND
1
OUT
TPS2045A
Power Supply
D+
D–
VBUS
USB
Control
3.3 V
10 µFInternal
Function
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed forlow-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USBinterface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided fordifferential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where poweris distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 Vfrom the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumptionrequirements:
•Hosts/self-powered hubs (SPH)•Bus-powered hubs (BPH)•Low-power, bus-powered functions•High-power, bus-powered functions•Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS204xA andTPS205xA can provide power-distribution solutions for many of these classes of devices.
Hosts and self-powered hubs have a local power supply that powers the embedded functions and thedownstream ports. This power supply must provide from 5.25 V to 4.75 V to the board side of the downstreamconnection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protectionand must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers,and stand-alone hubs.
Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs arerequired to power up with less than one unit load. The BPH usually has one embedded function, and power isalways available to the controller of the hub. If the embedded function and hub require more than 100 mA onpower up, the power to the embedded function may need to be kept off until enumeration is completed. This canbe accomplished by removing power or by shutting off the clock to the embedded function. Power switching theembedded function is not necessary if the aggregate power draw for the function and controller is less than oneunit load. The total current drawn by the bus-powered device is the sum of the current to the controller, theembedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-powerfunctions always draw less than 100 mA (see Figure 26); high-power functions must draw less than 100 mA atpower up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallelcombination of 44 Ωand 10 µF at power up, the device must implement inrush current limiting.
Figure 26. Low-Power Bus-Powered Function (Example, TPS2045A)
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USB POWER-DISTRIBUTION REQUIREMENTS
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
USB can be implemented in several ways, and, regardless of the type of USB device being developed, severalpower-distribution features must be implemented.•Hosts/self-powered hubs must:– Current-limit downstream ports– Report overcurrent conditions on USB V
BUS– Enable/disable power to downstream ports– Power up at <100 mA– Limit inrush current (<44 Ωand 10 µF)– Limit inrush currents– Power up at <100 mA•Bus-powered hubs must:– Enable/disable power to downstream ports– Power up at <100 mA– Limit inrush current (<44 Ωand 10 µF)– Limit inrush currents– Power up at <100 mA•Functions must:– Limit inrush currents– Power up at <100 mA
The feature set of the TPS204xA and TPS205xA allows them to meet each of these requirements. Theintegrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-levelenable and controlled rise times meet the need of both input and output ports on bus-power hubs, as well as theinput ports for bus-power functions.
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www.ti.com
†USB rev 1.1 requires 120 µF per hub.
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
DM4
DP0
DM0
VCC
XTAL1
XTAL2
OCSOFF
SN75240
D +
D −
5 V
GND
D +
D −
5 V
D +
D −
5 V
D +
D −
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
Tuning
Circuit
A
BC
D
33 µF†
SN75240
A
BC
D
GND
GND
GND
33 µF†
33 µF†
33 µF†
D +
D −
Upstream
Port
SN75240
A
B
5 V
GND
C
D
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGE
D
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
GND
EN
OC
IN
TPS2045A
OUT
EN
OC
IN
TPS2045A
OUT
EN
OC
IN
TPS2045A
OUT
EN
OC
IN
TPS2045A
OUT
TPS76333
0.1 µF
0.1 µF
0.1 µF
0.1 µF
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Figure 27. Bus-Powered Hub Implementation, TPS2045A
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DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
DM4
DP0
DM0
VCC
XTAL1
XTAL2
OCSOFF
SN75240
EN1
IN
OC1
OUT1
D +
D −
5 V
GND
D +
D −
5 V
D +
D −
5 V
D +
D −
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
TPS2046A
Tuning
Circuit
A
BC
D
33 µF†
SN75240
A
BC
D
GND
GND
GND
33 µF†
33 µF†
33 µF†
D +
D −
Upstream
Port
SN75240
A
B
5 V
GND
C
D
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGE
D
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
EN2
OC2
OUT2
EN1
IN
OC1
OUT1
TPS2046A
EN2
OC2
OUT2
0.1 µF
0.1 µF
GND
†USB rev 1.1 requires 120 µF per hub.
TPS76333
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Figure 28. Bus-Powered Hub Implementation, TPS2046A
24 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
www.ti.com
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
DM4
DP0
DM0
VCC
XTAL1
XTAL2
OCSOFF
SN75240
D +
D −
5 V
GND
D +
D −
5 V
D +
D −
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
Tuning
Circuit
A
BC
D
47 µF†
1/2 SN75240
A
BC
D
GND
GND
47 µF†
47 µF†
D +
D −
Upstream
Port
1/2 SN75240
A
B
5 V
GND
C
D
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGE
D
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
EN1
IN1
OC1
OUT1
TPS2047A
EN2
OC2
OUT2
0.1 µF
0.1 µF
GND
†USB rev 1.1 requires 120 µF per hub.
EN3
OC3
OUT3
IN2
GNDA
GNDB
TPS76333
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Figure 29. Bus-Powered Hub Implementation, TPS2047A
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
www.ti.com
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
DM4
DP0
DM0
VCC
XTAL1
XTAL2
OCSOFF
SN75240
D +
D −
5 V
GND
D +
D −
5 V
D +
D −
5 V
D +
D −
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
Tuning
Circuit
A
BC
D
33 µF†
SN75240
A
BC
D
GND
GND
GND
33 µF†
33 µF†
33 µF†
D +
D −
Upstream
Port
TPS2041A
SN75240
A
B
5 V
GND
C
D
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGE
D
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
EN1
IN1
OC1
OUT1
TPS2048A
EN2
OC2
OUT2
0.1 µF
0.1 µF
GND
†USB rev 1.1 requires 120 µF per hub.
EN3
OC3
OUT3
EN4
OC4
OUT4
IN2
GNDA
GNDB
TPS76333
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Figure 30. Bus-Powered Hub Implementation, TPS2048A
26 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
www.ti.com
GENERIC HOT-PLUG APPLICATIONS (see Figure 31 )
Power
Supply Block of
Circuitry
TPS2045A
GND
IN
IN
EN
OUT
OUT
OUT
OC
0.1 µF
1000 µF
Optimum
2.7 V to 5.5 V
PC Board
Overcurrent Response
TPS2045A , , TPS2046ATPS2047A , TPS2048A , TPS2055ATPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.These are considered hot-plug applications. Such implementations require the control of current surges seen bythe main power supply and the card being inserted. The most effective way to control these surges is to limit andslowly ramp the current and voltage being applied to the card, similar to the way in which a power supplynormally turns on. Due to the controlled rise times and fall times of the TPS204xA and TPS205xA, these devicescan be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO featureof the TPS204xA and TPS205xA also ensures the switch will be off after the card has been removed, and theswitch will be off during the next insertion. The UVLO feature insures a soft start with a controlled rise time forevery insertion of the card or module.
Figure 31. Typical Hot-Plug Implementation (Example, TPS2045A)
By placing the TPS204xA and TPS205xA between the V
CC
input and the rest of the circuitry, the input power willreach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing aslow voltage ramp at the output of the device. This implementation controls system surge currents and providesa hot-plugging mechanism for any device.
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2045AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2045ADG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2045ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2045ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2046AD NRND SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2046ADG4 NRND SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2046ADR NRND SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2046ADRG4 NRND SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2047ADR NRND SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2047ADRG4 NRND SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2048AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2048ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2048ADR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2048ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2055AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2055ADG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2055ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2055ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2056AD NRND SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2056ADG4 NRND SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2056ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2056ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2057AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2057ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2057ADR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2057ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2058AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2058ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2011
Addendum-Page 3
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2045ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2046ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2047ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPS2048ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPS2055ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2056ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2056ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2057ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2045ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2046ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2047ADR SOIC D 16 2500 333.2 345.9 28.6
TPS2048ADR SOIC D 16 2500 333.2 345.9 28.6
TPS2055ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2056ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2056ADR SOIC D 8 2500 367.0 367.0 35.0
TPS2057ADR SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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