Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 1 Introduction The last issue of this data sheet was December 17, 2003 - Revision 4. A change history is included in Section 13, Change History, on page 54. Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text are highlighted in red. Changes within figures, and the figure title itself, are highlighted in red, if feasible. Formatting or grammatical changes have not been highlighted. Deleted sections, paragraphs, figures, or tables will be specifically mentioned. The documentation package for the TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 system chip consists of the following documents: The Register Description and the System Design Guide. These documens are available on a password-protected website. The Ultraframer Product Description and the Ultraframer Hardware Design Guide (this document). These documents are available on the public website shown below (select Mappers/MUXes). If the reader displays this document using Acrobat Reader (R), clicking on any blue text will bring the reader to that reference point. Clicking on the back arrow (Go to previous View) in the toolbar of the Acrobat Reader will bring the reader back to the starting point. To access related documents, including the documents mentioned above, please go to the following public website, or contact your Agere representative (see the last page of this document). http://www.agere.com/enterprise_metro_access/index.html This document describes the hardware interfaces to the Agere Systems Inc. TFRA84J13 Ultraframer device. Information relevant to the use of the device in a board design is covered. Pin descriptions, dc electrical characteristics, timing diagrams, ac timing parameters, packaging, and operating conditions are included. 2 MPU IF FRM x84/x63 DS1/J1/E1 MPU 48 THSC Framer CLK CHI/PSB 5 CG Rx/Tx Clocks and Sync 5 FRM PLL IF System Interfaces (x3) M13/E13 Mux 1 E2AISCLK/ DS2AISCLK 1 21 MRXC Miscellaneous DS1/J1/E1 DS2/E2 DS3/E3 TPG/TPM x84/x63 DS1/E1 5 (framer) Shared Low Speed I/O Switching modes: Transport modes: DJA 4DS1/J1/E1 (x86) -x84/x63 + prot. 4DS2/E2 (X86) - x63/x36 + prot. 2 JTAG IF 380 (x3) NSMI 8PSB (x16)- x84/X63 DS1/J1/E1 x2016 DS0/E0 4CHI (x18) - x2016 DS0/E0 13 JTAG 24 (x3) DS3/E3 DS1XCLK, E1XCLK Power and GND pins not shown 10/10/02 Ultraframer Figure 1-1. Ultraframer Block Diagram and High-Level Interface Definition TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 Table of Contents Contents Page 1 Introduction ........................................................................................................................................................................1 2 Pin Information ...................................................................................................................................................................5 2.1 Ball Diagram ................................................................................................................................................................5 2.2 Package Pin Assignments ...........................................................................................................................................6 2.3 Pin Assignment Matrix ...............................................................................................................................................16 2.4 Pin Types ...................................................................................................................................................................19 2.5 Pin Definitions ............................................................................................................................................................20 3 Absolute Maximum Ratings .............................................................................................................................................30 3.1 Handling Precautions ................................................................................................................................................30 3.2 Thermal Parameters (Definitions and Values) ...........................................................................................................30 3.3 Reliability ...................................................................................................................................................................31 4 Electrical Characteristics .................................................................................................................................................32 4.1 Recommended Operating Voltages ..........................................................................................................................32 4.2 Recommended Powerup Sequence ..........................................................................................................................32 4.3 Power Consumption ..................................................................................................................................................32 4.4 ac and dc Characteristics ..........................................................................................................................................33 4.4.1 LVCMOS Interface Characteristics ..................................................................................................................33 4.4.2 LVDS Interface Characteristics ........................................................................................................................33 5 Timing ..............................................................................................................................................................................34 5.1 DS3/E3 Timing ..........................................................................................................................................................34 5.2 NSMI Timing ..............................................................................................................................................................35 5.3 Shared Low-Speed Line Timing ................................................................................................................................37 5.4 CHI Timing .................................................................................................................................................................37 5.5 Parallel System Bus (PSB) Timing ............................................................................................................................41 6 Reference Clocks ............................................................................................................................................................42 7 Microprocessor Interface Timing .....................................................................................................................................45 7.1 Synchronous Write Mode ..........................................................................................................................................45 7.2 Synchronous Read Mode ..........................................................................................................................................46 7.3 Asynchronous Write Mode ........................................................................................................................................47 7.4 Asynchronous Read Mode ........................................................................................................................................48 8 Other Timing ....................................................................................................................................................................50 9 Hardware Design File References ...................................................................................................................................50 10 909-Pin PBGA Diagram .................................................................................................................................................51 11 Ordering Information ......................................................................................................................................................52 12 Glossary .........................................................................................................................................................................53 13 Change History ...............................................................................................................................................................54 13.1 Navigating Through an Adobe Acrobat Document .................................................................................................54 2 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table of Contents (continued) Tables Page Table 2-1. Package Pin Assignments .....................................................................................................................................6 Table 2-2. Pin Matrix.............................................................................................................................................................16 Table 2-3. Pin Types.............................................................................................................................................................19 Table 2-4. LVDS Framer Reference Clock ...........................................................................................................................20 Table 2-5. DS3/E3 Out .........................................................................................................................................................20 Table 2-6. DS3/E3 In ............................................................................................................................................................20 Table 2-7. NSMI In................................................................................................................................................................21 Table 2-8. NSMI Out .............................................................................................................................................................21 Table 2-9. Shared Low-Speed Line In ..................................................................................................................................22 Table 2-10. Shared Low-Speed Line Out .............................................................................................................................23 Table 2-11. TDM Concentration Highway (CHI) In ...............................................................................................................24 Table 2-12. TDM Concentration Highway (CHI) Out ............................................................................................................24 Table 2-13. Framer (FRM) Block, CHI/Parallel System Bus (PSB) Clock and Sync ............................................................25 Table 2-14. Reference Clocks ..............................................................................................................................................25 Table 2-15. Clock Generator ................................................................................................................................................26 Table 2-16. Microprocessor Interface ...................................................................................................................................27 Table 2-17. Boundary Scan (IEEE(R) 1149.1)........................................................................................................................28 Table 2-18. General-Purpose Interface ................................................................................................................................28 Table 2-19. Analog Power and Ground Signals ...................................................................................................................28 Table 2-20. Digital Power and Ground Signals.....................................................................................................................29 Table 2-21. No Connects ......................................................................................................................................................29 Table 3-1. Absolute Maximum Ratings .................................................................................................................................30 Table 3-2. ESD Tolerance ....................................................................................................................................................30 Table 3-3. Thermal Parameter Values..................................................................................................................................31 Table 3-4. Reliability Data.....................................................................................................................................................31 Table 4-1. Recommended Operating Conditions .................................................................................................................32 Table 4-2. Typical Power Consumption Per Block ...............................................................................................................32 Table 4-3. LVCMOS Inputs Specifications ...........................................................................................................................33 Table 4-4. LVCMOS Outputs Specifications.........................................................................................................................33 Table 4-5. LVCMOS Bidirectionals Specifications ................................................................................................................33 Table 4-6. LVDS Interface dc Characteristics.......................................................................................................................33 Table 5-1. DS3/E3 Input Specifications ................................................................................................................................34 Table 5-2. DS3/E3 Output Specifications .............................................................................................................................34 Table 5-3. NSMI Input Specifications ...................................................................................................................................36 Table 5-4. NSMI Output Specifications.................................................................................................................................36 Table 5-5. Shared Low-Speed Line Timing Input Specifications ..........................................................................................37 Table 5-6. Shared Low-Speed Line Timing Output Specifications .......................................................................................37 Table 5-7. CHIRXGCLK and CHITXGCLK Timing Specifications ........................................................................................37 Table 5-8. CHI Interface Timing Specifications ....................................................................................................................38 Table 5-9. PSB Input Specifications .....................................................................................................................................41 Table 5-10. PSB Output Specifications ................................................................................................................................41 Table 6-1. Framer Input Clocks Specifications .....................................................................................................................42 Table 6-2. DS3/E3 Input Clocks Specifications ....................................................................................................................42 Table 6-3. DS1/E1 DJA Input Clocks Specifications ............................................................................................................42 Table 6-4. M13/E13 Input Clocks Specifications ..................................................................................................................42 Table 6-5. Microprocessor Interface Input Clocks Specifications .........................................................................................42 Table 6-6. Framer PLL Input Clocks Specifications.............................................................................................................43 Table 6-7. CHI Input Clocks Specifications ..........................................................................................................................43 Table 6-8. PSB Input Clocks Specifications .........................................................................................................................43 Table 6-9. DS3/E3 Output Clocks Specifications .................................................................................................................43 Table 6-10. Framer PLL Output Clocks Specifications ........................................................................................................43 Table 6-11. Shared Low-Speed Receive Line Input/Output Clocks Specifications ..............................................................43 Table 6-12. Shared Low-Speed Transmit Line Input/Output Clocks Specifications .............................................................44 Table 6-13. NSMI Input Clock Specifications .......................................................................................................................44 Table 6-14. NSMI Output Clocks Specifications ...................................................................................................................44 Table 7-1. Microprocessor Interface Synchronous Write Cycle Specifications.....................................................................45 Table 7-2. Microprocessor Interface Synchronous Read Cycle Specifications ....................................................................46 Table 7-3. Microprocessor Interface Asynchronous Write Cycle Specifications...................................................................48 Table 7-4. Microprocessor Interface Asynchronous Read Cycle Specifications...................................................................49 Table 8-1. General-Purpose Inputs Specifications ...............................................................................................................50 Table 8-2. General-Purpose Output Specifications ..............................................................................................................50 Table 11-1. Ordering Information..........................................................................................................................................52 Table 13-1. Changes ............................................................................................................................................................54 Agere Systems Inc. 3 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 Table of Contents (continued) Figures Page Figure 1-1. Ultraframer Block Diagram and High-Level Interface Definition...........................................................................1 Figure 2-1. Ultraframer Package Diagram (Top View) ...........................................................................................................5 Figure 5-1. DS3/E3 Interface Diagram in M13/E13 Block ....................................................................................................34 Figure 5-2. NSMI Clock and Data Diagram for M13 NSMI Mode (NSMI <---> M13 <---> DS3 External I/O) .......................35 Figure 5-3. NSMI Clock and Data Diagram for E13 NSMI Mode 1 (NSMI <---> E13 <---> E3 External I/O)........................35 Figure 5-4. NSMI Clock and Data Diagram for Framer (FRM) NSMI Mode .........................................................................36 Figure 5-5. Shared Low-Speed Line Clock and Data Timing ...............................................................................................37 Figure 5-6. CHI Clock Timing ...............................................................................................................................................37 Figure 5-7. CHI Bus Timing ..................................................................................................................................................38 Figure 5-8. Typical Receive CHI Timing (Non-CMS Mode--FRM_CMS = 0) ......................................................................38 Figure 5-9. Transmit CHI Timing (Non-CMS Mode--FRM_CMS = 0)..................................................................................39 Figure 5-10. Typical Receive CHI Timing (CMS Mode--FRM_CMS = 1) ............................................................................39 Figure 5-11. Transmit CHI Timing (CMS Mode--FRM_CMS = 1) .......................................................................................40 Figure 5-12. PSB Clock and Data Timing.............................................................................................................................41 Figure 7-1. Microprocessor Interface Synchronous Write Cycle--MPMODE Pin = 1 ..........................................................45 Figure 7-2. Microprocessor Interface Synchronous Read Cycle--MPMODE Pin = 1 ..........................................................46 Figure 7-3. Microprocessor Interface Asynchronous Write Cycle--MPMODE Pin = 0 ........................................................47 Figure 7-4. Microprocessor Interface Asynchronous Read Cycle--MPMODE Pin = 0 ........................................................48 Figure 10-1. Ultraframer 909-Pin PBGA Balls and Dimensions ...........................................................................................51 4 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 2 Pin Information 2.1 Ball Diagram The TFRA84J13 Ultraframer is housed in a 909-pin plastic ball grid array. Figure 2-1 shows the ball assignment viewed from the top of the package. The pins are spaced on a 1.0 mm pitch. 1 3 2 5 4 9 7 6 8 11 10 13 12 15 14 16 17 19 21 23 25 27 29 31 33 18 20 22 24 26 28 30 32 34 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP Figure 2-1. Ultraframer Package Diagram (Top View) Agere Systems Inc. 5 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 2.2 Package Pin Assignments Table 2-1. Package Pin Assignments (continued) Table 2-1. Package Pin Assignments 6 Signal Name Pin Signal Name Pin ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] ADDR[7] ADDR[8] ADDR[9] ADDR[10] ADDR[11] ADDR[12] ADDR[13] ADDR[14] ADDR[15] ADDR[16] ADDR[17] ADDR[18] ADDR[19] ADDR[20] ADSN NC NC CG_PLLCLKOUT CLKIN_PLL CSN NC NC CTAPTH NC DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13] K6 H4 G3 J8 J4 K5 F1 G2 L6 L5 H2 M6 K4 L8 M5 N6 J1 L3 M4 P8 N5 F3 Y1 AM13 AF26 AF27 G7 AF8 AG10 AG9 AG14 K1 L2 U2 N4 R8 M2 T5 M1 R5 U5 P4 N2 R4 T4 DATA[14] DATA[15] DS1XCLK DS2AISCLK DS3DATAINCLK[1] DS3DATAINCLK[2] DS3DATAINCLK[3] NC NC NC DS3DATAOUTCLK[1] DS3DATAOUTCLK[2] DS3DATAOUTCLK[3] NC NC NC DS3NEGDATAIN[1] DS3NEGDATAIN[2] DS3NEGDATAIN[3] NC NC NC DS3NEGDATAOUT[1] DS3NEGDATAOUT[2] DS3NEGDATAOUT[3] NC NC NC DS3POSDATAIN[1] DS3POSDATAIN[2] DS3POSDATAIN[3] NC NC NC DS3POSDATAOUT[1] DS3POSDATAOUT[2] DS3POSDATAOUT[3] NC NC NC DS3RXCLKOUT[1] DS3RXCLKOUT[2] DS3RXCLKOUT[3] NC NC U9 P1 AP21 V8 AB1 V4 V3 AE1 AF1 AB4 AB5 AB8 AC5 AD5 AE5 AG4 V1 AC1 Y4 AC2 Y5 AA5 AC3 AC4 AJ1 AL1 AG3 AJ2 W3 AB2 AD1 V5 W8 W5 V2 AA6 AH1 AK1 AG2 AF4 AD2 AD3 AB6 AC8 AD6 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 2-1. Package Pin Assignments (continued) Table 2-1. Package Pin Assignments (continued) Signal Name Pin Signal Name Pin NC DSN DTN E1XCLK E2AISCLK NC NC NC NC HP_INTN IC3STATEN IDDQ LINERXCLK[1] LINERXCLK[2] LINERXCLK[3] LINERXCLK[4] LINERXCLK[5] LINERXCLK[6] LINERXCLK[7] LINERXCLK[8] LINERXCLK[9] LINERXCLK[10] LINERXCLK[11] LINERXCLK[12] LINERXCLK[13] LINERXCLK[14] LINERXCLK[15] LINERXCLK[16] LINERXCLK[17] LINERXCLK[18] LINERXCLK[19] LINERXCLK[20] LINERXCLK[21] LINERXCLK[22] LINERXCLK[23] LINERXCLK[24] LINERXCLK[25] LINERXCLK[26] LINERXCLK[27] LINERXCLK[28] LINERXCLK[29] LINERXCLK[30] LINERXCLK[31] LINERXCLK[32] LINERXCLK[33] LINERXCLK[34] LINERXCLK[35] AE8 J5 T3 AM18 AA1 H18 AL14 AP15 AP16 U8 AL20 AL21 A18 C17 E16 C16 B16 A15 A14 C13 B13 D12 B12 D11 B11 E12 D10 H12 D9 C8 H11 B7 E9 E10 D7 E8 F9 E7 D6 G8 B4 F7 J9 F4 C1 H9 E5 LINERXCLK[36] LINERXCLK[37] LINERXCLK[38] LINERXCLK[39] LINERXCLK[40] LINERXCLK[41] LINERXCLK[42] LINERXCLK[43] LINERXCLK[44] LINERXCLK[45] LINERXCLK[46] LINERXCLK[47] LINERXCLK[48] LINERXCLK[49] LINERXCLK[50] LINERXCLK[51] LINERXCLK[52] LINERXCLK[53] LINERXCLK[54] LINERXCLK[55] LINERXCLK[56] LINERXCLK[57] LINERXCLK[58] LINERXCLK[59] LINERXCLK[60] LINERXCLK[61] LINERXCLK[62] LINERXCLK[63] LINERXCLK[64] LINERXCLK[65] LINERXCLK[66] LINERXCLK[67] LINERXCLK[68] LINERXCLK[69] LINERXCLK[70] LINERXCLK[71] LINERXCLK[72] LINERXCLK[73] LINERXCLK[74] LINERXCLK[75] LINERXCLK[76] LINERXCLK[77] LINERXCLK[78] LINERXCLK[79] LINERXCLK[80] LINERXCLK[81] LINERXCLK[82] F6 A10 A12 H14 D14 A16 E17 B18 D19 H20 D21 B24 F22 B28 A29 H24 A32 D29 D30 H26 E30 F29 L30 M27 M30 N29 M31 N30 L33 N31 P29 M34 N34 T27 T33 U33 V30 W34 W31 AA34 Y30 AC33 AH3 AH2 AE4 AD4 Y8 Agere Systems Inc. 7 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 Table 2-1. Package Pin Assignments (continued) 8 Table 2-1. Package Pin Assignments (continued) Signal Name Pin Signal Name Pin LINERXCLK[83] LINERXCLK[84] LINERXCLK[85] LINERXCLK[86] LINERXDATA[1] LINERXDATA[2] LINERXDATA[3] LINERXDATA[4] LINERXDATA[5] LINERXDATA[6] LINERXDATA[7] LINERXDATA[8] LINERXDATA[9] LINERXDATA[10] LINERXDATA[11] LINERXDATA[12] LINERXDATA[13] LINERXDATA[14] LINERXDATA[15] LINERXDATA[16] LINERXDATA[17] LINERXDATA[18] LINERXDATA[19] LINERXDATA[20] LINERXDATA[21] LINERXDATA[22] LINERXDATA[23] LINERXDATA[24] LINERXDATA[25] LINERXDATA[26] LINERXDATA[27] LINERXDATA[28] LINERXDATA[29] LINERXDATA[30] LINERXDATA[31] LINERXDATA[32] LINERXDATA[33] LINERXDATA[34] LINERXDATA[35] LINERXDATA[36] LINERXDATA[37] LINERXDATA[38] LINERXDATA[39] LINERXDATA[40] LINERXDATA[41] LINERXDATA[42] LINERXDATA[43] AA4 W4 U1 T2 E18 D17 B17 D16 H16 E15 E14 D13 F14 A13 E13 F13 H13 A11 A9 A8 B8 E11 A7 D8 F11 C7 A6 F10 B6 C6 F8 A5 A4 E6 H6 G5 H8 G6 F5 H10 F12 C11 C12 H15 D15 A17 H17 LINERXDATA[44] LINERXDATA[45] LINERXDATA[46] LINERXDATA[47] LINERXDATA[48] LINERXDATA[49] LINERXDATA[50] LINERXDATA[51] LINERXDATA[52] LINERXDATA[53] LINERXDATA[54] LINERXDATA[55] LINERXDATA[56] LINERXDATA[57] LINERXDATA[58] LINERXDATA[59] LINERXDATA[60] LINERXDATA[61] LINERXDATA[62] LINERXDATA[63] LINERXDATA[64] LINERXDATA[65] LINERXDATA[66] LINERXDATA[67] LINERXDATA[68] LINERXDATA[69] LINERXDATA[70] LINERXDATA[71] LINERXDATA[72] LINERXDATA[73] LINERXDATA[74] LINERXDATA[75] LINERXDATA[76] LINERXDATA[77] LINERXDATA[78] LINERXDATA[79] LINERXDATA[80] LINERXDATA[81] LINERXDATA[82] LINERXDATA[83] LINERXDATA[84] LINERXDATa[85] LINERXDATA[86] LINETXCLK[1] LINETXCLK[2] LINETXCLK[3] LINETXCLK[4] C18 A22 E21 D22 A26 H23 D25 A30 F25 A33 G27 E29 F28 G28 L29 L31 M29 N27 L32 K34 P30 M32 L34 M33 R27 P34 T32 U30 U34 V32 V31 W30 AB34 AC34 AD8 AE6 AC6 AA8 AG1 AB3 V9 W2 T1 K31 J34 H34 J30 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 2-1. Package Pin Assignments (continued) Table 2-1. Package Pin Assignments (continued) Signal Name Pin Signal Name Pin LINETXCLK[5] LINETXCLK[6] LINETXCLK[7] LINETXCLK[8] LINETXCLK[9] LINETXCLK[10] LINETXCLK[11] LINETXCLK[12] LINETXCLK[13] LINETXCLK[14] LINETXCLK[15] LINETXCLK[16] LINETXCLK[17] LINETXCLK[18] LINETXCLK[19] LINETXCLK[20] LINETXCLK[21] LINETXCLK[22] LINETXCLK[23] LINETXCLK[24] LINETXCLK[25] LINETXCLK[26] LINETXCLK[27] LINETXCLK[28] LINETXCLK[29] LINETXCLK[30] LINETXCLK[31] LINETXCLK[32] LINETXCLK[33] LINETXCLK[34] LINETXCLK[35] LINETXCLK[36] LINETXCLK[37] LINETXCLK[38] LINETXCLK[39] LINETXCLK[40] LINETXCLK[41] LINETXCLK[42] LINETXCLK[43] LINETXCLK[44] LINETXCLK[45] LINETXCLK[46] LINETXCLK[47] LINETXCLK[48] LINETXCLK[49] LINETXCLK[50] LINETXCLK[51] H32 H31 J29 G31 G30 H27 C31 J26 F27 F26 D28 C29 A31 E25 C28 B29 C27 D24 A28 A27 C24 A25 C23 A24 H21 A23 AA31 AA27 AD33 AB31 AB29 AD32 AC31 AB27 AG34 AD31 AD29 AD30 AG32 AE29 AE27 AJ28 AK29 AH28 AH27 AM31 AL28 LINETXCLK[52] LINETXCLK[53] LINETXCLK[54] LINETXCLK[55] LINETXCLK[56] LINETXCLK[57] LINETXCLK[58] LINETXCLK[59] LINETXCLK[60] LINETXCLK[61] LINETXCLK[62] LINETXCLK[63] LINETXCLK[64] LINETXCLK[65] LINETXCLK[66] LINETXCLK[67] LINETXCLK[68] LINETXCLK[69] LINETXCLK[70] LINETXCLK[71] LINETXCLK[72] LINETXCLK[73] LINETXCLK[74] LINETXCLK[75] LINETXCLK[76] LINETXCLK[77] LINETXCLK[78] LINETXCLK[79] LINETXCLK[80] LINETXCLK[81] LINETXCLK[82] LINETXCLK[83] LINETXCLK[84] LINETXCLK[85] LINETXCLK[86] LINETXDATA[1] LINETXDATA[2] LINETXDATA[3] LINETXDATA[4] LINETXDATA[5] LINETXDATA[6] LINETXDATA[7] LINETXDATA[8] LINETXDATA[9] LINETXDATA[10] LINETXDATA[11] LINETXDATA[12] AL26 AM27 AG22 AL30 AG20 AG24 AG25 AK19 AL19 AF17 AJ25 AH7 AN18 AJ12 AK12 AN16 AK14 AL4 AH6 AL3 AF9 AJ4 AH4 AG5 AF5 U3 N3 P5 P6 H1 G1 K8 F2 D1 H7 L27 K30 K29 J31 H33 K27 H30 H29 J27 G29 H28 B32 Agere Systems Inc. 9 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 Table 2-1. Package Pin Assignments (continued) 10 Table 2-1. Package Pin Assignments (continued) Signal Name Pin Signal Name Pin LINETXDATA[13] LINETXDATA[14] LINETXDATA[15] LINETXDATA[16] LINETXDATA[17] LINETXDATA[18] LINETXDATA[19] LINETXDATA[20] LINETXDATA[21] LINETXDATA[22] LINETXDATA[23] LINETXDATA[24] LINETXDATA[25] LINETXDATA[26] LINETXDATA[27] LINETXDATA[28] LINETXDATA[29] LINETXDATA[30] LINETXDATA[31] LINETXDATA[32] LINETXDATA[33] LINETXDATA[34] LINETXDATA[35] LINETXDATA[36] LINETXDATA[37] LINETXDATA[38] LINETXDATA[39] LINETXDATA[40] LINETXDATA[41] LINETXDATA[42] LINETXDATA[43] LINETXDATA[44] LINETXDATA[45] LINETXDATA[46] LINETXDATA[47] LINETXDATA[48] LINETXDATA[49] LINETXDATA[50] LINETXDATA[51] LINETXDATA[52] LINETXDATA[53] LINETXDATA[54] LINETXDATA[55] LINETXDATA[56] LINETXDATA[57] LINETXDATA[58] LINETXDATA[59] E28 B31 E27 H25 E26 D27 D26 F24 E24 F23 B27 E23 D23 H22 E22 F21 B23 C22 AA29 AB32 AD34 AA30 AC32 AE34 AB30 AF34 AC30 AC29 AG33 AE31 AC27 AE30 AJ33 AL31 AM33 AK30 AJ29 AM32 AN33 AK25 AK24 AK23 AP28 AP26 AP25 AN24 AM22 LINETXDATA[60] LINETXDATA[61] LINETXDATA[62] LINETXDATA[63] LINETXDATA[64] LINETXDATA[65] LINETXDATA[66] LINETXDATA[67] LINETXDATA[68] LINETXDATA[69] LINETXDATA[70] LINETXDATA[71] LINETXDATA[72] LINETXDATA[73] LINETXDATA[74] LINETXDATA[75] LINETXDATA[76] LINETXDATA[77] LINETXDATA[78] LINETXDATA[79] LINETXDATA[80] LINETXDATA[81] LINETXDATA[82] LINETXDATA[83] LINETXDATA[84] LINETXDATA[85] LINETXDATA[86] NC NC NC NC NC NC NC LP_INTN MODE0_PLL MODE1_PLL MODE2_PLL MPCLK MPMODE CHIRXDATA[17] CHIRXDATA[14] CHIRXDATA[18] CHIRXDATA[16] CHIRXDATA[15] CHIRXDATA[13] CHIRXDATA[10] AG18 AM19 AL18 AN19 AK11 AK16 AP17 AL15 AG8 AK5 AJ5 AK4 AH5 AG6 AL2 AF6 AJ3 N1 T8 L1 M3 M8 L4 H3 N8 E1 H5 B22 A21 D20 H19 E20 A20 AG27 W1 AJ31 AG30 AK31 G4 D2 N32 N33 P27 P31 R30 R31 R34 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 2-1. Package Pin Assignments (continued) Table 2-1. Package Pin Assignments (continued) Signal Name Pin Signal Name Pin CHIRXDATA[12] CHIRXDATA[11] CHIRXDATA[7] CHIRXDATA[6] CHIRXDATA[9] CHIRXDATA[8] CHIRXDATA[3] CHIRXDATA[4] CHIRXDATA[5] CHIRXGCLK CHIRXDATA[1] CHIRXDATA[2] CHITXGCLK CHIRXGTCLK CHIRXGFS CHITXGFS CHITXDATA[16] CHITXDATA[11] CHITXDATA[13] CHITXDATA[15] CHITXDATA[5] CHITXDATA[8] CHITXDATA[12] CHITXDATA[6] CHITXDATA[10] CHITXDATA[17] CHITXDATA[18] CHITXDATA[7] CHITXDATA[9] CHITXDATA[14] CHITXDATA[1] CHITXDATA[3] CHITXDATA[4] CHITXDATA[2] NSMIRXCLK[1] NSMIRXCLK[2] NSMIRXCLK[3] NSMIRXDATA[1] NSMIRXDATA[2] NSMIRXDATA[3] NSMIRXSYNC[1] NSMIRXSYNC[2] NSMIRXSYNC[3] NSMITXCLK[1] NSMITXCLK[2] NSMITXCLK[3] NSMITXDATA[1] T30 T31 T34 U27 U31 U32 V27 V33 V34 W27 W32 W33 Y27 Y31 Y34 AB33 AD27 AF29 AF30 AF31 AG28 AG29 AG31 AH29 AH32 AH33 AH34 AJ30 AJ32 AJ34 AK26 AK27 AL29 AN32 AJ22 AK28 AG21 AM24 AP27 AN27 AL22 AL23 AP29 AG23 AP31 AN31 AN28 NSMITXDATA[2] NSMITXDATA[3] NSMITXSYNC[1] NSMITXSYNC[2] NSMITXSYNC[3] PAR[0] PAR[1] PMRST REF10 REF14 RESHI RESLO NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC RSTN NC NC NC RWN RXDATAEN[1] RXDATAEN[2] RXDATAEN[3] SCAN_EN SCANMODE SCK1 SCK2 TCK TDI TDO THSCN AL25 AP33 AP30 AP32 AL27 R1 U4 AJ24 AK6 AJ6 AL5 AL6 AN1 AM1 AM3 AM2 AP22 AJ14 AN10 AM10 AP12 AP10 AM9 AP11 AM17 AG17 AP19 AM8 AM7 AP6 AN6 AK18 AM16 AK15 AN17 J6 AK21 AK22 AL24 AJ23 AK20 AP24 AM23 AN22 AP23 AJ21 AP4 Agere Systems Inc. 11 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 Table 2-1. Package Pin Assignments (continued) 12 Table 2-1. Package Pin Assignments (continued) Signal Name Pin Signal Name Pin NC NC THSCP NC NC NC NC NC NC NC NC NC NC TMS NC NC NC NC NC NC NC TRST NC NC NC NC NC NC TXDATAEN[1] TXDATAEN[2] TXDATAEN[3] VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 AP2 AN2 AN4 AM6 AM5 AL13 AK13 AM11 AN13 AP14 AN11 AN12 AP13 AN23 AL17 AK17 AP20 AP8 AN8 AN9 AP9 AG26 AJ13 AG15 AG7 AH8 AL16 AP18 AN29 AM28 AM29 J10 J13 J17 J18 J22 J25 K9 K17 K18 K26 N9 N13 N14 N15 N16 N17 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 N18 N19 N20 N21 N22 N26 P13 P22 R13 R22 T13 T22 U10 U13 U22 U25 U26 V10 V13 V22 V25 V26 W13 W22 Y13 Y22 AA9 AA13 AA22 AA26 AB9 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB26 AE9 AE17 AE18 AE26 AF10 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 2-1. Package Pin Assignments (continued) Table 2-1. Package Pin Assignments (continued) Signal Name Pin Signal Name Pin VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 NC NC NC NC NC VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 AF13 AF14 AF18 AF21 AF22 AF25 AH26 AJ26 AJ27 J14 J21 P9 P26 AG12 AL11 C19 B19 AM12 A2 A3 B1 B3 B5 B9 B10 B14 B15 B20 B21 B25 B26 B30 B33 B34 C2 C4 C32 C33 C34 D3 D5 D32 D33 D34 E2 E4 E33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 E34 J2 J11 J12 J15 J16 J19 J20 J23 J24 J33 K2 K33 L9 L26 M9 M26 P2 P33 R2 R9 R26 R33 T9 T26 W9 W26 Y2 Y9 Y26 Y33 AA2 AA33 AC9 AC26 AD9 AD26 AE2 AE33 AF2 AF11 AF12 AF15 AF16 AF19 AF20 AF23 Agere Systems Inc. 13 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 Table 2-1. Package Pin Assignments (continued) Signal Name Pin Signal Name Pin VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 AF24 AF33 AK2 AK33 AK34 AL33 AL34 AM34 AN14 AN15 AN20 AN21 AN25 AN26 AN30 AN34 AH30 B2 C3 C5 C9 C10 C14 C15 C20 C21 C25 C26 C30 D4 D31 E3 E31 E32 F30 F31 F32 F33 F34 G32 G33 G34 J3 J32 K3 K32 P3 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS P14 P15 P16 P17 P18 P19 P20 P21 P32 R3 R14 R15 R16 R17 R18 R19 R20 R21 R32 T14 T15 T16 T17 T18 T19 T20 T21 U14 U15 U16 U17 U18 U19 U20 U21 V14 V15 V16 V17 V18 V19 V20 V21 W14 W15 W16 W17 VDD33A_SFPLL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 14 Table 2-1. Package Pin Assignments (continued) Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 2-1. Package Pin Assignments (continued) Table 2-1. Package Pin Assignments (continued) Signal Name Pin Signal Name Pin VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS W18 W19 W20 W21 Y3 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y32 AA3 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA32 AE3 AE32 AF3 AF32 AG16 AG19 AJ7 AJ8 AJ9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC NC NC AJ10 AJ11 AK3 AK7 AK8 AK9 AK10 AK32 AL7 AL8 AL9 AL10 AL32 AM4 AM14 AM15 AM20 AM21 AM25 AM26 AM30 AN3 AN5 AN7 AP3 AP5 AP7 AG11 AG13 D18 A19 AH31 AL12 E19 Agere Systems Inc. VSSA_SFPLL NC NC 15 VDD33 LINETXCLK[84] ADDR[7] ADDR[10] VDD33 VDD33 DATA[1] DATA[5] DATA[11] VDD33 VDD33 LINERXCLK[86] DATA[2] LINETXDATA[85] ADDR[6] LINETXCLK[82] LINETXCLK[81] ADDR[16] DATA[0] LINETXDATA[79] DATA[7] LINETXDATA[77] DATA[15] PAR[0] LINERXDATA[86] LINERXCLK[85] D E F G H J K L M N P R T U VDD33 NC NC LINERXDATA[82] AF AG LINETXDATA[74] NC NC NC -- AL AM AN AP 16 NC NC NC VDD33 AK NC NC VDD33 NC AE LINERXCLK[79] DS3RXCLKOUT[1] DS3POSDATAIN[3] AD AJ DS3NEGDATAOUT[3] NC AH DS3POSDATAOUT[3] DS3POSDATAIN[2] DS3DATAINCLK[1] DS3NEGDATAIN[2] VDD33 E2AISCLK AA AC VDD33 NC Y AB LINERXDATA[85] LP_INTN W DS3NEGDATAIN[1] DS3POSDATAOUT[1] MPMODE LINETXCLK[85] C V VSS VDD33 VDD33 LINERXCLK[33] B 2 VDD33 1 -- A Table 2-2. Pin Matrix 3 LINERXDATA[83] VSS VSS DS3POSDATAIN[1] DS3DATAINCLK[3] LINETXCLK[77] DTN VSS VSS LINETXCLK[78] LINETXDATA[80] ADDR[17] VSS VSS LINETXDATA[83] ADDR[2] ADSN VSS VDD33 VSS VDD33 VDD33 4 NC LINERXCLK[83] DS3NEGDATAIN[3] LINERXCLK[84] DS3DATAINCLK[2] PAR[1] DATA[13] DATA[12] DATA[10] DATA[3] ADDR[18] LINETXDATA[82] ADDR[12] ADDR[4] ADDR[1] MPCLK LINERXCLK[32] VDD33 VSS VDD33 LINERXCLK[29] LINERXDATA[29] 5 DS3DATAOUTCLK[1] NC NC NC NC DATA[9] DATA[6] DATA[8] LINETXCLK[79] ADDR[20] ADDR[14] ADDR[9] ADDR[5] DSN LINETXDATA[86] LINERXDATA[32] LINERXDATA[35] LINERXCLK[35] VDD33 VSS VDD33 LINERXDATA[28] VSS VSS NC LINETXCLK[71] VSS LINETXDATA[76] LINERXCLK[78] NC VSS VSS DS3RXCLKOUT[2] LINETXDATA[69] RESHI NC VSS VSS LINETXCLK[69] VSS THSCP THSCN LINETXDATA[70] LINETXDATA[72] LINETXCLK[75] LINETXCLK[76] NC NC LINETXDATA[71] LINETXCLK[73] LINETXCLK[74] NC NC LINERXCLK[80] LINERXCLK[81] DS3NEGDATAOUT[1] DS3NEGDATAOUT[2] DS3DATAOUTCLK[3] 2.3 Pin Assignment Matrix TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 6 RPSDN NC NC RESLO REF10 REF14 LINETXCLK[70] LINETXDATA[73] LINETXDATA[75] LINERXDATA[79] NC LINERXDATA[80] DS3RXCLKOUT[3] DS3POSDATAOUT[2] -- -- -- -- -- -- LINETXCLK[80] ADDR[15] ADDR[11] ADDR[8] ADDR[0] RWN LINERXDATA[31] LINERXDATA[34] LINERXCLK[36] LINERXDATA[30] LINERXCLK[27] LINERXDATA[26] LINERXDATA[25] LINERXDATA[23] 7 VSS VSS NC VSS VSS VSS LINETXCLK[63] NC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LINETXCLK[86] CSN LINERXCLK[30] LINERXCLK[26] LINERXCLK[23] LINERXDATA[22] LINERXCLK[20] LINERXDATA[19] 8 NC NC NC VSS VSS VSS NC LINETXDATA[68] NC NC LINERXDATA[78] NC DS3DATAOUTCLK[2] LINERXDATA[81] LINERXCLK[82] NC DS2AISCLK HP_INTN LINETXDATA[78] DATA[4] ADDR[19] LINETXDATA[84] LINETXDATA[81] ADDR[13] LINETXCLK[83] ADDR[3] LINERXDATA[33] LINERXCLK[28] LINERXDATA[27] LINERXCLK[24] LINERXDATA[20] LINERXCLK[18] LINERXDATA[17] LINERXDATA[16] NC NC NC VSS VSS VSS -- CTAPTH LINETXCLK[72] VDD15 VDD33 VDD33 VDD15 VDD15 VDD33 VDD33 LINERXDATA[84] DATA[14] VDD33 VDD33 VDD15 VDD15 VDD33 VDD33 VDD15 LINERXCLK[31] LINERXCLK[34] -- LINERXCLK[25] LINERXCLK[21] LINERXCLK[17] VSS VDD33 LINERXDATA[15] 9 NC NC NC VSS VSS VSS -- NC VDD15 -- -- -- -- -- -- -- VDD15 VDD15 -- -- -- -- -- -- -- VDD15 LINERXDATA[36] -- LINERXDATA[24] LINERXCLK[22] LINERXCLK[15] VSS VDD33 LINERXCLK [37] 10 12 NC NC NC NC LINETXCLK[66] LINETXCLK[65] -- NC VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 LINERXCLK[16] -- LINERXDATA[37] LINERXCLK[14] LINERXCLK[10] LINERXDATA[39] LINERXCLK[11] LINERXCLK [38] Agere Systems Inc. NC NC NC NC LINETXDATA[64] VSS -- NC VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 LINERXCLK[19] -- LINERXDATA[21] LINERXDATA[18] LINERXCLK[12] LINERXDATA[38] LINERXCLK[13] LINERXDATA [14] 11 Hardware Design Guide, Revision 5 July 13, 2004 VSS -- -- -- VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 -- -- -- VDD15 NC -- NC NC NC NC NC NC K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP Agere Systems Inc. VSS VDD15 J -- NC VDD33 VSS NC LINETXCLK[68] NC -- NC VDD15 -- -- -- VDD15 VSS VSS VSS VSS VSS VSS VDD15 -- -- -- VDD15 LINERXCLK[39] -- LINERXDATA[13] LINERXDATA[9] H LINERXDATA[12] F LINERXDATA[7] LINERXCLK[40] VSS VDD33 LINERXCLK [7] 14 G LINERXDATA[8] LINERXDATA[11] LINERXCLK[8] C E LINERXCLK[9] B D LINERXDATA [10] A 13 Table 2-2. Pin Matrix (continued) NC VDD33 VSS LINETXDATA[67] NC -- -- NC VDD33 -- -- -- VDD15 VSS VSS VSS VSS VSS VSS VSS VSS VDD15 -- -- -- VDD33 LINERXDATA[40] -- -- LINERXDATA[6] LINERXDATA[41] VSS VDD33 LINERXCLK [6] 15 Hardware Design Guide, Revision 5 July 13, 2004 NC LINETXCLK[67] NC NC LINETXDATA[65] -- -- VSS VDD33 -- -- -- VDD15 VSS VSS VSS VSS VSS VSS VSS VSS VDD15 -- -- -- VDD33 LINERXDATA[5] -- -- LINERXCLK[3] LINERXDATA[4] LINERXCLK[4] LINERXCLK[5] LINERXCLK [41] 16 LINETXDATA[66] NC NC NC NC -- -- NC LINETXCLK[61] VDD15 -- -- VDD15 VSS VSS VSS VSS VSS VSS VSS VSS VDD15 -- -- VDD15 VDD15 LINERXDATA[43] -- -- LINERXCLK[42] LINERXDATA[2] LINERXCLK[2] LINERXDATA[3] LINERXDATA [42] 17 NC LINETXCLK[64] E1XCLK LINETXDATA[62] RSTN -- -- LINETXDATA[60] VDD15 VDD15 -- -- VDD15 VSS VSS VSS VSS VSS VSS VSS VSS VDD15 -- -- VDD15 VDD15 NC -- -- LINERXDATA[1] NC LINERXDATA[44] LINERXCLK[43] LINERXCLK [1] 18 NC LINETXDATA[63] LINETXDATA[61] LINETXCLK[60] LINETXCLK[59] -- -- VSS VDD33 -- -- -- VDD15 VSS VSS VSS VSS VSS VSS VSS VSS VDD15 -- -- -- VDD33 NC -- -- NC LINERXCLK[44] NC NC NC 19 NC VDD33 VSS IC3STATEN SCANMODE -- -- LINETXCLK[56] VDD33 -- -- -- VDD15 VSS VSS VSS VSS VSS VSS VSS VSS VDD15 -- -- -- VDD33 LINERXCLK[45] -- -- NC NC VSS VDD33 NC 20 DS1XCLK VDD33 VSS IDDQ RXDATAEN[1] TDO -- NSMIRXCLK[3] VDD15 -- -- -- VDD15 VSS VSS VSS VSS VSS VSS VSS VSS VDD15 -- -- -- VDD15 LINETXCLK[29] -- LINETXDATA[28] LINERXDATA[46] LINERXCLK[46] VSS VDD33 NC 21 NC TCK LINETXDATA[59] NSMIRXSYNC[1] RXDATAEN[2] NSMIRXCLK[1] -- LINETXCLK[54] VDD15 -- -- -- VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 -- -- -- VDD15 LINETXDATA[26] -- LINERXCLK[48] LINETXDATA[27] LINERXDATA[47] LINETXDATA[30] NC LINERXDATA[45] 22 TDI TMS SCK2 17 NSMIRXSYNC[2] LINETXDATA[54] SCAN_EN -- NSMITXCLK[1] VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 LINERXDATA[49] -- LINETXDATA[22] LINETXDATA[24] LINETXDATA[25] LINETXCLK[27] LINETXDATA[29] LINETXCLK[30] 23 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 LINERXDATA[52] LINETXDATA[16] VDD15 VDD15 VDD15 LINETXCLK[22] LINETXDATA[21] LINETXDATA[20] -- LINERXCLK[51] VDD33 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD33 LINETXCLK[57] -- PMRST LINETXDATA[53] RXDATAEN[3] NSMIRXDATA[1] LINETXDATA[58] SCK1 D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 18 LINETXCLK[18] LINETXCLK[25] C LINETXDATA[57] VDD33 VSS NSMITXDATA[2] LINETXDATA[52] LINETXCLK[62] -- LINETXCLK[58] VDD15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LINERXDATA[50] VSS VDD33 LINERXCLK[47] B 25 LINETXCLK[26] LINETXCLK[28] A 24 Table 2-2. Pin Matrix (continued) 26 LINETXDATA[56] VDD33 VSS LINETXCLK[52] CHITXDATA[1] VDD15 VDD15 TRST CG_PLLCLKOUT VDD15 VDD33 VDD33 VDD15 VDD15 VDD33 VDD33 VDD15 VDD15 VDD33 VDD33 VDD15 VDD15 VDD33 VDD33 VDD15 LINETXCLK[12] LINERXCLK[55] -- LINETXCLK[14] LINETXDATA[17] LINETXDATA[19] VSS VDD33 LINERXDATA[48] TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 27 NSMIRXDATA[2] NSMIRXDATA[3] LINETXCLK[53] NSMITXSYNC[3] CHITXDATA[3] VDD15 LINETXCLK[49] NC CLKIN_PLL LINETXCLK[45] CHITXDATA[16] LINETXDATA[43] LINETXCLK[38] LINETXCLK[32] CHIRXGCLK CHIRXGCLK CHIRXDATA[3] CHIRXDATA[6] LINERXCLK[69] LINERXDATA[68] CHIRXDATA[18] LINERXDATA[61] LINERXCLK[59] LINETXDATA[1] LINETXDATA[6] LINETXDATA[9] LINETXCLK[10] LINERXDATA[54] LINETXCLK[13] LINETXDATA[15] LINETXDATA[18] LINETXCLK[21] LINETXDATA[23] LINETXCLK[24] 28 LINETXDATA[55] NSMITXDATA[1] TXDATAEN[2] LINETXCLK[51] NSMIRXCLK[2] LINETXCLK[46] LINETXCLK[48] CHITXDATA[5] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LINETXDATA[11] LINERXDATA[57] LINERXDATA[56] LINETXDATA[13] LINETXCLK[15] LINETXCLK[19] LINERXCLK[49] LINETXCLK[23] 29 NSMIRXSYNC[3] TXDATAEN[1] TXDATAEN[3] CHITXDATA[4] LINETXCLK[47] LINETXDATA[49] CHITXDATA[6] CHITXDATA[8] CHITXDATA[11] LINETXCLK[44] LINETXCLK[41] LINETXDATA[40] LINETXCLK[35] LINETXDATA[31] -- -- -- -- -- -- LINERXCLK[66] LINERXCLK[61] LINERXDATA[60] LINERXDATA[58] LINETXDATA[3] LINETXCLK[7] LINETXDATA[8] LINETXDATA[10] LINERXCLK[57] LINERXDATA[55] LINERXCLK[53] LINETXCLK[16] LINETXCLK[20] LINERXCLK[50] 30 NSMITXSYNC[1] VDD33 VSS LINETXCLK[55] LINETXDATA[48] CHITXDATA[7] VDD33A_SFPLL MODE1_PLL CHITXDATA[13] LINETXDATA[44] LINETXCLK[42] LINETXDATA[39] LINETXDATA[37] LINETXDATA[34] LINERXCLK[76] LINERXDATA[75] LINERXCLK[72] LINERXDATA[71] CHIRXDATA[12] CHIRXDATA[15] LINERXDATA[64] LINERXCLK[63] LINERXCLK[60] LINERXCLK[58] LINETXDATA[2] LINETXCLK[4] LINETXDATA[7] LINETXCLK[9] VSS LINERXCLK[56] LINERXCLK[54] VSS VDD33 LINERXDATA[51] 31 NSMITXCLK[2] NSMITXCLK[3] LINETXCLK[50] LINETXDATA[46] MODE2_PLL MODE0_PLL VSSA_SFPLL CHITXDATA[12] CHITXDATA[15] LINETXDATA[42] LINETXCLK[40] LINETXCLK[37] LINETXCLK[34] LINETXCLK[31] CHIRXGTCLK LINERXCLK[74] LINERXDATA[74] CHIRXDATA[9] CHIRXDATA[11] CHIRXDATA[13] CHIRXDATA[16] LINERXCLK[65] LINERCLK[62] LINERXDATA[59] LINETXCLK[1] LINETXDATA[4] LINETXCLK[6] LINETXCLK[8] VSS VSS VSS LINETXCLK[11] LINETXDATA[14] LINETXCLK[17] NSMITXSYNC[2] CHITXDATA[2] LINETXDATA[50] VSS VSS CHITXDATA[9] CHITXDATA[10] LINETXCLK[43] VSS VSS LINETXCLK[36] LINETXDATA[35] LINETXDATA[32] VSS VSS CHIRXDATA[1] LINERXDATA[73] CHIRXDATA[8] LINERXDATA[70] VSS VSS CHIRXDATA[17] LINERXDATA[65] LINERXDATA[62] VSS VSS LINETXCLK[5] VSS VSS VSS VDD33 VDD33 LINETXDATA[12] LINERXCLK[52] 32 -- VDD33 VDD33 VDD33 VDD33 CHITXDATA[14] CHITXDATA[18] LINETXCLK[39] LINETXDATA[38] LINETXDATA[36] LINETXDATA[33] LINERXDATA[77] LINERXDATA[76] LINERXCLK[75] CHIRXGFS LINERXCLK[73] CHIRXDATA[5] LINERXDATA[72] CHIRXDATA[7] CHIRXDATA[10] LINERXDATA[69] LINERXCLK[68] LINERXCLK[67] LINERXDATA[66] LINERXDATA[63] LINETXCLK[2] LINETXCLK[3] VSS VSS VDD33 VDD33 VDD33 VDD33 -- 34 Agere Systems Inc. NSMITXDATA[3] LINETXDATA[51] LINETXDATA[47] VDD33 VDD33 LINETXDATA[45] CHITXDATA[17] LINETXDATA[41] VDD33 VDD33 LINETXCLK[33] LINERXCLK[77] CHITXGFS VDD33 VDD33 CHIRXDATA[2] CHIRXDATA[4] LINERXCLK[71] LINERXCLK[70] VDD33 VDD33 CHIRXDATA[14] LINERXDATA[67] LINERXCLK[64] VDD33 VDD33 LINETXDATA[5] VSS VSS VDD33 VDD33 VDD33 VDD33 LINERXDATA[53] 33 Hardware Design Guide, Revision 5 July 13, 2004 Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 2.4 Pin Types Table 2-3 describes each type of input, output, and I/O pin used in the Ultraframer device. Table 2-3. Pin Types Type Label I Description LVCMOS Input, LVTTL Switching Thresholds. I pd LVCMOS Input, LVTTL Switching Thresholds with Internal 50 k Pull-Down Resistor. I pu LVCMOS Input, LVTTL Switching Thresholds with Internal 50 k Pull-Up Resistor. O O od LVCMOS Output. Open-Drain Output. LIN LVDS Inputs. I/O Bidirectional Pin. LVCMOS input with LVTTL switching thresholds and LVCMOS output. I/O pd Bidirectional Pin. LVCMOS input with LVTTL switching thresholds with internal 50 k pull-down resistor and LVCMOS output. -- Power, Ground, Analog Inputs for External Resistors, Capacitors, Voltage References, etc. NC No Connect. Agere Systems Inc. 19 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 2.5 Pin Definitions This section describes the function of each of the device pins. Pin functionality is descriptive information. The actual functionality is dependent upon the device configuration via the registers. Table 2-4. LVDS Framer Reference Clock Pin Symbol Type Name/Description AN4 THSCP LIN AP4 THSCN Framer High-Speed Clock. The clock on this pin is internally routed to the DS1/E1 framers and is used as an internal master clock. This input clock can be at 155 MHz or 622 MHz. Note there are no advantages in using a 622 MHz clock vs. a 155 MHz clock. AG9 CTAPTH -- Center Tap TH. LVDS buffer terminator center tap for THSCP/N. An optional 0.1 F capacitor, connected between CTAP pin and ground, will improve the common-mode rejection of the LVDS input buffers. AL5 RESHI -- AL6 RESLO Resistor. A 100 , 1% resistor is required between the RESHI and RESLO pins as a reference for the LVDS input buffer termination. AK6 REF10* I Reference 1.0 V. External 1 V reference voltage pin (optional). AJ6 REF14* I Reference 1.4 V. External 1.4 V reference voltage pin (optional). * Optional: selected by MPU/top-level register UMPR_LVDS_REF_SEL. External reference voltage can be sourced from a low-impedance resistor (<1 k) divider circuit decoupled with a 0.1 F capacitor. Table 2-5. DS3/E3 Out Pin Symbol Type Name/Description AH1, AA6, V2 DS3POSDATAOUT[3:1] O AJ1, AC4, AC3 DS3NEGDATAOUT[3:1] O AC5, AB8, AB5 DS3DATAOUTCLK[3:1] I pd DS3/E3 Positive Data Output. Either contains the positive-rail of the B3ZS/HDB3 encoded output data, or single-rail NRZ data. DS3/E3 Negative Data Output. Negative-rail B3ZS/HDB3 encoded output data. Not used in single-rail mode (held low in this case). DS3/E3 Data Output Clock. 44.736 MHz or 34.368 MHz clock input and is typically connected to a crystal oscillator or clocking chip. AB6, AD3, AD2 DS3RXCLKOUT[3:1] O This clock is required for M13 and E13 applications. DS3/E3 Receive Clock Output. 44.736 MHz DS3/34.368 MHz E3 clock out to external circuit. Table 2-6. DS3/E3 In Pin Symbol Type Name/Description AD1, AB2, W3 DS3POSDATAIN[3:1] I pd Y4, AC1, V1 DS3NEGDATAIN[3:1] I pd V3, V4, AB1 DS3DATAINCLK[3:1] I pd DS3/E3 Positive Data Input. Either contains the positive-rail of the B3ZS/HDB3 encoded input data, or single-rail NRZ data. DS3/E3 Negative Data Input. Either contains the negative-rail of the B3ZS/HDB3 encoded input data, or in single-rail mode, this input may be used to count bipolar violations. DS3/E3 Data Input Clock. 44.736 MHz or 34.368 MHz clock for the DS3/E3 positive and negative data inputs. 20 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 2-7. NSMI In Pin Symbol Type AN27, AP27, AM24 NSMIRXDATA[3:1] I pd Name/Description Network Serial Multiplex Interface (NSMI) Receive* Data. This is used in the following applications: 51.84 Mbits/s serial data input that is used to bring in multiplexed DS1 or E1 channels to the framer. DS3/E3 rate clear channel receive data to M13/E13. I/O pd NSMI Receive Clock. Used in the following applications: AG21, AK28, AJ22 NSMIRXCLK[3:1] Input (51.84 MHz) for the DS1/E1 application. Output (44.736/34.368 MHz) for the DS3/E3 application. I/O pd NSMI Receive Frame Sync. Used in the following applications: AP29, AL23, AL22 NSMIRXSYNC[3:1] Input receive NSMI control for the framer. Output receive control frame sync signal for M13/E13. NSMI Receive Data Enable. In FRM NSMI mode, this pin is not used. In M13 NSMI mode, the signal output on this pin goes low during the M1 byte of the first M1 frame of the DS3 frame. AL24, AK22, AK21 RXDATAEN[3:1] O In E13 NSMI mode, the signal output on this pin goes low during the overhead bytes and control bits of the E3 frame. * The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., NSMIRXDATA, on the transmit path, are labeled receive. Low-speed outputs, e.g., NSMITXDATA, on the receive path, are labeled transmit. Table 2-8. NSMI Out Pin Symbol AP33, AL25, NSMITXDATA[3:1] AN28 AN31, AP31, NSMITXCLK[3:1] AG23 AL27, AP32, NSMITXSYNC[3:1] AP30 AM29, TXDATAEN[3:1] AM28, AN29 Type Name/Description O NSMI Transmit Data. NSMI output data from the framer or the M13/E13 blocks. NSMI Transmit Clock Output. Output clock at 51.84 MHz for the DS1/E1 application or a 44.736/34.368 MHz output clock for the DS3/E3 application. Transmit System Frame Sync Output. Output transmit control frame sync signal from the framer or M13/E13 blocks. Transmit Data Enable for NSMI Mode. This output is used to request data for a particular link when the FRM NSMI is operating in nonloop timing mode. This output acts as a sync signal when the FRM NSMI operates in loop-timing mode. O O O In M13 NSMI mode, the signal output on this pin goes low during the M1 byte of the first M1 frame of the DS3 frame. In E13 NSMI mode, the signal output on this pin goes low during the overhead bytes and control bits of the E3 frame. * The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., NSMIRXDATA, on the transmit path, are labeled receive. Low-speed outputs, e.g., NSMITXDATA, on the receive path, are labeled transmit. Agere Systems Inc. 21 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 The transmit path is toward the high-speed fiber output, and the receive path is from the high-speed input. Low-speed inputs, e.g., LINERXDATA, on the transmit path, are labeled receive. Low-speed outputs, e.g., LINETXDATA, on the receive path, are labeled transmit. Table 2-9. Shared Low-Speed Line In Pin Symbol T1, W2, V9, AB3, AG1, AA8, AC6, AE6, AD8, LINERXDATA[86:1] AC34, AB34, W30, V31, V32, U34, U30, T32, P34, R27, M33, L34, M32, P30, K34, L32, N27, M29, L31, L29, G28, F28, E29, G27, A33, F25, A30, D25, H23, A26, D22, E21, A22, C18, H17, A17, D15, H15, C12, C11, F12, H10, F5, G6, H8, G5, H6, E6, A4, A5, F8, C6, B6, F10, A6, C7, F11, D8, A7, E11, B8, A8, A9, A11, H13, F13, E13, A13, F14, D13, E14, E15, H16, D16, B17, D17, E18 T2, U1, W4, AA4, Y8, AD4, AE4, AH2, AH3, AC33, Y30, AA34, W31, W34, V30, U33, T33, T27, N34, M34, P29, N31, L33, N30, M31, N29, M30, M27, L30, F29, E30, H26, D30, D29, A32, H24, A29, B28, F22, B24, D21, H20, D19, B18, E17, A16, D14, H14, A12, A10, F6, E5, H9, C1, F4, J9, F7, B4, G8, D6, E7, F9, E8, D7, E10, E9, B7, H11, C8, D9, H12, D10, E12, B11, D11, B12, D12, B13, C13, A14, A15, B16, C16, E16, C17, A18 22 Type Name/Description I pd Line Receive Data [86:1]. Inputs to the internal multirate crossconnect. These signals are used for received single-rail DS1/E1 line data input, sourced from an external LIU. In this mode, these signals will be routed via the crossconnect to the M13 multiplexer, E13 multiplexer, or the receive line inputs of the DS1/E1 framers. These signals may also be used as input data for DS2/E2 applications (see the System Design Guide). LINERXCLK[86:1] I/O pd Line Receive Clock [86:1]. Configurable inputs to the internal multirate crossconnect. These inputs are used for asynchronous clocks associated with the line receive data inputs from external line interface units, or payload termination functions. In certain cases, this input can be used as an output. These pins may be used for DS2/E2 clocks in DS2/E2 applications. More information will be published in the System Design Guide. Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., LINERXDATA, on the transmit path, are labeled receive. Low-speed outputs, e.g., LINETXDATA, on the receive path, are labeled transmit. Table 2-10. Shared Low-Speed Line Out Pin Symbol H5, E1, N8, H3, L4, M8, M3, L1, T8, N1, LINETXDATA[86:1] AJ3, AF6, AL2, AG6, AH5, AK4, AJ5, AK5, AG8, AL15, AP17, AK16, AK11, AN19, AL18, AM19, AG18, AM22, AN24, AP25, AP26, AP28, AK23, AK24, AK25, AN33, AM32, AJ29, AK30, AM33, AL31, AJ33, AE30, AC27, AE31, AG33, AC29, AC30, AF34, AB30, AE34, AC32, AA30, AD34, AB32, AA29, C22, B23, F21, E22, H22, D23, E23, B27, F23, E24, F24, D26, D27, E26, H25, E27, B31, E28, B32, H28, G29, J27, H29, H30, K27, H33, J31, K29, K30, L27 Type Name/Description O Line Transmit Data [86:1]. Outputs from the internal multirate crossconnect. These signals are used for transmit of single-rail DS1/E1 line data output, sourced to an external LIU. In this mode, these signals will be routed via the crossconnect from the M13 multiplexer, the E13 multiplexer, or the transmit line outputs of the DS1/E1 framers. Each of these outputs comes from the internal MRXC and can be individually set to high impedance. These pins may be used for output data in DS2/E2 applications (see the System Design Guide). H7, D1, F2, K8, G1, H1, P6, P5, N3, U3, LINETXCLK[86:1] I/O pd Line Transmit Clock [86:1]. Configurable outputs from the internal multirate crossconnect. These AF5, AG5, AH4, AJ4, AF9, AL3, AH6, outputs are used for asynchronous clocks, AL4, AK14, AN16, AK12, AJ12, AN18, associated with the line transmit data outputs to AH7, AJ25, AF17, AL19, AK19, AG25, external line interface units or payload termination AG24, AG20, AL30, AG22, AM27, functions. AL26, AL28, AM31, AH27, AH28, AK29, AJ28, AE27, AE29, AG32, AD30, AD29, Each of these outputs comes from the internal AD31, AG34, AB27, AC31, AD32, MRXC and can be individually set to high AB29, AB31, AD33, AA27, AA31, A23, impedance. H21, A24, C23, A25, C24, A27, A28, In certain cases, these pins can be used as inputs D24, C27, B29, C28, E25, A31, C29, (input DS2/E2 clocks). More information will be D28, F26, F27, J26, C31, H27, G30, published in the System Design Guide . G31, J29, H31, H32, J30, H34, J34, K31 Agere Systems Inc. 23 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., CHIRXDATA, on the transmit path are labeled receive. Low-speed outputs, e.g., CHITXDATA, on the receive path are labeled transmit. Table 2-11. TDM Concentration Highway (CHI) In Pin Symbol Type P27, N32, P31, R30, N33, R31, T30, T31, R34, U31, U32, T34, U27, V34, V33, V27, W33, W32 CHIRXDATA[18:1] I pd Name/Description CHI Receive Data [42:1]. Configurable synchronous TDM inputs to the internal multirate cross connect. Can be used in one of the following modes: CHI mode: Receive TDM input highways. Can be configured to operate at 8.192 Mbits/s or 16.384 Mbits/s. Parallel system bus mode: The parallel system bus is a 16-bit wide 19.44 Mbits/s synchronous TDM highway. Bits [16:9] are used for time-slot data. Bits [8:1] are used for robbed-bit signaling data in a ASM like fashion and are optional. CHIRXGFS is the frame synchronization input for the parallel system bus and CHIRXGCLK is the 19.44 MHz clock input. Asynchronous mode: In this mode, these inputs are used for DS1/E1 received negative-rail data. These pins may be used as input data for DS2/E2 applications. More information will be published in the System Design Guide. Table 2-12. TDM Concentration Highway (CHI) Out Pin AH34, AH33, AD27, AF31, AJ34, AF30, AG31, AF29, AH32, AJ32, AG29, AJ30, AH29, AG28, AL29, AK27, AN32, AK26 Symbol Type Name/Description CHITXDATA[18:1] I/O pd CHI Transmit Data [42:1]. Configurable synchronous TDM outputs from the internal multirate cross connect. Can be used in one of the following modes: CHI mode: Transmit TDM output highways. Can be configured to operate at 8.192 Mbits/s or 16.384 Mbits/s. Parallel system bus mode: The parallel system bus is a 16-bit wide 19.44 Mbits/s synchronous TDM highway. Bits [16:9] are used for time-slot data. Bits [8:1] are used for robbed-bit signaling data in a ASM like fashion and are optional. CHITXGFS is the frame synchronization input for the parallel system bus and CHITXGCLK is the 19.44 MHz clock input. Asynchronous mode: In this mode, these outputs are used for DS1/E1 transmit negative-rail data. Each of these outputs comes from the internal MRXC and can be individually set to high impedance. In rare cases, this output can be used as an input. These pins have various functionalities in DS2/E2 applications. More information will be published in the System Design Guide. When running in CHI compression mode, CHITXDATA[17] becomes a frame sync output from the device, which signifies the beginning of the CHI output frame. This feature is only available in V3.0 devices and later. 24 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 2-13. Framer (FRM) Block, CHI/Parallel System Bus (PSB) Clock and Sync Pin Symbol Type Name/Description Y31 CHIRXGTCLK I pd W27 CHIRXGCLK I pd Y34 CHIRXGFS I pd Global Transmit Line Clock. This is the transmit line clock for the DS1 or E1 framer. Normally this input is not used and the transmit clock is generated by an internal phase-lock loop which uses CLKIN_PLL as a reference. Note that if this input is used all the transmit framers must run at the same rate, either 1.544 MHz or 2.048 MHz. This signal could be used for both CHI and parallel system bus. Receive Global System Clock. This signal is used for both CHI and parallel system bus. In CHI mode, it is a 8.192 MHz or 16.384 MHz TDM clock. In parallel system bus mode, it is a 19.44 MHz clock. Receive System Frame Sync. This signal is used for both CHI and parallel system bus. In CHI mode, it is an 8 kHz pulse that references the location of time slots in the receive CHI inputs. Its polarity, sampling edge, and offset from time slots in the concentration highways may all be programmed. AB33 CHITXGFS I pd In parallel system bus mode, it is an 8 kHz reference for time slots within the parallel system bus input highways. In this mode, the frame strobe is a positive pulse with active edge provisioned by a register. Transmit System Frame Sync. This signal is used for both CHI and parallel system bus. In CHI mode, it is an 8 kHz pulse that references the location of time slots in the transmit CHI outputs. Its polarity, sampling edge, and offset from time slots in the concentration highways may all be programmed. In parallel system bus mode, it is an 8 kHz reference for time slots within the parallel system bus output highways. In this mode, the frame strobe is a positive pulse with active edge provisioned by a register. Y27 CHITXGCLK I pd For version 3.0 devices and later, CHITXGFS also serves as a required 8 kHz frame sync when operating in NSMI slip mode. Transmit Global System Clock. This signal is used for both CHI and parallel system bus. In CHI mode, it is a 8.192 MHz or 16.384 MHz TDM clock. In parallel system bus mode, it is a 19.44 MHz clock. Table 2-14. Reference Clocks Pin Symbol Type Name/Description V8 DS2AISCLK I pd AA1 E2AISCLK I pd AM18 E1XCLK I pd DS2 AIS Clock. See separate DS2/E2 application note for use in DS2 mode. If used, this input can be provided by a free-running crystal or clocking chip. E2 AIS Clock. See separate DS2/E2 application note for use in E2 mode. If used, this input can be provided by a free-running crystal or clocking chip. E1 X Clock. This clock signal is used for three purposes: to generate E1 AIS (all 1s), as a reference to the E1 DJA, and as a clock source for the test pattern generator and test pattern monitor. This input may be provided by a 2.048 MHz, a 32.768 MHz, or a 65.536 MHz 50 ppm free-running crystal oscillator or clocking chip. AP21 DS1XCLK I pd Note: For the E1 DJA, an input of 32.768 MHz or 65.536 MHz must be used. DS1 X Clock. This clock signal is used for three purposes: to generate DS1 AIS (all 1s), as a reference to the DS1 DJA, and as a clock source for the test pattern generator and test pattern monitor. This input may be provided by a 1.544 MHz, a 24.704 MHz, or a 49.408 MHz 32 ppm free-running crystal oscillator or clocking chip. Note: For the DS1 DJA, an input of 24.704 MHz or 49.408 MHz must be used. Agere Systems Inc. 25 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 Table 2-15. Clock Generator 26 Pin Symbol Type Name/Description AF27 CLKIN_PLL I pd AF26 CG_PLLCLKOUT O AK31, AG30, AJ31 MODE[2:0]_PLL I pd Transmit Line Clock Generator Reference Input. The clock generator is used to derive a transmit line clock of the appropriate frequency (DS1/E1) synchronized to CLKIN_PLL. The derived clock is used in the DS1/E1 transmit framer sections. Framer PLL Test Mode Output. Framer PLL clock (1.544 MHz, 2.048 MHz) selected by the device register. Framer PLL Input Clock Mode Select Bits. The settings of these mode select pins must correspond to the frequency of CLKIN_PLL as shown below. MODE[2:0]_PLL CLKIN_PLL MODE[2:0]_PLL CLKIN_PLL 000 001 010 011 Reserved 51.840 MHz 26.624 MHz 19.440 MHz 100 101 110 111 16.384 MHz 8.192 MHz 4.096 MHz 2.048 MHz Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 2-16. Microprocessor Interface Pin Symbol Type G4 MPCLK I D2 MPMODE G7 CSN F3 ADSN J6 J5 RWN DSN N5, P8, M4, L3, J1, N6, M5, L8, K4, M6, H2, L5, L6, G2, F1, K5, J4, J8, G3, H4, K6 ADDR[20:0] P1, U9, T4, R4, N2, P4, U5, R5, M1, T5, M2, R8, N4, U2, L2, K1 U4, R1 DATA[15:0] I/O PAR[1:0] I/O T3 DTN U8 W1 HP_INTN LP_INTN Agere Systems Inc. Name/Description Microprocessor Clock. This clock is required to properly sample address, data, and control signals from the microprocessor in both asynchronous and synchronous modes of operation. I Microprocessor Mode. If the microprocessor interface is synchronous, MPMODE should be set to 1. If the microprocessor interface is asynchronous, MPMODE should be set to 0. I pu Chip Select. Active-low high-order address signal. Chip select must be set low at the beginning of any read or write access and returned high at the end of the cycle. I Address Strobe. Active-low address strobe that indicates the beginning of a read or write access. It is a one MPCLK cycle-wide pulse for synchronous mode. In asynchronous mode, it is active for the entire read/write cycle. Address bus signals, ADDR[20:0], are available to the Ultraframer when ADSN is low. The address bus should remain valid for the duration of ADSN. I Read/Write. RWN is set high during a read cycle, or set low during a write cycle. I Data Strobe. For a read cycle, the contents of the internal register will be output on DATA [15:0]. For a write cycle, the DATA [15:0] will be clocked into the internal register. To initiate the start of the read/write operation, DSN must be low during the entire read/write cycle. This signal should only be used for asynchronous mode. I Address [20:0]. ADDR[20] is the MSB and ADDR[0] is the LSB for addressing all the internal registers during microprocessor access cycles. All addresses are 21-bit word addresses; therefore, in a typical application, ADDR[0] of the TFRA84J13 device would be connected to address bit 1 of a byte-addressable system address bus. Note: The Ultraframer is little endian, i.e., the least significant byte is stored in the lowest address and the most significant byte is stored in the highest address. Care must be exercised in connection with microprocessors that use big endian byte ordering. Data [15:0]. 16-bit data bus input for write operations and output for read operations. DATA[15] is the MSB, and DATA[0] is the LSB. Data Parity. Byte-wide parity bits for data. PAR[1] is the parity for DATA[15:8], and PAR[0] is the parity for DATA[7:0] O Data Transfer Acknowledge. The delay associated with DTN going low depends on the Ultraframer block being accessed. In asynchronous mode, when ADSN or DSN is deasserted it will drive the DTN signal high. When inactive, CSN will drive DTN to be 3-stated. The microprocessor should wait after DTN is deasserted, before starting the next operation. O od High-Priority and Low-Priority Interrupt. Active-low. Each functional block contains its individual low-priority interrupt. High-priority interrupts are generated by E13 blocks. Each interrupt is individually maskable. Requires an external 5 k pullup resistor. 27 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 Table 2-17. Boundary Scan (IEEE(R) 1149.1) Pin Symbol Type Name/Description AN22 AP23 TCK TDI I I pu AN23 TMS I pu AG26 TRST I pu AJ21 TDO O Test Clock. This signal provides timing for boundary-scan test operations. Test Data In. Boundary-scan test data input signal, sampled on the rising edge of TCK. Test Mode Select. Controls boundary-scan test operations. TMS is sampled on the rising edge of TCK. Test Reset (Active-Low). This signal provides an asynchronous reset for the boundary-scan TAP controller. Test Data Out. Boundary-scan test data output signal is updated on the falling edge of TCK. The TDO output will be high-impedance, except when transmitting test data. Table 2-18. General-Purpose Interface Pin Symbol Type AK18 RSTN I pu AJ24 PMRST AL20 IC3STATEN AP24 AM23 AJ23 AK20 AL21 SCK1 SCK2 SCAN_EN SCANMODE IDDQ Name/Description Global Hardware Reset. Active-low. Initializes all internal registers to their default state. This is an asynchronous reset on the falling edge, but RSTN should be held low for at least 1 s. RSTN should be held low until both power supplies (1.5 V and 3.3 V) are stabilized upon power up. I/O pd Performance Monitor Reset. Resets error counters. When enabled as an input, it is a 1s square wave that forces an update of PM counters upon the rising edge. When the PMRST is generated internally from the MPU clock, this pin is an output. I pu Output Enable. When high, output buffers will operate normally. When low, all outputs will be forced to a high-impedance state. IC3STATEN should be held low until both power supplies (1.5 V and 3.3 V) are stabilized upon power up. I pd Scan Clock 1. Reserved. Do not connect. I pd Scan Clock 2. Reserved. Do not connect. I pd Scan Enable. Reserved. Do not connect. I pd Serial Scan Input for Testing. Reserved. Do not connect. I IDDQ Input. This pin must be externally pulled down with a 1 k resistor. Table 2-19. Analog Power and Ground Signals 28 Pin Symbol Type Name/Description AH31 AH30 VSSA_SFPLL VDD33A_SFPLL -- -- SFPLL Ground. Isolated ground for the internal SFPLL. SFPLL Power. This is a 3.3 V power supply for the internal SFPLL. Good engineering practice needs to be applied. Please refer to the System Design Guide. Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 2-20. Digital Power and Ground Signals Pin Symbol Type Name/Description J10, J13, J14, J17, J18, J21, J22, J25, K9, K17, K18, K26, N9, N13, N14, N15, N16, N17, N18, N19, N20, N21, N22, N26, P9, P13, P22, P26, R13, R22, T13, T22, U10, U13, U22, U25, U26, V10, V13, V22, V25, V26, W13, W22, Y13, Y22, AA9, AA13, AA22, AA26, AB9, AB13, AB14, AB15, AB16, AB17, AB18, AB19, AB20, AB21, AB22, AB26, AE9, AE17, AE18, AE26, AF10, AF13, AF14, AF18, AF21, AF22, AF25, AH26, AJ26, AJ27 A2, A3, B1, B3, B5, B9, B10, B14, B15, B20, B21, B25, B26, B30, B33, B34, C2, C4, C32, C33, C34, D3, D5, D32, D33, D34, E2, E4, E33, E34, J2, J11, J12, J15, J16, J19, J20, J23, J24, J33, K2, K33, L9, L26, M9, M26, P2, P33, R2, R9, R26, R33, T9, T26, W9, W26, Y2, Y9, Y26, Y33, AA2, AA33, AC9, AC26, AD9, AD26, AE2, AE33, AF2, AF11, AF12, AF15, AF16, AF19, AF20, AF23, AF24, AF33, AK2, AK33, AK34, AL33, AL34, AM34, AN14, AN15, AN20, AN21, AN25, AN26, AN30, AN34 B2, C3, C5, C9, C10, C14, C15, C20, C21, C25, C26, C30, D4, D31, E3, E31, E32, F30, F31, F32, F33, F34, G32, G33, G34, J3, J32, K3, K32, P3, P14, P15, P16, P17, P18, P19, P20, P21, P32, R3, R14, R15, R16, R17, R18, R19, R20, R21, R32, T14, T15, T16, T17, T18, T19, T20, T21, U14, U15, U16, U17, U18, U19, U20, U21, V14, V15, V16, V17, V18, V19, V20, V21, W14, W15, W16, W17, W18, W19, W20, W21, Y3, Y14, Y15, Y16, Y17, Y18, Y19, Y20, Y21, Y32, AA3, AA14, AA15, AA16, AA17, AA18, AA19, AA20, AA21, AA32, AE3, AE32, AF3, AF32, AG16, AG19, AJ7, AJ8, AJ9, AJ10, AJ11, AK3, AK7, AK8, AK9, AK10, AK32, AL7, AL8, AL9, AL10, AL32, AM4, AM14, AM15, AM20, AM21, AM25, AM26, AM30, AN3, AN5, AN7, AP3, AP5, AP7 VDD15 -- Common power signals for 1.5 V VDD. VDD33 -- Common power signals for 3.3 V VDD. VSS -- Common ground signals. Symbol Type Table 2-21. No Connects Pin Y1, AM13, AF8, AG10, AG14, AE1, AF1, AB4, AD5, AE5, No Connect AG4, AC2, Y5, AA5, AL1, AG3, AJ2, V5, W8, W5, AK1, AG2, AF4, AC8, AD6, AE8, H18, AL14, AP15, AP16, B22, A21, D20, H19, E20, A20, AG27, AN1, AM1, AM3, AM2, AP22, AJ14, AN10, AM10, AP12, AP10, AM9, AP11, AM17, AG17, AP19, AM8, AM7, AP6, AN6, AM16, AK15, AN17, AP2, AN2, AM6, AM5, AL13, AK13, AM11, AN13, AP14, AN11, AN12, AP13, AL17, AK17, AP20, AP8, AN8, AN9, AP9, AJ13, AG15, AG7, AH8, AL16, AP18, AG12, AL11, C19, B19, AM12, AG11, AG13, D18, A19, AL12, E19 Agere Systems Inc. Name/Description NC No Connects. These pins are not used in the Ultraframer device. 29 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 3 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 3-1. Absolute Maximum Ratings Parameter Supply Voltage (VDD33) Supply Voltage (VDD15) Input Voltage: LVCMOS LVDS Power Dissipation Storage Temperature Range Min -0.5 -0.3 Max 4.2 2.0 Unit V V -0.3 -0.3 -- -65 5.25 VDD33 + 0.3 -- 125 V V mW C 3.1 Handling Precautions Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114 (HBM) and JESD22-C101 (CDM) standards. Table 3-2. ESD Tolerance Device TFRA84J13 Minimum Threshold HBM 2000 V CDM 500 V 3.2 Thermal Parameters (Definitions and Values) System and circuit board level performance depends not only on device electrical characteristics, but also on device thermal characteristics. The thermal characteristics frequently determine the limits of circuit board or system performance, and they can be a major cost adder or cost avoidance factor. When the die temperature is kept below 125 C, temperature-activated failure mechanisms are minimized. The thermal parameters that Agere provides for its packages help the chip and system designer choose the best package for their applications, including allowing the system designer to thermally design and integrate their systems. It should be noted that all the parameters listed below are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. JA - Junction to Air Thermal Resistance JA is a number used to express the thermal performance of a part under JEDEC standard natural convection conditions. JA is calculated using the following formula: JA = (TJ - Tamb) / P; where P = power 30 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 JMA - Junction to Moving Air Thermal Resistance JMA is effectively identical to JA but represents performance of a part mounted on a JEDEC four layer board inside a wind tunnel with forced air convection. JMA is reported at airflows of 200 LFPM and 500 LFPM (linear feet per minute), which roughly correspond to 1 m/s and 2.5 m/s (respectively). JMA is calculated using the following formula: JMA = (TJ - Tamb) / P JC - Junction to Case Thermal Resistance JC is the thermal resistance from junction to the top of the case. This number is determined by forcing nearly 100% of the heat generated in the die out the top of the package by lowering the top case temperature. This is done by placing the top of the package in contact with a copper slug kept at room temperature using a liquid refrigeration unit. JC is calculated using the following formula: JC = (TJ - TC) / P JB - Junction to Board Thermal Resistance JB is the thermal resistance from junction to board. This number is determined by forcing the heat generated in the die out of the package through the leads or balls by lowering the board temperature and insulating the package top. This is done using a special fixture, which keeps the board in contact with a water chilled copper slug around the perimeter of the package while insulating the package top. JB is calculated using the following formula: JB = (TJ - TB) / P JT JT correlates the junction temperature to the case temperature. It is generally used by the customer to infer the junction temperature while the part is operating in their system. It is not considered a true thermal resistance. JT is calculated using the following formula: JT = (TJ - TC) / P Table 3-3. Thermal Parameter Values Parameter Temperature C/Watt JA 12.8 JMA (1 m/s) 9.5 JMA (2.5 m/s) 8 JC 2.5 JB 7.6 JT 1 3.3 Reliability Product reliability can be calculated as the probability that the product will perform under normal operating conditions for a set period of time. Factors influencing the reliability of a product cover a range of variables, including design and manufacturing. The failure rate of a product is given as the number of units failing per unit time. This failure rate is known as FIT, which is as follows: 1 FIT = 1 failure/1 x 109 hours. Another unit used for failure rate is known as MTBF, which is 1/FIT. Many assumptions are made when calculating the failure rate for a product, such as the average junction temperature and activation energy. The assumptions made for calculating FIT and MTBF are shown in Table 3-4: Table 3-4. Reliability Data Junction Temperature 55 C Agere Systems Inc. FIT (Per 1 x 109 Device Hours) MTBF Activation Energy 36 107 0.7eV 2.78 x hours 31 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 4 Electrical Characteristics 4.1 Recommended Operating Voltages The following table lists the voltages, along with the tolerances, required for proper operation of the TFRA84J13 device. Table 4-1. Recommended Operating Conditions Parameter 3.3 V Power Supply 1.5 V Power Supply Ground 1.0 V--LVDS Reference* 1.4 V--LVDS Reference* Ambient Temperature Symbol Min Typ Max Unit VDD33 VDD15 VSS REF10 REF14 TA 3.14 1.4 -- -- -- -40 3.3 1.5 0.0 1.0 1.4 -- 3.47 1.6 -- -- -- 85 V V V V V C * Internal reference voltage is used if UMPR_LVDS_REF_SEL = 1, or else external voltage is used. 4.2 Recommended Powerup Sequence The Ultraframer device requires dual power supplies, a 3.3 V supply for the I/O and a 1.5 V supply for the core. During power up, RSTN should be held low (holding the device in reset) and IC3STATEN should be held low (3-stating all output buffers). After the 3.3 V and 1.5 V supplies are stable, MPCLK (which affects the device reset) should be applied and must be present for at least two clock cycles before RSTN and IC3STATEN are released. It is then recommended that IC3STATEN be released concurrent with, or after, the release of RSTN. There are no constraints as to which supply (3.3 V or 1.5 V) must come up first, nor does it matter how long it takes the second supply to come up after the first supply. 4.3 Power Consumption The power consumption of the device is application dependent since it is not possible to use all the device features simultaneously. The nominal measured values for power per block are shown in Table 4-2. Table 4-2. Typical Power Consumption Per Block Typical power by block refers to all instances being used. Block E13 M13 TPG/TPM FRM DS1DJA MPU LVDS I/O NSMI I/O DS3 I/O MRXC Maximum Instance Typical, Per Single Instance Unit 3 3 1 3 3 1 2 3 3 1 0.013 0.013 TBD 0.195 0.026 0.420* 0.020 0.032 0.050 0.050 W W W W W W W W W W * Measured with a 50 MHz MPCLK. With a 25 MHz MPCLK, the typical per single instance value of MPU power is approximately 0.2 W. Testing has shown that, on the average, approximately 0.35 W can be saved by utilizing the divide by 16 MPU clock power down feature. Please refer to MPU register 0x0019 in the UltramapperTM Register Description document for further information. Additional MPU clock divisor options are available. 32 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 4.4 ac and dc Characteristics 4.4.1 LVCMOS Interface Characteristics Table 4-3. LVCMOS Inputs Specifications Parameter Input Leakage Current High-input Voltage Low-input Voltage Input Capacitance Symbol Conditions Min Typ Max Unit II VIH VIL CI VSS < VIN < VDD33 -- -- -- -- 2.0 VSS -- -- -- -- -- 1.0* -- 0.8 1.5 A V V pF * Excludes current due to pull-up or pull-down resistors. Table 4-4. LVCMOS Outputs Specifications Parameter Symbol Conditions Min Typ Max Unit Output Voltage Low Output Voltage High Output Current Low Output Current High Output Capacitance HIZ Output Leakage Current VOL VOH IOL IOH CO IOZ IOL = max IOL = max -- -- -- -- VSS VDD - 0.5 -- -- -- -- -- -- -- -- 3 -- 0.5 VDD 6* -6* -- 10 V V mA mA pF A * DTN output current is 10 mA max. Table 4-5. LVCMOS Bidirectionals Specifications Parameter Leakage Current Symbol Conditions Min Typ Max Unit IL VSS < VIN < VDD33 -- -- 11 A High-input Voltage VIH -- 2.0 -- VDD33 + 0.3 V Low-input Voltage VIL -- VSS -- 0.8 V Biput Capacitance CIB -- -- 5.0 -- pF Output Voltage Low VOL IOL = -6 mA* -- -- 0.5 V Output Voltage High VOH IOH = 6 mA* 2.4 -- -- V * The following bidirectional pins can sink/source 10 mA: NSMIRXCLK[3:1]. 4.4.2 LVDS Interface Characteristics 3.3 V 5% VDD, -40 C to +125 C junction temperature. . Table 4-6. LVDS Interface dc Characteristics Parameter Symbol Input Voltage Range High (VIA or VIB) Low (VIA or VIB) Input Differential Threshold Input Differential Hysteresis Receiver Differential Input Impedance VI VIH VIL VIDTH VHYST RIN Test Conditions Min Typ Max Unit -- 0 dc-- 450 MHz -100 (+VIDTH) - (-VIDTH) -- With build-in termination, center-tapped 80 -- -- -- -- 100 2.4 -- 100 * 120 V V mV mV Input Buffer Parameters |VGPD| < 925 mV, dc--1 MHz * The buffer will not produce output transitions when input is open-circuited. When the true and complement inputs are floating, the input buffer will not oscillate. Agere Systems Inc. 33 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 5 Timing 5.1 DS3/E3 Timing Figure 5-1 shows a simplified representation of the DS3/E3 I/O. M13/E13 BLOCK DEMUX MUX DS3RXCLKOUT Q CLK CLK D D Q DS3DATAINCLK DS3POSDATAOUT DS3POSDATAIN DS3NEGDATAOUT DS3DATAOUTCLK DS3NEGDATAIN Figure 5-1. DS3/E3 Interface Diagram in M13/E13 Block Table 5-1. DS3/E3 Input Specifications Name DS3POSDATAIN[3:1] DS3NEGDATAIN[3:1] Reference DS3DATAINCLK Edge Rising/Falling R/F Max Rise Time (ns) 5 Max Fall Time (ns) 5 Min Setup (ns) 3 Min Hold (ns) 3 Table 5-2. DS3/E3 Output Specifications Name DS3POSDATAOUT[3:1] DS3NEGDATAOUT[3:1] 34 Reference DS3RXCLKOUT Edge Rising/Falling R/F Propagation Delay Min (ns) Max (ns) 0 3 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 5.2 NSMI Timing 4760 bits DS3 frame (for info only) X2 X1 M1 M3 X1 NSMI_TXCLK 44.736 MHz NSMI_TXDATAEN NSMI_TXDATA NSMI_TXSYNC Position of this pulse is provisionable 0-256 bits before M1 4760 bits DS3 Frame X2 X1 M1 M3 X1 NSMI_RXCLK 44.736 MHz Output NSMI_RXDATAEN NSMI_RXDATA NSMI_RXSYNC Position of this pulse is provisionable 0-256 bits before M1 Notes: Clock from M13 is at 44.736 MHz rate and is not gapped. TXDATAEN is provided to mark the DS3 frame overhead times. M1 can occur asynchronously and its position is optionally marked by TXSYNC, which is provisioned to be 0 to 255 bits before the M1 bit. TXDATAEN goes low during DS3 frame overhead bits. Figure 5-2. NSMI Clock and Data Diagram for M13 NSMI Mode (NSMI <---> M13 <---> DS3 External I/O) 1536 bits E3 frame (for info only) C11 = 0 FRAME, RAI, RSVD Cj3 = 0 Stuff = data Frame NSMI_TXCLK (34.368 MHz output) NSMI_TXDATAEN (output) NSMI_TXDATA (output) NSMI_TXSYNC (output) Position of this pulse is provisionable 0-256 bits before C11 1536 bits E3 Frame (For Info only) FRAME, RAI, RSVD C11 = 0 Cj3 = 0 Stuff = data Frame NSMI_RXCLK (34.368 MHz output) NSMI_RXDATAEN (output) NSMI_RXDATA (input) NSMI_RXSYNC (output) Position of this pulse is provisionable 0-256 bits before C11 Notes: Clock from E13 is at 34.368 MHz rate and is not gapped. TXDATAEN is provided to mark the overhead time and control bits time of the E3 frame. C11's (the first C bit of the first tributary) position is optionally marked by TXSYNC, which is provisioned to be 0 to 255 bits before C11 (bit 385 of the E3 frame). During periods where the OH is present the TXDATAEN signal goes low. All C bits are zero and the stuff bits are used for data. Figure 5-3. NSMI Clock and Data Diagram for E13 NSMI Mode 1 (NSMI <---> E13 <---> E3 External I/O) Agere Systems Inc. 35 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 NSMI_TXCLK Data Byte (Timeslot) for a DS0/E0 Link NSMI_TXDATA NSMI_TXSYNC MSB LSB START FSYNC LSB MSB RSVD Link number[0:4] NSMI_TXCLK 51.84 MHz NSMI_TXDATA DATA Link#, Byte# DATA 1, 1 DATA 2, 1 DATA 1, 2 DATA 2, 2 DATA 5, 1 DATA 5, 2 DATA 5, 3 NSMI_TXSYNC 01100000 01010000 } Binary Value 00100000 00010000 01101000 Link number provisionable 1:28 or 0:27 for DS1 FSYNC high signifies 1st byte of link N Start goes low to signify data, high otherwise Links may appear in any order, bytes per link are sequential Note: The 193rd bit of a DS1 frame is not transmitted on the NSMI but is used to locate the FSYNC position. As a consequence of this, signaling bits are not transported in Ultraframer. Figure 5-4. NSMI Clock and Data Diagram for Framer (FRM) NSMI Mode Table 5-3. NSMI Input Specifications Name NSMIRXDATA[3:1] NSMIRXSYNC[3:1] Reference NSMIRXCLK NSMIRXCLK Edge Rising/Falling R R Max Rise Time (ns) 3.5 3.5 Max Fall Time (ns) 3.5 3.5 Min Setup (ns) 5 5 Min Hold (ns) 0 0 Table 5-4. NSMI Output Specifications Name NSMITXDATA[3:1] NSMITXSYNC[3:1] RXDATAEN[3:1] TXDATAEN[3:1] NSMIRXSYNC[3:1] 36 Reference NSMITXCLK NSMITXCLK NSMIRXCLK NSMITXCLK NSMIRXCLK Edge Rising/Falling Propagation Delay Min (ns) Max (ns) R R R R R 0.5 0.5 0.5 0.5 0.5 8.75 8.75 8.75 8.75 8.75 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 5.3 Shared Low-Speed Line Timing LINERXCLK LINETXCLK tSU tH LINERXDATA tPD LINETXDATA Note: Single-rail shown. Figure 5-5. Shared Low-Speed Line Clock and Data Timing Table 5-5. Shared Low-Speed Line Timing Input Specifications Name Reference LINERXDATA[86:1] Edge Rising/Falling R/F LINERXCLK[86:1] Max Rise Time (ns) 10* Max Fall Time (ns) 10* Min Setup Min Hold (ns) (ns) 15 10* * Alternative spec: the maximum rise and fall times may be increased to 20 ns each if the minimum hold time is increased to 12 ns. The minimum setup time will remain at 15 ns. Table 5-6. Shared Low-Speed Line Timing Output Specifications Name LINETXDATA[86:1] Reference Edge Rising/Falling LINETXCLK[86:1] R/F Propagation Delay Min (ns) Max (ns) -10 10 5.4 CHI Timing t2 t3 t1 VDD33 VIH VIH 50% VIL VIL t4 Figure 5-6. CHI Clock Timing Table 5-7. CHIRXGCLK and CHITXGCLK Timing Specifications Parameter Description Min Typ Max Unit -- 2 7 ns t1 Rise Time t2 Width (8.192 MHz)* 48.84 -- 73.24 ns t2 Width (16.384 MHz)* 24.42 -- 36.62 ns t3 Fall Time -- 2 7 ns t4 Period (8.192 MHz) -- 122.07 -- ns t4 Period (16.384 MHz) -- 61.03 -- ns * VIH to VIH or VIL to VIL. Agere Systems Inc. 37 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 CHIRXGFS CHITXGFS t5 t6 t7 t8 Hardware Design Guide, Revision 5 July 13, 2004 CHIRXGCLK CHITXGCLK CHIRXDATA t9 CHITXDATA Note: This figure assumes TFRA84J13 is programmed to sample the frame sync signal on rising edge of the bit clock. Figure 5-7. CHI Bus Timing Table 5-8. CHI Interface Timing Specifications Parameter Description Min Max Unit t5 Frame Sync Setup Time to Active CHI Clock Edge 15 -- ns t6 Frame Sync Hold Time from Active CHI Clock Edge 4 -- ns t7 CHIRXDATA Setup to Active CHI Clock Edge 15 -- ns t8 CHIRXDATA Hold Time from Active CHI Clock Edge 4 -- ns t9 CHITXDATA Propagation Delay from Active CHI Clock Edge 4 30 ns CHIRXGFS CHIRXGCLK w/ 0 offset w/ 1/2 bit offset w/ bit offset = 1 TS0 B0 TS0 B1 data sampled TS0 B2 TS0 B0 TS0 B1 data sampled TS0 B0 data sampled w/ bit offset = 7 TS0 B3 TS0 B2 TS0 B1 TS0 B4 TS0 B3 TS0 B2 TS0 B5 TS0 B4 TS0 B3 TS0 B5 TS0 B4 TS0 B 0 TS0 B1 data sampled w/ TS offset = 1, bit offset = 0 TS0 B0 data sampled Note: For this timing diagram, it is assumed that the frame sync signal has been programmed to be active-high, and to be sampled by the rising edge of the bit clock. Figure 5-8. Typical Receive CHI Timing (Non-CMS Mode--FRM_CMS = 0) 38 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 CHIRXGFS CHIRXGCLK w/ 0 offset TS0 B0 w/ 1/2 bit offset TS0 B1 TS0 B0 w/ bit offset = 1 w/ TS offset = 1, bit offset = 0 TS255 B0 w/ TS offset = 255, bit offset = 71/2 TS0 B0 TS0 B2 TS0 B1 TS0 B3 TS0 B2 TS0 B4 TS0 B3 TS0 B5 TS0 B4 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 TS255 B1 TS255 B2 TS255 B3 TS255 B4 TS255 B5 TS0 B1 TS0 B2 TS0 B3 TS0 B4 TS0 B5 Note: For this timing diagram, it is assumed that the frame sync signal has been programmed to be active-high, and to be sampled by the rising edge of the bit clock. Figure 5-9. Transmit CHI Timing (Non-CMS Mode--FRM_CMS = 0) CHIRXGFS CHIRXGCLK w/ 0 offset TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled TSn B7 w/ 1/4 bit offset TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled TSn B7 w/ 1/2 bit offset TS0 B0 TS0 B1 TS0 B2 TS0 B3 data sampled w/ 3/4 bit offset TSn B6 TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 data sampled w/ bit offset = 1 TSn B6 TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 data sampled w/ 23/4 bit offset TSn B4 TSn B5 TSn B6 TS0 B0 TSn B7 TS0 B1 data sampled w/ bit offset = 7 TSn B0 TSn B1 TSn B2 TSn B3 TSn B4 TSn B5 TSn B1 TSn B2 TSn B3 TSn B4 data sampled w/ TS offset = 1, bit offset = 0 TSn - 1 B7 data sampled w/ TS offset = 13, bit offset = 31/4 w/ TS offset = 127, bit offset = 73/4 TSn B0 TSn - 13 B4 TSn - 13 B5 TSn - 13 B6 TSn - 13 B7 TSn - 12 B0 TSn - 12 B1 data sampled TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 TS0 B4 data sampled Notes: n = 127 at 16 MHz, n = 63 at 8 MHz. For this timing diagram, it is assumed that the frame sync signal has been programmed to be active-high, and to be sampled by the rising edge of the bit clock. Figure 5-10. Typical Receive CHI Timing (CMS Mode--FRM_CMS = 1) Agere Systems Inc. 39 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 CHIRXGFS CHIRXGCLK w/ 0 offset w/ 1/4 bit offset TSn B6 TSn B7 TSn B6 w/ 1/2 bit offset TS0 B0 TSn B7 TSn B6 TS0 B1 TS0 B0 TSn B7 TS0 B2 TS0 B1 TS0 B0 TS0 B3 TS0 B3 TS0 B2 TS0 B1 TS0 B2 TS0 B3 w/ bit offset = 1 TSn B5 TSn B6 TSn B7 TS0 B0 TS0 B1 TS0 B2 w/ TS offset = 1, bit offset = 0 TSn - 1 B6 TSn - 1 B7 TSn B0 TSn B1 TSn B2 TSn B3 w/ TS offset = 127, bit offset = 73/4 TSn B7 TS0 B0 TS0 B1 TS0 B2 TS0 B3 Note: For this timing diagram, it is assumed that the frame sync signal has been programmed to be active-high, and to be sampled by the rising edge of the bit clock. Figure 5-11. Transmit CHI Timing (CMS Mode--FRM_CMS = 1) 40 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 5.5 Parallel System Bus (PSB) Timing CHIRXGCLK CHITXGCLK CHIRXGFS CHITXGFS 10 ns tSU 0 ns tH CHIRXDATA tPD CHITXDATA Figure 5-12. PSB Clock and Data Timing Table 5-9. PSB Input Specifications Name Reference CHIRXDATA[16:1] (PSB mode) CHIRXGCLK CHIRXGFS (PSB mode) CHIRXGCLK CHITXGFS (PSB mode) CHITXGCLK Edge Rising/Falling R/F R/F R/F Max Rise Time (ns) 10 10 10 Max Fall Time (ns) 10 10 10 Min Setup (ns) 10 10 10 Min Hold (ns) 0 0 0 Table 5-10. PSB Output Specifications Name Reference CHITXDATA[16:1] (PSB mode) CHITXGCLK Agere Systems Inc. Edge Rising (R) Falling (F) R/F Propagation Delay Min (ns) Max (ns) 4 22 41 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 6 Reference Clocks Duty cycles indicated in the following tables should be interpreted as follows: 50% 10% means 45%--55%; 50% 5% means 47.5%--52.5%. Table 6-1. Framer Input Clocks Specifications Clock Name THSCP/N THSCP/N Period Frequency Accuracy (ns) (ppm) 6.43 155.52 MHz 20 1.6 622.08 MHz 20 Jitter Rise Fall Min/ Duty Cycle (ns) (ns) Max 0.4 0.4 Nom 50% 5% 0.01 UIp-p or 64 psp-p or 0.001 UIrms (12 KHz--1.3 MHz) 0.4 0.6 0.04 UIp-p or 64 psp-p 12 KHz--5 MHz nom max -- 50% 5% Table 6-2. DS3/E3 Input Clocks Specifications Clock Name Period Frequency Accuracy Jitter (ns) (ppm) DS3DATAOUTCLK[3:1] (DS3) 22.353 44.736 MHz 20 0.05 UIp-p or 1.12 nsp-p (10 kHz--400 kHz) DS3DATAINCLK[3:1] (DS3) 22.353 44.736 MHz 20 -- DS3DATAOUTCLK[3:1] (E3) 29.09 34.368 MHz 20 0.03 UIp-p or 0.87 nsp-p (100 kHz--800 kHz) DS3DATAINCLK[3:1] (E3) 29.09 34.368 MHz 20 -- Rise Fall Min/ Duty Cycle (ns) (ns) Max 5 5 Max 50% 10% 3.5 5 2.5 5 Max 50% 5% Max 50% 10% 3.5 2.5 Max 50% 5% Table 6-3. DS1/E1 DJA Input Clocks Specifications Clock Name E1XCLK DS1XCLK E1XCLK DS1XCLK Period Frequency Accuracy Jitter (ns) (ppm) 15.25 65.536 MHz 50 0.1 UIp-p or 1.5 nsp-p (20 kHz--100 kHz) 20.20 49.408 MHz 32 0.1 UIp-p or 2.0 nsp-p (10 kHz--40 kHz) 30.52 32.768 MHz 50 0.1 UIp-p or 3.0 nsp-p (20 kHz--100 kHz) 40.40 24.704 MHz 32 0.1 UIp-p or 4.0 nsp-p (10 kHz--40 kHz) Rise Fall Min/ Duty Cycle (ns) (ns) Max 3.5 3.5 Max 50% 10% 3.5 3.5 Max 50% 10% 3.5 3.5 Max 50% 10% 3.5 3.5 Max 50% 10% Table 6-4. M13/E13 Input Clocks Specifications Clock Name DS2AISCLK E2AISCLK Period Frequency (ns) 158.42 6.312 MHz 118.37 8.448 MHz Accuracy (ppm) 30 30 Jitter -- -- Rise Fall Min/ Duty Cycle (ns) (ns) Max 5 5 Max 50% 5% 5 5 Max 50% 5% Table 6-5. Microprocessor Interface Input Clocks Specifications Clock Name MPCLK (min)* MPCLK (max) Period Frequency (ns) 62.5 15.15 16 MHz 66 MHz Accuracy (ppm) Jitter -- -- -- -- Rise Fall Min/ Duty Cycle (ns) (ns) Max 4 4 4 4 Min Max 50% 10% 50% 10% * The following applies to the synchronous microprocessor mode (MPMODE pin = 1): If DTN is used, then the maximum frequency for MPCLK is determined by the processor's setup specification for DTN. MPU maximum bus operating frequency = 1/(MPU DTN setup time + tDTNVPD). For example, an 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detection. 42 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 6-6. Framer PLL Input Clocks Specifications Clock Name Period (ns) 19.2 Frequency 51.84 MHz Accuracy (ppm) 20 CHIRXGTCLK (DS1 mode) 647.66 CHIRXGTCLK (E1 mode) 488.28 1.544 MHz 2.048 MHz 32 50 CLKIN_PLL Jitter GR-499 and G.823 GR-499 G.823 Rise Fall (ns) (ns) -- -- Min/ Max -- Duty Cycle Max Max 50% 10% 50% 10% Rise Fall (ns) (ns) 10 10 10 10 10 10 10 10 Min/ Max Max Max Max Max Duty Cycle Rise Fall (ns) (ns) 10 10 10 10 Min/ Max Max Max Duty Cycle Rise (ns) 1.5 1.5 Fall (ns) 1.5 1.5 Min/ Max Nom Nom Duty Cycle Rise (ns) -- -- Fall (ns) -- -- Min/ Max -- -- Duty Cycle Fall (ns) 10 10 10 10 10 10 10 10 10 10 Min/ Max Max Max Max Max Max Max Max Max Max Max Duty Cycle 10 10 10 10 50% 10% Table 6-7. CHI Input Clocks Specifications Clock Name CHIRXGCLK (CHI mode) CHIRXGCLK (CHI mode) CHITXGCLK (CHI mode) CHITXGCLK (CHI mode) Period (ns) 122.07 61.035 122.07 61.035 Frequency 8.192 MHz 16.384 MHz 8.192 MHz 16.384 MHz Accuracy (ppm) 50 50 50 50 Jitter Accuracy (ppm) 20 20 Jitter Accuracy (ppm) 20 20 Jitter -- -- -- -- 50% 10% 50% 10% 50% 10% 50% 10% Table 6-8. PSB Input Clocks Specifications Clock Name CHIRXGCLK (PSB mode) CHITXGCLK (PSB mode) Period (ns) 51.44 51.44 Frequency 19.44 MHz 19.44 MHz -- -- 50% 10% 50% 10% Table 6-9. DS3/E3 Output Clocks Specifications Clock Name Period (ns) DS3RXCLKOUT [3:1](DS3) 22.353 DS3RXCLKOUT [3:1](E3) 29.09 Frequency 44.736 MHz 34.368 MHz GR-253 G.783 50% 5% 50% 5% Table 6-10. Framer PLL Output Clocks Specifications Clock Name CG_PLLCLKOUT CG_PLLCLKOUT Period (ns) 647.66 488.28 Frequency 1.544 MHz 2.048 MHz Accuracy (ppm) 32 50 Jitter GR-499 G.823 50% 5% 50% 5% Table 6-11. Shared Low-Speed Receive Line Input/Output Clocks Specifications Clock Name Period (ns) LINERXCLK (framer; DS1) 647.66 LINERXCLK (framer; E1) 488.28 LINERXCLK (M12) 647.66 LINERXCLK (E12) 488.28 LINERXCLK (M23) 158.42 LINERXCLK (E23) 118.37 LINERXCLK (DJA; DS1) 647.66 LINERXCLK (DJA; E1) 488.28 LINERXCLK (TPG; DS1) 647.66 LINERXCLK (TPG; E1) 488.28 Agere Systems Inc. Frequency 1.544 MHz 2.048 MHz 1.544 MHz 2.048 MHz 6.312 MHz 8.448 MHz 1.544 MHz 2.048 MHz 1.544 MHz 2.048 MHz Accuracy (ppm) 32 50 32 50 30 30 32 50 32 50 Jitter -- -- -- -- -- -- -- -- -- -- Rise (ns) 10 10 10 10 10 10 10 10 10 10 50% 5% 50% 5% 50% 5% 50% 5% 50% 5% 50% 5% 50% 5% 50% 5% 50% 5% 50% 5% 43 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 Table 6-12. Shared Low-Speed Transmit Line Input/Output Clocks Specifications Clock Name LINETXCLK (framer; DS1) LINETXCLK (framer; E1) LINETXCLK (M12) LINETXCLK (E12) LINETXCLK (M23) LINETXCLK (E23) LINETXCLK (DJA; DS1) LINETXCLK (DJA; E1) LINETXCLK (TPG; DS1) LINETXCLK (TPG; E1) Period (ns) Frequency Accuracy (ppm) 32 50 32 50 30 30 32 50 32 50 Jitter 647.66 488.28 647.66 488.28 158.42 118.37 647.66 488.28 647.66 488.28 1.544 MHz 2.048 MHz 1.544 MHz 2.048 MHz 6.312 MHz 8.448 MHz 1.544 MHz 2.048 MHz 1.544 MHz 2.048 MHz Accuracy (ppm) 51.84 MHz 20 44.736 MHz 20 34.368 MHz 20 Jitter -- -- -- -- -- -- -- -- -- -- Rise Fall (ns) (ns) 1.5 1.5 1.5 1.5 10 10 10 10 10 10 10 10 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Min/Max Duty Cycle Nominal Nominal Max Max Max Max Nominal Nominal Nominal Nominal 50% 5% 50% 5% 50% 5% 50% 5% 50% 5% 50% 5% 50% 5% 50% 5% 50% 5% 50% 5% Table 6-13. NSMI Input Clock Specifications Clock Name NSMIRXCLK (framer) NSMIRXCLK (M13) NSMIRXCLK (E13) Period (ns) 19.29 22.35 29.09 Frequency -- -- -- Rise (ns) 3.5 1.5 1.5 Fall Min/Max (ns) 3.5 Max 1.5 Nominal 1.5 Nominal Duty Cycle Rise (ns) 1.5 1.5 Fall (ns) 1.5 1.5 Min/Max Duty Cycle Nominal Nominal 50% 5% 50% 5% 50% 5% 50% 5% 50% 5% Table 6-14. NSMI Output Clocks Specifications Clock Name RXDATAEN NSMITXCLK 44 Period (ns) Frequency 19.29 19.29 51.84 MHz 51.84 MHz Accuracy (ppm) 20 20 Jitter -- -- Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 7 Microprocessor Interface Timing 7.1 Synchronous Write Mode The synchronous microprocessor interface mode is selected when MPMODE (pin D2) = 1. In this mode, MPCLK used for the Ultraframer is the same as the microprocessor clock. Interface timing for the synchronous mode write cycle is given in Figure 7-1 and in Table 7-1, and for the read cycle in Figure 7-2 and in Table 7-2. T0 T1 T2 T3 Tn - 2 Tn - 1 Tn MPCLK tADDRVS tAPD tCSNVS tAPD ADDR[20:0] CSN tWS tAIPD ADSN tAPD tWS RWN tAPD tWS DATA[15:0] (INPUT) tDTNVPD tDTNIPD tADSNVDTF DTN HIGH Z HIGH Z Notes: MPCLK ADDR [20:0] CSN (Input) ADSN (Input) RWN (Input) DATA[15:0] DTN (Output) Input clock to Ultraframer MPU block. The address will be available throughout the entire cycle. Chip select is an active-low signal. Address strobe is active-low. ADSN must be one MPCLK clock period wide. The read (H) write (L) signal is always high except during a write cycle. Data will be available during cycle T1. Data transfer acknowledge is active-low for one clock and then driven high before entering a high-impedance state. (This is done with an I/ O pad using the input as feedback to qualify the 3-state term.) DTN will become 3-stated when CSN is high. Typically, DTN is active four or five MPCLK cycles after ADSN is low. Figure 7-1. Microprocessor Interface Synchronous Write Cycle--MPMODE Pin = 1 Table 7-1. Microprocessor Interface Synchronous Write Cycle Specifications Symbol MPCLK Parameter Setup (min) Hold (min) Delay (min) Delay (max) Unit * MPCLK 16 MHz Min--66 MHz Max Frequency -- -- -- -- ns tWS ADSN, RWN, DATA (write) Valid to MPCLK 6.7 -- -- -- ns tAPD MPCLK to ADDR, RWN, DATA, CSN (write) Invalid -- 0 -- -- ns tCSNVS CSN Valid to MPCLK 6 -- -- -- ns tADDRVS ADDR Valid to MPCLK 3.5 -- -- -- ns tAIPD MPCLK to ADSN Invalid -- 0 -- -- ns tDTNVPD MPCLK to DTN Valid -- -- 2.5 12 ns tDTNIPD MPCLK to DTN Invalid -- -- 2.5 12 ns -- TADSNVDTF ADSN Valid to DTN Falling -- -- -- ns * If DTN is used, then the maximum frequency for MPCLK is determined by the processor's setup specification for DTN. MPU maximum bus operating frequency = 1/(MPU DTN setup time + tDTNVPD). For example, an 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detection. DTN fall is variable, depending on the block selected for access and in some cases the state of the SONET frame. This interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. It should never exceed 50 MPCLK cycles. . Agere Systems Inc. 45 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 7.2 Synchronous Read Mode T0 T1 T2 Tn - 4 Tn - 3 Tn - 2 Tn - 1 Tn MPCLK tAPD tAVS ADDR[20:0] tCSNSU CSN tADSNSU tSNIPD ADSN RWN tDNVPD tDNIPD tADSNVDTF DTN HIGH Z HIGH Z tDAIPD DATA[15:0] (OUTPUT) Notes: MPCLK ADDR [20:0] CSN (Input) ADSN (Input) RWN (Input) DTN (Output) DATA [15:0] Input clock to Ultraframer MPU block. The address will be available throughout the entire cycle, and must be stable before ADSN turns high. Chip select is an active-low signal. Address strobe is active-low. ADSN must be one MPCLK clock period wide. The read (H) write (L) signal is always high during the read cycle. Data transfer acknowledge on the host bus interface is initiated on T6. This signal is active for one clock, and then driven high before entering a high-impedance state. (This is done with an I/O pad using the input as feedback to qualify the 3-state term.) DTN will become 3stated when CSN is high. Typically, DTN is active four or five MPCLK cycles after ADSN is low. Read data is stable in Tn - 1. Figure 7-2. Microprocessor Interface Synchronous Read Cycle--MPMODE Pin = 1 Table 7-2. Microprocessor Interface Synchronous Read Cycle Specifications Symbol Parameter Setup (Min) Hold (Min) Delay (Min) Delay (Max) Unit MPCLK MPCLK 16 MHz Min--66* MHz Max Frequency -- -- -- -- ns tAVS ADDR Valid to MPCLK 3.5 -- -- -- ns tAPD MPCLK to ADDR Invalid -- 0 -- -- ns tCSNSU CSN Active to MPCLK 6 -- -- -- ns tADSNSU ADSN Valid to MPCLK 6 -- -- -- ns tSNIPD MPCLK to ADSN Inactive -- 0 -- -- ns tDNVPD MPCLK to DTN Valid -- -- 2.5 12 ns tDNIPD MPCLK to DTN Invalid -- -- 2.5 12 ns tDAIPD MPCLK to DATA 3-state -- -- 3.5 15 ns -- -- ns tADSNVDTF ADSN Valid to DTN Falling -- -- * If DTN is used, then the maximum frequency for MPCLK is determined by the processor's setup specification for DTN. MPU maximum bus operating frequency = 1/(MPU DTN setup time + tDNVPD). For example, an 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detection. DTN fall is variable, depending on the block selected for access and in some cases the state of the SONET frame. This interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. It should never exceed 50 MPCLK cycles. 46 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 7.3 Asynchronous Write Mode The asynchronous microprocessor interface mode is selected when MPMODE (pin D2) = 0. Interface timing for the asynchronous mode write cycle is given in Figure 7-3 and in Table 7-3, and for the read cycle in Figure 7-4 and in Table 7-4. Although this is an asynchronous interface, an MPCLK is still required. This clock can be different (asynchronous) from the MPU clock. Internal to the chip, RWN, ADSN, and DSN will be sampled by MPCLK. ADDR[20:0] tCSFDSF tAICSR CSN tAVADSF tADSRAI ADSN tAVDSF tDSNRAI DSN tRWFDSF tDSRRWR RWN tDSRDI tDVDSF DATA[15:0] (INPUT) tADSRDTR tCSRDT3 tCSFDTR tDSFDTF DTN HIGH Z HIGH Z Notes: ADDR [20:0] Address is asynchronously passed from the host bus to the internal bus. The address will be available throughout the entire cycle. ADDR must be held constant while ADSN and DSN are valid (low). CSN (Input) Chip select is an active-low signal. CSN must be held low (active) until ADSN and DSN are deasserted. ADSN (Input) Address strobe is active-low. ADSN must be stable for the entire period. ADSN and CSN may be connected and driven from the same source. DSN (Input) Data strobe is active-low. DATA [15:0] Write data is asynchronously passed from the host bus to the internal bus. Data will be available throughout the entire cycle. DATA must be held constant while DSN is valid (low). RWN (Input) The read/write signal should be high for a read cycle and low for a write cycle. It should always be held high, except during a write cycle. RWN must be held low (write) until DSN is deasserted (high). DTN (Output) Data transfer acknowledge (active-low). DTN is driven out of 3-state to inactive-high on the assertion of CSN. When the internal transaction is complete, DTN goes active-low. DTN is then driven high again when either ADSN or DSN is deasserted. DTN will become 3-stated when CSN is high. DTN fall is variable, depending on the block selected for access and in some cases the state of the SONET frame. This interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. In lab measurements, it has never exceeded 1000 ns. Figure 7-3. Microprocessor Interface Asynchronous Write Cycle--MPMODE Pin = 0 Agere Systems Inc. 47 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 Table 7-3. Microprocessor Interface Asynchronous Write Cycle Specifications Symbol Parameter Setup (Min) Hold (Min) Delay (Min) Delay (Max) Unit MPCLK tCSFDSF tAICSR tAVADSF tADSRAI tAVDSF tDSNRAI tRWFDSF tDSRRWR tDVDSF tDSRDI tCSFDTR tDSFDTF tADSRDTR tCSRDT3 MPCLK 16 MHz Min--66 MHz Max Frequency CSN Fall Setup and Hold to DSN Fall CSN Rise to ADDR Invalid ADDR Valid Setup and Hold to ADSN Fall ADSN Rise to ADDR Invalid ADDR Valid Setup and Hold to DSN Fall DSN Rise to ADDR Invalid RWN Fall Setup and Hold to DSN Fall DSN Rise to RWN Rise DATA Valid Setup and Hold to DSN Fall DSN Rise to DATA Invalid CSN Fall to DTN Rise DSN Fall to DTN Fall ADSN or DSN Rise to DTN Rise CSN Rise to DTN 3-state -- 0 -- 1.0 -- 0 -- 0 -- 0 -- -- -- -- -- -- -- 0 -- 1.42 -- 0 -- 0 -- 0 -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- 5.2 -- 2.9 2.9 -- -- -- -- -- -- -- -- -- -- -- 16.0 -- 13.3 13 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7.4 Asynchronous Read Mode ADDR[20:0] tAICSR tCSFDSF CSN tADSRAI tAVADSF ADSN tDSNRAI tAVDSF DSN RWN tCSFDTR tCSRDT3 tADSRDTR tDSFDTF DTN HIGH Z HIGH Z tDTVDV HIGH Z tADSRD3 HIGH Z DATA[15:0] Notes: ADDR [20:0] CSN (Input) ADSN (Input) DSN (Input) RWN (Input) DTN (Output) DATA [15:0] Address is asynchronously passed from the host bus to the internal bus. The address will be available throughout the entire cycle. Chip select is an active-low signal. Address strobe is active-low. Data strobe is active-low. The read (H) write (L) signal is always high during a read cycle. Data transfer acknowledge (active-low). DTN is driven out of 3-state to inactive-high on the assertion of CSN. When the internal transaction is complete, DTN goes active-low. DTN is then driven high again when either ADSN or DSN is deasserted. DTN will become 3-stated when CSN is high. 16-bit data bus. Figure 7-4. Microprocessor Interface Asynchronous Read Cycle--MPMODE Pin = 0 48 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 7-4. Microprocessor Interface Asynchronous Read Cycle Specifications Symbol Parameter Setup (Min) Hold (Min) Delay (Min) Delay (Max) Unit MPCLK MPCLK 16 MHz Min--66 MHz Max Frequency -- -- -- -- ns 0 * -- -- ns tCSFDSF tAICSR CSN Fall Setup and Hold to DSN Fall -- CSN Rise to ADDR Invalid -- 0 -- -- ns tAVADSF ADDR Valid Setup and Hold to ADSN Fall 1.0 -- -- -- ns tADSRAI ADSN Rise to ADDR Invalid -- 1.42 tAVDSF ADDR Valid Setup and Hold to DSN Fall 0 -- -- -- ns -- -- ns tDSNRAI DSN Rise to ADDR Invalid -- 0 -- -- ns tCSFDTR CSN Fall to DTN Rise -- -- 5.2 16.0 ns tDSFDTF DSN Fall to DTN Fall -- 0 -- -- ns tADSRDTR ADSN or DSN Rise to DTN Rise -- -- 2.9 13.3 ns tCSRDT3 CSN Rise to DTN 3-state -- -- 2.9 13.0 ns tDTVDV DTN Valid to DATA Valid -- -- -- 0 ns tADSRD3 ADSN Rise to DATA 3-state -- -- 2.9 14 + MPCLK ns * CSN must be held low (active) until ADSN and DSN are deasserted. ADDR must be held constant while ADSN and DSN are valid (low). DTN fall is variable, depending on the block selected for access and in some cases, the state of the SONET frame. This interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. It should never exceed 50 MPCLK cycles. DATA[15:0] is enabled by a retimed version of the ADSN. Agere Systems Inc. 49 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 8 Other Timing This interface may be used as either synchronous or asynchronous mode. Table 8-1. General-Purpose Inputs Specifications Name Reference RSTN PMRST TDI and TMS Async Async TCLK Edge Rising/Falling -- -- R Rise Time (ns) -- -- 5 Fall Time (ns) -- -- 5 Setup (ns) -- -- 19.5 Hold (ns) -- -- 6.4 Table 8-2. General-Purpose Output Specifications Name TDO Reference TCLK Edge Rising/Falling F Propagation Delay Min (ns) Max (ns) 12.5 45 9 Hardware Design File References (IBIS, Spice, BSDL, etc.) Available upon request. 50 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 10 909-Pin PBGA Diagram Figure 10-1. Ultraframer 909-Pin PBGA Balls and Dimensions Agere Systems Inc. 51 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Hardware Design Guide, Revision 5 July 13, 2004 11 Ordering Information Table 11-1. Ordering Information Device TFRA84J131BL-21 TFRA84J131BL-3 52 Package 909-pin PBGA 909-pin PBGA Comcode 700055303 700052826 Agere Systems Inc. Hardware Design Guide, Revision 5 July 13, 2004 12 Glossary AIS Alarm indication signal AMI Alternate mark inversion APS Automatic protection switch ASM Associated signaling mode BER Bit error rate BOM Bit-oriented message BPV Bipolar violation B8ZS Binary 8 zero code suppression CCI Common channel signaling CDR Clock and data recovery CHI Concentrated highway interface CMI Coded mark inversion CRC Cyclic redundancy check CRV Coding rule violation DACS Digital access cross connects DJA Digital jitter attenuation ESF Extended superframe EXZ Excessive zeros FCS Frame check sequence FDL Facility data link FEAC Far-end alarm and control FEBE Far-end block error HDB3 High-density bipolar of order three Agere Systems Inc. TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 HDLC High-level data link control LIU Line interface unit LOC Loss of clock LOF Loss of frame LOS Loss of signal LOPOH Low-order path overhead MCDR Mate clock and data recovery MRXC Multirate cross connect NSMI Network serial multiplexed interface OOF Out of frame PBGA Pin ball grid array POAC Path overhead access channel PRBS Pseudorandom bit sequence PRM Performance report message QRSS Quasirandom signal source RAI Remote alarm indicator RDI Remote defect indication RPOAC Receive path overhead access channel REI Remote error indication SDH Synchronous digital hierarchy SEF Severely errored frame SONET Synchronous optical network TCM Tandem connection monitoring TOAC Transport overhead access channels UPSR Unidirectional path switch ring 53 Hardware Design Guide, Serializer/Deserializer (SERDES) RevisionSerial 5 Serial Interface July 13, 2004 for the MACROs TFRA84J13 Hardware Ultraframer DeDS3/E3/DS2/E2/DS1/E1/DS0 sign Guide, Revi- 13 Change History On page 47, the second paragraph was deleted. Other changes that were made to this document (since revision 4) are listed in Table 13-1. Table 13-1. Changes Change page 21 Change page 24 Change page 31 Change page 42 Change page 45 Change page 46 Change page 47 Change page 48 Change page 49 Change page 52 13.1 Navigating Through an Adobe Acrobat Document If the reader displays this document in Acrobat Reader, clicking on any blue entry in the text will bring the reader to that reference point. Clicking on the back arrow in the toolbar of the Acrobat Reader (Go to previous View) will bring the reader back to the starting point. For example, clicking on page 21 in Table 13-1 will bring the reader to page 21 of this document, which is the first change. Clicking on the back arrow in Acrobat Reader, will bring the reader back to this page. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Adobe Acrobat and Acrobat Reader are registered trademarks of Adobe Systems Incorporated. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: CHINA: (86) 21-54614688 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere is a registered trademark of Agere Systems Inc. Agere Systems, Supermapper, Ultramapper, Hypermapper, and the Agere logo are trademarks of Agere Systems Inc. Copyright (c) 2004 Agere Systems Inc. All Rights Reserved July 13, 2004 DS02-402BBAC-5 (Replaces DS02-402BBAC-4)