CY8C20XX6A/S (R) 1.8 V Programmable CapSense Controller with SmartSenseTM Auto-tuning 1-33 Buttons, 0-6 Sliders 1.8 V Programmable CapSense(R) Controller with SmartSenseTM Auto-tuning 1-33 Buttons, 0-6 Sliders Features Low power CapSense(R) block with SmartSense Auto-tuning Patented CSA_EMC, CSD sensing algorithms SmartSense_EMC Auto-Tuning * Sets and maintains optimal sensor performance during run time * Eliminates system tuning during development and production * Compensates for variations in manufacturing process Low average power consumption - 28 A/sensor in run time (wake-up and scan once every 125 ms) Powerful Harvard-architecture processor M8C CPU with a max speed of 24 MHz Operating Range: 1.71 V to 5.5 V Standby Mode 1.1 A (Typ) Deep Sleep 0.1 A (Typ) Operating Temperature range: -40 C to +85 C Flexible on-chip memory 8 KB flash, 1 KB SRAM 16 KB flash, 2 KB SRAM 32 KB flash, 2 KB SRAM Read while Write with EEPROM emulation 50,000 flash erase/write cycles In-system programming simplifies manufacturing process Four Clock Sources Internal main oscillator (IMO): 6/12/24 MHz Internal low-speed oscillator (ILO) at 32 kHz for watchdog and sleep timers External 32 KHz Crystal Oscillator External Clock Input Programmable pin configurations Up to 36 general-purpose I/Os (GPIOs) configurable as buttons or sliders Dual mode GPIO (Analog inputs and Digital I/O supported) High sink current of 25 mA per GPIO * Max sink current 120 mA for all GPIOs Source Current * 5 mA on ports 0 and 1 * 1 mA on ports 2,3 and 4 Configurable internal pull-up, high-Z and open drain modes Selectable, regulated digital I/O on port 1 Configurable input threshold on port 1 Versatile Analog functions Internal analog bus supports connection of multiple sensors to form ganged proximity sensor Internal Low-Dropout voltage regulator for high power supply rejection ratio (PSRR) Full-Speed USB 12 Mbps USB 2.0 compliant Additional system resources I2C Slave: * Selectable to 50 kHz, 100 kHz, or 400 kHz Configurable up to 12 MHz SPI master and slave Three 16-bit timers Watchdog and sleep timers Integrated supervisory circuit 10-bit incremental analog-to-digital converter (ADC) with internal voltage reference Two general-purpose high speed, low power analog comparators Complete development tools Free development tool (PSoC DesignerTM) Sensor and Package options 10 Sensors - QFN 16, 24 16 Sensors - QFN 24 22 / 25 Sensors - QFN 32 24 Sensors - WLCSP 30 31 Sensors - SSOP 48 33 Sensors - QFN 48 Errata: For information on silicon errata, see "Errata" on page 46. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation Document Number: 001-54459 Rev. *Y * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised May 18, 2017 CY8C20XX6A/S Logic Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 1.8/2.5/3V LDO PWRSYS[1] (Regulator) PSoC CORE SYSTEM BUS Global Analog Interconnect 1K/2K SRAM Supervisory ROM (SROM) Interrupt Controller 8K/16K/32K Flash Nonvolatile Memory Sleep and Watchdog CPU Core (M8C) 6/12/24 MHz Internal Main Oscillator (IMO) Internal Low Speed Oscillator (ILO) Multiple Clock Sources CAPSENSE SYSTEM Two Comparators Analog Reference CapSense Module Analog Mux SYSTEM BUS USB I2C Slave Internal Voltage References System Resets POR and LVD SPI Master/ Slave Three 16-Bit Programmable Timers Digital Clocks SYSTEM RESOURCES Note 1. Internal voltage regulator for internal circuitry Document Number: 001-54459 Rev. *Y Page 2 of 53 CY8C20XX6A/S More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article KBA92181, Resources Available for CapSense(R) Controllers. Following is an abbreviated list for CapSense devices: Overview: CapSense Portfolio, CapSense Roadmap Product Selectors: CapSense, CapSense Plus, CapSense Express, PSoC3 with CapSense, PSoC5 with CapSense, PSoC4. In addition, PSoC Designer offers a device selection tool at the time of creating a new project. Application notes: Cypress offers CapSense application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with CapSense are: AN64846: Getting Started With CapSense (R) AN73034: CY8C20xx6A/H/AS CapSense Design Guide AN2397: CapSense(R) Data Viewing Tools Technical Reference Manual (TRM): PSoC(R) CY8C20xx6A/AS/L Family Technical Reference Manual Development Kits: CY3280-20x66 Universal CapSense Controller Kit features a predefined control circuitry and plug-in hardware to make prototyping and debugging easy. Programming and I2C-to-USB Bridge hardware are included for tuning and data acquisition. CY3280-BMM Matrix Button Module Kit consists of eight CapSense sensors organized in a 4x4 matrix format to form 16 physical buttons and eight LEDs. This module connects to any CY3280 Universal CapSense Controller Board, including CY3280-20x66 Universal CapSense Controller. CY3280-BSM Simple Button Module Kit consists of ten CapSense buttons and ten LEDs. This module connects to any CY3280 Universal CapSense Controller Board, including CY3280-20x66 Universal CapSense Controller. The CY3217-MiniProg1 and CY8CKIT-002 PSoC(R) MiniProg3 device provides an interface for flash programming. PSoC Designer PSoC Designer is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design of systems based on CapSense (see Figure 1). With PSoC Designer, you can: 1. Drag and drop User Modules to build your hardware system 3. Configure User Module design in the main design workspace 4. Explore the library of user modules 2. Codesign your application firmware with the PSoC hardware, 5. Review user module datasheets using the PSoC Designer IDE C compiler Figure 1. PSoC Designer Features 1 2 3 4 5 Document Number: 001-54459 Rev. *Y Page 3 of 53 CY8C20XX6A/S Contents PSoC(R) Functional Overview ............................................ 5 PSoC Core .................................................................. 5 CapSense System ....................................................... 5 Additional System Resources ..................................... 6 Getting Started .................................................................. 7 CapSense Design Guides ........................................... 7 Silicon Errata ............................................................... 7 Development Kits ........................................................ 7 Training ....................................................................... 7 CYPros Consultants .................................................... 7 Solutions Library .......................................................... 7 Technical Support ....................................................... 7 Development Tools .......................................................... 8 PSoC Designer Software Subsystems ........................ 8 Designing with PSoC Designer ....................................... 9 Select User Modules ................................................... 9 Configure User Modules .............................................. 9 Organize and Connect ................................................ 9 Generate, Verify, and Debug ....................................... 9 Pinouts ............................................................................ 10 16-pin QFN (10 Sensing Inputs)[3, 4] ....................... 10 24-pin QFN (17 Sensing Inputs) [8] ........................... 11 24-pin QFN (15 Sensing Inputs (With USB)) [13] ...... 12 30-ball WLCSP (24 Sensing Inputs) [18] ................... 13 32-pin QFN (25 Sensing Inputs) [22] ......................... 14 32-pin QFN (22 Sensing Inputs (With USB)) [27] ...... 15 48-pin SSOP (31 Sensing Inputs) [32] ...................... 16 48-pin QFN (33 Sensing Inputs) [36] ......................... 17 48-pin QFN (33 Sensing Inputs (With USB)) [41] ...... 18 48-pin QFN (OCD) (33 Sensing Inputs) [46] ............. 19 Electrical Specifications ................................................ 20 Absolute Maximum Ratings ....................................... 20 Operating Temperature ............................................. 20 DC Chip-Level Specifications .................................... 21 DC GPIO Specifications ............................................ 22 DC Analog Mux Bus Specifications ........................... 24 DC Low Power Comparator Specifications ............... 24 Comparator User Module Electrical Specifications .................................................... 25 ADC Electrical Specifications .................................... 25 DC POR and LVD Specifications .............................. 26 Document Number: 001-54459 Rev. *Y DC Programming Specifications ............................... 26 DC I2C Specifications ............................................... 27 DC Reference Buffer Specifications .......................... 27 DC IDAC Specifications ............................................ 27 AC Chip-Level Specifications .................................... 28 AC GPIO Specifications ............................................ 29 AC Comparator Specifications .................................. 30 AC External Clock Specifications .............................. 30 AC Programming Specifications ................................ 31 AC I2C Specifications ................................................ 32 Packaging Information ................................................... 35 Thermal Impedances ................................................. 38 Capacitance on Crystal Pins ..................................... 38 Solder Reflow Specifications ..................................... 38 Development Tool Selection ......................................... 39 Software .................................................................... 39 Development Kits ...................................................... 39 Evaluation Tools ........................................................ 39 Device Programmers ................................................. 39 Accessories (Emulation and Programming) .............. 40 Third Party Tools ....................................................... 40 Build a PSoC Emulator into Your Board .................... 40 Ordering Information ...................................................... 41 Ordering Code Definitions ......................................... 43 Acronyms ........................................................................ 44 Reference Documents .................................................... 44 Document Conventions ................................................. 44 Units of Measure ....................................................... 44 Numeric Naming ........................................................ 45 Glossary .......................................................................... 45 Errata ............................................................................... 46 Qualification Status ................................................... 46 Errata Summary ........................................................ 46 Document History Page ................................................. 49 Sales, Solutions, and Legal Information ...................... 53 Worldwide Sales and Design Support ....................... 53 Products .................................................................... 53 PSoC(R)Solutions ....................................................... 53 Cypress Developer Community ................................. 53 Technical Support ..................................................... 53 Page 4 of 53 CY8C20XX6A/S PSoC(R) Functional Overview The PSoC family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (MCU)-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The architecture for this device family, as shown in the Logic Block Diagram on page 2, consists of three main areas: The Core CapSense Analog System System Resources (including a full-speed USB port). A common, versatile bus allows connection between I/O and the analog system. required tuning parameters. SmartSense allows engineers to go from prototyping to mass production without re-tuning for manufacturing variations in PCB and/or overlay material properties. SmartSense_EMC In addition to the SmartSense auto tuning algorithm to remove manual tuning of CapSense applications, SmartSense_EMC user module incorporates a unique algorithm to improve robustness of capacitive sensing algorithm/circuit against high frequency conducted and radiated noise. Every electronic device must comply with specific limits for radiated and conducted external noise and these limits are specified by regulatory bodies (for example, FCC, CE, U/L and so on). A very good PCB layout design, power supply design and system design is a mandatory for a product to pass the conducted and radiated noise tests. An ideal PCB layout, power supply design or system design is not often possible because of cost and form factor limitations of the product. SmartSense_EMC with superior noise immunity is well suited and handy for such applications to pass radiated and conducted noise test. Figure 2. CapSense System Block Diagram Each CY8C20XX6A/S PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 36 GPIO are also included. The GPIO provides access to the MCU and analog mux. CS1 IDAC The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO and ILO. The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit Harvard-architecture microprocessor. CSN Vr Reference Buffer CapSense System The analog system contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. The analog system is composed of the CapSense PSoC block and an internal 1 V or 1.2 V analog reference, which together support capacitive sensing of up to 33 inputs [2]. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins are completed quickly and easily across multiple ports. Comparator Cinternal Cexternal (P0[1] or P0[3]) Mux Mux Refs Cap Sense Counters CSCLK SmartSense SmartSense is an innovative solution from Cypress that removes manual tuning of CapSense applications. This solution is easy to use and provides a robust noise immunity. It is the only auto-tuning solution that establishes, monitors, and maintains all CS2 Analog Global Bus PSoC Core IMO CapSense Clock Select Oscillator Note 2. 36 GPIOs = 33 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulator capacitor. Document Number: 001-54459 Rev. *Y Page 5 of 53 CY8C20XX6A/S Analog Multiplexer System Additional System Resources The Analog Mux Bus can connect to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. System resources provide additional capability, such as configurable USB and I2C slave, SPI master/slave communication interface, three 16-bit programmable timers, and various system resets supported by the M8C. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: These system resources provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The merits of each system resource are listed here: Complex capacitive sensing interfaces, such as sliders and touchpads. Chip-wide mux that allows analog input from any I/O pin. Crosspoint connection between any I/O pin combinations. Document Number: 001-54459 Rev. *Y The I2C slave/SPI master-slave module provides 50/100/400 kHz communication over two wires. SPI communication over three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). Low-voltage detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced power-on-reset (POR) circuit eliminates the need for a system supervisor. An internal reference provides an absolute reference for capacitive sensing. A register-controlled bypass mode allows the user to disable the LDO regulator. Page 6 of 53 CY8C20XX6A/S Getting Started The quickest way to understand PSoC silicon is to read this datasheet and then use the PSoC Designer Integrated Development Environment (IDE). This datasheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming details, see the Technical Reference Manual for the CY8C20XX6A/S PSoC devices. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web at www.cypress.com/psoc. CapSense Design Guides Design Guides are an excellent introduction to the wide variety of possible CapSense designs. They are located at www.cypress.com/go/CapSenseDesignGuides. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. Solutions Library Refer Getting Started with CapSense design guide for information on CapSense design and CY8C20XX6A/H/AS CapSense(R) Design Guide for specific information on CY8C20XX6A/AS CapSense controllers. Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Silicon Errata Technical Support Errata documents known issues with silicon including errata trigger conditions, scope of impact, available workarounds and silicon revision applicability. Refer to Silicon Errata for the PSoC(R) CY8C20x36A/46A/66A/96A/46AS/66AS/36H/46H families available at http://www.cypress.com/?rID=56239 for errata information on CY8C20xx6A/AS/H family of device. Compare errata document with datasheet for a complete functional description of device. Technical support - including a searchable Knowledge Base articles and technical forums - is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Document Number: 001-54459 Rev. *Y Page 7 of 53 CY8C20XX6A/S Development Tools PSoC DesignerTM is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration Extensive user module catalog C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Integrated source-code editor (C and assembly) Debugger Free C compiler with no size restrictions or time limits Built-in debugger In-circuit emulation PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also lets you to create a trace buffer of registers and memory locations of interest. Built-in support for communication interfaces: 2 Hardware and software I C slaves and masters Full-speed USB 2.0 Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this lets you to use more than 100 percent of PSoC's resources for an application. Document Number: 001-54459 Rev. *Y Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality in-circuit emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24 MHz) operation. Page 8 of 53 CY8C20XX6A/S Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is: 6. Select user modules. 7. Configure user modules. 8. Organize and connect. 9. Generate, verify, and debug. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called "user modules". User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each eight bits of resolution. Using these parameters, you can establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All of the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. Document Number: 001-54459 Rev. *Y Organize and Connect Build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. Perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the "Generate Configuration Files" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides APIs with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. A complete code development environment lets you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger (accessed by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full-speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. It lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Page 9 of 53 CY8C20XX6A/S Pinouts The CY8C20XX6A/S PSoC device is available in a variety of packages, which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES are not capable of Digital I/O. 16-pin QFN (10 Sensing Inputs)[3, 4] Table 1. Pin Definitions - CY8C20236A, CY8C20246A, CY8C20246AS PSoC Device Crystal output (XOut) I/O I P2[3] Crystal input (XIn) 3 IOHR I P1[7] I2C SCL, SPI SS 4 IOHR I P1[5] I2C 5 IOHR I P1[3] SPI CLK 6 IOHR I P1[1] ISSP CLK[5], I2C SCL, SPI MOSI 7 Power VSS 8 IOHR I P1[0] 9 IOHR I P1[2] 10 IOHR I 11 12 13 Input IOH P1[4] SDA, SPI MISO Ground connection[7] ISSP DATA[5], I2C SDA, SPI CLK[6] Optional external clock (EXTCLK) XRES Active high external reset with internal pull-down I P0[4] Power VDD Supply voltage 14 IOH I P0[7] 15 IOH I P0[3] Integrating input 16 IOH I P0[1] Integrating input AI , XOut, P2[5] AI, XIn, P2[3] AI, I2 C SCL, SPI SS, P1[7] AI , I2 C SDA, SPI MISO, P1[5] 1 2 14 13 2 P0[1], AI P0[3], AI P0[7], AI Vdd P2[5] 16 15 I 12 3 4 QFN ( Top View) 11 10 9 5 6 7 8 I/O Figure 3. CY8C20236A, CY8C20246A, CY8C20246AS P0[4] , AI XRES P1[4] , EXTCLK, AI P1[2] , AI AI, SPI CLK , P1[3] AI, ISSP CLK, SPI MOSI, P1[1] Vss [5,6] AI, ISSP DATA , I2C SDA, SPI CLK , P1[0] 1 Description [5] Type Pin No. Digital Analog Name LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 3. 13 GPIOs = 10 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor. 4. No Center Pad. 5. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 6. Alternate SPI clock. 7. All VSS pins should be brought out to one common GND plane. Document Number: 001-54459 Rev. *Y Page 10 of 53 CY8C20XX6A/S 24-pin QFN (17 Sensing Inputs) [8] Table 2. Pin Definitions - CY8C20336A, CY8C20346A, CY8C20346AS [9] P1[3] SPI CLK P1[1] ISSP CLK[10], I2C SCL, SPI MOSI IOHR I 8 9 Power NC No connection VSS Ground connection[12] 10 IOHR I P1[0] 11 IOHR I P1[2] 12 IOHR I P1[4] 13 IOHR I P1[6] 14 Input XRES 15 I/O I P2[0] 16 IOH I P0[0] 17 IOH I P0[2] 18 IOH I P0[4] 19 IOH I P0[6] 20 Power VDD ISSP DATA[10], I2C SDA, SPI CLK[11] Optional external clock input (EXTCLK) IOH I P0[7] IOH I P0[5] 23 IOH I P0[3] Integrating input 24 IOH I P0[1] Integrating input VSS P0[5], AI P0[7], AI Vdd P0[6], AI 22 21 20 19 3 QFN 4 (T o p V ie w ) 16 15 5 14 6 13 Supply voltage 22 Power P 2 [1 ] P 1 [7 ] P 1 [5 ] P 1 [3 ] P 0 [4 ], A I P 0 [2 ], A I P 0 [0 ], A I P 2 [0 ], A I XRES P 1 [6 ], A I Active high external reset with internal pull-down 21 CP A I, A I, I2 C S C L , S P I S S , A I, I2 C S D A , S P I M IS O , A I, S P I C L K , 17 [10, 7 SDA, SPI MISO 18 12 P1[5] I 2 AI, EXTCLK, P1[4] I IOHR 1 11 IOHR 6 A I, X O u t, P 2 [5] A I, X In , P 2 [3 ] AI, P1[2] 5 I2C 9 I2C SCL, SPI SS 10 P1[7] Vss P2[1] I 2 I IOHR AI, ISSP DATA , I2C SDA, SPI CLK, P1[0] I/O 4 P0[1], AI 3 P0[3], AI Crystal input (XIn) 24 Crystal output (XOut) P2[3] 23 P2[5] I 8 I I/O Figure 4. CY8C20336A, CY8C20346A, CY8C20346AS 7 I/O 2 Description NC 1 Name 2 Analog SPI MOSI, P1[1] Digital AI, ISSP CLK , I2C SCL Type Pin No. Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 8. 20 GPIOs = 17 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor. 9. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 10. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 11. Alternate SPI clock. 12. All VSS pins should be brought out to one common GND plane. Document Number: 001-54459 Rev. *Y Page 11 of 53 CY8C20XX6A/S 24-pin QFN (15 Sensing Inputs (With USB)) [13] Table 3. Pin Definitions - CY8C20396A [14] Digital Analog 1 I/O I P2[5] 2 I/O I P2[3] 3 I/O I P2[1] 4 IOHR I P1[7] I2C SCL, SPI SS Description IOHR I P1[1] ISSP CLK[15], I2C SCL, SPI MOSI Power 9 I/O 10 I/O 11 I I Power VSS Ground[17] D+ USB D+ D- USB D- VDD Supply ISSP DATA[15], I2C SDA, SPI CLK[16] 12 IOHR I P1[0] 13 IOHR I P1[2] 14 IOHR I P1[4] 15 IOHR I P1[6] 16 RESET INPUT XRES 17 IOH I P0[0] 18 IOH I P0[2] 19 IOH I P0[4] 20 IOH I P0[6] 21 IOH I P0[7] 22 IOH I P0[5] 23 IOH I P0[3] Integrating input 24 IOH I P0[1] Integrating input CP Power VSS Optional external clock input (EXTCLK) Active high external reset with internal pull-down P2[1], AI AI, I 2 C SCL, SPI SS,P1[7] AI, I2C SDA , SPI MISO,P1[5] AI, SPI CLK ,P1[3] 19 21 20 22 24 23 QFN 3 16 4 (Top View) 15 5 14 6 13 AI, ISSP DATA, I2C SDA, SPI CLK, P1[0] 7 SDA, SPI MISO 11 12 SPI CLK P0[2], AI P0[0], AI XRES P1[6], AI P1[4] , AI, EXTCLK P1[2 ], AI [15, P1[3] 9 10 P1[5] I 18 17 2 8 I IOHR 1 7 IOHR 6 P2[5], AI P2[3], AI AI, ISSP CLK, I2C SCL, SPI MOSI, P1[1] Vss D+ DVDD 5 I2C 8 Figure 5. CY8C20396A P0[1], AI P0[3], AI P0[5], AI P0[7], AI P0[6], AI P0[4], AI Name [1 Type Pin No. Center pad must be connected to Ground LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output Notes 13. 20 GPIOs = 15 pins for capacitive sensing + 2 pins for I2C + 2 pins for USB + 1 pin for modulation capacitor. 14. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 15. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 16. Alternate SPI clock. 17. All VSS pins should be brought out to one common GND plane. Document Number: 001-54459 Rev. *Y Page 12 of 53 CY8C20XX6A/S 30-ball WLCSP (24 Sensing Inputs) [18] Table 4. Pin Definitions - CY8C20766A, CY8C20746A 30-ball WLCSP Type Pin No. Digital Analog A1 IOH I P0[2] A2 IOH I P0[6] A3 Power Name Description Figure 6. CY8C20766A 30-ball WLCSP Bottom View VDD Supply voltage Integrating Input A4 IOH I P0[1] A5 I/O I P2[7] B1 I/O I P2[6] B2 IOH I P0[0] B3 IOH I P0[4] B4 IOH I P0[3] Integrating Input B5 I/O I P2[5] Crystal Output (Xout) C1 I/O I P2[2] C2 I/O I P2[4] C3 IOH I P0[7] C4 IOH I P0[5] C5 I/O I P2[3] D1 I/O I P2[0] D2 I/O I P3[0] D3 I/O I P3[1] D4 I/O I P3[3] D5 I/O I P2[1] E1 Input XRES 2 1 A D E F Top View Crystal Input (Xin) 1 2 3 4 5 A B Active high external reset with internal pull-down C D I P1[6] E3 IOHR I P1[4] Optional external clock input (EXT CLK) E4 IOHR I P1[7] I2C E5 IOHR I P1[5] I2C SDA, SPI MISO F1 IOHR I P1[2] F2 IOHR I P1[0] VSS 3 C IOHR Power 4 B E2 F3 5 SCL, SPI SS E F ISSP DATA[19], I2C SDA, SPI CLK[20] Supply ground[21] F4 IOHR I P1[1] ISSP CLK[19], I2C SCL, SPI MOSI F5 IOHR I P1[3] SPI CLK Notes 18. 27 GPIOs = 24 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor. 19. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 20. Alternate SPI clock. 21. All VSS pins should be brought out to one common GND plane. Document Number: 001-54459 Rev. *Y Page 13 of 53 CY8C20XX6A/S 32-pin QFN (25 Sensing Inputs) [22] Table 5. Pin Definitions - CY8C20436A, CY8C20446A, CY8C20446AS, CY8C20466A, CY8C20466AS[23] P2[5] Crystal output (XOut) 4 I/O I P2[3] Crystal input (XIn) 5 I/O I P2[1] 6 I/O I P3[3] 7 I/O I P3[1] 8 IOHR I P1[7] I2C SCL, SPI SS 9 IOHR I P1[5] I2C SDA, SPI MISO 10 IOHR I P1[3] SPI CLK. 11 IOHR I P1[1] ISSP CLK[24], I2C SCL, SPI MOSI. 12 Power VSS 13 IOHR I P1[0] 14 IOHR I P1[2] 15 IOHR I P1[4] 16 IOHR I P1[6] 17 Input XRES I/O I P3[0] 19 I/O I P3[2] 20 I/O I P2[0] 21 I/O I P2[2] 22 I/O I P2[4] 23 I/O I P2[6] 24 IOH I P0[0] 25 IOH I P0[2] 26 IOH I P0[4] 27 IOH I P0[6] ISSP DATA[24], I2C SDA, SPI CLK[25] Optional external clock input (EXTCLK) Active high external reset with internal pull-down 32 31 Vss P0 [3], AI P0 [5], AI Ground connection[26] 9 1 2 3 4 5 6 7 8 QFN (Top View) 24 23 22 21 20 19 18 17 P0[0] , AI P2[6] , AI P2[4] , AI P2[2] , AI P2[0] , AI P3[2] , AI P3[0] , AI XRES [24] 18 AI , P0[1] AI , P2[7] AI, XOut, P2[5] AI , XIn, P2[3] AI , P2[1] AI , P3[3] AI , P3[1] AI , I2 C SCL, SPI SS, P1[7] P0 [4], AI P0 [2], AI P2[7] I 26 25 I I/O 15 16 I/O 3 AI, E XTCLK, P 1[4] AI, P 1[6] 2 CY8C20466A, CY8C20466AS Integrating input P0 [7], AI Vd d P0 [6], AI P0[1] 28 27 I Figure 7. CY8C20436A, CY8C20446A, CY8C20446AS, 13 14 IOH Description 30 29 1 Name A I,ISSP CLK , I2C SCL, SPI MOSI, P1[1] Vss [24] AI , ISSP DATA , I2C SDA, SPI CLK, P1[0] AI, P 1[2] Analog 10 11 12 Digital AI, I2C SDA, SPI MISO, P 1[5] AI, SPI CLK, P 1[3] Type Pin No. 28 Power VDD 29 IOH I P0[7] 30 IOH I P0[5] 31 IOH I P0[3] Supply voltage Integrating input 32 Power VSS Ground connection[26] CP Power VSS Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 22. 28 GPIOs = 25 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor. 23. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 24. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 25. Alternate SPI clock. 26. All VSS pins should be brought out to one common GND plane. Document Number: 001-54459 Rev. *Y Page 14 of 53 CY8C20XX6A/S 32-pin QFN (22 Sensing Inputs (With USB)) [27] Table 6. Pin Definitions - CY8C20496A[28] P2[1] 5 IOHR I P1[7] IOHR I P1[5] I C SDA, SPI MISO 7 IOHR I P1[3] SPI CLK 8 IOHR I P1[1] ISSP CLK[29], I2C SCL, SPI MOSI Ground Pin[31] 9 Power VSS 10 I I D+ USB D+ 11 D- USB D- 12 Power VDD Power pin ISSP DATA[29], I2C SDA, SPI CLKI[30] 13 IOHR I P1[0] 14 IOHR I P1[2] 15 IOHR I P1[4] 16 IOHR I P1[6] 17 Input XRES 18 I/O I P3[0] 19 I/O I P3[2] 20 I/O I P2[0] 21 I/O I P2[2] 22 I/O I P2[4] 23 I/O I P2[6] 24 IOH I P0[0] 25 IOH I P0[2] 26 IOH I P0[4] 27 IOH I P0[6] 28 Power VDD 29 IOH I P0[7] 30 IOH I P0[5] 31 IOH I P0[3] 32 Power VSS Vss P0 [3], AI P0 [5], AI SPI CLK , P1 [3] [29] ISSP CLK, I2C SCL, SPI MOSI,P1 [ 1 ] Optional external clock input (EXTCLK) Active high external reset with internal pull-down QFN (Top View) 32 9 6 XTAL IN , P2 [ 3 ] AI , P2[ 1 ] I2C SCL, SPI SS , P 1[ 7] I2C SDA, SPI MISO , P 1[ 5] 10 11 12 2 1 2 3 4 5 6 7 8 Vss I2C SCL, SPI SS AI , P 0[ 1] XTAL OUT, P 2 [ 5] P0 [4], AI P0 [2], AI I 26 25 I/O 24 23 22 21 20 19 18 17 15 16 4 AI, P 1[2] XTAL In P0[0] , AI P2[6] , AI P2[4] , AI P2[2] , AI P2[0] , AI P3[2] , AI P3[0] , AI XRES AI, E XTCLK, P 1[4] AI, P 1[6] XTAL Out P2[3] P0 [7], AI Vd d P0 [6], AI P2[5] I 29 I I/O 28 27 I/O 3 Integrating Input 13 14 2 P0[1] 30 I Vdd ISSP , DATA, I2C SDA, SPI CLK, P1[0] IOH Figure 8. CY8C20496A Description USB D- 1 Name [29, 30] Analog 31 Digital USB PHY, D+ Type Pin No. Power Pin Integrating Input Ground Pin[31] LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 27. 27 GPIOs = 22 pins for capacitive sensing + 2 pins for I2C + 2 pins for USB + 1 pin for modulation capacitor. 28. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 29. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 30. Alternate SPI clock. 31. All VSS pins should be brought out to one common GND plane. Document Number: 001-54459 Rev. *Y Page 15 of 53 CY8C20XX6A/S 48-pin SSOP (31 Sensing Inputs) [32] Table 7. Pin Definitions - CY8C20536A, CY8C20546A, and CY8C20566A[33] Figure 9. CY8C20536A, CY8C20546A, and CY8C20566A Pin No. Digital Analog 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 IOH IOH IOH IOH I/O I/O I/O I/O I I I I I I I I IOHR IOHR IOHR IOHR I I I I 25 IOHR I P1[0] 26 IOHR I P1[2] 27 IOHR I P1[4] 28 29 30 31 IOHR I P1[6] NC NC NC No connection No connection No connection 32 NC No connection Pin No. Digital 33 34 NC NC 41 42 I/O I/O I I P2[2] P2[4] 35 XRES No connection No connection Active high external reset with internal pull-down 43 I/O I P2[6] 44 45 46 47 48 IOH IOH IOH IOH Power I I I I P0[0] P0[2] P0[4] P0[6] VDD 36 37 38 39 40 I/O I/O I I I/O I/O I/O I/O I I I I I/O I/O I/O I/O I/O I I I I I Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] NC NC P4[3] P4[1] NC P3[7] P3[5] P3[3] P3[1] NC NC P1[7] P1[5] P1[3] P1[1] VSS Description AI, P0[7] AI, P0[5] AI, P0[3] AI P0[1] AI , P2[7] XTALOUT, P2[5] XTALIN, P2[3] AI , P2[1] NC NC AI, P4[3] AI, P4[1] NC AI, P3[7] AI, P3[5] AI, P3[3] AI, P3[1] NC NC I2 C SCL, SPI SS, P1[7] I2 C SDA, SPI MISO, P1[5 ] SPI CLK, P1[3] [33] ISSP CLK, I2 C SCL, SPI MOSI, P1[1 ] VSS Integrating Input Integrating Input XTAL Out XTAL In No connection No connection No connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD P0[6] , AI P0[4] , AI P0[2] , AI P0[0] , AI P2[6] , AI P2[4] , AI P2[2] , AI P2[0] , AI P3[6] , AI P3[4] , AI P3[2] , AI P3[0] , AI XRES NC NC NC NC NC NC P1[6] , AI P1[4] , EXT CLK P1[2] , AI [33, 34] P1[0] , ISSP DATA, I2C SDA, SPI CLK No connection No connection I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK ISSP CLK[33], I2C SCL, SPI MOSI Ground Pin[35] ISSP DATA[33], I2C SDA, SPI CLK[34] Optional external clock input (EXT CLK) P3[0] P3[2] P3[4] P3[6] P2[0] Analog Name Description VREF Power Pin LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option. Notes 32. 34 GPIOs = 31 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor. 33. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 34. Alternate SPI clock. 35. All VSS pins should be brought out to one common GND plane. Document Number: 001-54459 Rev. *Y Page 16 of 53 CY8C20XX6A/S 48-pin QFN (33 Sensing Inputs) [36] Table 8. Pin Definitions - CY8C20636A[37, 38] 17 18 19 20 21 I I I I I I I I I I I I IOHR I NC P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] NC NC P1[3] IOHR I P1[1] Power VSS DNU DNU VDD Power 22 IOHR I P1[0] 23 IOHR I P1[2] 24 IOHR I P1[4] 25 IOHR I P1[6] 26 Input XRES No connection P0[1], AI Vss P0[3], AI P0[5 ], AI P0[7], AI NC NC Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOHR IOHR Figure 10. CY8C20636A Description Crystal output (XOut) Crystal input (XIn) NC AI ,P2[7] AI , XOut,P2[5] AI , XIn ,P2[3] AI ,P2[1] AI ,P4[3] AI ,P4[1] AI ,P3[7] AI ,P3[5] AI ,P3[3] AI P3[1] AI ,I2 C SCL, SPI SS,P1[7] I2C SCL, SPI SS I2C SDA, SPI MISO No connection No connection SPI CLK ISSP CLK[37], I2C SCL, SPI MOSI Ground connection[40] 48 47 46 45 44 43 42 41 40 39 38 37 Name 1 2 3 4 5 6 7 8 9 10 11 12 QFN (Top View) 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Digital Analog 36 35 34 33 32 31 30 29 28 27 26 25 P2[6] ,AI P2[4] AI , P2[2] ,AI P2[0] AI , P4[2] ,AI P4[0] ,AI P3[6] ,AI P3[4] , AI P3[2] ,AI P3[0] , AI XRES P1[6] , AI I2C SDA, SPI MISO, A I, P1[5] NC NC SPI CLK, AI, P1[3] [37] AI, ISSP CLK, I2C SCL, SPI MOSI, P1[1] Vss DNU DNU [37, 39] Vdd AI, ISSP DATA1 , I2C SDA, SPI CLK, P1[0] AI, P 1[2] AI, EXTCLK, P1[4] Pin No. Supply voltage ISSP DATA[37], I2C SDA, SPI CLK[39] Optional external clock input (EXTCLK) Active high external reset with internal pull-down 27 28 I/O I/O I I P3[0] P3[2] 29 I/O I P3[4] Pin No. 30 31 32 33 34 35 36 37 38 39 I/O I/O I/O I/O I/O I/O I/O IOH IOH IOH I I I I I I I I I I P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] 40 41 42 43 44 45 46 47 48 CP Digital IOH IOH IOH IOH Analog I Power I I I Power IOH I Power Name P0[6] VDD NC NC P0[7] P0[5] P0[3] VSS P0[1] VSS Description Supply voltage No connection No connection Integrating input Ground connection[40] Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output. Notes 36. 36 GPIOs = 33 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor. 37. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 38. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal 39. Alternate SPI clock. 40. All VSS pins should be brought out to one common GND plane. Document Number: 001-54459 Rev. *Y Page 17 of 53 CY8C20XX6A/S 48-pin QFN (33 Sensing Inputs (With USB)) [41] Table 9. Pin Definitions - CY8C20646A, CY8C20646AS, CY8C20666A, CY8C20666AS [42, 43] Pin Figure 11. CY8C20646A, CY8C20646AS, CY8C20666A, Name Description No. Digital Analog CY8C20666AS P1[0] 23 IOHR I P1[2] 24 IOHR I P1[4] 25 IOHR I P1[6] 26 Input XRES Crystal output (XOut) Crystal input (XIn) NC AI , P2[7] AI , XOut, P2[5] AI , XIn , P2[3] AI , P2[1] AI , P4[3] AI , P4[1] AI , P3[7] AI , P3[5] AI , P3[3] AI , P3[1] AI , I2 C SCL, SPI SS, P1[7] I2C SCL, SPI SS I2C SDA, SPI MISO No connection No connection SPI CLK ISSP CLK[42], I2C SCL, SPI MOSI Ground connection[45] USB D+ USB DSupply voltage ISSP DATA[42], I2C SDA, SPI CLK[44] Vss P0[3], AI P0[5 ], AI P0[7], AI NC NC Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI I P0[1], AI IOHR No connection 48 47 46 45 44 43 42 41 40 39 38 37 22 I I I I I I I I I I I I 1 2 3 4 5 6 7 8 9 10 11 12 QFN (Top View) 13 14 15 16 17 18 19 20 21 22 23 24 IOHR I IOHR I Power I/O I/O Power NC P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] NC NC P1[3] P1[1] VSS D+ DVDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOHR IOHR 36 35 34 33 32 31 30 29 28 27 26 25 P2[6] , AI P2[4] ,AI P2[2] ,AI P2[0] ,AI P4[2] ,AI P4[0] ,AI P3[6] ,AI P3[4] , AI P3[2] ,AI P3[0] , AI XRES P1[6] , AI I2C SDA, SPI MISO, A I, P1[5] NC NC SPI CLK, A I, P1[3] [42] AI,ISSP CLK , I2C SCL, SPI MOSI, P1[1] Vss D+ DVdd [42, 44] AI,ISSP DATA, I2C SDA, SPI CLK, P1[0] AI, P1[2] AI, EXTCLK, P1[4] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Optional external clock input (EXTCLK) Active high external reset with internal pull-down 27 28 I/O I/O I I P3[0] P3[2] 29 I/O I P3[4] Pin No. 30 31 32 33 34 35 36 37 38 39 I/O I/O I/O I/O I/O I/O I/O IOH IOH IOH I I I I I I I I I I P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] 40 41 42 43 44 45 46 47 48 CP Digital IOH IOH IOH IOH Analog I Power I I I Power IOH I Power Name P0[6] VDD NC NC P0[7] P0[5] P0[3] VSS P0[1] VSS Description Supply voltage No connection No connection Integrating input Ground connection[45] Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output. Notes 41. 38 GPIOs = 33 pins for capacitive sensing + 2 pins for I2C + 2 pins for USB + 1 pin for modulation capacitor. 42. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance (5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 43. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 44. Alternate SPI clock. 45. All VSS pins should be brought out to one common GND plane. Document Number: 001-54459 Rev. *Y Page 18 of 53 CY8C20XX6A/S 48-pin QFN (OCD) (33 Sensing Inputs) [46] 17 IOHR I P1[1] 18 19 20 21 I/O I/O 22 IOHR I P1[0] 23 IOHR I P1[2] 24 IOHR I P1[4] 25 IOHR I P1[6] Power VSS D+ DVDD Power 26 Input XRES 27 28 29 30 31 32 33 34 35 I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] 36 I/O I P2[6] Crystal output (XOut) Crystal input (XIn) OCDO A E , P2[7] I AI , XOut, P2[5] AI , XIn , P2[3] AI , P2[1] AI , P4[3] AI , P4[1] AI , P3[7] AI , P3[5] AI , P3[3] AI , P3[1] AI , I2 C SCL, SPI SS, P1[7] I2C SCL, SPI SS I2C SDA, SPI MISO OCD CPU clock output OCD high speed clock output SPI CLK. ISSP CLK[50], I2C SCL, SPI MOSI Ground connection[52] USB D+ USB DSupply voltage ISSP DATA[50], I2C SDA, SPI CLK[51] Optional external clock input (EXTCLK) Active high external reset with internal pull-down OCDO Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI I OCD mode direction pin Vss P0[3], AI P0[5 ], AI P0[7], AI OCDE IOHR OCDOE P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] CCLK HCLK P1[3] 48 47 46 45 44 43 42 41 40 39 38 37 I I I I I I I I I I I I 1 2 3 4 5 6 7 8 9 10 11 12 QFN (Top View) 13 14 15 16 17 18 19 20 21 22 23 24 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOHR IOHR 36 35 34 33 32 31 30 29 28 27 26 25 P2[6] , AI P2[4] , AI P2[2] , AI P2[0] , AI P4[2] , AI P4[0] , AI P3[6] , AI P3[4] , AI P3[2] , AI P3[0] , AI XRES P1[6] , AI I2C SDA, SPI MISO, AI, P1[5] CCLK HCLK SPI CLK, A I, P1[3] [50] AI,ISSP CLK6, I2C SCL, SPI MOSI, P1[1] Vss D+ DVdd [50, 51] AI,ISSP DATA1 , I2C SDA, SPI CLK, P1[0] AI, P1[2] AI, EXTCLK, P1[4] No. 1[49] 2 3 4 5 6 7 8 9 10 11 12 13 14[49] 15[49] 16 P0[1], AI The 48-pin QFN part is for the CY8C20066A On-Chip Debug (OCD). Note that this part is only used for in-circuit debugging. Table 10. Pin Definitions - CY8C20066A [47, 48] Pin Figure 12. CY8C20066A Digital Analog Name Description Pin No. 37 Digital Analog IOH I P0[0] 38 39 IOH IOH I I P0[2] P0[4] 40 41 42[49] 43[49] 44 45 46 47 48 CP IOH I P0[6] VDD OCDO OCDE P0[7] P0[5] P0[3] VSS P0[1] VSS Power IOH IOH IOH I I I Power IOH I Power Name Description Supply voltage OCD even data I/O OCD odd data output Integrating input Ground connection[52] Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output. Notes 46. 38 GPIOs = 33 pins for capacitive sensing + 2 pins for I2C + 2 pins for USB + 1 pin for modulation capacitor. 47. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes. 48. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 49. This pin (associated with OCD part only) is required for connecting the device to ICE-Cube In-Circuit Emulator for firmware debugging purpose. To know more about the usage of ICE-Cube, refer to CY3215-DK PSoC(R) IN-CIRCUIT EMULATOR KIT GUIDE. 50. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance (5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 51. Alternate SPI clock. 52. All VSS pins should be brought out to one common GND plane. Document Number: 001-54459 Rev. *Y Page 19 of 53 CY8C20XX6A/S Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C20XX6A/S PSoC devices. For the latest electrical specifications, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc. Figure 13. Voltage versus CPU Frequency 5.5V Vdd Voltage li d ng Va rati n e io Op Reg 1.71V 750 kHz 3 MHz CPU 24 MHz Frequency Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 11. Absolute Maximum Ratings Symbol Description Conditions Min Typ Max Units Higher storage temperatures reduce data retention time. Recommended Storage Temperature is +25 C 25 C. Extended duration storage temperatures above 85 C degrades reliability. -55 +25 +125 C TSTG Storage temperature VDD Supply voltage relative to VSS - -0.5 - +6.0 V VIO DC input voltage - VSS - 0.5 - VDD + 0.5 V VIOZ[53] DC voltage applied to tristate - VSS - 0.5 - VDD + 0.5 V IMIO Maximum current into any port pin - -25 - +50 mA ESD Electrostatic discharge voltage Human body model ESD 2000 - - V LU Latch-up current In accordance with JESD78 standard - - 200 mA Operating Temperature Table 12. Operating Temperature Conditions Min Typ Max Units TA Symbol Ambient temperature - -40 - +85 C TC Commercial temperature range - 0 - 70 C The temperature rise from ambient to junction is package specific. Refer the Thermal Impedances on page 38. The user must limit the power consumption to comply with this requirement. -40 - +100 C TJ Description Operational die temperature Note 53. Port1 pins are hot-swap capable with I/O configured in High-Z mode, and pin input voltage above VDD. Document Number: 001-54459 Rev. *Y Page 20 of 53 CY8C20XX6A/S DC Chip-Level Specifications Table 13 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 13. DC Chip-Level Specifications Symbol Description Conditions Min Typ Max Units 1.71 - 5.50 V VDD[54, 55, 56, 57] Supply voltage No USB activity. Refer the table "DC POR and LVD Specifications" on page 26 VDDUSB[54, 55, 56, 57] Operating voltage USB activity, USB regulator enabled 4.35 - 5.25 V USB activity, USB regulator bypassed 3.15 3.3 3.60 V IDD24 Conditions are VDD 3.0 V, TA = 25 C, Supply current, IMO = 24 MHz CPU = 24 MHz. CapSense running at 12 MHz, no I/O sourcing current - 2.88 4.00 mA IDD12 Conditions are VDD 3.0 V, TA = 25 C, Supply current, IMO = 12 MHz CPU = 12 MHz. CapSense running at 12 MHz, no I/O sourcing current - 1.71 2.60 mA IDD6 Conditions are VDD 3.0 V, TA = 25 C, Supply current, IMO = 6 MHz CPU = 6 MHz. CapSense running at 6 MHz, no I/O sourcing current - 1.16 1.80 mA IDDAVG10 Average supply current per sensor One sensor scanned at 10 mS rate - 250 - A IDDAVG100 Average supply current per sensor One sensor scanned at 100 mS rate - 25 - A IDDAVG500 Average supply current per sensor One sensor scanned at 500 mS rate - 7 - A ISB0[58, 59, 60, 61, 62, 63] Deep sleep current VDD 3.0 V, TA = 25 C, I/O regulator turned off - 0.10 1.05 A ISB1[58, 59, 60, 61, 62, 63] Standby current with POR, LVD and sleep timer VDD 3.0 V, TA = 25 C, I/O regulator turned off - 1.07 1.50 A ISBI2C[58, 59, 60, 61, 62, 63] Standby current with I2C enabled Conditions are VDD = 3.3 V, TA = 25 C and CPU = 24 MHz - 1.64 - A Notes 54. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 s, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be slower than 1 V/500 s to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter. 55. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken: a.Bring the device out of sleep before powering down. b.Assure that VDD falls below 100 mV before powering back up. c.Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep. d.Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register. For the referenced registers, refer to the CY8C20X36 Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows VDD brown out conditions to be detected for edge rates slower than 1V/ms. 56. For USB mode, the VDD supply for bus-powered application should be limited to 4.35 V-5.35 V. For self-powered application, VDD should be 3.15 V-3.45 V. 57. For proper CapSense block functionality, if the drop in VDD exceeds 5% of the base VDD, the rate at which VDD drops should not exceed 200 mV/s. Base VDD can be between 1.8 V and 5.5 V. 58. Errata: When the device is put to sleep in Standby or I2C_USB Mode and the bandgap circuit is refreshed less frequently than every 8 ms (default), the device may not come out of sleep when a sleep-ending input is received. For more information, see the "Errata" on page 46. 59. Errata: The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is in or out of transition of sleep mode. For more information, see the "Errata" on page 46. 60. Errata: When programmable timer 0 is used in "one-shot" mode by setting bit 1 of register 0,B0h (PT0_CFG), and the timer interrupt is used to wake the device from sleep, the interrupt service routine (ISR) may be executed twice. For more information, see the "Errata" on page 47. 61. Errata: When in sleep mode, if a GPIO interrupt happens simultaneously with a Timer0 or Sleep Timer interrupt, the GPIO interrupt may be missed, and the corresponding GPIO ISR not run. For more information, see the "Errata" on page 47. 62. Errata: If an interrupt is posted a short time (within 2.5 CPU cycles) before firmware commands the device to sleep, the interrupt will be missed. For more information, see the "Errata" on page 48. 63. Errata: Device wakes up from sleep when an analog interrupt is trigger. For more information, see the "Errata" on page 48. Document Number: 001-54459 Rev. *Y Page 21 of 53 CY8C20XX6A/S DC GPIO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and -40 C TA 85 C, 2.4 V to 3.0 V and -40 C TA 85 C, or 1.71 V to 2.4 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 14. 3.0 V to 5.5 V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units - RPU Pull-up resistor 4 5.60 8 k VOH1 High output voltage Port 2 or 3 or 4 pins IOH < 10 A, maximum of 10 mA source current in all I/Os VDD - 0.20 - - V VOH2 High output voltage Port 2 or 3 or 4 pins IOH = 1 mA, maximum of 20 mA source current in all I/Os VDD - 0.90 - - V VOH3 High output voltage Port 0 or 1 pins with LDO regulator Disabled for port 1 IOH < 10 A, maximum of 10 mA source current in all I/Os VDD - 0.20 - - V VOH4 High output voltage Port 0 or 1 pins with LDO regulator Disabled for port 1 IOH = 5 mA, maximum of 20 mA source current in all I/Os VDD - 0.90 - - V VOH5 High output voltage Port 1 Pins with LDO Regulator Enabled IOH < 10 A, VDD > 3.1 V, maximum of 4 I/Os all sourcing 5 mA for 3 V out 2.85 3.00 3.30 V VOH6 High output voltage Port 1 pins with LDO regulator enabled for IOH = 5 mA, VDD > 3.1 V, maximum of 20 mA source current in all I/Os 3 V out 2.20 - - V VOH7 High output voltage IOH < 10 A, VDD > 2.7 V, maximum of 20 mA Port 1 pins with LDO enabled for 2.5 V out source current in all I/Os 2.35 2.50 2.75 V VOH8 High output voltage IOH = 2 mA, VDD > 2.7 V, maximum of 20 mA Port 1 pins with LDO enabled for 2.5 V out source current in all I/Os 1.90 - - V VOH9 High output voltage IOH < 10 A, VDD > 2.7 V, maximum of 20 mA Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os 1.60 1.80 2.10 V VOH10 High output voltage IOH = 1 mA, VDD > 2.7 V, maximum of 20 mA Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os 1.20 - - V - - 0.75 V VOL Low output voltage IOL = 25 mA, VDD > 3.3 V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]) VIL Input low voltage - - - 0.80 V VIH Input high voltage - 2.00 - - V VH Input hysteresis voltage - - 80 - mV IIL Input leakage (Absolute Value) - - 0.001 1 A 0.50 1.70 7 pF CPIN Pin capacitance Package and pin dependent Temp = 25 C VILLVT3.3 Input Low Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 0.8 V - - VIHLVT3.3 Input High Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 1.4 - - V VILLVT5.5 Input Low Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 0.8 V - - VIHLVT5.5 Input High Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 1.7 - - V Document Number: 001-54459 Rev. *Y Page 22 of 53 CY8C20XX6A/S Table 15. 2.4 V to 3.0 V DC GPIO Specifications Symbol Description Conditions Min Typ 4 5.60 8 k IOH < 10 A, maximum of 10 mA source current in all I/Os VDD - 0.20 - - V High output voltage Port 2 or 3 or 4 pins IOH = 0.2 mA, maximum of 10 mA source current in all I/Os VDD - 0.40 - - V VOH3 High output voltage Port 0 or 1 pins with LDO regulator Disabled for port 1 IOH < 10 A, maximum of 10 mA source current in all I/Os VDD - 0.20 - - V VOH4 High output voltage Port 0 or 1 pins with LDO regulator Disabled for Port 1 IOH = 2 mA, maximum of 10 mA source current in all I/Os VDD - 0.50 - - V VOH5A High output voltage IOH < 10 A, VDD > 2.4 V, maximum of Port 1 pins with LDO enabled for 1.8 V out 20 mA source current in all I/Os 1.50 1.80 2.10 V VOH6A High output voltage IOH = 1 mA, VDD > 2.4 V, maximum of 20 mA Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os 1.20 - - V - - 0.75 V 0.72 RPU Pull-up resistor - VOH1 High output voltage Port 2 or 3 or 4 pins VOH2 IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) Max Units VOL Low output voltage VIL Input low voltage - - - VIH Input high voltage - 1.40 - VH Input hysteresis voltage - - 80 - mV IIL Input leakage (absolute value) - - 1 1000 nA CPIN Capacitive load on pins Package and pin dependent Temp = 25 C 0.50 1.70 7 pF VILLVT2.5 Input Low Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 0.7 V - VIHLVT2.5 Input High Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 1.2 V V - V Table 16. 1.71 V to 2.4 V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units - 4 RPU Pull-up resistor 5.60 8 k VOH1 High output voltage Port 2 or 3 or 4 pins IOH = 10 A, maximum of 10 mA VDD - 0.20 source current in all I/Os - - V VOH2 High output voltage Port 2 or 3 or 4 pins IOH = 0.5 mA, maximum of 10 mA VDD - 0.50 source current in all I/Os - - V VOH3 High output voltage Port 0 or 1 pins with LDO regulator Disabled for Port 1 IOH = 100 A, maximum of 10 mA VDD - 0.20 source current in all I/Os - - V VOH4 High output voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 IOH = 2 mA, maximum of 10 mA source VDD - 0.50 current in all I/Os - - V VOL Low output voltage IOL = 5 mA, maximum of 20 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) - - 0.40 V VIL Input low voltage - - - 0.30 x VDD V Document Number: 001-54459 Rev. *Y Page 23 of 53 CY8C20XX6A/S Table 16. 1.71 V to 2.4 V DC GPIO Specifications (continued) Symbol Description Conditions Min Typ Max Units VIH Input high voltage - 0.65 x VDD - - V VH Input hysteresis voltage - - 80 - mV IIL Input leakage (absolute value) - - 1 1000 nA 0.50 1.70 7 pF CPIN Capacitive load on pins Package and pin dependent temp = 25 C Table 17. DC Characteristics - USB Interface Symbol Description Conditions Min Typ Max Units 900 - 1575 1425 - 3090 2.8 - 3.6 V - - - 0.3 V - 0.2 - - 0.8 - 2.5 V - 0.8 - 2.0 V RUSBI USB D+ pull-up resistance With idle bus RUSBA USB D+ pull-up resistance While receiving traffic VOHUSB Static output high VOLUSB Static output low VDI Differential input sensitivity VCM Differential input common mode range VSE Single ended receiver threshold CIN Transceiver capacitance IIO High Z state data line leakage RPS2 PS/2 pull-up resistance REXT External USB series resistor - - - - 50 pF -10 - +10 A 3000 5000 7000 21.78 22.0 22.22 On D+ or D- line - In series with each USB pin V DC Analog Mux Bus Specifications Table 18 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 18. DC Analog Mux Bus Specifications Symbol Description Conditions Min Typ Max Units RSW Switch resistance to common analog bus - - - 800 RGND Resistance of initialization switch to VSS - - - 800 The maximum pin voltage for measuring RSW and RGND is 1.8 V DC Low Power Comparator Specifications Table 19 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 19. DC Comparator Specifications Symbol Description Conditions Min Typ Max Units Maximum voltage limited to VDD 0.0 - 1.8 V VLPC Low power comparator (LPC) common mode ILPC LPC supply current - - 10 40 A VOSLPC LPC voltage offset - - 3 30 mV Document Number: 001-54459 Rev. *Y Page 24 of 53 CY8C20XX6A/S Comparator User Module Electrical Specifications Table 20 lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: -40 C TA 85 C, 1.71 V VDD 5.5 V. Table 20. Comparator User Module Electrical Specifications Symbol Min Typ Max Units 50 mV overdrive - 70 100 ns Offset Valid from 0.2 V to VDD - 0.2 V - 2.5 30 mV Current Average DC current, 50 mV overdrive - 20 80 A Supply voltage > 2 V Power supply rejection ratio - 80 - dB Supply voltage < 2 V Power supply rejection ratio - 40 - dB 1.5 V tCOMP PSRR Description Comparator response time Conditions Input range - 0 ADC Electrical Specifications Table 21. ADC User Module Electrical Specifications Symbol Description Conditions Min Typ Max Units - 0 - VREFADC V - - - 5 pF Input VIN Input voltage range CIIN Input capacitance RIN Input resistance Equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution 1/(500fF x 1/(400fF x 1/(300fF x data clock) data clock) data clock) Reference VREFADC ADC reference voltage - 1.14 - 1.26 V 2.25 - 6 MHz Conversion Rate FCLK Data clock Source is chip's internal main oscillator. See AC Chip-Level Specifications for accuracy S8 8-bit sample rate Data clock set to 6 MHz. sample rate = 0.001/ (2^Resolution/Data Clock) - 23.43 - ksps S10 10-bit sample rate Data clock set to 6 MHz. sample rate = 0.001/ (2^resolution/data clock) - 5.85 - ksps RES Resolution Can be set to 8-, 9-, or 10-bit 8 - 10 bits DNL Differential nonlinearity - -1 - +2 LSB INL Integral nonlinearity - -2 - +2 LSB EOFFSET Offset error EGAIN Gain error DC Accuracy 8-bit resolution 0 3.20 19.20 LSB 10-bit resolution 0 12.80 76.80 LSB For any resolution -5 - +5 %FSR - Power IADC PSRR Operating current Power supply rejection ratio Document Number: 001-54459 Rev. *Y - 2.10 2.60 mA PSRR (VDD > 3.0 V) - 24 - dB PSRR (VDD < 3.0 V) - 30 - dB Page 25 of 53 CY8C20XX6A/S DC POR and LVD Specifications Table 22 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 22. DC POR and LVD Specifications Symbol Description Conditions Min Typ Max Units 1.61 1.66 1.71 V - 2.36 2.41 V - 2.60 2.66 V - 2.82 2.95 V 2.45 V selected in PSoC Designer 2.40 2.45 2.51 V 2.71 V selected in PSoC Designer 2.64[64] 2.71 2.78 V VLVD2 2.92 V selected in PSoC Designer 2.85[65] 2.92 2.99 V VLVD3 3.02 V selected in PSoC Designer 2.95[66] 3.02 3.09 V VLVD4 3.13 V selected in PSoC Designer 3.06 3.13 3.20 V VLVD5 1.90 V selected in PSoC Designer 1.84 1.90 2.32 V VLVD6 1.80 V selected in PSoC Designer 1.75[67] 1.80 1.84 V VLVD7 4.73 V selected in PSoC Designer 4.62 4.73 4.83 V VPOR0 1.66 V selected in PSoC Designer VPOR1 2.36 V selected in PSoC Designer VPOR2 2.60 V selected in PSoC Designer VPOR3 2.82 V selected in PSoC Designer VLVD0 VLVD1 VDD must be greater than or equal to 1.71 V during startup, reset from the XRES pin, or reset from watchdog. - DC Programming Specifications Table 23 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 23. DC Programming Specifications Symbol VOLP Description Supply voltage for flash write operations Supply current during programming or verify Input low voltage during programming or verify Input high voltage during programming or verify Input current when Applying VILP to P1[0] or P1[1] during programming or verify Input current when applying VIHP to P1[0] or P1[1] during programming or verify Output low voltage during programming or verify VOHP Output high voltage during programming or verify FlashENPB Flash write endurance FlashDR Flash data retention VDDIWRITE IDDP VILP VIHP IILP IIHP Conditions Min Typ Max Units - 1.71 - 5.25 V - - 5 25 mA - - VIL V VIH - - V Driving internal pull-down resistor - - 0.2 mA Driving internal pull-down resistor - - 1.5 mA - - VSS + 0.75 V VOH - VDD V 50,000 - - - 20 - - Years See the appropriate DC Specifications on page 22 See the appropriate "DC Specifications" on page 22 GPIO GPIO - See appropriate DC GPIO Specifications on page 22. For VDD > 3 V use VOH4 in Table 12 on page 20. Erase/write cycles per block Following maximum Flash write cycles; ambient temperature of 55 C Notes 64. Always greater than 50 mV above VPPOR1 voltage for falling supply. 65. Always greater than 50 mV above VPPOR2 voltage for falling supply. 66. Always greater than 50 mV above VPPOR3 voltage for falling supply. 67. Always greater than 50 mV above VPPOR0 voltage for falling supply. Document Number: 001-54459 Rev. *Y Page 26 of 53 CY8C20XX6A/S DC I2C Specifications Table 24 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and -40 C TA 85 C, 2.4 V to 3.0 V and -40 C TA 85 C, or 1.71 V to 2.4 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 24. DC I2C Specifications Symbol VILI2C VIHI2C Description Input low level Input high level Conditions Min Typ Max Units 3.1 V VDD 5.5 V - - 0.25 x VDD V 2.5 V VDD 3.0 V - - 0.3 x VDD V 1.71 V VDD 2.4 V - - 0.3 x VDD V 1.71 V VDD 5.5 V 0.65 x VDD - - V DC Reference Buffer Specifications Table 25 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and -40 C TA 85 C, 2.4 V to 3.0 V and -40 C TA 85 C, or 1.71 V to 2.4 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 25. DC Reference Buffer Specifications Symbol VRef Description Reference buffer output Conditions 1.7 V VDD 5.5 V Min 1 Typ - Max 1.05 Units V VRefHi Reference buffer output 1.7 V VDD 5.5 V 1.2 - 1.25 V DC IDAC Specifications Table 26 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 26. DC IDAC Specifications Symbol IDAC_DNL IDAC_INL IDAC_Gain (Source) Description Differential nonlinearity Integral nonlinearity Range = 0.5x Range = 1x Range = 2x Range = 4x Range = 8x Document Number: 001-54459 Rev. *Y Min -4.5 -5 6.64 14.5 42.7 91.1 184.5 Typ - - - - - - - Max +4.5 +5 22.46 47.8 92.3 170 426.9 Units LSB LSB A A A A A Notes - - DAC setting = 128 dec. Not recommended for CapSense applications. DAC setting = 128 dec DAC setting = 128 dec Page 27 of 53 CY8C20XX6A/S AC Chip-Level Specifications Table 27 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 27. AC Chip-Level Specifications Conditions Min Typ Max Units FIMO24 Symbol IMO frequency at 24 MHz Setting - 22.8 24 25.2 MHz FIMO12 IMO frequency at 12 MHz setting - 11.4 12 12.6 MHz FIMO6 IMO frequency at 6 MHz setting - 5.7 6.0 6.3 MHz FCPU CPU frequency - 0.75 - 25.20 MHz F32K1 ILO frequency - 15 32 50 kHz F32K_U ILO untrimmed frequency - 13 32 82 kHz DCIMO Duty cycle of IMO - 40 50 60 % DCILO ILO duty cycle - 40 50 60 % SRPOWER_UP Power supply slew rate - - 250 V/ms tXRST External reset pulse width at power-up After supply voltage is valid 1 - - ms tXRST2 External reset pulse width after power-up[68] 10 - - s tOS Startup time of ECO - - 1 - s 6 MHz IMO cycle-to-cycle jitter (RMS) - 0.7 6.7 ns 6 MHz IMO long term N (N = 32) cycle-to-cycle jitter (RMS) - 4.3 29.3 ns 6 MHz IMO period jitter (RMS) - 0.7 3.3 ns 12 MHz IMO cycle-to-cycle jitter (RMS) - 0.5 5.2 ns 12 MHz IMO long term N (N = 32) cycle-to-cycle jitter (RMS) - 2.3 5.6 ns 12 MHz IMO period jitter (RMS) - 0.4 2.6 ns 24 MHz IMO cycle-to-cycle jitter (RMS) - 1.0 8.7 ns 24 MHz IMO long term N (N = 32) cycle-to-cycle jitter (RMS) - 1.4 6.0 ns 24 MHz IMO period jitter (RMS) - 0.6 4.0 ns tJIT_IMO[69] Description N=32 VDD slew rate during power-up Applies after part has booted Notes 68. The minimum required XRES pulse length is longer when programming the device (see Table 33 on page 31). 69. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products - AN5054 for more information. Document Number: 001-54459 Rev. *Y Page 28 of 53 CY8C20XX6A/S AC GPIO Specifications Table 28 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 28. AC GPIO Specifications Symbol FGPIO tRISE23 tRISE23L tRISE01 tRISE01L tFALL tFALLL Description Conditions GPIO operating frequency Min Typ 0 - 0 - VDD = 3.0 to 3.6 V, 10% to 90% 15 - 80 ns VDD = 1.71 to 3.0 V, 10% to 90% 15 - 80 ns 10 - 50 ns 10 - 80 ns VDD = 3.0 to 3.6 V, 10% to 90% 10 - 50 ns VDD = 1.71 to 3.0 V, 10% to 90% 10 - 70 ns Normal strong mode Port 0, 1 Rise time, strong mode, Cload = 50 pF Port 2 or 3 or 4 pins Rise time, strong mode low supply, Cload = 50 pF, Port 2 or 3 or 4 pins Rise time, strong mode, Cload = 50 pF Ports 0 or 1 Rise time, strong mode low supply, Cload = 50 pF, Ports 0 or 1 Fall time, strong mode, Cload = 50 pF all ports Fall time, strong mode low supply, Cload = 50 pF, all ports VDD = 3.0 to 3.6 V, 10% to 90% LDO enabled or disabled VDD = 1.71 to 3.0 V, 10% to 90% LDO enabled or disabled Max Units 6 MHz for MHz 1.71 V <VDD < 2.40 V 12 MHz for MHz 2.40 V < VDD< 5.50 V Figure 14. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% tRISE23 tRISE01 tRISE23L tRISE01L Document Number: 001-54459 Rev. *Y tFALL tFALLL Page 29 of 53 CY8C20XX6A/S Table 29. AC Characteristics - USB Data Timings Min Typ tDRATE Symbol Full speed data rate Description Average bit rate Conditions 12 - 0.25% 12 Max Units tJR1 Receiver jitter tolerance To next transition -18.5 - 18.5 ns tJR2 Receiver jitter tolerance To pair transition -9.0 - 9 ns tDJ1 FS Driver jitter To next transition -3.5 - 3.5 ns tDJ2 FS Driver jitter To pair transition -4.0 - 4.0 ns tFDEOP Source jitter for differential transition To SE0 transition -2.0 - 5 ns 12 + 0.25% MHz tFEOPT Source SE0 interval of EOP - 160.0 - 175 ns tFEOPR Receiver SE0 interval of EOP - 82.0 - - ns tFST Width of SE0 interval during differential transition - - - 14 ns Conditions Min Typ Max Units Table 30. AC Characteristics - USB Driver Symbol Description tFR Transition rise time 50 pF 4 - 20 ns tFF Transition fall time 50 pF 4 - 20 ns tFRFM[70] Rise/fall time matching - 90 - 111 % VCRS Output signal crossover voltage - 1.30 - 2.00 V AC Comparator Specifications Table 31 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 31. AC Low Power Comparator Specifications Symbol tLPC Description Comparator response time, 50 mV overdrive Conditions 50 mV overdrive does not include offset voltage Min Typ Max Units - - 100 ns AC External Clock Specifications Table 32 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 32. AC External Clock Specifications Symbol Description Frequency (external oscillator frequency) FOSCEXT Conditions Min Typ Max Units - 0.75 - 25.20 MHz High period - 20.60 - 5300 ns Low period - 20.60 - - ns Power-up IMO to switch - 150 - - s Note 70. TFRFM is not met under all conditions. There is a corner case at lower supply voltages, such as those under 3.3 V. This condition does not affect USB communications. Signal integrity tests show an excellent eye diagram at 3.15 V. Document Number: 001-54459 Rev. *Y Page 30 of 53 CY8C20XX6A/S AC Programming Specifications Figure 15. AC Waveform SCLK (P1[1]) T FSCLK T RSCLK SDATA (P1[0]) TSSCLK T HSCLK TDSCLK Table 33 lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 33. AC Programming Specifications Symbol tRSCLK tFSCLK tSSCLK tHSCLK FSCLK tERASEB tWRITE tDSCLK tDSCLK3 tDSCLK2 tXRST3 tXRES tVDDWAIT[71] tVDDXRES[71] tPOLL Description Conditions Rise time of SCLK - Fall time of SCLK - Data setup time to falling edge of SCLK - Data hold time from falling edge of SCLK - Frequency of SCLK - Flash erase time (block) - Flash block write time - Data out delay from falling edge of SCLK 3.6 VDD Data out delay from falling edge of SCLK 3.0 VDD 3.6 Data out delay from falling edge of SCLK 1.71 VDD 3.0 Required to enter programming External reset pulse width after power-up mode when coming out of sleep tACQ[71] XRES pulse length VDD stable to wait-and-poll hold off VDD stable to XRES assertion delay SDATA high pulse time "Key window" time after a VDD ramp acquire event, based on 256 ILO clocks. tXRESINI[71] "Key window" time after an XRES event, based on 8 ILO clocks Min 1 1 40 40 0 - - - - - Typ - - - - - - - - - - Max 20 20 - - 8 18 25 60 85 130 Units ns ns ns ns MHz ms ms ns ns ns 300 - - s - - - - 300 0.1 14.27 0.01 - - - - - 1 - 200 s ms ms ms - 3.20 - 19.60 ms - 98 - 615 s Note 71. Valid from 5 to 50 C. See the spec, CY8C20X66, CY8C20X46, CY8C20X36, CY7C643XX, CY7C604XX, CY8CTST2XX, CY8CTMG2XX, CY8C20X67, CY8C20X47, CY8C20X37, Programming Spec for more details. Document Number: 001-54459 Rev. *Y Page 31 of 53 CY8C20XX6A/S AC I2C Specifications Table 34 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 34. AC Characteristics of the I2C SDA and SCL Pins Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF tSP Description SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH Period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Bus free time between a STOP and START condition Pulse width of spikes are suppressed by the input filter Standard Mode Min Max 0 100 Fast Mode Min Max 0 400 Units kHz 4.0 - 0.6 - s 4.7 4.0 4.7 0 250 4.0 4.7 - - - - 3.45 - - - - 1.3 0.6 0.6 0 100[72] 0.6 1.3 0 - - - 0.90 - - - 50 s s s s ns s s ns Figure 16. Definition for Timing for Fast/Standard Mode on the I2C Bus Note 72. A Fast-Mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-54459 Rev. *Y Page 32 of 53 CY8C20XX6A/S Table 35. SPI Master AC Specifications Symbol Description Conditions VDD 2.4 V VDD < 2.4 V FSCLK SCLK clock frequency DC SCLK duty cycle tSETUP MISO to SCLK setup time - VDD 2.4 V VDD < 2.4 V Min Typ Max Units - - - - 6 3 MHz MHz - 50 - % 60 100 - - - - ns ns tHOLD SCLK to MISO hold time - 40 - - ns tOUT_VAL SCLK to MOSI valid time - - - 40 ns tOUT_H MOSI high time - 40 - - ns Figure 17. SPI Master Mode 0 and 2 SPI Master, modes 0 and 2 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TSETUP MISO (input) THOLD LSB MSB TOUT_SU TOUT_H MOSI (output) Figure 18. SPI Master Mode 1 and 3 SPI Master, modes 1 and 3 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TSETUP MISO (input) THOLD TOUT_SU MOSI (output) Document Number: 001-54459 Rev. *Y LSB MSB TOUT_H MSB LSB Page 33 of 53 CY8C20XX6A/S Table 36. SPI Slave AC Specifications Symbol FSCLK tLOW tHIGH tSETUP tHOLD tSS_MISO tSCLK_MISO tSS_HIGH tSS_CLK tCLK_SS Description SCLK clock frequency SCLK low time SCLK high time MOSI to SCLK setup time SCLK to MOSI hold time SS high to MISO valid SCLK to MISO valid SS high time Time from SS low to first SCLK Time from last SCLK to SS high Conditions - - - - - - - - - - Min - 42 42 30 50 - - 50 2/SCLK 2/SCLK Typ - - - - - - - - - - Max 4 - - - - 153 125 - - - Units MHz ns ns ns ns ns ns ns ns ns Figure 19. SPI Slave Mode 0 and 2 SPI Slave, modes 0 and 2 TCLK_SS TSS_CLK TSS_HIGH /SS 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TOUT_H TSS_MISO MISO (output) TSETUP MOSI (input) THOLD LSB MSB Figure 20. SPI Slave Mode 1 and 3 SPI Slave, modes 1 and 3 TSS_CLK TCLK_SS /SS 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TOUT_H TSCLK_MISO TSS_MISO MISO (output) MSB TSETUP MOSI (input) Document Number: 001-54459 Rev. *Y LSB THOLD MSB LSB Page 34 of 53 CY8C20XX6A/S Packaging Information This section illustrates the packaging specifications for the CY8C20XX6A/S PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. Figure 21. 16-pin QFN (No E-Pad) (3 x 3 x 0.6 mm) LG16A (Sawn) Package Outline, 001-09116 001-09116 *J Figure 22. 24-pin QFN (4 x 4 x 0.55 mm) LQ24A 2.65 x 2.65 E-Pad (Sawn) Package Outline, 001-13937 001-13937 *F Document Number: 001-54459 Rev. *Y Page 35 of 53 CY8C20XX6A/S Figure 23. 32-pin QFN (5 x 5 x 0.55 mm) LQ32 3.5 x 3.5 E-Pad (Sawn) Package Outline, 001-42168 001-42168 *E Figure 24. 48-pin SSOP (300 Mils) O483 Package Outline, 51-85061 51-85061 *F Document Number: 001-54459 Rev. *Y Page 36 of 53 CY8C20XX6A/S Figure 25. 48-pin QFN (7 x 7 x 1.0 mm) LT48A 5.1 x 5.1 E-Pad (Sawn) Package Outline, 001-13191 001-13191 *H Figure 26. 48-pin QFN (6 x 6 x 0.6 mm) LQ48A 4.6 x 4.6 E-Pad (Sawn) Package Outline, 001-57280 001-57280 *E Important Notes For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Pinned vias for thermal conduction are not required for the low power PSoC device. Document Number: 001-54459 Rev. *Y Page 37 of 53 CY8C20XX6A/S Thermal Impedances Table 37. Thermal Impedances per Package Typical JA [73] Typical JC 16-pin QFN (No Center Pad) 33 C/W - 24-pin QFN [74] 21 C/W - [74] 20 C/W - 69 C/W - Package 32-pin QFN 48-pin SSOP [74] 25.20 C/W 3.04 C/W 48-pin QFN (7 x 7 x 1.0 mm) [74] 18 C/W - 30-ball WLCSP 54 C/W - 48-pin QFN (6 x 6 x 0.6 mm) Capacitance on Crystal Pins Table 38. Typical Package Capacitance on Crystal Pins Package Package Capacitance 32-pin QFN 3.2 pF 48-pin QFN 3.3 pF Solder Reflow Specifications Table 39 shows the solder reflow temperature limits that must not be exceeded. Table 39. Solder Reflow Specifications Package Maximum Peak Temperature (TC) Maximum Time above TC - 5 C 16-pin QFN 260 C 30 seconds 24-pin QFN 260 C 30 seconds 32-pin QFN 260 C 30 seconds 48-pin SSOP 260 C 30 seconds 48-pin QFN (6 x 6 x 0.6 mm) 260 C 30 seconds 48-pin QFN (7 x 7 x 1.0 mm) 260 C 30 seconds 30-ball WLCSP 260 C 30 seconds Notes 73. TJ = TA + Power x JA. 74. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane. Document Number: 001-54459 Rev. *Y Page 38 of 53 CY8C20XX6A/S Development Tool Selection 28-pin CY8C29466A-24PXI PDIP PSoC Device Sample Software 28-pin CY8C27443A-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable PSoC DesignerTM At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for over half a decade. PSoC Designer is available free of charge at http://www.cypress.com. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC Programmer is available free of charge at http://www.cypress.com. CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466A-24PXI PDIP PSoC Device Sample (2) Development Kits PSoC Designer Software CD All development kits are sold at the Cypress Online Store. Getting Started Guide CY3215-DK Basic Development Kit USB 2.0 Cable The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. PSoC Designer supports the advance emulation features also. The kit includes: CY3280-20X66 Universal CapSense Controller The CY3280-20X66 CapSense Controller Kit is designed for easy prototyping and debug of CY8C20XX6A CapSense Family designs with pre-defined control circuitry and plug-in hardware. Programming hardware and an I2C-to-USB bridge are included for tuning and data acquisition. PSoC Designer Software CD The kit includes: ICE-Cube In-Circuit Emulator CY3280-20X66 CapSense Controller Board ICE Flex-Pod for CY8C29X66A Family CY3240-I2USB Bridge Cat-5 Adapter CY3210 MiniProg1 Programmer Mini-Eval Programming Board USB 2.0 Retractable Cable 110 ~ 240 V Power Supply, Euro-Plug Adapter CY3280-20X66 Kit CD iMAGEcraft C Compiler (Registration Required) Device Programmers ISSP Cable USB 2.0 Cable and Blue Cat-5 Cable All device programmers are purchased from the Cypress Online Store. 2 CY8C29466A-24PXI 28-PDIP Chip Samples CY3216 Modular Programmer Evaluation Tools All evaluation tools are sold at the Cypress Online Store. CY3210-MiniProg1 The CY3210-MiniProg1 kit enables the user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board Document Number: 001-54459 Rev. *Y The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: Modular Programmer Base Three Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide USB 2.0 Cable Page 39 of 53 CY8C20XX6A/S CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production programming environment. Note that CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240 V Power Supply, Euro-Plug Adapter USB 2.0 Cable Accessories (Emulation and Programming) Table 40. Emulation and Programming Accessories Part Number Pin Package Flex-Pod Kit[75] Foot Kit[76] Adapter[77] CY8C20236A-24LKXI 16-pin QFN (No E-Pad) CY3250-20246QFN CY3250-20246QFN-POD See note 74 CY8C20246A-24LKXI 16-pin QFN (No E-Pad) CY3250-20246QFN CY3250-20246QFN-POD See note 77 CY8C20246AS-24LKXI 16-pin QFN (No E-Pad) CY8C20336A-24LQXI 24-pin QFN CY3250-20346QFN CY3250-20346QFN-POD See note 74 CY8C20346A-24LQXI 24-pin QFN CY3250-20346QFN CY3250-20346QFN-POD See note 77 CY8C20396A-24LQXI 24-pin QFN CY8C20436A-24LQXI 32-pin QFN CY3250-20466QFN CY3250-20466QFN-POD See note 74 CY8C20446A-24LQXI 32-pin QFN CY3250-20466QFN CY3250-20466QFN-POD See note 77 CY3250-20466QFN CY3250-20466QFN-POD Not Supported Not Supported CY8C20446AS-24LQXI 32-pin QFN CY8C20466A-24LQXI 32-pin QFN Not Supported CY8C20466AS-24LQXI 32-pin QFN Not Supported CY8C20496A-24LQXI 32-pin QFN Not Supported CY8C20536A-24PVXI 48-pin SSOP CY3250-20566 CY3250-20566-POD See note 77 CY8C20546A-24PVXI 48-pin SSOP CY3250-20566 CY3250-20566-POD See note 77 CY8C20566A-24PVXI 48-pin SSOP CY3250-20566 CY3250-20566-POD See note 77 See note 77 Third Party Tools Several tools have been specially designed by third-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under Documentation > Evaluation Boards. Build a PSoC Emulator into Your Board For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, refer Application Note Debugging - Build a PSoC Emulator into Your Board - AN2323. Notes 75. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 76. Foot kit includes surface mount feet that can be soldered to the target PCB. 77. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. Document Number: 001-54459 Rev. *Y Page 40 of 53 CY8C20XX6A/S Ordering Information Table 41 lists the CY8C20XX6A/S PSoC devices' key package features and ordering codes. Table 41. PSoC Device Key Features and Ordering Information Package 16-pin (3 x 3 x 0.6 mm) QFN (no E-Pad) 16-pin (3 x 3 x 0.6 mm) QFN (no E-Pad) (Tape and Reel) 16-pin (3 x 3 x 0.6 mm) QFN (no E-Pad) 16-pin (3 x 3 x 0.6 mm) QFN (no E-Pad) 16-pin (3 x 3 x 0.6 mm) QFN (no E-Pad) (Tape and Reel) 16-pin (3 x 3 x 0.6 mm) QFN (no E-Pad) (Tape and Reel) 24-pin (4 x 4 x 0.6 mm) QFN 24-pin (4 x 4 x 0.6 mm) QFN (Tape and Reel) Ordering Code Flash SRAM CapSense Digital Analog XRES USB ADC (Bytes) (Bytes) Blocks I/O Pins Inputs [78] Pin CY8C20236A-24LKXI 8K 1K 1 13 13 Yes No Yes CY8C20236A-24LKXIT 8K 1K 1 13 13 Yes No Yes CY8C20246A-24LKXI 16K 2K 1 13 13 Yes No Yes CY8C20246AS-24LKXI 16K 2K 1 13 13 Yes No Yes CY8C20246A-24LKXIT 16K 2K 1 13 13 Yes No Yes CY8C20246AS-24LKXIT 16K 2K 1 13 13 Yes No Yes CY8C20336A-24LQXI 8K 1K 1 20 20 Yes No Yes CY8C20336A-24LQXIT 8K 1K 1 20 20 Yes No Yes CY8C20346A-24LQXI 16K 2K 1 20 20 Yes No Yes CY8C20346A-24LQXIT 16K 2K 1 20 20 Yes No Yes CY8C20346AS-24LQXIT 16K 2K 1 20 20 Yes No Yes CY8C20396A-24LQXI 16K 2K 1 19 19 Yes Yes Yes CY8C20396A-24LQXIT 16K 2K 1 19 19 Yes Yes Yes CY8C20436A-24LQXI 8K 1K 1 28 28 Yes No Yes CY8C20436A-24LQXIT 8K 1K 1 28 28 Yes No Yes 32-pin (5 x 5 x 0.6 mm) QFN CY8C20446A-24LQXI 16K 2K 1 28 28 Yes No Yes 32-pin (5 x 5 x 0.6 mm) QFN CY8C20446AS-24LQXI 16K 2K 1 28 28 Yes No Yes CY8C20446A-24LQXIT 16K 2K 1 28 28 Yes No Yes CY8C20446AS-24LQXIT 16K 2K 1 28 28 Yes No Yes 32-pin (5 x 5 x 0.6 mm) QFN CY8C20466A-24LQXI 32K 2K 1 28 28 Yes No Yes 32-pin (5 x 5 x 0.6 mm) QFN CY8C20466AS-24LQXI 32K 2K 1 28 28 Yes No Yes CY8C20466A-24LQXIT 32K 2K 1 28 28 Yes No Yes CY8C20466AS-24LQXIT 32K 2K 1 28 28 Yes No Yes 32-pin (5 x 5 x 0.6 mm) QFN CY8C20496A-24LQXI 16K 2K 1 25 25 Yes Yes Yes 32-pin (5 x 5 x 0.6 mm) QFN (Tape and Reel) CY8C20496A-24LQXIT 16K 2K 1 25 25 Yes Yes Yes 24-pin (4 x 4 x 0.6 mm) QFN 24-pin (4 x 4 x 0.6 mm) QFN (Tape and Reel) 24-pin (4 x 4 x 0.6 mm) QFN (Tape and Reel) 24-pin (4 x 4 x 0.6 mm) QFN 24-pin (4 x 4 x 0.6 mm) QFN (Tape and Reel) 32-pin (5 x 5 x 0.6 mm) QFN 32-pin (5 x 5 x 0.6 mm) QFN (Tape and Reel) 32-pin (5 x 5 x 0.6 mm) QFN (Tape and Reel) 32-pin (5 x 5 x 0.6 mm) QFN (Tape and Reel) 32-pin (5 x 5 x 0.6 mm) QFN (Tape and Reel) 32-pin (5 x 5 x 0.6 mm) QFN (Tape and Reel) Note 78. Dual-function Digital I/O Pins also connect to the common analog mux. Document Number: 001-54459 Rev. *Y Page 41 of 53 CY8C20XX6A/S Table 41. PSoC Device Key Features and Ordering Information (continued) Package 48-pin SSOP [79] CY8C20536A-24PVXI [79] 48-pin SSOP (Tape and Reel) [79] 48-pin SSOP Flash SRAM CapSense Digital Analog XRES USB ADC (Bytes) (Bytes) Blocks I/O Pins Inputs [78] Pin Ordering Code [79] [79] CY8C20536A-24PVXIT CY8C20546A-24PVXI [79] 48-pin SSOP (Tape and Reel) [79] CY8C20546A-24PVXIT [79] 48-pin SSOP [79] CY8C20566A-24PVXI [79] [79] 8K 1K 1 34 34 Yes No Yes 8K 1K 1 34 34 Yes No Yes 16K 2K 1 34 34 Yes No Yes 16K 2K 1 34 34 Yes No Yes 32K 2K 1 34 34 Yes No Yes 32K 2K 1 34 34 Yes No Yes 48-pin SSOP (Tape and Reel) [79] CY8C20566A-24PVXIT 48-pin (6 x 6 x 0.6 mm) QFN CY8C20636A-24LQXI 8K 1K 1 36 36 Yes No Yes 48-pin (6 x 6 x 0.6 mm) QFN (Tape and Reel) CY8C20636A-24LQXIT 8K 1K 1 36 36 Yes No Yes 48-pin (7 x 7 x 1.0 mm) QFN [79] CY8C20636A-24LTXI [79] 8K 1K 1 36 36 Yes No Yes 48-pin (7 x 7 x 1.0 mm) QFN (Tape and Reel) [79] CY8C20636A-24LTXIT [79] 8K 1K 1 36 36 Yes No Yes 48-pin (6 x 6 x 0.6 mm) QFN CY8C20646A-24LQXI 16K 2K 1 36 36 Yes Yes Yes 48-pin (6 x 6 x 0.6 mm) QFN (Tape and Reel) CY8C20646A-24LQXIT 16K 2K 1 36 36 Yes Yes Yes 48-pin (7 x 7 x 1.0 mm) QFN [79] CY8C20646A-24LTXI [79] 16K 2K 1 36 36 Yes Yes Yes 48-pin (7 x 7 x 1.0 mm) QFN (Tape and Reel) [79] CY8C20646A-24LTXIT [79] 16K 2K 1 36 36 Yes Yes Yes 48-pin (6 x 6 x 0.6 mm) QFN CY8C20666A-24LQXI 32K 2K 1 36 36 Yes Yes Yes 48-pin (6 x 6 x 0.6 mm) QFN (Tape and Reel) CY8C20666A-24LQXIT 32K 2K 1 36 36 Yes Yes Yes 48-pin (7 x 7 x 1.0 mm) QFN [79] CY8C20666A-24LTXI [79] 32K 2K 1 36 36 Yes Yes Yes [79] 32K 2K 1 36 36 Yes Yes Yes 48-pin (7 x 7 x 1.0 mm) QFN (Tape and Reel) [79] 48-pin (7 x 7 x 1.0 mm) QFN (Tape and Reel) [79] 48-pin (7 x 7 x 1.0 mm) QFN (OCD) [80] CY8C20666A-24LTXIT [79] 32K 2K 1 36 36 Yes Yes Yes CY8C20666AS-24LTXIT [79] 32K 2K 1 36 36 Yes Yes Yes CY8C20066A-24LTXI [80] 32K 2K 1 36 36 Yes Yes Yes 30-ball WLCSP CY8C20746A-24FDXC 16K 1K 1 27 27 Yes No Yes 30-ball WLCSP (Tape and Reel) CY8C20746A-24FDXCT 16K 1K 1 27 27 Yes No Yes 30-ball WLCSP 32K 2K 1 27 27 Yes No Yes 30-ball WLCSP (Tape and Reel) CY8C20766A-24FDXCT 32K 2K 1 27 Yes No Yes 32-pin (5 x 5 x 0.6 mm) QFN 32-pin (5 x 5 x 0.6 mm) QFN (Tape and Reel) 16-pin (3 x 3 x 0.6 mm) QFN (no E-Pad) 16-pin (3 x 3 x 0.6 mm) QFN (no E-Pad, Tape and Reel) 24-pin (4 x 4 x 0.6 mm) QFN (Tape and Reel) CY8C20436AN-24LQXI 8K 1K 1 28 27 28 Yes No No CY8C20436AN-24LQXIT 8K 1K 1 28 28 Yes No No CY8C20246AS-24LKXI 16K 2K 1 13 13 Yes No Yes CY8C20246AS-24LKXIT 16K 2K 1 13 13 Yes No Yes CY8C20346AS-24LQXIT 16K 2K 1 20 20 Yes No Yes 48-pin (7 x 7 x 1.0 mm) QFN [79] CY8C20666AS-24LTXI CY8C20766A-24FDXC Notes 79. Not Recommended for New Designs. 80. Dual-function Digital I/O Pins also connect to the common analog mux. Document Number: 001-54459 Rev. *Y Page 42 of 53 CY8C20XX6A/S Table 41. PSoC Device Key Features and Ordering Information (continued) Package 32-pin (5 x 5 x 0.6 mm) QFN 32-pin (5 x 5 x 0.6 mm) QFN (Tape and Reel) 32-pin (5 x 5 x 0.6 mm) QFN 32-pin (5 x 5 x 0.6 mm) QFN (Tape and Reel) 48-pin (6 x 6 x 0.6 mm) QFN 48-pin (6 x 6 x 0.6 mm) QFN (Tape and Reel) 48-pin (7 x 7 x 1.0 mm) QFN [81] 48-pin (7 x 7 x 1.0 mm) QFN (Tape and Reel) [81] 48-pin (6 x 6 x 0.6 mm) QFN 48-pin (6 x 6 x 0.6 mm) QFN (Tape and Reel) 48-pin (7 x 7 x 1.0 mm) QFN [81] 48-pin (7 x 7 x 1.0 mm) QFN (Tape and Reel) [81] Flash SRAM CapSense Digital Analog XRES USB ADC (Bytes) (Bytes) Blocks I/O Pins Inputs [78] Pin Ordering Code CY8C20446AS-24LQXI 16K 2K 1 28 28 Yes No Yes CY8C20446AS-24LQXIT 16K 2K 1 28 28 Yes No Yes CY8C20466AS-24LQXI 32K 2K 1 28 28 Yes No Yes CY8C20466AS-24LQXIT 32K 2K 1 28 28 Yes No Yes CY8C20666AS-24LQXI 32K 2K 1 36 36 Yes Yes Yes 32K 2K 1 36 36 Yes Yes Yes 32K 2K 1 36 36 Yes Yes Yes CY8C20666AS-24LTXIT [81] 32K 2K 1 36 36 Yes Yes Yes CY8C20646AS-24LQXI 16K 2K 1 36 36 Yes Yes Yes CY8C20646AS-24LQXIT 16K 2K 1 36 36 Yes Yes Yes 16K 2K 1 36 36 Yes Yes Yes 16K 2K 1 36 36 Yes Yes Yes CY8C20666AS-24LQXIT CY8C20666AS-24LTXI [81] CY8C20646AS-24LTXI [81] CY8C20646AS-24LTXIT [81] Ordering Code Definitions CY 8 C 20 XX6AX - 24 XX X X T Tape and Reel Temperature range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: XX = LK or LQ or PV or LT or FD LK = 16-pin QFN (no E-Pad) LQ = 24-pin QFN, 32-pin QFN, 48-pin (6 x 6 x 0.6 mm) QFN PV = 48-pin SSOP LT = 48-pin (7 x 7 x 1.0 mm) QFN FD = 30-ball WLCSP Speed Grade: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = PSoC Company ID: CY = Cypress Note 81. Not Recommended for New Designs. Document Number: 001-54459 Rev. *Y Page 43 of 53 CY8C20XX6A/S Acronyms Reference Documents Table 42. Acronyms Used in this Document Acronym Description AC alternating current ADC analog-to-digital converter API application programming interface CMOS complementary metal oxide semiconductor CPU central processing unit DAC digital-to-analog converter DC direct current EOP end of packet FSR full scale range GPIO general purpose input/output GUI graphical user interface I 2C inter-integrated circuit ICE in-circuit emulator IDAC digital analog converter current ILO internal low speed oscillator IMO internal main oscillator I/O input/output ISSP in-system serial programming LCD liquid crystal display LDO low dropout (regulator) LSB least-significant bit LVD low voltage detect MCU micro-controller unit MIPS mega instructions per second MISO master in slave out MOSI master out slave in MSB most-significant bit OCD on-chip debugger POR power on reset PPOR precision power on reset PSRR power supply rejection ratio PWRSYS power system PSoC(R) Programmable System-on-Chip SLIMO slow internal main oscillator SRAM static random access memory SNR signal to noise ratio QFN quad flat no-lead SCL serial I2C clock SDA serial I2C data SDATA serial ISSP data SPI serial peripheral interface SS slave select SSOP shrink small outline package TC test controller USB universal serial bus USB D+ USB Data+ USB D- USB Data- WLCSP wafer level chip scale package XTAL crystal Technical Reference Manual for CY8C20xx6 devices In-system Serial Programming (ISSP) protocol for 20xx6 (AN2026C) Host Sourced Serial Programming for 20xx6 devices (AN59389) Document Number: 001-54459 Rev. *Y Document Conventions Units of Measure Table 43. Units of Measure Symbol C dB fF g Hz KB Kbit KHz Ksps k MHz M A F H s W mA ms mV nA nF ns nV W pA pF pp ppm ps sps s V W Unit of Measure degree Celsius decibels femtofarad gram hertz 1024 bytes 1024 bits kilohertz kilo samples per second kilohm megahertz megaohm microampere microfarad microhenry microsecond microwatt milliampere millisecond millivolt nanoampere nanofarad nanosecond nanovolt ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volt watt Page 44 of 53 CY8C20XX6A/S Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal. Glossary Crosspoint connection Connection between any GPIO combination via analog multiplexer bus. Differential non-linearity Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one LSB apart. Differential non-linearity is a measure of the worst case deviation from the ideal 1 LSB step. Hold time Hold time is the time following a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct. I2C It is a serial multi-master bus used to connect low speed peripherals to MCU. Integral nonlinearity It is a term describing the maximum deviation between the ideal output of a DAC/ADC and the actual output level. Latch-up current Current at which the latch-up test is conducted according to JESD78 standard (at 125 degree Celsius) Power supply rejection ratio (PSRR) The PSRR is defined as the ratio of the change in supply voltage to the corresponding change in output voltage of the device. Scan The conversion of all sensor capacitances to digital values. Setup time Period required to prepare a device, machine, process, or system for it to be ready to function. Signal-to-noise ratio The ratio between a capacitive finger signal and system noise. SPI Serial peripheral interface is a synchronous serial data link standard. Document Number: 001-54459 Rev. *Y Page 45 of 53 CY8C20XX6A/S Errata This section describes the errata for the PSoC(R) CY8C20x36A/46A/66A/96A/46AS/66AS/36H/46H families. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. Qualification Status Product Status: Production released. Errata Summary The following Errata items apply to CY8C20x36A/46A/66A/96A/46AS/66AS/36H/46H families. 1. Wakeup from sleep may intermittently fail Problem Definition When the device is put to sleep in Standby or I2C_USB Mode and the bandgap circuit is refreshed less frequently than every 8 ms (default), the device may not come out of sleep when a sleep-ending input is received. Parameters Affected None Trigger Condition(S) By default, when the device is in the Standby or I2C_USB sleep modes, the bandgap circuit is powered-up approximately every 8 ms to facilitate detection of POR or LVD events. This interval can be lengthened or the periodic power-up disabled to reduce sleep current by setting the ALT_BUZZ bits in the SLP_CFG2 register or the Disable Buzz bit in the OSC_CR0 register respectively. If the bandgap circuit refresh interval is set longer than the default 8 ms, the device may fail to wakeup from sleep and enter a locked up state that can only be recovered by Watchdog Reset, XRES, or POR. Scope of Impact The trigger conditions outlined above may cause the device to never wakeup. Workaround Prior to entering Standby or I2C_USB sleep modes, do not lengthen or disable the bandgap refresh interval by manipulating the ALT_BUZZ bits in the SLP_CFG2 register or the Disable Buzz bit in the OSC_CR0 register respectively. Fix Status This issue will not be corrected in the next silicon revision. 2. I2C Errors Problem Definition The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is transitioning in to or out of sleep mode. Parameters Affected Affects reliability of I2C communication to device, and between I2C master and third party I2C slaves. Trigger Condition(S) Triggered by transitions into and out of the device's sleep mode. Scope of Impact Data errors result in incorrect data reported to the I2C master, or incorrect data received from the master by the device. Bus corruption errors can corrupt data in transactions between the I2C master and third party I2C slaves. Workaround Firmware workarounds are available in firmware. Generally the workaround consists of disconnecting the I2C block from the bus prior to going to sleep modes. I2C transactions during sleep are supported by a protocol in which the master wakes the device prior to the I2C transaction. Fix Status Changes None To be fixed in future silicon. Document Number: 001-54459 Rev. *Y Page 46 of 53 CY8C20XX6A/S 3. DoubleTimer0 ISR Problem Definition When programmable timer 0 is used in "one-shot" mode by setting bit 1 of register 0,B0h (PT0_CFG), and the timer interrupt is used to wake the device from sleep, the interrupt service routine (ISR) may be executed twice. Parameters Affected No datasheet parameters are affected. Trigger Condition(S) Triggered by enabling one-shot mode in the timer, and using the timer to wake from sleep mode. Scope of Impact The ISR may be executed twice. Workaround In the ISR, firmware should clear the one-shot bit with a statement such as "and reg[B0h], FDh" Fix Status Will not be fixed Changes None 4. Missed GPIO Interrupt Problem Definition When in sleep mode, if a GPIO interrupt happens simultaneously with a Timer0 or Sleep Timer interrupt, the GPIO interrupt may be missed, and the corresponding GPIO ISR not run. Parameters Affected No datasheet parameters are affected. Trigger Condition(S) Triggered by enabling sleep mode, then having GPIO interrupt occur simultaneously with a Timer 0 or Sleep Timer interrupt. Scope of Impact The GPIO interrupt service routine will not be run. Workaround The system should be architected such that a missed GPIO interrupt may be detected. For example, if a GPIO is used to wake the system to perform some function, the system should detect if the function is not performed, and re-issue the GPIO interrupt. Alternatively, if a GPIO interrupt is required to wake the system, then firmware should disable the Sleep Timer and Timer0. Alternatively, the ISR's for Sleep Timer and Timer0 should manually check the state of the GPIO to determine if the host system has attempted to generate a GPIO interrupt. Fix Status Will not be fixed Changes None Document Number: 001-54459 Rev. *Y Page 47 of 53 CY8C20XX6A/S 5. Missed Interrupt During Transition to Sleep Problem Definition If an interrupt is posted a short time (within 2.5 CPU cycles) before firmware commands the device to sleep, the interrupt will be missed. Parameters Affected No datasheet parameters are affected. Trigger Condition(S) Triggered by enabling sleep mode just prior to an interrupt. Scope of Impact The relevant interrupt service routine will not be run. Workaround None. Fix Status Will not be fixed Changes None 6. Wakeup from sleep with analog interrupt Problem Definition Device wakes up from sleep when an analog interrupt is trigger Parameters Affected No datasheet parameters are affected. Trigger Condition(S) Triggered by enabling analog interrupt during sleep mode when device operating temperature is 50 C or above Scope of Impact Device unexpectedly wakes up from sleep Workaround Disable the analog interrupt before entering sleep and turn it back on upon wakeup. Fix Status Will not be fixed Changes None Document Number: 001-54459 Rev. *Y Page 48 of 53 CY8C20XX6A/S Document History Page Document Title: CY8C20XX6A/S, 1.8 V Programmable CapSense(R) Controller with SmartSenseTM Auto-tuning 1-33 Buttons, 0-6 Sliders Document Number: 001-54459 Orig. of Submission Revision ECN Description of Change Change Date 2737924 SNV 07/14/2009 New silicon and document ** *A 2764528 MATT 09/16/2009 Updated AC Chip Level Specifications Updated ADC User Module Electrical Specifications table Added Note 5. Added SRPOWER_UP parameter. Updated Ordering information. Updated Capacitance on Crystal Pins *B 2803229 VZD 11/10/2009 Added "Contents" on page 4. Added Note 6 on page 20. Edited Features section to include reference to Incremental ADC. *C 2846083 DST / 01/12/2010 Updated "AC Programming Specifications" on page 31 per CDT 56531. KEJO Updated Idd typical values in "DC Chip-Level Specifications" on page 21. Added 30-pin WLCSP pin and package details. Added Contents on page 2. *D 2935141 KEJO / ISW 03/05/2010 Updated "Features" on page 1. Added "SmartSense" on page 5. / SSHH Updated "PSoC(R) Functional Overview" on page 5. Removed SNR statement regarding on page 4 (Analog Multiplexer section). Updated Additional System Resources on page 6 with the I2C enhanced slave interface point. Removed references to "system level" in "Designing with PSoC Designer" on page 9. Changed TC CLK and TC DATA to ISSP CLK and ISSP DATA respectively in all the pinouts. Modified notes in Pinouts. Updated 30-ball pin diagram. Removed IMO frequency trim options diagram in "Electrical Specifications" on page 20. Updated and formatted values in DC and AC specifications. Updated Ordering information table. Updated 48-pin SSOP package diagram. Added 30-Ball WLCSP package spec 001-50669. Removed AC Analog Mux Bus Specifications section. Added SPI Master and Slave mode diagrams. Modified Definition for Timing for Fast/Standard Mode on the I2C Bus on page 28. Updated "Thermal Impedances" on page 38. Combined Development Tools with "Development Tool Selection" on page 39. Removed references to "system level". Updated "Evaluation Tools" on page 39. Added "Ordering Code Definitions" on page 43. Updated "Acronyms" on page 44. Added Glossary and "Reference Documents" on page 44. Changed datasheet status from Preliminary to Final *E 3043291 SAAC 09/30/2010 Change: Added the line "Supports SmartSense" in the "Low power CapSense(R) block" bullet in the Features section. Impact: Helps to know that this part has the feature of Auto Tuning. Change: Replaced pod MPNs. Areas affected: Foot kit column of table 37. Change: Template and Styles update. Areas affected: Entire datasheet. Impact: Datasheet adheres to Cypress standards. *F 3071632 JPX 10/26/2010 In Table 36 on page 34, modified tLOW and tHIGH min values to 42. Updated tSS_HIGH min value to 50; removed max value. Document Number: 001-54459 Rev. *Y Page 49 of 53 CY8C20XX6A/S Document History Page (continued) Document Title: CY8C20XX6A/S, 1.8 V Programmable CapSense(R) Controller with SmartSenseTM Auto-tuning 1-33 Buttons, 0-6 Sliders Document Number: 001-54459 Orig. of Submission Revision ECN Description of Change Change Date *G 3247491 TTO / JPM / 06/16/2011 Add 4 new parameters to Table 14 on page 22, and 2 new parameters to Table ARVM / BVI 15 on page 23. Changed Typ values for the following parameters: IDD24, IDD12, IDD6, VOSLPC. Added footnote # 49 and referred it to pin numbers 1, 14, 15, 42, and 43 under Table 10 on page 19. Added footnote # 53 and referred it to parameter VIOZ under Table 11 on page 20. Added "tJIT_IMO" parameter to Table 27 on page 28. Included footnote # 69 and added reference to tJIT_IMO specification under Table 27 on page 28. Updated Solder Reflow Specifications on page 38 as per specs 25-00090 and 25-00103. ISB0 Max value changed from 0.5 A to 1.1 A in Table 13 on page 21. Added Table 26 on page 27. Updated part numbers for "SmartSense_EMC" enabled CapSense controller. 3367332 BTK / 09/09/2011 Added parameter "tOS" to Table 27 on page 28. *H SSHH / Added parameter "ISBI2C" to Table 13 on page 21. Added Table 24 on page 27. JPM / TTO / Added Table 25 on page 27. VMAD Replaced text "Port 2 or 3 pins" with "Port 2 or 3 or 4 pins" in Table 14, Table 15, Table 16, and Table 28. *I 3371807 MATT 09/30/2011 Updated Packaging Information (Updated the next revision package outline for Figure 21, Figure 24 and included a new package outline Figure 26). Updated Ordering Information (Added new part numbers CY8C20636A-24LQXI, CY8C20636A-24LQXIT, CY8C20646A-24LQXI, CY8C20646A-24LQXIT, CY8C20666A-24LQXI, CY8C20666A-24LQXIT, CY8C20666AS-24LQXI, CY8C20666AS-24LQXIT, CY8C20646AS-24LQXI and CY8C20646AS-24LQXIT). Updated to new template. *J 3401666 MATT 10/11/2011 No technical updates. *K 3414479 KPOL 10/19/2011 Removed clock stretching feature on page 1. Removed I2C enhanced slave interface point from Additional System Resources. *L 3452591 BVI / UDYG 12/01/2011 Changed document title. Updated DC Chip-Level Specifications table. Updated Solder Reflow Specifications section. Updated Getting Started and Designing with PSoC Designer sections. Included Development Tools section. Updated Software under Development Tool Selection section. *M 3473330 ANBA 12/22/2011 Updated DC Chip-Level Specifications under Electrical Specifications (updated maximum value of ISB0 parameter from 1.1 A to 1.05 A). *N 3587003 DST 04/16/2012 Added note for WLCSP package on page 1. Added Sensing inputs to pin table captions. Updated Conditions for DC Reference Buffer Specifications. Updated tJIT_IMO description in AC Chip-Level Specifications. Added note for tVDDWAIT, tVDDXRES, tACQ, and tXRESINI specs. Removed WLCSP package outline. *O 3638569 BVI 06/06/2012 Updated FSCLK parameter in the Table 36, "SPI Slave AC Specifications," on page 34. Changed tOUT_HIGH to tOUT_H in Table 35, "SPI Master AC Specifications," on page 33. Updated package diagram 001-57280 to *C revision. Document Number: 001-54459 Rev. *Y Page 50 of 53 CY8C20XX6A/S Document History Page (continued) Document Title: CY8C20XX6A/S, 1.8 V Programmable CapSense(R) Controller with SmartSenseTM Auto-tuning 1-33 Buttons, 0-6 Sliders Document Number: 001-54459 Orig. of Submission Revision ECN Description of Change Change Date *P 3774062 UBU 10/11/2012 Updated Electrical Specifications: Updated AC Chip-Level Specifications: Updated Table 27: Changed minimum value of F32K1 parameter from 19 kHz to 15 kHz. Updated Packaging Information: spec 001-09116 - Changed revision from *F to *G. spec 001-13937 - Changed revision from *D to *E. spec 51-85061 - Changed revision from *E to *F. spec 001-13191 - Changed revision from *F to *G. spec 001-57280 - Changed revision from *C to *D. *Q 3807186 PKS 15/11/2012 No content update; appended to EROS document. *R 3836626 SRLI 01/03/2013 Updated Document Title to read as "CY8C20XX6A/S, 1.8 V Programmable CapSense(R) Controller with SmartSenseTM Auto-tuning 1-33 Buttons, 0-6 Sliders". Updated Features. Updated PSoC(R) Functional Overview: Replaced "CY8C20X36A/46A/66A/96A/46AS/66AS" with "CY8C20XX6A/S". Updated Getting Started: Replaced "CY8C20X36A/46A/66A/96A/46AS/66AS" with "CY8C20XX6A/S". Updated Pinouts: Updated 16-pin QFN (10 Sensing Inputs)[3, 4]: Replaced "12 Sensing Inputs" with "10 Sensing Inputs" in heading, added Note 3 only. Updated 24-pin QFN (17 Sensing Inputs) [8]: Replaced "12 Sensing Inputs" with "17 Sensing Inputs" in heading, added Note 8 only. Updated 24-pin QFN (15 Sensing Inputs (With USB)) [13]: Replaced "18 Sensing Inputs" with "15 Sensing Inputs" in heading, added Note 13 only. Updated 30-ball WLCSP (24 Sensing Inputs) [18]: Replaced "26 Sensing Inputs" with "24 Sensing Inputs" in heading, added Note 18 only. Updated 32-pin QFN (25 Sensing Inputs) [22]: Replaced "27 Sensing Inputs" with "25 Sensing Inputs" in heading, added Note 22 only. updated 32-pin QFN (22 Sensing Inputs (With USB)) [27]: Replaced "24 Sensing Inputs" with "22 Sensing Inputs" in heading, added Note 27 only. Updated 48-pin SSOP (31 Sensing Inputs) [32]: Replaced "33 Sensing Inputs" with "31 Sensing Inputs" in heading, added Note 32 only. Updated 48-pin QFN (33 Sensing Inputs) [36]: Replaced "35 Sensing Inputs" with "33 Sensing Inputs" in heading, added Note 36 only. Updated 48-pin QFN (33 Sensing Inputs (With USB)) [41]: Replaced "35 Sensing Inputs" with "33 Sensing Inputs" in heading, added Note 41 only. Updated 48-pin QFN (OCD) (33 Sensing Inputs) [46]: Added "33 Sensing Inputs" in heading, added Note 46 only. Updated Packaging Information: spec 001-42168 - Changed revision from *D to *E. spec 001-57280 - Changed revision from *D to *E. *S 3997568 BVI 05/11/2013 Added Errata. *T 4044148 BVI 06/28/2013 Added Errata Footnotes. Updated Packaging Information: spec 001-09116 - Changed revision from *G to *H. Updated to new template. Document Number: 001-54459 Rev. *Y Page 51 of 53 CY8C20XX6A/S Document History Page (continued) Document Title: CY8C20XX6A/S, 1.8 V Programmable CapSense(R) Controller with SmartSenseTM Auto-tuning 1-33 Buttons, 0-6 Sliders Document Number: 001-54459 Orig. of Submission Revision ECN Description of Change Change Date *U 4185313 BVI 11/07/2013 Updated Features. Updated Packaging Information: spec 001-09116 - Changed revision from *H to *I. *V 4622119 SSHH 01/13/2015 Added More Information. *W 4825924 SSHH 07/07/2015 Updated Pinouts: Updated 16-pin QFN (10 Sensing Inputs)[3, 4]: Updated Table 1: Added Note 7 and referred the same note in description of VSS pin. Updated 24-pin QFN (17 Sensing Inputs) [8]: Updated Table 2: Added Note 12 and referred the same note in description of VSS pin. Updated 24-pin QFN (15 Sensing Inputs (With USB)) [13]: Updated Table 3: Added Note 17 and referred the same note in description of VSS pin. Updated 30-ball WLCSP (24 Sensing Inputs) [18]: Updated Table 4: Added Note 21 and referred the same note in description of VSS pin. Updated 32-pin QFN (25 Sensing Inputs) [22]: Updated Table 5: Added Note 26 and referred the same note in description of VSS pin. Updated 32-pin QFN (22 Sensing Inputs (With USB)) [27]: Updated Table 6: Added Note 31 and referred the same note in description of VSS pin. Updated 48-pin SSOP (31 Sensing Inputs) [32]: Updated Table 7: Added Note 35 and referred the same note in description of VSS pin. Updated 48-pin QFN (33 Sensing Inputs) [36]: Updated Table 8: Added Note 40 and referred the same note in description of VSS pin. Updated 48-pin QFN (33 Sensing Inputs (With USB)) [41]: Updated Table 9: Added Note 45 and referred the same note in description of VSS pin. Updated 48-pin QFN (OCD) (33 Sensing Inputs) [46]: Updated Table 10: Added Note 52 and referred the same note in description of VSS pin. Updated Ordering Information: Updated Table 41: Updated part numbers. Updated Packaging Information: spec 001-13937 - Changed revision from *E to *F. spec 001-13191 - Changed revision from *G to *H. *X 5394582 SSHH 08/08/2016 Updated to new template. Completing Sunset Review. *Y 5741602 SSHH 05/18/2017 Updated Development Tool Selection: Updated Accessories (Emulation and Programming): Updated Table 40: Updated part numbers. Updated Ordering Information: Updated Table 41: Updated part numbers. Updated to new template. Document Number: 001-54459 Rev. *Y Page 52 of 53 CY8C20XX6A/S Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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