ADC14DS105CISQ/NOPB - National Semiconductor

December 11, 2007

ADC14DS105

Dual 14-Bit, 105 MSPS A/D Converter with Serial LVDS

Outputs

General Description

The ADC14DS105CISQ and ADC14DS105AISQ are high-

performance CMOS analog-to-digital converters capable of

converting two analog input signals into 14-bit digital words at

rates up to 105 Mega Samples Per Second (MSPS). The dig-

ital outputs are serialized and provided on differential LVDS

signal pairs. Both parts provide excellent performance, how-

ever, the ADC14DS105AISQ offers higher SFDR. These con-

verters use a differential, pipelined architecture with digital

error correction and an on-chip sample-and-hold circuit to

minimize power consumption and the external component

count, while providing excellent dynamic performance. The

ADC14DS105 may be operated from a single +3.0V or 3.3V

power supply. A power-down feature reduces the power con-

sumption to very low levels while still allowing fast wake-up

time to full operation. The differential inputs accept a 2V full

scale differential input swing. A stable 1.2V internal voltage

reference is provided, or the ADC14DS105 can be operated

with an external 1.2V reference. The selectable duty cycle

stabilizer maintains performance over a wide range of clock

duty cycles. A serial interface allows access to the internal

registers for full control of the ADC14DS105's functionality.

The ADC14DS105 is available in a 60-lead LLP package and

operates over the industrial temperature range of −40°C to

+85°C.

Features

■Clock Duty Cycle Stabilizer

■Single +3.0V or 3.3V supply operation

■Serial LVDS Outputs

■Serial Control Interface

■Overrange outputs

■60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)

Key Specifications

■For ADC14DS105A

■Resolution 14 Bits

■Conversion Rate 105 MSPS

■SNR (fIN = 240 MHz) 70.5 dBFS (typ)

■SFDR (fIN = 240 MHz) 83 dBFS (typ)

■Full Power Bandwidth 1 GHz (typ)

■Power Consumption 1 W (typ)

Applications

■High IF Sampling Receivers

■Wireless Base Station Receivers

■Test and Measurement Equipment

■Communications Instrumentation

■Portable Instrumentation

Connection Diagram

20211201

ADC14DS105 Dual 14-Bit, 105 MSPS A/D Converter with Serial LVDS Outputs

Block Diagram

20211202

Ordering Information

Industrial (−40°C ≤ TA ≤ +85°C) Package

ADC14DS105AISQ 60 Pin LLP

(offers higher SFDR)

ADC14DS105CISQ 60 Pin LLP

ADC14DS105LFEB Evaluation Board for

input frequency < 70MHz

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ADC14DS105

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

ANALOG I/O

VINA+

VINB+

Differential analog input pins. The differential full-scale input signal

level is 2VP-P with each input pin signal centered on a common

mode voltage, VCM.

VINA-

VINB-

VRPA

VRPB

These pins should each be bypassed to AGND with a low ESL

(equivalent series inductance) 0.1 µF capacitor placed very close

to the pin to minimize stray inductance. An 0201 size 0.1 µF

capacitor should be placed between VRP and VRN as close to the

pins as possible, and a 1 µF capacitor should be placed in parallel.

VRP and VRN should not be loaded. VCMO may be loaded to 1mA

for use as a temperature stable 1.5V reference.

It is recommended to use VCMO to provide the common mode

voltage, VCM, for the differential analog inputs.

VCMOA

VCMOB

VRNA

VRNB

59 VREF

Reference Voltage. This device provides an internally developed

1.2V reference. When using the internal reference, VREF should be

decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series

inductance (ESL) capacitor.

This pin may be driven with an external 1.2V reference voltage.

This pin should not be used to source or sink current.

29 LVDS_Bias LVDS Driver Bias Resistor is applied from this pin to Analog

Ground. The nominal value is 3.6KΩ

DIGITAL I/O

18 CLK The clock input pin.

The analog inputs are sampled on the rising edge of the clock input.

28 Reset_DLL

Reset_DLL input. This pin is normally low. If the input clock

frequency is changed abruptly, the internal timing circuits may

become unlocked. Cycle this pin high for 1 microsecond to re-lock

the DLL. The DLL will lock in several microseconds after

Reset_DLL is asserted.

19 OF/DCS

This is a four-state pin controlling the input clock mode and output

data format.

OF/DCS = VA, output data format is 2's complement without duty

cycle stabilization applied to the input clock

OF/DCS = AGND, output data format is offset binary, without duty

cycle stabilization applied to the input clock.

OF/DCS = (2/3)*VA, output data is 2's complement with duty cycle

stabilization applied to the input clock

OF/DCS = (1/3)*VA, output data is offset binary with duty cycle

stabilization applied to the input clock.

Note: This signal has no effect when SPI_EN is high and the SPI

interface is enabled.

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ADC14DS105

Pin No. Symbol Equivalent Circuit Description

PD_A

PD_B

This is a two-state input controlling Power Down.

PD = VA, Power Down is enabled and power dissipation is reduced.

PD = AGND, Normal operation.

Note: This signal has no effect when SPI_EN is high and the SPI

interface is enabled. Thus, Power Down is not available when the

SPI Interface is enabled.

27 TEST

Test Mode. When this signal is asserted high, a fixed test pattern

(10100110001110 msb->lsb) is sourced at the data outputs

With this signal deasserted low, the device is in normal operation

mode. Note: This signal has no effect when SPI_EN is high and

the SPI interface is enabled.

47 WAM

Word Alignment Mode.

In single-lane mode this pin must be set to logic-0.

In dual-lane mode only, when this signal is at logic-0 the serial data

words are offset by half-word. With this signal at logic-1 the serial

data words are aligned with each other.

Note: This signal has no effect when SPI_EN is high and the SPI

interface is enabled.

48 DLC

Dual-Lane Configuration. The dual-lane mode is selected when

this signal is at logic-0. With this signal at logic-1, all data is sourced

on a single lane (SD1_x) for each channel. Note: This signal has

no effect when SPI_EN is high and the SPI interface is enabled.

OUTCLK+

OUTCLK-

Serial Clock. This pair of differential LVDS signals provides the

serial clock that is synchronous with the Serial Data outputs. A bit

of serial data is provided on each of the active serial data outputs

with each falling and rising edge of this clock. This differential

output is always enabled while the device is powered up. In power-

down mode this output is held in logic-low state. A 100-ohm

termination resistor must always be used between this pair of

signals at the far end of the transmission line.

FRAME+

FRAME-

Serial Data Frame. This pair of differential LVDS signals transitions

at the serial data word boundries. The SD1_A+/- and SD1_B+/-

output words always begin with the rising edge of the Frame signal.

The falling edge of the Frame signal defines the start of the serial

data word presented on the SD0_A+/- and SD0_B+/- signal pairs

in the Dual-Lane mode. This differential output is always enabled

while the device is powered up. In power-down mode this output is

held in logic-low state. A 100-ohm termination resistor must always

be used between this pair of signals at the far end of the

transmission line.

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ADC14DS105

Pin No. Symbol Equivalent Circuit Description

SD1_A+

SD1_A-

Serial Data Output 1 for Channel A. This is a differential LVDS pair

of signals that carries channel A ADC’s output in serialized form.

The serial data is provided synchronous with the OUTCLK output.

In Single-Lane mode each sample’s output is provided in

succession. In Dual-Lane mode every other sample output is

provided on this output. This differential output is always enabled

while the device is powered up. In power-down mode this output

holds the last logic state. A 100-ohm termination resistor must

always be used between this pair of signals at the far end of the

transmission line.

SD1_B+

SD1_B-

Serial Data Output 1 for Channel B. This is a differential LVDS pair

of signals that carries channel B ADC’s output in serialized form.

The serial data is provided synchronous with the OUTCLK output.

In Single-Lane mode each sample’s output is provided in

succession. In Dual-Lane mode every other sample output is

provided on this output. This differential output is always enabled

while the device is powered up. In power-down mode this output

holds the last logic state. A 100-ohm termination resistor must

always be used between this pair of signals at the far end of the

transmission line.

SD0_A+

SD0_A-

Serial Data Output 0 for Channel A. This is a differential LVDS pair

of signals that carries channel A ADC’s alternating samples’ output

in serialized form in Dual-Lane mode. The serial data is provided

synchronous with the OUTCLK output. In Single-Lane mode this

differential output is held in high impedance state. This differential

output is always enabled while the device is powered up. In power-

down mode this output holds the last logic state. A 100-ohm

termination resistor must always be used between this pair of

signals at the far end of the transmission line.

SD0_B+

SD0_B-

Serial Data Output 0 for Channel B. This is a differential LVDS pair

of signals that carries channel B ADC’s alternating samples’ output

in serialized form in Dual-Lane mode. The serial data is provided

synchronous with the OUTCLK output. In Single-Lane mode this

differential output is held in high impedance state. This differential

output is always enabled while the device is powered up. In power-

down mode this output holds the last logic state. A 100-ohm

termination resistor must always be used between this pair of

signals at the far end of the transmission line.

56 SPI_EN

SPI Enable: The SPI interface is enabled when this signal is

asserted high. In this case the direct control pins have no effect.

When this signal is deasserted, the SPI interface is disabled and

the direct control pins are enabled.

55 SCSb

Serial Chip Select: While this signal is asserted SCLK is used to

accept serial data present on the SDI input and to source serial

data on the SDO output. When this signal is deasserted, the SDI

input is ignored and the SDO output is in TRI-STATE mode.

52 SCLK Serial Clock: Serial data are shifted into and out of the device

synchronous with this clock signal.

54 SDI Serial Data-In: Serial data are shifted into the device on this pin

while SCSb signal is asserted.

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ADC14DS105

Pin No. Symbol Equivalent Circuit Description

53 SDO

Serial Data-Out: Serial data are shifted out of the device on this pin

while SCSb signal is asserted. This output is in TRI-STATE mode

when SCSb is deasserted.

ORA

ORB

Overrange. These CMOS outputs are asserted logic-high when

their respective channel’s data output is out-of-range in either high

or low direction.

24 DLL_Lock

DLL_Lock Output. When the internal DLL is locked to the input

CLK, this pin outputs a logic high. If the input CLK is changed

abruptly, the internal DLL may become unlocked and this pin will

output a logic low. Cycle Reset_DLL (pin 28) to re-lock the DLL to

the input CLK.

ANALOG POWER

8, 16, 17, 58,

60 VA

Positive analog supply pins. These pins should be connected to a

quiet source and be bypassed to AGND with 0.1 µF capacitors

located close to the power pins.

1, 4, 12, 15,

Exposed Pad AGND The ground return for the analog supply.

DIGITAL POWER

26, 40, 50 VDR

Positive driver supply pin for the output drivers. This pin should be

connected to a quiet voltage source and be bypassed to DRGND

with a 0.1 µF capacitor located close to the power pin.

25, 39, 51 DRGND

The ground return for the digital output driver supply. This pins

should be connected to the system digital ground, but not be

connected in close proximity to the ADC's AGND pins.

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ADC14DS105

Absolute Maximum Ratings (Notes 1, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VA, VDR) −0.3V to 4.2V
Voltage on Any Pin
  (Not to exceed 4.2V)
−0.3V to (VA +0.3V)
Input Current at Any Pin other
than Supply Pins (Note 4)
±5 mA
Package Input Current (Note 4) ±50 mA
Max Junction Temp (TJ) +150°C
Thermal Resistance (θJA)30°C/W
ESD Rating  
  Human Body Model (Note 6) 2500V
  Machine Model (Note 6) 250V
Storage Temperature −65°C to +150°C
Soldering process must comply with National
Semiconductor's Reflow Temperature Profile
specifications. Refer to www.national.com/packaging.
(Note 7)
Operating Ratings  (Notes 1, 3)
Operating Temperature −40°C ≤ TA ≤ +85°C
Supply Voltages +2.7V to +3.6V
Clock Duty Cycle  
(DCS Enabled) 30/70 %
(DCS disabled) 45/55 %
VCM 1.4V to 1.6V
|AGND-DRGND| ≤100mV
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = 3.3V, VDR = +3.0V, Internal VREF =
+1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤
TMAX. All other limits apply for TA = 25°C (Notes 8, 9)
Symbol Parameter Conditions Typical
(Note 10) Limits Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
  Resolution with No Missing Codes     14 Bits (min)
INL Integral Non Linearity  ±1.5 4LSB (max)
-4 LSB (min)
DNL Differential Non Linearity  ±0.5 1.5 LSB (max)
-0.9 LSB (min)
PGE Positive Gain Error   -0.2 ±1 %FS (max)
NGE Negative Gain Error   0.1 ±1 %FS (max)
TC PGE Positive Gain Error −40°C ≤ TA ≤ +85°C -8   ppm/°C
TC NGE Negative Gain Error −40°C ≤ TA ≤ +85°C -12   ppm/°C
VOFF Offset Error  0.15 ±0.55 %FS (max)
TC VOFF Offset Error Tempco −40°C ≤ TA ≤ +85°C 10   ppm/°C
  Under Range Output Code   0 0 
  Over Range Output Code   16383 16383  
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VCMO Common Mode Output Voltage   1.5 1.4
1.6
V (min)
V (max)
VCM Analog Input Common Mode Voltage   1.5 1.4
1.6
V (min)
V (max)
CIN
VIN Input Capacitance (each pin to GND)
(Note 11)
VIN = 1.5 Vdc
± 0.5 V
(CLK LOW) 8.5   pF
(CLK HIGH) 3.5   pF
VREF Internal Reference Voltage   1.20 1.176
1.224
V (min)
V (max)
TC VREF Internal Reference Voltage Tempco −40°C ≤ TA ≤ +85°C 18   ppm/°C
VRP Internal Reference Top   2.0    
VRN Internal Reference Bottom   1.0    
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ADC14DS105

Symbol Parameter Conditions Typical

(Note 10) Limits Units

(Limits)

Internal Reference Accuracy (VRP-VRN)1.0 0.89

1.06

V (min)

V (max)

EXT

VREF

External Reference Voltage (Note 12) 1.20 1.176

1.224

V (min)

V (max)

Dynamic Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = 3.3V, VDR = +3.0V, Internal VREF =

+1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤

TMAX. All other limits apply for TA = 25°C (Notes 8, 9)

Symbol Parameter Conditions Typical

(Note 10) Limits

Units

(Limits)

(Note 2)

DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS

FPBW Full Power Bandwidth -1 dBFS Input, −3 dB Corner 1.0 GHz

SNR Signal-to-Noise Ratio

fIN = 10 MHz 73 dBFS

fIN = 70 MHz 72.5 dBFS

fIN = 240 MHz 70.5 69 dBFS

SFDR Spurious Free Dynamic Range

(ADC14DS105AISQ)

fIN = 10 MHz 90 dBFS

fIN = 70 MHz 86 dBFS

fIN = 240 MHz 83 80 dBFS

SFDR Spurious Free Dynamic Range

(ADC14DS105CISQ)

fIN = 10 MHz 88 dBFS

fIN = 70 MHz 85 dBFS

fIN = 240 MHz 80 77.5 dBFS

ENOB Effective Number of Bits

fIN = 10 MHz 11.8 Bits

fIN = 70 MHz 11.7 Bits

fIN = 240 MHz 11.3 11 Bits

THD Total Harmonic Disortion

(ADC14DS105AISQ)

fIN = 10 MHz −86 dBFS

fIN = 70 MHz −85 dBFS

fIN = 240 MHz −80 -75 dBFS

THD Total Harmonic Disortion

(ADC14DS105CISQ)

fIN = 10 MHz -86 dBFS

fIN = 70 MHz -84 dBFS

fIN = 240 MHz -78 -75 dBFS

H2 Second Harmonic Distortion

(ADC14DS105AISQ)

fIN = 10 MHz −95 dBFS

fIN = 70 MHz −90 dBFS

fIN = 240 MHz −83 -80 dBFS

H2 Second Harmonic Distortion

(ADC14DS105CISQ)

fIN = 10 MHz -90 dBFS

fIN = 70 MHz -88 dBFS

fIN = 240 MHz -80 -77.5 dBFS

H3 Third Harmonic Distortion

(ADC14DS105AISQ)

fIN = 10 MHz −88 dBFS

fIN = 70 MHz −85 dBFS

fIN = 240 MHz −84 -80 dBFS

H3 Third Harmonic Distortion

(ADC14DS105CISQ)

fIN = 10 MHz -87 dBFS

fIN = 70 MHz -83 dBFS

fIN = 240 MHz -80 -77.5 dBFS

SINAD Signal-to-Noise and Distortion Ratio

fIN = 10 MHz 72.8 dBFS

fIN = 70 MHz 72.3 dBFS

fIN = 240 MHz 70 68 dBFS

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ADC14DS105

Logic and Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +3.0V, Internal VREF =
+1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤
TMAX. All other limits apply for TA = 25°C (Notes 8, 9)
Symbol Parameter Conditions Typical
(Note 10) Limits Units
(Limits)
DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B,SCSb,SPI_EN,SCLK,SDI,TEST,WAM,DLC)
VIN(1) Logical “1” Input Voltage VA = 3.6V  2.0 V (min)
VIN(0) Logical “0” Input Voltage VA = 3.0V  0.8 V (max)
IIN(1) Logical “1” Input Current VIN = 3.3V 10   µA
IIN(0) Logical “0” Input Current VIN = 0V −10   µA
CIN Digital Input Capacitance   5   pF
DIGITAL OUTPUT CHARACTERISTICS (ORA,ORB,SDO)
VOUT(1) Logical “1” Output Voltage IOUT = −0.5 mA , VDR = 2.7V  2.0 V (min)
VOUT(0) Logical “0” Output Voltage IOUT = 1.6 mA, VDR = 2.7V  0.4 V (max)
+ISC Output Short Circuit Source Current VOUT = 0V −10  mA
−ISC Output Short Circuit Sink Current VOUT = VDR 10   mA
COUT Digital Output Capacitance   5   pF
POWER SUPPLY CHARACTERISTICS
IAAnalog Supply Current Full Operation 240 270 mA (max)
IDR Digital Output Supply Current Full Operation 70 80 mA
  Power Consumption   1000 1130 mW (max)
  Power Down Power Consumption Clock disabled 33   mW
Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = 3.3V, VDR = +3.0V, Internal VREF =
+1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of
the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9)
Symb Parameter Conditions Typical
(Note 10) Limits Units
(Limits)
  Maximum Clock Frequency In Single-Lane Mode
In Dual-Lane Mode  65
105 MHz (max)
  Minimum Clock Frequency In Single-Lane Mode
In Dual-Lane Mode  25
52.5 MHz (min)
tCONV Conversion Latency
Single-Lane Mode
Dual-Lane, Offset Mode
Dual-Lane, Word Aligned Mode
 
7.5
8
9
Clock Cycles
tAD Aperture Delay   0.6   ns
tAJ Aperture Jitter   0.1  ps rms
Serial Control Interface Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = 3.3V, VDR = +3.0V, Internal VREF =
+1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of
the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9)
Symb Parameter Conditions Typical
(Note 10) Limits Units
(Limits)
fSCLK Serial Clock Frequency fSCLK = fCLK/10   10.5 MHz (max)
tPH SCLK Pulse Width - High % of SCLK Period   40
60
% (min)
% (max)
tPL SCLK Pulse Width - Low % of SCLK Period   40
60
% (min)
% (max)
tSU SDI Setup Time     5 ps (min)
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ADC14DS105

Symb Parameter Conditions Typical

(Note 10) Limits Units

(Limits)

tHSDI Hold Time 5 ns (min)

tODZ SDO Driven-to-Tri-State Time 40 50 ns (max)

tOZD SDO Tri-State-to-Driven Time 15 20 ns (max)

tOD SDO Output Delay Time 15 20 ns (max)

tCSS SCSb Setup Time 5 10 ns (min)

tCSH SCSb Hold Time 5 10 ns (min)

tIAG Inter-Access Gap Minimum time SCSb must be deasserted

between accesses 3 Cycles of

SCLK

LVDS Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = 3.3V, VDR = +3.0V, Internal VREF =

+1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of

the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9)

Symbol Parameter Conditions Typical

(Note 10) Limits Units

(Limits)

LVDS DC CHARACTERISTICS

VOD

Output Differential Voltage

(SDO+) - (SDO-) RL = 100Ω 350 250

450

mV (min)

mV (max)

delta

VOD

Output Differential Voltage Unbalance RL = 100Ω ±25 mV (max)

VOS Offset Voltage RL = 100Ω 1.25 1.125

1.375

V (min)

V (max)

delta VOS Offset Voltage Unbalance RL = 100Ω ±25 mV (max)

IOS Output Short Circuit Current DO = 0V, VIN = 1.1V, -10 mA (max)

LVDS OUTPUT TIMING AND SWITCHING CHARACTERISTICS

tDP Output Data Bit Period Dual-Lane Mode 1.36 ns

tHO

Output Data Edge to Output Clock Edge

Hold Time (Note 12) Dual-Lane Mode 680 300 ps (min)

tSUO

Output Data Edge to Output Clock Edge

Set-Up Time (Note 12) Dual-Lane Mode 640 300 ps (min)

tFP Frame Period Dual-Lane Mode 19.05 ns

tFDC Frame Clock Duty Cycle (Note 12) 50 45

% (min)

% (max)

tDFS Data Edge to Frame Edge Skew 50% to 50% 15 ps

tODOR Output Delay of OR output From rising edge of CLKL to ORA/ORB

valid 4 ns

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.

The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under

the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.

Note 2: This parameter is specified in units of dBFS - indicating the value that would be attained with a full-scale input signal.

Note 3: All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.

Note 4: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to ±5 mA. The

±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10.

Note 5: The maximum allowable power dissipation is dictated by TJ,max, the junction-to-ambient thermal resistance, (θJA), and the ambient temperature, (TA), and

can be calculated using the formula PD,max = (TJ,max - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the device is

operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such

conditions should always be avoided.

Note 6: Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0 Ω

Note 7: Reflow temperature profiles are different for lead-free and non-lead-free packages.

Note 8: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per

(Note 4). However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section.

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ADC14DS105

20211211

Note 9: With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV.

Note 10: Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not

guaranteed.

Note 11: The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.

Note 12: This parameter is guaranteed by design and/or characterization and is not tested in production.

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ADC14DS105

Specification Definitions

APERTURE DELAY is the time after the rising edge of the

clock to when the input signal is acquired or held for conver-

sion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the

variation in aperture delay from sample to sample. Aperture

jitter manifests itself as noise in the output.

CLOCK DUTY CYCLE is the ratio of the time during one cycle

that a repetitive digital waveform is high to the total time of

one period. The specification here refers to the ADC clock

input signal.

COMMON MODE VOLTAGE (VCM) is the common DC volt-

age applied to both input terminals of the ADC.

CONVERSION LATENCY is the number of clock cycles be-

tween initiation of conversion and when that data is presented

to the output driver stage. New data is available at every clock

cycle, but the data lags the conversion by the pipeline delay.

CROSSTALK is coupling of energy from one channel into the

other channel.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion Ratio or SINAD. ENOB is defined as (SINAD -

1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the

transfer function. It can be calculated as:

Gain Error = Positive Full Scale Error − Negative Full Scale

Error

It can also be expressed as Positive Gain Error and Negative

Gain Error, which are calculated as:

PGE = Positive Full Scale Error - Offset Error

NGE = Offset Error - Negative Full Scale Error

INTEGRAL NON LINEARITY (INL) is a measure of the de-

viation of each individual code from a best fit straight line. The

deviation of any given code from this straight line is measured

from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of

additional spectral components as a result of two sinusoidal

frequencies being applied to the ADC input at the same time.

It is defined as the ratio of the power in the intermodulation

products to the total power in the original frequencies. IMD is

usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-

est value or weight of all bits. This value is VFS/2n, where

“VFS” is the full scale input voltage and “n” is the ADC reso-

lution in bits.

LVDS Differential Output Voltage (VOD) is the absolute val-

ue of the difference between the differential output pair volt-

ages (VD+ and VD-), each measured with respect to ground.

LVDS Output Offset Voltage (VOS) is the midpoint between

the differential output pair voltages.

MISSING CODES are those output codes that will never ap-

pear at the ADC outputs. The ADC is guaranteed not to have

any missing codes.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest

value or weight. Its value is one half of full scale.

NEGATIVE FULL SCALE ERROR is the difference between

the actual first code transition and its ideal value of ½ LSB

above negative full scale.

OFFSET ERROR is the difference between the two input

voltages [(VIN+) – (VIN-)] required to cause a transition from

code 8191 to 8192.

OUTPUT DELAY is the time delay after the falling edge of the

clock before the data update is presented at the output pins.

PIPELINE DELAY (LATENCY) See CONVERSION LATEN-

CY.

POSITIVE FULL SCALE ERROR is the difference between

the actual last code transition and its ideal value of 1½ LSB

below positive full scale.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure

of how well the ADC rejects a change in the power supply

voltage. PSRR is the ratio of the Full-Scale output of the ADC

with the supply at the minimum DC supply limit to the Full-

Scale output of the ADC with the supply at the maximum DC

supply limit, expressed in dB.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal to the rms value of the

sum of all other spectral components below one-half the sam-

pling frequency, not including harmonics or DC.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or

SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral com-

ponents below half the clock frequency, including harmonics

but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the rms values of the input

signal and the peak spurious signal, where a spurious signal

is any signal present in the output spectrum that is not present

at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-

pressed in dB, of the rms total of the first six harmonic levels

at the output to the level of the fundamental at the output. THD

is calculated as

where f1 is the RMS power of the fundamental (output) fre-

quency and f2 through f7 are the RMS power of the first six

harmonic frequencies in the output spectrum.

SECOND HARMONIC DISTORTION (2ND HARM) is the dif-

ference expressed in dB, between the RMS power in the input

frequency at the output and the power in its 2nd harmonic

level at the output.

THIRD HARMONIC DISTORTION (3RD HARM) is the dif-

ference, expressed in dB, between the RMS power in the

input frequency at the output and the power in its 3rd harmonic

level at the output.

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ADC14DS105

Timing Diagrams

20211214

FIGURE 1. Serial Output Data Timing

20211217

FIGURE 2. Serial Output Data Format in Single-Lane Mode

13 www.national.com

ADC14DS105

20211218

FIGURE 3. Serial Output Data Format in Dual-Lane Mode

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ADC14DS105

Transfer Characteristic

20211210

FIGURE 4. Transfer Characteristic

15 www.national.com

ADC14DS105

Typical Performance Characteristics DNL, INL Unless otherwise specified, the following

specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +3.0V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle,

DCS disabled, VCM = VCMO, TA = 25°C.

DNL

20211241

INL

20211242

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ADC14DS105

Typical Performance Characteristics Unless otherwise specified, the following specifications apply:

AGND = DRGND = 0V, VA = +3.3V, VDR = +3.0V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM =

VCMO, fIN = 40 MHz, TA = 25°C.

SNR, SINAD, SFDR vs. VA

20211251

Distortion vs. VA

20211252

SNR, SINAD, SFDR vs. Clock Duty Cycle

20211257

Distortion vs. Clock Duty Cycle

20211258

SNR, SINAD, SFDR vs. Clock Duty Cycle, DCS Enabled

20211259

Distortion vs. Clock Duty Cycle, DCS Enabled

20211260

17 www.national.com

ADC14DS105

Spectral Response @ 10 MHz Input

20211268

Spectral Response @ 70 MHz Input

20211269

Spectral Response @ 240 MHz Input

20211270

IMD, fIN1 = 20 MHz, fIN2 = 21 MHz

20211271

www.national.com 18

ADC14DS105

Functional Description

Operating on a single +3.3V supply, the ADC14DS105 digi-

tizes two differential analog input signals to 14 bits, using a

differential pipelined architecture with error correction circuitry

and an on-chip sample-and-hold circuit to ensure maximum

performance. The user has the choice of using an internal

1.2V stable reference, or using an external 1.2V reference.

Any external reference is buffered on-chip to ease the task of

driving that pin. Duty cycle stabilization and output data format

are selectable using the quad state function OF/DCS pin (pin

19). The output data can be set for offset binary or two's com-

plement.

Applications Information

1.0 OPERATING CONDITIONS

We recommend that the following conditions be observed for

operation of the ADC14DS105:

2.7V ≤ VA ≤ 3.6V

2.7V ≤ VDR ≤ VA

25 MHz ≤ fCLK ≤ 105 MHz

1.2V internal reference

VREF = 1.2V (for an external reference)

VCM = 1.5V (from VCMO)

2.0 ANALOG INPUTS

2.1 Signal Inputs

2.1.1 Differential Analog Input Pins

The ADC14DS105 has a pair of analog signal input pins for

each of two channels. VIN+ and VIN− form a differential input

pair. The input signal, VIN, is defined as

VIN = (VIN+) – (VIN−)

Figure 5 shows the expected input signal range. Note that the

common mode input voltage, VCM, should be 1.5V. Using

VCMO (pins 7,9) for VCM will ensure the proper input common

mode level for the analog input signal. The positive peaks of

the individual input signals should each never exceed 2.6V.

Each analog input pin of the differential pair should have a

maximum peak-to-peak voltage of 1V, be 180° out of phase

with each other and be centered around VCM.The peak-to-

peak voltage swing at each analog input pin should not ex-

ceed the 1V or the output data will be clipped.

20211280

FIGURE 5. Expected Input Signal Range

For single frequency sine waves the full scale error in LSB

can be described as approximately

EFS = 16384 ( 1 - sin (90° + dev))

Where dev is the angular difference in degrees between the

two signals having a 180° relative phase relationship to each

other (see Figure 6). For single frequency inputs, angular er-

rors result in a reduction of the effective full scale input. For

complex waveforms, however, angular errors will result in

distortion.

20211281

FIGURE 6. Angular Errors Between the Two Input Signals

Will Reduce the Output Level or Cause Distortion

It is recommended to drive the analog inputs with a source

impedance less than 100Ω. Matching the source impedance

for the differential inputs will improve even ordered harmonic

performance (particularly second harmonic).

Table 1indicates the input to output relationship of the AD-

C14DS105.

19 www.national.com

ADC14DS105

TABLE 1. Input to Output Relationship

VIN+VIN−Binary Output 2’s Complement Output

VCM − VREF/2 VCM + VREF/2 00 0000 0000 0000 10 0000 0000 0000 Negative Full-Scale

VCM − VREF/4 VCM + VREF/4 01 0000 0000 0000 11 0000 0000 0000

VCM VCM 10 0000 0000 0000 00 0000 0000 0000 Mid-Scale

VCM + VREF/4 VCM − VREF/4 11 0000 0000 0000 01 0000 0000 0000

VCM + VREF/2 VCM − VREF/2 11 1111 1111 1111 01 1111 1111 1111 Positive Full-Scale

2.1.2 Driving the Analog Inputs

The VIN+ and the VIN− inputs of the ADC14DS105 have an

internal sample-and-hold circuit which consists of an analog

switch followed by a switched-capacitor amplifier.

Figure 7 and Figure 8 show examples of single-ended to dif-

ferential conversion circuits. The circuit in Figure 7 works well

for input frequencies up to approximately 70MHz, while the

circuit in Figure 8 works well above 70MHz.

20211282

FIGURE 7. Low Input Frequency Transformer Drive Circuit

20211283

FIGURE 8. High Input Frequency Transformer Drive Circuit

One short-coming of using a transformer to achieve the sin-

gle-ended to differential conversion is that most RF trans-

formers have poor low frequency performance. A differential

amplifier can be used to drive the analog inputs for low fre-

quency applications. The amplifier must be fast enough to

settle from the charging glitches on the analog input resulting

from the sample-and-hold operation before the clock goes

high and the sample is passed to the ADC core.

2.1.3 Input Common Mode Voltage

The input common mode voltage, VCM, should be in the range

of 1.4V to 1.6V and be a value such that the peak excursions

of the analog signal do not go more negative than ground or

more positive than 2.6V. It is recommended to use VCMO (pins

7,9) as the input common mode voltage.

2.2 Reference Pins

The ADC14DS1050 is designed to operate with an internal or

external 1.2V reference. The internal 1.2 Volt reference is the

default condition when no external reference input is applied

to the VREF pin. If a voltage is applied to the VREF pin, then

that voltage is used for the reference. The VREF pin should

always be bypassed to ground with a 0.1 µF capacitor close

to the reference input pin.

It is important that all grounds associated with the reference

voltage and the analog input signal make connection to the

ground plane at a single, quiet point to minimize the effects of

noise currents in the ground path.

The Reference Bypass Pins (VRP, VCMO, and VRN) for chan-

nels A and B are made available for bypass purposes. These

pins should each be bypassed to AGND with a low ESL

(equivalent series inductance) 1 µF capacitor placed very

close to the pin to minimize stray inductance. A 0.1 µF ca-

pacitor should be placed between VRP and VRN as close to

the pins as possible, and a 1 µF capacitor should be placed

in parallel. This configuration is shown in Figure 9. It is nec-

essary to avoid reference oscillation, which could result in

reduced SFDR and/or SNR. VCMO may be loaded to 1mA for

use as a temperature stable 1.5V reference. The remaining

pins should not be loaded.

Smaller capacitor values than those specified will allow faster

recovery from the power down mode, but may result in de-

www.national.com 20

ADC14DS105

graded noise performance. Loading any of these pins, other

than VCMO may result in performance degradation.

The nominal voltages for the reference bypass pins are as

follows:

VCMO = 1.5 V

VRP = 2.0 V

VRN = 1.0 V

2.3 OF/DCS Pin

Duty cycle stabilization and output data format are selectable

using this quad state function pin. When enabled, duty cycle

stabilization can compensate for clock inputs with duty cycles

ranging from 30% to 70% and generate a stable internal clock,

improving the performance of the part. With OF/DCS = VA the

output data format is 2's complement and duty cycle stabi-

lization is not used. With OF/DCS = AGND the output data

format is offset binary and duty cycle stabilization is not used.

With OF/DCS = (2/3)*VA the output data format is 2's com-

plement and duty cycle stabilization is applied to the clock. If

OF/DCS is (1/3)*VA the output data format is offset binary and

duty cycle stabilization is applied to the clock. While the sense

of this pin may be changed "on the fly," doing this is not rec-

ommended as the output data could be erroneous for a few

clock cycles after this change is made.

Note: This signal has no effect when SPI_EN is high and the

serial control interface is enabled.

3.0 DIGITAL INPUTS

Digital CMOS compatible inputs consist of CLK, and PD_A,

PD_B, Reset_DLL, DLC, TEST, WAM, SPI_EN, SCSb,

SCLK, and SDI.

3.1 Clock Input

The CLK controls the timing of the sampling process. To

achieve the optimum noise performance, the clock input

should be driven with a stable, low jitter clock signal in the

range indicated in the Electrical Table. The clock input signal

should also have a short transition region. This can be

achieved by passing a low-jitter sinusoidal clock source

through a high speed buffer gate. The trace carrying the clock

signal should be as short as possible and should not cross

any other signal line, analog or digital, not even at 90°.

The clock signal also drives an internal state machine. If the

clock is interrupted, or its frequency is too low, the charge on

the internal capacitors can dissipate to the point where the

accuracy of the output data will degrade. This is what limits

the minimum sample rate.

The clock line should be terminated at its source in the char-

acteristic impedance of that line. Take care to maintain a

constant clock line impedance throughout the length of the

line. Refer to Application Note AN-905 for information on set-

ting characteristic impedance.

It is highly desirable that the the source driving the ADC clock

pins only drive that pin. However, if that source is used to drive

other devices, then each driven pin should be AC terminated

with a series RC to ground, such that the resistor value is

equal to the characteristic impedance of the clock line and the

capacitor value is

where tPD is the signal propagation rate down the clock line,

"L" is the line length and ZO is the characteristic impedance

of the clock line. This termination should be as close as pos-

sible to the ADC clock pin but beyond it as seen from the clock

source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4

board material. The units of "L" and tPD should be the same

(inches or centimeters).

The duty cycle of the clock signal can affect the performance

of the A/D Converter. Because achieving a precise duty cycle

is difficult, the ADC14DS105 has a Duty Cycle Stabilizer.

3.2 Power-Down (PD_A and PD_B)

The PD_A and PD_B pins, when high, hold the respective

channel of the ADC14DS105 in a power-down mode to con-

serve power when that channel is not being used. The chan-

nels may be powereed down individually or together. The data

in the pipeline is corrupted while in the power down mode.

The Power Down Mode Exit Cycle time is determined by the

value of the components on the reference bypass pins

( VRP, VCMO and VRN ). These capacitors loose their charge

in the Power Down mode and must be recharged by on-chip

circuitry before conversions can be accurate. Smaller capac-

itor values allow slightly faster recovery from the power down

mode, but can result in a reduction in SNR, SINAD and ENOB

performance.

Note: This signal has no effect when SPI_EN is high and the

serial control interface is enabled.

3.3 Reset_DLL

This pin is normally low. If the input clock frequency is

changed abruptly, the internal timing circuits may become

unlocked. Cycle this pin high for 1 microsecond to re-lock the

DLL. The DLL will lock in several microseconds after

Reset_DLL is asserted.

3.4 DLC

This pin sets the output data configuration. With this signal at

logic-1, all data is sourced on a single lane (SD1_x) for each

channel. When this signal is at logic-0, the data is sourced on

dual lanes (SD0_x and SD1_x) for each channel. This sim-

plifies data capture at higher data rates.

Note: This signal has no effect when SPI_EN is high and the

SPI interface is enabled.

3.5 TEST

When this signal is asserted high, a fixed test pattern

(10100110001110 msb->lsb) is sourced at the data outputs.

When low, the ADC is in normal operation. The user may

specify a custom test pattern via the serial control interface.

Note: This signal has no effect when SPI_EN is high and the

SPI interface is enabled.

3.6 WAM

In dual-lane mode only, when this signal is at logic-0 the serial

data words are offset by half-word. With this signal at logic-1

the serial data words are aligned with each other. In single

lane mode this pin must be set to logic-0.

Note: This signal has no effect when SPI_EN is high and the

SPI interface is enabled.

3.7 SPI_EN

The SPI interface is enabled when this signal is asserted high.

In this case the direct control pins (OF/DCS, PD_A, PD_B,

DLC, WAM, TEST) have no effect. When this signal is de-

asserted, the SPI interface is disabled and the direct control

pins are enabled.

21 www.national.com

ADC14DS105

3.8 SCSb, SDI, SCLK

These pins are part of the SPI interface. See Section 5.0 for

more information.

4.0 DIGITAL OUTPUTS

Digital outputs consist of six LVDS signal pairs (SD0_A,

SD1_A, SD0_B, SD1_B, OUTCLK, FRAME) and CMOS logic

outputs ORA, ORB, DLL_Lock, and SDO.

4.1 LVDS Outputs

The digital data for each channel is provided in a serial format.

Two modes of operation are available for the serial data for-

mat. Single-lane serial format (shown in Figure 2) uses one

set of differential data signals per channel. Dual-lane serial

format (shown in Figure 3) uses two sets of differential data

signals per channel in order to slow down the data and clock

frequency by a factor of 2. At slower rates of operation (typi-

cally below 65 MSPS) the single-lane mode may the most

efficient to use. At higher rates the user may want to employ

the dual-lane scheme. In either case DDR-type clocking is

used. For each data channel, an overrange indication is also

provided. The OR signal is updated with each frame of data.

4.2 ORA, ORB

These CMOS outputs are asserted logic-high when their re-

spective channel’s data output is out-of-range in either high

or low direction.

4.3 DLL_Lock

When the internal DLL is locked to the input CLK, this pin

outputs a logic high. If the input CLK is changed abruptly, the

internal DLL may become unlocked and this pin will output a

logic low. Cycle Reset_DLL to re-lock the DLL to the input

CLK.

4.4 SDO

This pin is part of the SPI interface. See Section 5.0 for more

information.

20211285

FIGURE 9. Application Circuit

5.0 Serial Control Interface

The ADC14DS105 has a serial interface that allows access

to the control registers. The serial interface is a generic 4-wire

synchronous interface that is compatible with SPI type inter-

faces that are used on many microcontrollers and DSP con-

trollers.

The ADC's input clock must be running for the Serial Control

Interface to operate. It is enabled when the SPI_EN (pin 56)

signal is asserted high. In this case the direct control pins (OF/

DCS, PD_A, PD_B, DLC, WAM, TEST) have no effect. When

this signal is deasserted, the SPI interface is disabled and the

direct control pins are enabled.

Each serial interface access cycle is exactly 16 bits long. Fig-

ure 10 shows the access protocol used by this interface. Each

signal's function is described below. The Read Timing is

shown in Figure 11, while the Write Timing is shown in Figure

www.national.com 22

ADC14DS105

20211219

FIGURE 10. Serial Interface Protocol

SCLK: Used to register the input data (SDI) on the rising

edge; and to source the output data (SDO) on the falling edge.

User may disable clock and hold it in the low-state, as long as

clock pulse-width min spec is not violated when clock is en-

abled or disabled.

SCSb: Serial Interface Chip Select. Each assertion starts a

new register access - i.e., the SDATA field protocol is re-

quired. The user is required to deassert this signal after the

16th clock. If the SCSb is deasserted before the 16th clock,

no address or data write will occur. The rising edge captures

the address just shifted-in and, in the case of a write opera-

tion, writes the addressed register. There is a minimum pulse-

width requirement for the deasserted pulse - which is

specified in the Electrical Specifications section.

SDI: Serial Data. Must observe setup/hold requirements with

respect to the SCLK. Each cycle is 16-bits long.

R/Wb: A value of '1' indicates a read operation, while a

value of '0' indicates a write operation.

Reserved: Reserved for future use. Must be set to 0.

ADDR: Up to 3 registers can be addressed.

DATA: In a write operation the value in this field will be

written to the register addressed in this cycle

when SCSb is deasserted. In a read operation

this field is ignored.

SDO: This output is normally at TRI-STATE and is driven only

when SCSb is asserted. Upon SCSb assertion, contents of

the register addressed during the first byte are shifted out with

the second 8 SCLK falling edges. Upon power-up, the default

23 www.national.com

ADC14DS105

20211216

FIGURE 11. Read Timing

20211215

FIGURE 12. Write Timing

Device Control Register, Address 0h

7 6 5 4 3 2 1 0

OM DLC DCS OF WAM PD_A PD_B

Reset State : 08h

Bits (7:6) Operational Mode

0 0 Normal Operation.

0 1 Test Output mode. A fixed test pattern

(10100110001110 msb->lsb) is sourced at the

data outputs.

1 0 Test Output mode. Data pattern defined by

user in registers 01h and 02h is sourced at data

outputs.

1 1 Reserved.

Bit 5 Data Lane Configuration. When this bit is set to '0',

the serial data interface is configured for dual-lane

mode where the data words are output on two data

outputs (SD1 and SD0) at half the rate of the

single-lane interface. When this bit is set to ‘1’,

serial data is output on the SD1 output only and

the SD0 outputs are held in a high-impedance

state

Bit 4 Duty Cycle Stabilizer. When this bit is set to '0' the

DCS is off. When this bit is set to ‘1’, the DCS is

on.

Bit 3 Output Data Format. When this bit is set to ‘1’ the

data output is in the “twos complement” form.

When this bit is set to ‘0’ the data output is in the

“offset binary” form.

Bit 2 Word Alignment Mode.

This bit must be set to '0' in the single-lane mode

of operation.

In dual-lane mode, when this bit is set to '0' the

serial data words are offset by half-word. This

gives the least latency through the device. When

this bit is set to '1' the serial data words are in

word-aligned mode. In this mode the serial data

on the SD1 lane is additionally delayed by one

CLK cycle. (Refer to Figure 3).

Bit 1 Power-Down Channel A. When this bit is set to '1',

Channel A is in power-down state and Normal

operation is suspended.

Bit 0 Power-Down Channel B. When this bit is set to '1',

Channel B is in power-down state and Normal

operation is suspended.

User Test Pattern Register 0, Address 1h

7 6 5 4 3 2 1 0

Reserved User Test Pattern (13:8)

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ADC14DS105

Reset State : 00h

Bits (7:6) Reserved. Must be set to '0'.

Bits (5:0) User Test Pattern. Most-significant 6 bits of the

14-bit pattern that will be sourced out of the data

outputs in Test Output Mode.

User Test Pattern Register 1, Address 2h

76543210

User Test Pattern (7:0)

Reset State : 00h

Bits (7:0) User Test Pattern. Least-significant 8 bits of the

14-bit pattern that will be sourced out of the data

outputs in Test Output Mode.

6.0 POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 0.1 µF ca-

pacitor and with a 100 pF ceramic chip capacitor close to each

power pin. Leadless chip capacitors are preferred because

they have low series inductance.

As is the case with all high-speed converters, the AD-

C14DS105 is sensitive to power supply noise. Accordingly,

the noise on the analog supply pin should be kept below 100

mVP-P.

No pin should ever have a voltage on it that is in excess of the

supply voltages, not even on a transient basis. Be especially

careful of this during power turn on and turn off.

7.0 LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essen-

tial to ensure accurate conversion. Maintaining separate ana-

log and digital areas of the board, with the ADC14DS105

between these areas, is required to achieve specified perfor-

mance.

Capacitive coupling between the typically noisy digital circuit-

ry and the sensitive analog circuitry can lead to poor perfor-

mance. The solution is to keep the analog circuitry separated

from the digital circuitry, and to keep the clock line as short as

possible.

Since digital switching transients are composed largely of

high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise.

This is because of the skin effect. Total surface area is more

important than is total ground plane area.

Generally, analog and digital lines should cross each other at

90° to avoid crosstalk. To maximize accuracy in high speed,

high resolution systems, however, avoid crossing analog and

digital lines altogether. It is important to keep clock lines as

short as possible and isolated from ALL other lines, including

other digital lines. Even the generally accepted 90° crossing

should be avoided with the clock line as even a little coupling

can cause problems at high frequencies. This is because oth-

er lines can introduce jitter into the clock line, which can lead

to degradation of SNR. Also, the high speed clock can intro-

duce noise into the analog chain.

Best performance at high frequencies and at high resolution

is obtained with a straight signal path. That is, the signal path

through all components should form a straight line wherever

possible.

Be especially careful with the layout of inductors and trans-

formers. Mutual inductance can change the characteristics of

the circuit in which they are used. Inductors and transformers

should not be placed side by side, even with just a small part

of their bodies beside each other. For instance, place trans-

formers for the analog input and the clock input at 90° to one

another to avoid magnetic coupling.

The analog input should be isolated from noisy signal traces

to avoid coupling of spurious signals into the input. Any ex-

ternal component (e.g., a filter capacitor) connected between

the converter's input pins and ground or to the reference input

pin and ground should be connected to a very clean point in

the ground plane.

All analog circuitry (input amplifiers, filters, reference compo-

nents, etc.) should be placed in the analog area of the board.

All digital circuitry and dynamic I/O lines should be placed in

the digital area of the board. The ADC14DS105 should be

between these two areas. Furthermore, all components in the

reference circuitry and the input signal chain that are con-

nected to ground should be connected together with short

traces and enter the ground plane at a single, quiet point. All

ground connections should have a low inductance path to

ground.

8.0 DYNAMIC PERFORMANCE

To achieve the best dynamic performance, the clock source

driving the CLK input must have a sharp transition region and

be free of jitter. Isolate the ADC clock from any digital circuitry

with buffers, as with the clock tree shown in Figure 13. The

gates used in the clock tree must be capable of operating at

frequencies much higher than those used if added jitter is to

be prevented.

As mentioned in Section 6.0, it is good practice to keep the

ADC clock line as short as possible and to keep it well away

from any other signals. Other signals can introduce jitter into

the clock signal, which can lead to reduced SNR perfor-

mance, and the clock can introduce noise into other lines.

Even lines with 90° crossings have capacitive coupling, so try

to avoid even these 90° crossings of the clock line.

20211286

FIGURE 13. Isolating the ADC Clock from other Circuitry

with a Clock Tree

25 www.national.com

ADC14DS105

Physical Dimensions inches (millimeters) unless otherwise noted

TOP View...............................SIDE View...............................BOTTOM View

60-Lead LLP Package

Ordering Numbers:

ADC14DS105AISQ / ADC14DS105CISQ

NS Package Number SQA60A

www.national.com 26

ADC14DS105

Notes

27 www.national.com

ADC14DS105

Notes

ADC14DS105 Dual 14-Bit, 105 MSPS A/D Converter with Serial LVDS Outputs

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