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FEATURES
Integrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
Clock registers are access ed id entical ly to the
static RAM. These registers are resident in
the eight top RAM locations.
Totally nonvolatile with over 10 years of
operation in the absence of power
BCD coded year, month, date, day, hours,
minutes, and seconds with leap year
compensation valid up to 2100
Power-fail write protection allows for ±10%
VCC power supply tolerance
DS1644 only (DIP Module)
− Upward compatible with the DS1643
Timekeeping RAM to achieve higher RAM
density
− Standard JEDEC bytewide 32k x 8 static
RAM pinout
DS1644P only (PowerCap® Module Board)
− Surface mountable package for direct
connection to PowerCap containing battery
and crystal
− Replaceable battery (PowerCap)
− Power-fail output
− Pin-for-pin compatible with other densities
of DS164XP Timekeeping RAM
PIN ASSIGNMENT
PIN DESCRIPTION
A0-A14 - Address Input
CE - Chip Enable
OE - Output Enable
WE - Write Enable
VCC - +5V
GND - Ground
DQ0-DQ7 - Data Input/Output
NC - No Connection
PFO - Power-fail Output
(DS1644P only)
X1, X2 - Crystal Connection
VBAT - Battery Connection
15
DS1644/DS1644P
Non volatile Timekeeping RAM
www.dalsemi.com
13
27
28-Pin Encapsulated Package (720-mil
Extended)
A7
A5
A3
A2
A1
A0
DQ0
DQ1
GND
DQ2
VCC
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
DQ7
DQ6
DQ5
DQ3
DQ4
1
2
3
4
5
6
7
8
9
10
11
12
14
28
26
25
24
23
22
21
20
19
18
17
16
A12
A
6
A4
A14
1
NC 2
3
NC
NC
PFO
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC
A
14
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
34 NC
X1 GND VBAT X2
34-Pin PowerCap Module Board
(Uses DS9034PCX PowerCap)
A12
DS1644/DS1644P
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ORDERING INFORMATION
DS1644 28-pin DIP module
*DS1644P 34-pin PowerCap Module
Board
*DS9034PCX (Power Cap) Required;
must be ordered separately
DESCRIPTION
The DS1644 is a 32k x 8 nonvolatile static RAM with a full function real time clock, which are both
accessible in a byte-wide format. The nonvolatile timekeeping RAM is function equivalent to any JEDEC
standard 32k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and EEPROM,
providing read/write nonvolatility and the addition of the real time clock function. The real time clock
information resides in the eight uppermost RAM locations. The RTC registers contain year, month, date,
day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and
leap year are made automatically. The RTC clock registers are double-buffered to avoid access of
incorrect data that can occur during clock update cycles. The double-buffered system also prevents time
loss as the timekeeping countdown continues unabated by access to time register data. The DS1644 also
contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-of-
tolerance condition. This feature prevents loss of data from unpredictabl e system operation brou ght on by
low VCC as errant access and update cycles are avoided.
PACKAGES
The DS1644 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for conne ction to a separa te PowerC ap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1644P after the completion of the surface-mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crys tal and b atter y due to the hi gh temperatur es requir ed for solde r
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS - READING THE CLOCK
While the double-buffered re gister structure redu ces the ch ance of r eadin g incor rect d ata, internal updat es
to the DS1644 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is da y, date, and time that was present at the moment the halt command was issued. Howev er,
the internal clock registers of the doubl e-buffered system continue to update so that the clock accur acy is
not affected b y the access of data. All of the DS1644 registers are updated simultaneousl y after the clock
status is reset. Updating is within a second after the read bit is written to 0.
DS1644/DS1644P
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DS1644 BLOCK DIAGRAM Figure 1
DS1644 TRUTH TABLE Table 1
VCC CE OE WE MODE DQ POWER
VIH X X DESELECT HIGH-Z STANDBY
X X X DESELECT HIGH-Z STANDBY
VIL XV
IL WRITE DATA IN ACTIVE
VIL VIL VIH READ DATA OUT ACTIVE
5V ± 10%
VIL VIH VIH READ HIGH-Z ACTIVE
<4.5V >VBAT X X X DESELECT HIGH-Z CMOS STANDBY
<VBAT X X X DESELECT HIGH-Z DATA RETENTION
MODE
SETTING THE CLOCK
The MSB Bit, (B7) of the control register is the write bit. Setting the write bit to a 1, like the read bit,
halts updates to the DS1644 registers. The user can then load them with the correct day, date and time
data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those valu es to the actual clock
counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at an y time. To increase the shelf life, the oscillator can be turn ed off
to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Setting it to
a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512 Hz frequ ency as long as conditions for access remain valid
(i.e., CE low, OE low, and address for seconds register remain valid and stable).
DS1644/DS1644P
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CLOCK ACCURACY (DIP MODULE)
The DS1644 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. Clock accuracy is also effected by the electrical environment and caution should be taken to
place the RTC in the lowest level EMI section of the PCB layout. For additional information please see
application note 58.
CLOCK ACCUR ACY (POWERCAP MODULE)
The DS1644 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in
the lowest level EMI section of the PCB layout. For additional information please see application note
58.
DS1644 REGISTER MAP - BANK1 Table 2
DATA
ADDRESS B7B6B5B4B3B2B1B0FUNCTION
7FFF - - - - - - - - YEAR 00-99
7FFE X X X - - - - - MONTH 01-12
7FFD XX------DATE 01-31
7FFC X FT X X X - - - DAY 01-07
7FFB X X - - - - - - HOUR 00-23
7FFA X-------MINUTES00-59
7FF9 OSC -------SECONDS 00-59
7FF8 WRXXXXXXCONTROLA
OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST
W = WRITE BIT X = UNUSED
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
DS1644/DS1644P
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RETRIEVING D ATA FROM RAM OR CLOCK
The DS1644 is in the read mode whenever WE (write enable) is high, and CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA, the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DAT A TO RAM OR CLOCK
The DS1644 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring high to low transition of WE or CE . The addresses must be held valid
throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of
another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH
afterward. In a t ypical application, the OE signal will be high during a write c ycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
When VCC is within nominal limits (VCC > 4.5 volts) the DS1644 can be accessed as described above with
read or write cycles. However, when VCC is below the power-fail point VPF (point at which write
protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
internally by inhibiting access via the CE signal. At this time the power-fail output signal (PFO ) will be
driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the
level of the internal battery supply, power input is switched from the VCC pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal
level.
DS1644/DS1644P
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ABSOLUTE MAXIMU M RATINGS*
Voltage on Any Pin Relative to Ground -0.3V to +7.0V
Storage Temperature -40°C to +85°C
Soldering Temperature 260°C for 10 seconds (DIP Package) (See Note 7)
See IPC/JEDEC Standard J-STD-020A for
Surface Mount Devices
*This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
Range Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
RECOMMENDED DC OPERATING CONDITIONS (Over the Operating Range)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage VCC 4.5 5.5 V 1
Logic 1 Voltage All Inputs VIH 2.2 VCC+0.3 V
Logic 0 Voltage All Inputs VIL -0.3 0.8 V
DC ELECTRICAL CHARACTERISTICS (Over the Operating Range)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Average VCC Power Supply Current ICC1 75 mA 3
TTL Standby Current (CE =VIH)ICC2 6mA3
CMOS Standby Current (CE =VCC-
0.2V) ICC3 4.0 mA 3
Input Leakage Current (an y input) IIL -1 +1 µA
Output Leakage Current IOL -1 +1 µA
Output Logic 1 Voltage
(IOUT = -1.0 mA) VOH 2.4 V
Output Logic 0 Voltage
(IOUT = +2.1 mA) VOL 0.4 V
Write Protection Voltage VPF 4.0 4.5 V
DS1644/DS1644P
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AC ELE CTRICAL CHARACTERISTICS (Over the Operating Range)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time tRC 120 ns
Address Access Time tAA 120 ns
CE Access Time tCEA 120 ns
CE Data Off Time tCEZ 40 ns
Output Enable Access Time tOEA 100 ns
Output Enable Data Off Time tOEZ 40 ns
Output Enable to DQ Low-Z tOEL 5ns
CE to DQ Low-Z tCEL 5ns
Output Hold from Address tOH 5ns
Write Cycle Time tWC 120 ns
Address Setup Time tAS 0ns
CE Pulse Width tCEW 100 ns
Address Hold from End of Write tAH1
tAH2
5
30 ns
ns 5
6
Write Pulse Width tWEW 75 ns
WE Data Off Time tWEZ 40 ns
WE or CE Inactive Time tWR 10 ns
Data Setup Time tDS 85 ns
Data Hold Time High tDH1
tDH2
0
15 ns
ns 5
6
AC TEST CONDITIONS
Input Levels: 0V to 3V
Transition Times: 5 ns
CAPACITA NCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Capacitance on all pins (except DQ) CI7pF
Capacitance on DQ pins CDQ 10 pF
AC ELE CTRICAL CHARACTERISTICS
(POWER-UP/DOWN TIMING) (Over the Operating Range)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE or WE at VIH before Power Down tPD 0µs
VPF (Max) to VPF (Min) VCC Fall Time tF300 µs
VPF (Min) to VSO VCC Fall Time tFB 10 µs
VSO to VPF (Min) VCC Rise Time tRB 1µs
VPF (Min) to VPF (Max) VCC Rise Time tR0µs
Power-Up tREC 15 35 ms
Expected Data Retention Time
(Oscillator On) tDR 10 years 4
DS1644/DS1644P
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DS1644 READ CYCLE TIMING
DS1644 WRITE CYCLE TIMING
DS1644/DS1644P
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POWER-DOWN/POWER-UP TIMING
NOTES:
1. All voltages are referenced to ground.
2. Typical values are at 25°C and nominal
supplies.
3. Outputs are open.
4. Data retention time is at 25°C and is
calculated from the date code on the device
package. The date code XXYY is the year
followed by the week of the year in which
the device was manufactured. For example,
9225 would mean the 25th week of 1992.
OUTPUT LOAD
5. tAH1, tDH1 are measured from WE going high.
6. tAH2, tDH2 are measured from CE going high.
7. Real-Time Clock Modules (DIP) can be successfull y processed through conventional wave-soldering
techniques as long as temperatures as long as temperature exposure to the lithium energy source
contained within does not exceed +85°C. Post solder cleaning with water washing techniques is
acceptable, provided that ultrasonic vibration is not used.
In addition, for the PowerCap version:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up (“live - bug”).
b. Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than
3 (three) seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To
remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick
to remove solder.
DS1644/DS1644P
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DS1644 28-PIN PACKAGE
PKG 28-PIN
DIM MIN MAX
A IN.
MM 1.470
37.34 1.490
37.85
B IN.
MM 0.715
18.16 0.740
18.80
C IN.
MM 0.335
8.51 0.365
9.27
D IN.
MM 0.075
1.91 0.105
2.67
E IN.
MM 0.015
0.38 0.030
0.76
F IN.
MM 0.140
3.56 0.180
4.57
G IN.
MM 0.090
2.29 0.110
2.79
H IN.
MM 0.590
14.99 0.630
16.00
J IN.
MM 0.010
0.25 0.018
0.45
K IN.
MM 0.015
0.38 0.025
0.64
DS1644P
PKG INCHES
DIM MIN NOM MAX
A0.920 0.925 0.930
B0.980 0.985 0.990
C- - 0.080
D0.052 0.055 0.058
E0.048 0.050 0.052
F0.015 0.020 0.025
G0.025 0.027 0.030
NOTE:
For the PowerCap version:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up (“live - bug”).
b. Hand Soldering and touch - up: Do not touch or apply the soldering iron to leads for more than
3 (three) seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To
remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick
to remove solder.
DS1644/DS1644P
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DS1644P WITH DS9034PCX ATTACHED
PKG INCHES
DIM MIN NOM MAX
A0.920 0.925 0.930
B0.955 0.960 0.965
C0.240 0.245 0.250
D0.052 0.055 0.058
E0.048 0.050 0.052
F0.015 0.020 0.025
G0.020 0.025 0.030
RECOMME NDED POWERC AP MODULE L AND PATTERN
PKG INCHES
DIM MIN NOM MAX
A- 1.050 -
B- 0.826 -
C- 0.050 -
D- 0.030 -
E- 0.112 -
