1/31October 20 05
M93C86, M93C76, M93C66
M93C56, M93C46
16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide)
MICROWIRE® Serial Access EEPRO M
FEATURES SUMMARY
■Industry Standard MICROWIRE Bus
■Single Supply Voltage:
– 4.5 to 5.5V for M93Cx6
– 2.5 to 5.5V for M93Cx6-W
– 1.8 to 5.5V for M93Cx6-R
■Dual Organization: by Word (x16) or Byte (x8)
■Programming Instructions that work on: Byte,
Word or Entire Memory
■Self-timed Programming Cycle with Auto-
Erase: 5ms
■Ready/Busy Signal During Programming
■2MHz Clock Rate
■Sequential Read Operation
■Enhanced ESD/Latch-Up Behavior
■More than 1 Million Erase/Write Cycles
■More than 40 Year Data Retention
■Packages
– ECOPACK® (RoHS c o mpl iant)
Table 1. Product List
Figure 1. Packages
Reference Part
Number Reference Part
Number
M93C86
M93C86
M93C56
M93C56
M93C86-W M93C56-W
M93C86-R M93C56-R
M93C76
M93C76
M93C46
M93C46
M93C76-W M93C46-W
M93C76-R M93C46-R
M93C66
M93C66
M93C66-W
M93C66-R
PDIP8 (BN)
SO8 (MN)
150 mil width
8
1
TSSOP8 (DW)
169 mil width
TSSOP8 (DS)
3x3mm² body size (MSOP)
8
1
UFDFPN8 (MB)
2x3mm² (MLP)
M93C86, M93C76, M93C66, M93C56, M93C46
2/31
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Memory Size versus Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 4. Instruction Set for the M93Cx6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. DIP, SO, TSSOP and MLP Connections (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
INTERNAL DEVICE RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ACTIVE POWER AND STANDBY POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Instruction Set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 6. Instruction Set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Instruction Set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Erase/Write Enable and Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. READ, WRITE, EWEN, EWDS Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. ERASE, ERAL Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. WRAL Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
READY/BUSY STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CLOCK PULSE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Operating Conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. Operating Conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 11. Operating Conditions (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3/31
M93C86, M93C76, M93C66, M93C56, M93C46
Table 12. AC Measurement Conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 13. AC Measurement Conditions (M93Cx6-W and M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 15. DC Characteristics (M93Cx6, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 16. DC Characteristics (M93Cx6, Device Grade 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 17. DC Characteristics (M93Cx6-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 18. DC Characteristics (M93Cx6-W, Device Grade 7 or 3). . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 19. DC Characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 20. AC Characteristics (M93Cx6, Device Grade 6, 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 21. AC Characteristics (M93Cx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 22. AC Characteristics (M93Cx6-W, Device Grade 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 23. AC Characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9. Synchronous Timing (Start and Op-Code Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 24
Table 24. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data. . . . . . . . . . 24
Figure 13.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 25
Table 25. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Data . . . . . . 25
Figure 14.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 26. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package
Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 27. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size,
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 28
Table 28. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 28
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
M93C86, M93C76, M93C66, M93C56, M93C46
4/31
SUMMARY D ESCRIPTION
These elec tric all y e rasa ble pr ogram mab le m emo -
ry (EEPROM) devices are accessed through a Se-
rial Data Input (D) and Serial Data Output (Q)
using the MICROWIRE bus protocol.
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
ECOPACK® packages are Lead-free and RoHS
compliant.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at:
www.st.com
.
Figure 2. Logic Diagram
Table 2. Signal Names
The memory array organization may be divided
into either bytes (x8) or words (x16) which may be
selected by a signal applied on Organization Se-
lect (ORG). The bit, byte and word sizes of the
memories are as shown in Table 3.
Table 3. Memory Size versus Organization
The M93Cx 6 is access ed by a set of in structi ons,
as summarized in Table 4., and in more detail in
Table 5. to Table 7.).
Table 4. Instruction Set for the M93Cx6
A Read Data from Memory (READ) instruction
loads the address of the first byte or word to be
read in an internal address register. The data at
this address is then clocked out serially. The ad-
dress register is automatically incremented after
the data is output and, if Chip Select Input (S) is
held High, the M93Cx6 can output a sequential
stream of data bytes or words. In this way, the
memory ca n be read as a data stre am from eight
to 16384 bits long (in the case of the M93C86), or
continuously (the address counter automatically
rolls over to 00h when the highest address is
reached).
Program ming is inte rnally self-ti med (the ex ternal
clock signal on Serial Clock (C) may be stopped or
left running after the start of a Write cycle) and
does not requir e an Erase cyc le prior to the Write
instruction. The Write instruction writes 8 or 16 bits
at a time into one o f the byte or word lo cations of
the M93Cx6. After the start of the programming cy-
cle, a Busy/Ready signal is available on Serial
S Chip Select Input
D Serial Data Input
Q Serial Data Output
C Serial Clock
ORG Organisation Select
VCC Supply Voltage
VSS Ground
AI01928
D
VCC
M93Cx6
VSS
C
Q
S
ORG
Device Number
of Bits
Number
of 8-bit
Bytes
Number
of 16-bit
Words
M93C86 16384 2048 1024
M93C76 8192 1024 512
M93C66 4096 512 256
M93C56 2048 256 128
M93C46 1024 128 64
Instruction Description Data
READ Read Data from Memory Byte or Word
WRITE Write Data to Memory Byte or Word
EWEN Erase/Write En able
EWDS Erase/Write Dis able
ERASE Erase Byte or Word Byte or Word
ERAL Erase All Memory
WRAL Write All Memory
with same Data
5/31
M93C86, M93C76, M93C66, M93C56, M93C46
Data Output (Q) when Chip Select Input (S) is driv-
en High.
An internal Power-on Data Protection mechanism
in the M93Cx6 inhibits the device when the supply
is too low.
Figure 3. DIP, SO, TSSOP and MLP
Connections (Top View)
Note: 1. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
2. DU = Don’t Use.
The DU (Don’t Use) pin does not contribute to the
normal operation of the device. It is reserved for
use by STMicroelectronics during test sequences.
The pin may be left unconnected o r may be con-
nected to VCC or VSS. Direct conne ction of DU to
VSS is recommended for the lowest stand-by pow-
er consumption.
VSS
QORG
DUC
SV
CC
D
AI01929B
M93Cx6
1
2
3
4
8
7
6
5
M93C86, M93C76, M93C66, M93C56, M93C46
6/31
MEMORY ORGANIZATION
The M93Cx6 memory is organized either as bytes
(x8) or as words (x16). If Organization Select
(ORG) is left unconnected (or connected to VCC)
the x16 organization is selected; w hen Organiza-
tion Select (ORG) is connected to Ground (VSS)
the x8 organization is selected. When the M93Cx6
is in stand-by mode, Organization Select (ORG)
should be set either to VSS or VCC for minimum
power consumption. Any voltage between VSS
and VCC applied to Organization Select (ORG)
may increase the stand-by current.
INTERNAL DEVICE RESET
In order to prevent inadvertent Write operations
during Power-up, a Power On Reset (POR) circuit
is included.
At Power-up and Power-down, the device must
not
be selected (that is, the Chip Select Input (S)
must be driven Low) until the supply voltage
reaches the operating voltage VCC (as defined in
Tables 9, 10 and 11).
During Power -up (phas e dur ing whi c h VCC is low-
er than VCCmin but increases continuously), the
device will not respond to any instruction until VCC
has reached the Power On Reset threshold volt-
age (this threshold is lower than the minimum VCC
operating voltage defined in DC AND AC PARAM-
ETERS). Once VCC has passed the POR thresh -
old, the device is reset.
Prior to selecting the memory and issuing instruc-
tions to it, a valid and stab le VCC v oltage must be
applied. This voltage must remain stable and valid
until the end o f the transmis sion of the instr uction
and, for a Write instruction, until the completion of
the internal write cycle (tW).
During Power-down (phase during which VCC de-
creases continuously), as soon as VCC drops from
the normal ope ra tin g voltag e bel ow the Po wer On
Reset threshold voltage, the device stops re-
sponding to any instruction sent to it.
ACTIVE POWER AND STANDBY POWER MODES
When Chip Select (S) is High, the device is select-
ed and in the Active Power mode. It consumes
ICC, as specified in Tables 15, 16, 17, 18 and 19.
When Chip Select (S) is Low, the device is dese-
lected.
If no Erase/Write cycle is in progress when Chip
Select goes Low, the device enters the Standby
Power mode, and the power consumption drops to
ICC1.
For the M93Cx6 devices (5V range) the POR
threshold voltage is around 3V. For the M93Cx6-
W (3V range) and M93Cx6-R (2V range) the POR
threshold voltage is around 1.5V.
7/31
M93C86, M93C76, M93C66, M93C56, M93C46
INSTRUCTIONS
The instruction set of the M93Cx6 devices con-
tains seven instructions, as summarized in Table
5. to Table 7.. Each instruction consists of the fol-
lowing parts, as shown in Figure 4.:
■Each instruction is preceded by a rising edge
on Chip Select Input (S) with Serial Clock (C)
being held Low.
■A start bit, which is the first ‘1’ read on Serial
Data Input (D) during the rising edge of Serial
Clock (C).
■Two op-code bits, read on Serial Data Input
(D) during the rising edge of Serial Clock (C).
(Some instructions also use the first two bits of
the address to define the op-code).
■The address bits of the byte or word that is to
be accessed. For the M93C46, the address is
made up of 6 bits for the x16 organization or 7
bits for the x8 organization (see Table 5.). For
the M93C56 and M93C66, the address is
made up of 8 bits for the x16 organization or 9
bits for the x8 organization (see Table 6.). For
the M93C76 and M93C86, the address is
made up of 10 bits for the x16 organization or
11 bits for the x8 organization (see Table 7.).
The M93Cx6 devices are fabricated in CMOS
technology and are therefore able to run as slow
as 0 Hz (static input signals) or as fast as the max-
imum rat i ngs specified in Table 20. to Table 23..
Table 5. Instruction Set for the M93C46
Note: 1. X = Don't Care bit.
Instruc
tion Description Start
bit Op-
Code
x8 Origination (ORG = 0) x16 Origination (ORG = 1)
Address(1) Data Required
Clock
Cycles Address(1) Data Required
Clock
Cycles
READ Read Data from
Memory 1 10 A6-A0 Q7-Q0 A5-A0 Q15-Q0
WRITE Write Data to
Memory 1 01 A6-A0 D7-D0 18 A5-A0 D15-D0 25
EWEN Erase/Write Enable 1 00 11X XXXX 10 11 XXXX 9
EWDS Erase/Write Disable 1 00 00X XXXX 10 00 XXXX 9
ERASE Erase Byte or Word 1 11 A6-A0 10 A5-A0 9
ERAL Erase All Memory 1 00 10X XXXX 10 10 XXXX 9
WRAL Write All Memory
with same Data 1 00 01X XXXX D7-D0 18 01 XXXX D15-D0 25
M93C86, M93C76, M93C66, M93C56, M93C46
8/31
Table 6. Instruction Set for the M93C56 and M93C66
Note: 1. X = Don't Care bit.
2. Address bit A8 is not decoded by the M93C5 6.
3. Address bit A7 is not decoded by the M93C5 6.
Table 7. Instruction Set for the M93C76 and M93C86
Note: 1. X = Don't Care bit.
2. Addres s bit A10 is not decoded by the M93C76.
3. Address bit A9 is not decoded by the M93C7 6.
Instruction Description Start
bit Op-
Code
x8 Origination (ORG = 0) x16 Origination (ORG = 1)
Address(1,2) Data Required
Clock
Cycles Address(1,3) Data Required
Clock
Cycles
READ Read Data from
Memory 1 10 A8-A0 Q7-Q0 A7-A0 Q15-Q0
WRITE Write Data to
Memory 1 01 A8-A0 D7-D0 20 A7-A0 D15-D0 27
EWEN Erase/Write Enable 1 00 1 1XXX
XXXX 12 11XX XXXX 11
EWDS Erase/Write Disable 1 00 0 0XXX
XXXX 12 00XX XXXX 11
ERASE Erase Byte or Word 1 11 A8-A0 12 A7-A0 11
ERAL Erase All Me mo ry 1 00 1 0XXX
XXXX 12 10XX XXXX 11
WRAL Write All Memory
with same Data 100 0 1XXX
XXXX D7-D0 20 01XX XXXX D15-D0 27
Instruction Description Start
bit Op-
Code
x8 Origination (ORG = 0) x16 Origination (ORG = 1)
Address(1,2) Data Required
Clock
Cycles Address(1,3) Data Required
Clock
Cycles
READ Read Data from
Memory 1 10 A10-A0 Q7-Q0 A9-A0 Q15-Q0
WRITE Write Data to
Memory 1 01 A10-A0 D7-D0 22 A9-A0 D15-D0 29
EWEN Erase/Write Enable 1 00 11X XXXX
XXXX 14 11 XXXX
XXXX 13
EWDS Erase/Write Disable 1 00 00 X XX XX
XXXX 14 00 XXXX
XXXX 13
ERASE Erase Byte or Word 1 11 A10-A0 14 A9-A0 13
ERAL Erase All Me mo ry 1 00 10X XX XX
XXXX 14 10 XXXX
XXXX 13
WRAL Write All Memory
with same Data 100
01X XXXX
XXXX D7-D0 22 01 XXXX
XXXX D15-D0 29
9/31
M93C86, M93C76, M93C66, M93C56, M93C46
Read
The Read Data from Memory (READ) instruction
outputs data on Se rial Data Out put (Q) . Wh en the
instruction is received, the op-code and address
are decoded, and the data from the memory is
transferred to an output shift register. A dummy 0
bit is out put first, follo wed by the 8-bit b yte or 16-
bit word, with the most significant bit first. Output
data changes are triggered by the rising edge of
Serial Clock (C). The M93Cx6 automatically incre-
ments the internal address register and clocks out
the next byt e (or wo rd ) as l ong as th e Chi p Se le ct
Input (S) is held High. In this case, the dummy 0 bit
is
not
output between bytes (or words) and a con-
tinuous stream of data can be read.
Erase/Write Enable and Disable
The Erase/Write Enable (EWEN) instruction en-
ables the future execution of erase or write instruc-
tions, and the Erase/Write Disable (EWDS)
instruction disables it. When power is first applied,
the M93Cx6 initializes itself so that erase and write
instructions are disabled. After an Erase/Write En-
able (EWEN) instruction has been executed, eras-
ing and writing remains enabled until an Erase/
Write Disable (EWDS) instruction is executed, or
until VCC falls be low the po wer -on r eset thr es ho ld
voltage. T o protec t the memor y co ntents from ac-
cidental corruption, it is advisable to issue the
Erase/Write Disable (EWDS) instruction after ev-
ery write cycle. The Read Data from Memory
(READ) instruction is not affected by the Erase/
Write Enable (EWEN) or Erase/Write Disable
(EWDS) instructions.
Figure 4. READ, WRITE, EWEN, EWDS Sequences
Note: For the meanings of An, Xn, Qn and Dn, see Table 5., Table 6. and Tab l e 7..
AI00878C
1 1 0 An A0
Qn Q0
DATA OUT
D
S
Q
READ
SWRITE
ADDR
OP
CODE
10An A0
DATA IN
D
Q
OP
CODE
Dn D01
BUSY READY
SERASE
WRITE
ENABLE
10XnX0
D
OP
CODE
101
SERASE
WRITE
DISABLE
10XnX0D
OP
CODE
0 00
CHECK
STATUS
ADDR
M93C86, M93C76, M93C66, M93C56, M93C46
10/31
Erase
The Erase Byte or Word (ERASE) instruction sets
the bits of the addressed memory byte (or word) to
1. Once the ad dress ha s been c orrec tly decod ed,
the falling edge of th e Chip S elect Input (S ) star ts
the self- timed Erase cycle. The c ompletion of the
cycle can be detected by monitoring the Ready/
Busy line, as described in the READY /BUSY S TA-
TUS section.
Write
For the Write Data to Memory (WRITE) instruction,
8 or 16 data bits follow the op-code and address
bits. These form the byte or word that is to be writ-
ten. As with the oth er bit s, Ser ial Dat a Inpu t (D ) is
sampled on the rising edge of Serial Clock (C).
After the l ast data bit h as been sa mpl ed,
the Ch ip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C).
If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
be started , and the address ed location will not be
program med. The completi on of the cycle ca n be
detected by monitoring the Ready/Busy line, as
described later in this document.
Once the W rite cycle h as been started , it is inter -
nally self-timed (the external clock signal on Serial
Clock (C) m ay be st opp ed o r left r un nin g aft er the
start of a Write cycle). The cycle is automatically
preceded by an Er ase cycle, s o it is unnecess ary
to execute an explicit erase instruction before a
Write Data to Memory (WRITE) instruction.
Figure 5. ERASE, ERAL Sequences
Note: For the meanings of An and Xn, please see Table 5., Table 6. and Table 7..
AI00879B
SERASE
1 1D
Q
ADDR
OP
CODE
1
BUSY READY
CHECK
STATUS
SERASE
ALL
1 0D
Q
OP
CODE
1
BUSY READY
CHECK
STATUS
0 0
An A0
Xn X0
ADDR
11/31
M93C86, M93C76, M93C66, M93C56, M93C46
Erase All
The Erase All Memory (ERAL) instruction erases
the whole memory (all memory bits are set to 1).
The format of the instr uction requires that a dum-
my address be provided. The E rase cycle is c on-
ducted in the same way as the Erase instruction
(ERASE). The completion of the cycle can be de-
tected by monitoring the Ready/Busy line, as de-
scribed in the READY/BUSY STATUS section.
Write All
As with the Erase All Memory (ERAL) instruction,
the format of the Write All Memory with same Data
(WRAL) instruction requires that a dummy ad-
dre ss be prov ided. As wit h the Writ e Data to Me m-
ory (WRITE) instruction, the format of the Write All
Memory with same Data (WRAL) instruction re-
quires tha t an 8-bi t data by te, or 1 6-bi t d ata wor d,
be provided. This value is written to all the ad-
dresses of th e memor y devic e. The com pletio n of
the cycle can be detected by monitoring the
Ready/Busy line, as described next.
Figure 6. WRAL Sequence
Note: For the meanings of Xn and Dn, please see Table 5., Table 6. and Tabl e 7..
AI00880C
SWRITE
ALL
DATA IN
D
Q
ADDR
OP
CODE
Dn D0
BUSY READY
CHECK
STATUS
10 00 1 Xn X0
M93C86, M93C76, M93C66, M93C56, M93C46
12/31
READY/BUSY STATUS
While the Write or Era se cycle is unde rway, for a
WRITE, ERASE, WRAL or ERAL instruction, the
Busy signal (Q=0) is returned whenever Chip Se-
lect Input (S) is driven High. (Please note, though,
that there is an initial delay, of tSLSH, before this
status information becomes available). In this
state, the M93Cx6 ignores any data on the bus.
When the Write cycle is complet ed, and Chip Se -
lect Input (S) is driven High, the Ready signal
(Q=1) indicates that the M93Cx6 is ready to re-
ceive the next instruction. Serial Data Output (Q)
remains set to 1 until the Ch ip Select Input (S) is
brought Low or until a new start bit is decoded.
INITIAL DELIVERY STATE
The device is delivered with all bits in the memory
array set to 1 (each byte contains FFh).
COMMON I/O OPERATION
Serial Data Output (Q) and Serial Data Input (D)
can be connecte d to geth er , through a cur re nt l im-
iting resistor, to form a common, single-wire data
bus. Some precautions must be taken when oper-
ating th e memory in t his way, m ostly to p revent a
short circuit current from flowing when the last ad-
dress bit (A0) clashes with the first data bit on Se-
rial Data Output (Q). Please see the application
note
AN394
for details.
CLOCK PULSE COUNTER
In a noisy environment, the number of pulses re-
ceived on Serial Clock (C) may be greater than the
number delivered by the master (the microcontrol-
ler). This can lead to a misalignment of the instruc-
tion of one or more bits (as shown in Figure 7.) and
may lead to the writing of erroneous data at an er-
roneous add re ss .
To combat this problem, the M93Cx6 has an on-
ch ip counter that counts the clock pulses from the
start bit until the falling edge of the Chip Select In-
put (S). If the number of clock pulses received is
not the number expected, the WRITE, ERASE,
ERAL or WRAL instruction is aborted, and the
contents of the memory are not modified.
The number of c lock cyc les expected for each in-
struction, and for each member of the M93Cx6
family, are summarized in Table 5. to Table 7.. For
example, a Write Data to Memory (WRITE) in-
struction o n th e M9 3C5 6 ( or M9 3C66 ) ex pec ts 20
clock cycles (for the x8 organization) from the start
bit to the falling edge of Chip Select Input (S). That
is: 1 Start bit
+ 2 Op-code bits
+ 9 Address bits
+ 8 Data bits
Figure 7. Write Sequence wi th One Clock Glitch
AI01395
S
An-1
C
D
WRITE
START D0"1""0"
An
Glitch
An-2
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
13/31
M93C86, M93C76, M93C66, M93C56, M93C46
MAXIMUM RATING
Stressing the dev ice above the ratin g lis ted in the
Absolute Maximum Ratin gs table ma y cause pe r-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other cond itions above thos e indicated in the
Operating sections of this specification is not im-
plie d. Exposu re to Abso lute Max imum Rat ing con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute Maximum Ratings
Note: 1. TLEADmax must
not
be applied for more than 10s.
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω).
Symbol Parameter Min. Max. Unit
TAAmbient Operating Temperature –40 130 °C
TSTG Storage Temperat ure –65 150 °C
TLEAD PDIP-Specific Lead Temperature during Soldering 260(1) °C
VOUT Output range (Q = VOH or Hi-Z) –0.50 VCC+0.5 V
VIN Input range –0.50 VCC+1 V
VCC Supply Voltage –0.50 6.5 V
VESD Electrostatic Discharge Voltage (Human Body model)(2) –4000 4000 V
M93C86, M93C76, M93C66, M93C56, M93C46
14/31
DC AND AC PARA METERS
This section summarizes th e operating and mea-
suremen t cond itions, and the D C and A C ch arac -
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. De si gne rs s ho uld c heck tha t th e op er ati ng
conditio ns in their circ uit match the meas urement
conditions when relying on the quoted parame-
ters.
Table 9. Operating Conditions (M93Cx6)
Table 10. Operating Conditions (M93Cx6-W)
Table 11. Operating Conditions (M93Cx6-R)
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5.5 V
TA
Ambient Operating Temperature (Device Grade 6) –40 85 °C
Ambient Operating Temperature (Device Grade 7) –40 105 °C
Ambient Operating Temperature (Device Grade 3) –40 125 °C
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.5 5.5 V
TA
Ambient Operating Temperature (Device Grade 6) –40 85 °C
Ambient Operating Temperature (Device Grade 7) –40 105 °C
Ambient Operating Temperature (Device Grade 3) –40 125 °C
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 1.8 5.5 V
TAAmbient Operating Temperature (Device Grade 6) –40 85 °C
15/31
M93C86, M93C76, M93C66, M93C56, M93C46
Table 12. AC Measurement Conditions (M93Cx6)
Note: 1. Outpu t Hi-Z is defined as the point where data ou t is no longer driven.
Table 13. AC Measurement Conditions (M93Cx6-W a nd M93Cx6-R)
Note: 1. Outpu t Hi-Z is defined as the point where data ou t is no longer driven.
Figure 8. AC Testing Input Output Waveforms
Table 14. Capacitance
Note: Sampled only, not 100% tested, at TA=25°C and a frequ ency of 1MHz.
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 100 pF
Input Rise and Fall Times 50 ns
Input Pulse Voltages 0.4 V to 2.4 V V
Input Timing Reference Voltages 1.0 V and 2.0 V V
Output Timing Reference Voltages 0.8 V and 2.0 V V
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 100 pF
Input Rise and Fall Times 50 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input Timing Reference Voltages 0.3VCC to 0.7VCC V
Output Timing Reference Voltages 0.3VCC to 0.7VCC V
Symbol Parameter Test Condition Min Max Unit
COUT Output
Capacitance VOUT = 0V 5pF
CIN Input
Capacitance VIN = 0V 5pF
AI02553
2.4V
0.4V
2.0V
0.8V
2V
1V
INPUT OUTPUT
0.8VCC
0.2VCC
0.7VCC
0.3VCC
M93CXX-W & M93CXX-R
M93CXX
M93C86, M93C76, M93C66, M93C56, M93C46
16/31
Table 15. DC Characteristics (M93Cx6, Device Grade 6)
Table 16. DC Characteristics (M93Cx6, Device Grade 7 or 3)
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA
ICC Supply Current VCC = 5V, S = VIH, f = 2 MHz, Q = open 2 mA
ICC1 Supply Current (Stand-by) VCC = 5V, S = VSS, C = VSS,
ORG = VSS or VCC 15 µA
VIL Input Low Voltage VCC = 5V ± 10% –0.45 0.8 V
VIH Input High Voltage VCC = 5V ± 10% 2VCC + 1 V
VOL Output Low Voltage VCC = 5V, IOL = 2.1mA 0.4 V
VOH Output High Voltage VCC = 5V, IOH = –400µA 2.4 V
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA
ICC Supply Current VCC = 5V, S = VIH, f = 2 MHz, , Q = open 2 mA
ICC1 Supply Current (Stand-by) VCC = 5V, S = VSS, C = VSS,
ORG = VSS or VCC 15 µA
VIL Input Low Voltage VCC = 5V ± 10% –0.45 0.8 V
VIH Input High Voltage VCC = 5V ± 10% 2VCC + 1 V
VOL Output Low Voltage VCC = 5V, IOL = 2.1mA 0.4 V
VOH Output High Voltage VCC = 5V, IOH = –400µA 2.4 V
17/31
M93C86, M93C76, M93C66, M93C56, M93C46
Table 17. DC Characteristics (M93Cx6-W, Device Grade 6)
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA
ICC Supply Current (CMOS
Inputs) VCC = 5V, S = VIH, f = 2 MHz, Q = open 2 mA
VCC = 2.5V, S = VIH, f = 2 MHz, Q = open 1 mA
ICC1 Supply Current (Stand-by) VCC = 2.5V, S = VSS, C = VSS,
ORG = VSS or VCC 5 µA
VIL Input Low Voltage (D, C, S) –0.45 0.2 VCC V
VIH Input High Voltage (D, C, S) 0.7 VCC VCC + 1 V
VOL Output Low Voltage (Q) VCC = 5V, IOL = 2.1mA 0.4 V
VCC = 2.5V, IOL = 100µA 0.2 V
VOH Output High Voltage (Q) VCC = 5V, IOH = –400µA 2.4 V
VCC = 2.5V, IOH = –100µA VCC–0.2 V
M93C86, M93C76, M93C66, M93C56, M93C46
18/31
Table 18. DC Characteristics (M93Cx6-W, Device Grade 7 or 3)
Note: 1. New produ ct : identified by Process Identification letter W or G or S.
Table 19. DC Characteristics (M93Cx6-R)
Note: 1. This product is under development. F or more informatio n, please contact your neares t ST sales office.
Symbol Parameter Test Condition Min. (1) Max. (1) Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA
ICC Supply Current (CMOS
Inputs) VCC = 5V, S = VIH, f = 2 MHz, Q = open 2 mA
VCC = 2.5V, S = VIH, f = 2 MHz, Q = open 1 mA
ICC1 Supply Current (Stand-by) VCC = 2.5V, S = VSS, C = VSS,
ORG = VSS or VCC 5 µA
VIL Input Low Voltage (D, C, S) –0.45 0.2 VCC V
VIH Input High Voltage (D, C, S) 0.7 VCC VCC + 1 V
VOL Output Low Voltage (Q) VCC = 5V, IOL = 2.1mA 0.4 V
VCC = 2.5V, IOL = 100µA 0.2 V
VOH Output High Voltage (Q) VCC = 5V, IOH = –400µA 2.4 V
VCC = 2.5V, IOH = –100µA VCC–0.2 V
Symbol Parameter Test Condition Min. (1) Max. (1) Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA
ICC Supply Current (CMOS
Inputs) VCC = 5V, S = VIH, f = 2 MHz, Q = open 2 mA
VCC = 1.8V, S = VIH, f = 1 MHz, Q = open 1 mA
ICC1 Supply Current (Stand-by) VCC = 1.8V, S = VSS, C = VSS,
ORG = VSS or VCC 2 µA
VIL Input Low Voltage (D, C, S) –0.45 0.2 VCC V
VIH Input High Voltage (D, C, S) 0.8 VCC VCC + 1 V
VOL Output Low Voltage (Q) VCC = 1.8V, IOL = 100µA 0.2 V
VOH Output High Voltage (Q) VCC = 1.8V, IOH = –100µA VCC–0.2 V
19/31
M93C86, M93C76, M93C66, M93C56, M93C46
Table 20. AC Characteristics (M93Cx6, Device Grade 6, 7 or 3)
Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chip Select Input (S) must be broug ht Low for a minimum of tSLSH between consecutive inst ruction cycle s.
Test conditions specified in Table 12. and Table 9.
Symbol Alt. Parameter Min. Max. Unit
fCfSK Clock Frequency D.C. 2 MHz
tSLCH Chip Select Low to Clock High 50 ns
tSHCH tCSS
Chip Select Set-up Time
M93C46, M93C56, M93C66 50 ns
Chip Select Set-up time
M93C76, M93C86 50 ns
tSLSH(2) tCS Chip Select Low to Chip Select High 200 ns
tCHCL(1) tSKH Clock High Time 200 ns
tCLCH(1) tSKL Clock Low Time 200 ns
tDVCH tDIS Data In Set-up Time 50 ns
tCHDX tDIH Data In Hold Time 50 ns
tCLSH tSKS Clock Set-up Time (relative to S) 50 ns
tCLSL tCSH Chip Select Hold Time 0 ns
tSHQV tSV Chip Select to Ready/Busy Status 200 ns
tSLQZ tDF Chip Select Low to Output Hi-Z 100 ns
tCHQL tPD0 Delay to Output Low 200 ns
tCHQV tPD1 Delay to Output Valid 200 ns
tWtWP Erase/Write Cycle time 5 ms
M93C86, M93C76, M93C66, M93C56, M93C46
20/31
Table 21. AC Characteristics (M93Cx6-W, Device Grade 6)
Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chip Select Input (S) must be broug ht Low for a minimum of tSLSH between consecutive inst ruction cycle s.
Test co ndi tio ns spec ifi ed in Table 13. and Table 10.
Symbol Alt. Parameter Min. Max. Unit
fCfSK Clock Frequency D.C. 2 MHz
tSLCH Chip Select Low to Clock High 50 ns
tSHCH tCSS Chip Select Set-up Time 50 ns
tSLSH(2) tCS Chip Select Low to Chip Select High 200 ns
tCHCL(1) tSKH Clock High Time 200 ns
tCLCH(1) tSKL Clock Low Time 200 ns
tDVCH tDIS Data In Set-up Time 50 ns
tCHDX tDIH Data In Hold Time 50 ns
tCLSH tSKS Clock Set-up Time (relative to S) 50 ns
tCLSL tCSH Chip Select Hold Time 0 ns
tSHQV tSV Chip Select to Ready/Busy Status 200 ns
tSLQZ tDF Chip Select Low to Output Hi-Z 100 ns
tCHQL tPD0 Delay to Output Low 200 ns
tCHQV tPD1 Delay to Output Valid 200 ns
tWtWP Erase/Write Cycle time 5 ms
21/31
M93C86, M93C76, M93C66, M93C56, M93C46
Table 22. AC Characteristics (M93Cx6-W, Device Grade 7 or 3)
Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chip Select Input (S) must be broug ht Low for a minimum of tSLSH between consecutive inst ruction cycle s.
Test conditions specified in Table 13. and Table 10.
Symbol Alt. Parameter Min. Max. Unit
fCfSK Clock Frequency D.C. 2 MHz
tSLCH Chip Select Low to Clock High 50 ns
tSHCH tCSS Chip Select Set-up Time 50 ns
tSLSH(2) tCS Chip Select Low to Chip Select High 200 ns
tCHCL(1) tSKH Clock High Time 200 ns
tCLCH(1) tSKL Clock Low Time 200 ns
tDVCH tDIS Da ta In Se t-u p Tim e 50 ns
tCHDX tDIH Data In Hold Tim e 50 n s
tCLSH tSKS Clock Set-up Time (relative to S) 50 ns
tCLSL tCSH Chip Select Hold Time 0 ns
tSHQV tSV Chip Select to Ready/Busy Status 200 ns
tSLQZ tDF Chip Select Low to Output Hi-Z 100 ns
tCHQL tPD0 Delay to Output Low 200 ns
tCHQV tPD1 Delay to Output Valid 200 ns
tWtWP Erase/Wr ite Cycle time 5 ms
M93C86, M93C76, M93C66, M93C56, M93C46
22/31
Table 23. AC Characteristics (M93Cx6-R)
Note: 1. tCHCL + tCLCH ≥ 1 / fC.
2. Chip Select Input (S) must be broug ht Low for a minimum of tSLSH between consecutive inst ruction cycle s.
3. This produ ct is under development. For more information, please contact y our nearest ST sale s of fice.
Test conditions specified in Table 13. and Table 11.
Symbol Alt. Parameter Min.(3) Max.(3) Unit
fCfSK Clock Frequency D.C. 1 MHz
tSLCH Chip Select Low to Clock High 250 ns
tSHCH tCSS Chip Select Set-up Time 50 ns
tSLSH(2) tCS Chip Select Low to Chip Select High 250 ns
tCHCL(1) tSKH Clock High Time 250 ns
tCLCH(1) tSKL Clock Low Time 250 ns
tDVCH tDIS Da ta In Se t-u p Tim e 100 ns
tCHDX tDIH Data In Hold Tim e 100 ns
tCLSH tSKS Clock Set-up Time (relative to S) 100 ns
tCLSL tCSH Chip Select Hold Time 0 ns
tSHQV tSV Chip Select to Ready/Busy Status 400 ns
tSLQZ tDF Chip Select Low to Output Hi-Z 200 ns
tCHQL tPD0 Delay to Output Low 400 ns
tCHQV tPD1 Delay to Output Valid 400 ns
tWtWP Erase/Wr ite Cycle time 10 ms
23/31
M93C86, M93C76, M93C66, M93C56, M93C46
Figure 9. Synchronous Timing (Start and Op-Code Input)
Figure 10. Synchronous Timing (Read or Write)
Figure 11. Synchronous Timing (Read or Write)
AI01428
C
OP CODE OP CODE
START
S
D
OP CODE INPUTSTART
tDVCH
tSHCH
tCLSH tCHCL
tCLCH
tCHDX
AI00820C
C
D
Q
ADDRESS INPUT
Hi-Z
tDVCH
tCLSL
A0
S
DATA OUTPUT
tCHQVtCHDX
tCHQL
An
tSLSH
tSLQZ
Q15/Q7 Q0
AI01429
C
D
Q
ADDRESS/DATA INPUT
Hi-Z
tDVCH
tSLCH
A0/D0
S
WRITE CYCLE
tSLSHtCHDX
An
tCLSL
tSLQZ
BUSY
tSHQV
tW
READY
M93C86, M93C76, M93C66, M93C56, M93C46
24/31
PACKAGE MECHANICAL
Figure 12. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
Note: Drawing is not to scale.
Table 24. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A5.330.210
A1 0.38 0.015
A2 3.30 2.92 4.95 0.130 0.115 0.195
b 0.46 0.36 0.56 0.018 0.014 0.022
b2 1.52 1.14 1.78 0.060 0.045 0.070
c 0.25 0.20 0.36 0.010 0.008 0.014
D 9.27 9.02 10.16 0.365 0.355 0.400
E 7.87 7.62 8.26 0.310 0.300 0.325
E1 6.35 6.10 7.11 0.250 0.240 0.280
e 2.54 – – 0.100 – –
eA 7.62 – – 0.300 – –
eB 10.92 0.430
L 3.30 2.92 3.81 0.130 0.115 0.150
PDIP-B
A2
A1
A
L
be
D
E1
8
1
c
eA
b2
eB
E
25/31
M93C86, M93C76, M93C66, M93C56, M93C46
Figure 13. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
Note: Drawing is not to scale.
Table 25. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
ddd 0.10 0.004
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α0° 8° 0° 8°
N (pin number) 8 8
SO-A
E
8
ddd
Be
A
D
C
LA1 α
1
H
h x 45˚
A2
M93C86, M93C76, M93C66, M93C56, M93C46
26/31
Figure 14. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Outline
Note: 1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is pulled, inter nally, to VSS. It must not be allowed to be connected to
any other voltage or signal line on the PCB, for example during the soldering process.
Table 26. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A 0.55 0.50 0.60 0.022 0.020 0.024
A1 0.00 0.05 0.000 0.002
b 0.25 0.20 0.30 0.010 0.008 0.012
D 2.00 0.079
D2 1.55 1.65 0.061 0.065
ddd 0.05 0.002
E 3.00 0.118
E2 0.15 0.25 0.006 0.010
e 0.50 – – 0.020 – –
L 0.45 0.40 0.50 0.018 0.016 0.020
L1 0.15 0.006
L3 0.30 0.012
N (pin number) 8 8
D
E
UFDFPN-01
A
A1 ddd
L1
eb
D2
L
E2
L3
27/31
M93C86, M93C76, M93C66, M93C56, M93C46
Figure 15. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package
Outline
Note: Drawing is not to scale.
Table 27. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size,
Mechanical Data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A 1.100 0.0433
A1 0.050 0.150 0.0020 0.0059
A2 0.850 0.750 0.950 0.0335 0.0295 0.0374
b 0.250 0.400 0.0098 0.0157
c 0.130 0.230 0.0051 0.0091
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
E 4.900 4.650 5.150 0.1929 0.1831 0.2028
E1 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
CP 0.100 0.0039
L 0.550 0.400 0.700 0.0217 0.0157 0.0276
L1 0.950 0.0374
α0° 6° 0° 6°
N (pin number) 8 8
TSSOP8BM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
M93C86, M93C76, M93C66, M93C56, M93C46
28/31
Figure 16. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
Note: Drawing is not to scale.
Table 28. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α0° 8° 0° 8°
N (pin number) 8 8
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
29/31
M93C86, M93C76, M93C66, M93C56, M93C46
PART NUMBERING
Table 29. Ordering Information Scheme
Note: 1. ST stro ngly recomme nds th e us e of th e Automo tiv e Grade devic es fo r use in an aut omotiv e envir onmen t. The High Reliabi lity Cer-
tified Flow (HRCF) is described in the quality note QNE E9801. Please ask you r nearest ST sales offi ce for a copy.
2. Used only for Devic e Grade 3.
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please c ontact yo ur neare st ST Sal es Of-
fice.
The category of second-Level Interconnect is
marked on the package and on the inner box label,
in compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions
are also marked on the inner box label.
Example: M93C86 – W MN 6 T P /S
Device Type
M93 = MICROWIRE serial access EEPROM
Device Function
86 = 16 Kbit (2048 x 8)
76 = 8 Kbit (1024 x 8)
66 = 4 Kbit (512 x 8)
56 = 2 Kbit (256 x 8)
46 = 1 Kbit (128 x 8)
Operatin g Voltag e
blank = VCC = 4.5 to 5.5V
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V
Package
BN = PDIP8
MN = SO8 (150 mil width )
MB = UDFDFPN8 (MLP8)
DW = TSSOP8 (169 mil width)
DS = TSSOP8 (3x3mm body size)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
7 = Device tested with High Reliability Certified Flow(1).
Automotive temperatur e range (–40 to 105 °C)
3 = Device tested with High Reliability Certified Flow(1).
Automotive temperatur e range (–40 to 125 °C)
Packing
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P or G = ECOPACK® (RoHS compliant)
Process(2)
/W or /S = F6SP36 %
M93C86, M93C76, M93C66, M93C56, M93C46
30/31
REVISION HISTORY
Table 30. Document Revision History
Date Rev. Description of Revision
04-Feb-2003 2.0
Document reformatted, and reworded, using the new template. Temperature range 1 removed.
TSSOP8 (3x3mm) package added. New products, identified by the process letter W, added,
with fc(max) increased to 1MHz for -R voltage range, and to 2MHz for all other range s (and
corresponding parameters adjusted)
26-Mar-2003 2.1 Value of standby current (max) corrected in DC characteristics tables for -W and -R ranges
VOUT and VIN separated from VIO in the Absolute Maximum Ratings table
04-Apr-2003 2.2 Values cor rec ted in AC ch ar act eristi cs tab l es for - W r ang e (t SLSH, tDVCH, tCLSL) f or de vi ces wit h
Process Identification Letter W
23-May-2003 2.3 Standby current corrected for -R range
27-May-2003 2.4 Turned-die option re-instated in Ordering Information Scheme
25-Nov-2003 3.0 Table of contents, and Pb-free options added. Temperature range 7 added. VIL(min) im proved
to –0.45V.
30-Mar-2004 4.0 MLP package added. Absolute Maximum Ratings for VIO(min) and VCC(min) changed.
Solder in g tem pe ratu re infor ma tio n cla r ifi ed for RoHS com plia nt devices. Device grade
information clarified. Process identification letter “G” information added
16-Aug-2004 5.0 M93C06 removed. Device grade information further clarified. Process identification letter “S”
information added. Turned-die package option removed. Product list summary added.
27-Oct-2005 6.0
current product/new product distinction removed. ICC and ICC1 values for current product
removed from tables 15, 16 and 17 and AC characteristics for current product removed from
Tables 20 and 21. Clock rate added to FEATURES SUMMARY.
“Q = open” adde d to ICC Test conditions in DC Characteristics Tables 15, 16, 17, 18 and 19.
Process(2) added to Table 29., Ordering Information Scheme. POWER ON DATA
PROTECTION section removed, replaced by INTERNAL DEVICE RESET and ACTIVE
POWER AND STANDBY POWER MODES. INITIAL DELIVERY STATE added.
SO8N and TSSOP8 packages updated. PDIP-specific TLEAD added to Table 8., Absolute
Maximum Ratings.
31/31
M93C86, M93C76, M93C66, M93C56, M93C46
Informatio n furnis hed is believ ed to be a ccurate and reli able. Howe ver, STMic roelectr onics assumes no r esponsib ility for th e consequences
of use of such inf ormation nor for any infrin gement of patent s or other rights of third p arties which may result from its use. N o license is grant ed
by implication or otherwise under any patent or patent rights of S TMicroelectronics. Specifications ment ioned in this publicat ion are subject
to change wi thout notic e. T his pub licat ion su persed es and repl aces all info rmat ion previou sly su pplie d. STMicroele ctro nics prod ucts ar e not
authorize d for use as critic al co mponents in life support devices or systems without express written approval of STMicroelectronics.
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