1
LTC1292/LTC1297
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FEATURES
DESCRIPTIO
U
KEY SPECIFICATIO S
U
TYPICAL APPLICATIO
U
Single Chip 12-Bit
Data Acquisition Systems
■
Resolution: 12 Bits
■
Fast Conversion Time: 12µs Max Over Temp
■
Low Supply Current: 6.0mA
■
Shutdown Supply Current: 5µA (LTC1297)
■
Single Supply 5V Operation
■
Power Shutdown After Each Conversion (LTC1297)
■
Built-In Sample-and-Hold
■
60kHz Maximum Throughput Rate (LTC1292)
■
Direct 3-Wire Interface to Most MPU Serial Ports and
All MPU Parallel Ports
■
Analog Inputs Common Mode to Supply Rails
The LTC
®
1292/LTC1297 are data acquisition systems that
contain a 12-bit, switched-capacitor successive approxi-
mation A/D, a differential input, sample-and-hold on the
(+) input, and serial I/O. When the LTC1297 is idle between
conversions it automatically powers down reducing the
supply current to 5µA, typically. The LTC1292 is capable
of digitizing signals at a 60kHz rate and with the device’s
excellent AC characteristics, it can be used for DSP appli-
cations. All these features are packaged in an 8-pin DIP
and are made possible using LTCMOS
TM
switched-capaci-
tor technology.
The serial I/O is designed to communicate without external
hardware to most MPU serial ports and all MPU parallel
I/O ports allowing data to be transmitted over three wires.
Because of their accuracy, ease of use and small package
size these devices are well suited for digitizing analog
signals in remote applications where minimum number of
interconnects and power consumption are important.
12-Bit Differential Input Data Acquisition System
+
–
DIFFERENTIAL
INPUTS
COMMON MODE
RANGE
0V TO 5V
*
1N4148
V
REF
D
OUT
CLK
V
CC
LTC1297
+IN
GND
CS
–IN
LT1027
4.7µF
TANTALUM
8V TO 40V
1µF
22µF
TANTALUM
DO
MC68HC11
SCK
MISO
*FOR OVERVOLTAGE PROTECTION LIMIT THE INPUT CURRENT TO 15mA
PER PIN OR CLAMP THE INPUTS TO V
CC
AND GND WITH 1N4148 DIODES.
CONVERSION RESULTS ARE NOT VALID WHEN ANY INPUT IS OVERVOLTAGED
(V
IN
< GND OR V
IN
> V
CC
). SEE SECTION ON OVERVOLTAGE PROTECTION IN
THE APPLICATIONS INFORMATION.
LTC1292/7 TA01
5V
+
+
f
SAMPLE
(Hz)
10
AVERAGE I
CC
(µA)
100
1000
10000
1 100 10k
LTC1297• TA02
110 1k 100k
Power Supply Current
vs Sampling Frequency
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTCMOS is trademark of Linear Technology Corporation
2
LTC1292/LTC1297
12927fb
WU
U
PACKAGE/ORDER I FOR ATIO
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
IS
(Notes 1 and 2)
Supply Voltage (V
CC
) to GND.................................. 12V
Voltage
Analog and Reference
Inputs..................................... –0.3V to V
CC
+ 0.3V
Digital Inputs........................................ –0.3V to 12V
Digital Outputs .......................... –0.3V to V
CC
+ 0.3V
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC1292/LTC1297BC, LTC1292/LTC1297CC,
LTC1292/LTC1297DC ............................ 0°C to 70°C
LTC1292BI, LTC1292CI,
LTC1292DI ......................................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
ORDER PART NUMBER
T
JMAX
= 150°C, θ
JA
=100°C/W (J8)
CO VERTER A D ULTIPLEXER CHARACTERISTICS
UU W
N8 PACKAGE
8-LEAD PLASTIC DIP
1
2
3
4
TOP VIEW
CS
+IN
–IN
GND
J8 PACKAGE
8-LEAD CERAMIC DIP
8
7
6
5
V
CC
CLK
D
OUT
V
REF
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Offset Error (Note 4) ●±3.0 ±3.0 ±3.0 LSB
Linearity Error (INL) (Note 4 & 5) ●±0.5 ±0.5 ±0.75 LSB
Gain Error (Note 4) ●±0.5 ±1.0 ±4.0 LSB
Minimum Resolution for Which No 12 12 12 Bits
Missing Codes are Guaranteed
Analog and REF Input Range (Note 7) ● –0.05V to V
CC
+ 0.05V V
On Channel Leakage Current On Channel = 5V ●±1±1±1µA
(Note 8) Off Channel = 0V
On Channel = 0V ●±1±1±1µA
Off Channel = 5V
Off Channel Lekage Current On Channel = 5V ●±1±1±1µA
(Note 8) Off Channel = 0V
On Channel = 0V ●±1±1±1µA
Off Channel = 5V
LTC1292C
LTC1297C
LTC1292B
LTC1297B LTC1292D
LTC1297D
LTC1292BIN8
LTC1292CIN8
LTC1292DIN8
LTC1292BCN8
LTC1292CCN8
LTC1292DCN8
Consult LTC Marketing for parts specified with wider operating temperature ranges.
T
JMAX
= 100°C, θ
JA
=130°C/W (N8)
LTC1292BCJ8 LTC1297BCJ8
LTC1292CCJ8 LTC1297CCJ8
LTC1292DCJ8 LTC1297DCJ8
LTC1297BCN8
LTC1297CCN8
LTC1297DCN8
The ● denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
OBSOLETE PACKAGE
Consider the N8 Package for Alternate Source
3
LTC1292/LTC1297
12927fb
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
CLK
Clock Frequency V
CC
= 5V (Note 6) (Note 9) 1.0 MHz
t
SMPL
Analog Input Sample Time See Operating Sequence LTC1292 1.5CLK
LTC1297 0.5CLK+5.5µs
t
CONV
Conversion Time See Operating Sequence 12 CLK
Cycles
t
CYC
Total Cycle Time See Operating Sequence LTC1292 14CLK+2.5µs
(Note 6) LTC1297 14CLK+6µs
t
dDO
Delay Time, CLK↓ to D
OUT
Data Valid See Test Circuits ●160 300 ns
t
dis
Delay Time, CS↑ to D
OUT
Hi-Z See Test Circuits ●80 150 ns
t
en
Delay Time, CLK↓ to D
OUT
Enabled See Test Circuits ●80 200 ns
t
hDO
Time Output Data Remains Valid After CLK↓130 ns
t
f
D
OUT
Fall Time See Test Circuits ●65 130 ns
t
r
D
OUT
Rise Time See Test Circuits ●25 50 ns
t
WHCLK
CLK High Time V
CC
= 5V (Note 6) 300 ns
t
WLCLK
CLK Low Time V
CC
= 5V (Note 6) 400 ns
t
suCS
Setup Time, CS↓ Before CLK↑V
CC
= 5V (Note 6) LTC1292 50 ns
(LTC1297 Wakeup Time) LTC1297 5.5 µs
t
WHCS
CS High Time Between Data Transfer Cycles V
CC
= 5V (Note 6) LTC1292 2.5 µs
LTC1297 0.5 µs
t
WLCS
CS Low Time During Data Transfer V
CC
= 5V (Note 6) LTC1292 14CLK
LTC1297 14CLK+5.5µs
C
IN
Input Capacitance Analog Inputs On Channel 100 pF
Analog Inputs Off Channel 5 pF
Digital Inputs 5 pF
AC CHARACTERISTICS
LTC1292B/LTC1297B
LTC1292C/LTC1297C
LTC1292D/LTC1297D
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
CC
= 5.25V ●2.0 V
V
IL
Low Level Input Voltage V
CC
= 4.75V ●0.8 V
I
IH
High Level Input Current V
IN
= V
CC
●2.5 µA
I
IL
Low Level Input Current V
IN
= 0V ●–2.5 µA
V
OH
High Level Output Voltage V
CC
= 4.75V, I
O
= –10µA 4.7 V
I
O
= 360µA●2.4 4.0 V
V
OL
Low Level Output Voltage V
CC
= 4.75V, I
O
= 1.6mA ●0.4 V
I
OZ
High Z Output Leakage V
OUT
= V
CC
, CS High ●3µA
V
OUT
= 0V, CS High ●–3 µA
I
SOURCE
Output Source Current V
OUT
= 0V –20 mA
I
SINK
Output Sink Current V
OUT
= V
CC
20 mA
LTC1292B/LTC1297B
LTC1292C/LTC1297C
LTC1292D/LTC1297D
DIGITAL A D DC ELECTRICAL CHARACTERISTICS
U
The ● denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
4
LTC1292/LTC1297
12927fb
LTC1292B/LTC1297B
LTC1292C/LTC1297C
LTC1292D/LTC1297D
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
CC
Positive Supply Current CS High LTC1292 ●612 mA
CS Low LTC1297 ●612 mA
CS High Power Shutdown CLK Off LTC1297 ●510 µA
I
REF
Reference Current CS High ●10 50 µA
DIGITAL A D DC ELECTRICAL CHARACTERISTICS
U
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
AMBIENT TEMPERATURE (°C)
–50
SUPPLY CURRENT (mA)
7
8
9
30 70
LTC1292/7 G02
6
5
–30 –10 50 90 110
4
3
10
10 130
CLK = 1MHz
VCC = 5V
SUPPLY VOLTAGE (V)
4
SUPPLY CURRENT (mA)
4
6
6
LTC1292/7 G01
2
05
10
8
CLK = 1MHz
T
A
= 25°C
LTC1297 Supply Current (Power
Shutdown) vs Temperature
AMBIENT TEMPERATURE (°C)
–50
0
SUPPLY CURRENT (µA)
1
3
4
5
10
7
050 75
LTC1292/7 G03
2
8
9
6
–25 25 100 125
V
CC
= 5V
V
REF
= 5V
CS HIGH
CLK OFF
Supply Current vs TemperatureSupply Current vs Supply Voltage
below GND or one diode drop above V
CC
. Be careful during testing at low
V
CC
levels (4.5V), as high level reference or analog inputs (5V) can cause
this input diode to conduct, especially at elevated temperatures, and cause
errors for inputs near full scale. This spec allows 50mV forward bias of
either diode. This means that as long as the reference or analog input does
not exceed the supply voltage by more than 50mV, the output code will be
correct. To achieve an absolute 0V to 5V input voltage range will therefore
require a minimum supply voltage of 4.950V over initial tolerance,
temperature variations and loading.
Note 8: Channel leakage current is measured after the channel selection.
Note 9: Increased leakage currents at elevated temperatures cause the
S/H to droop, therefore it is recommended that f
CLK
≥125kHz at 125°C,
f
CLK
≥ 31kHz at 85°C, and f
CLK
≥ 3kHz at 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground (unless otherwise
noted).
Note 3: V
CC
= 5V, V
REF
= 5V, CLK = 1.0MHz unless otherwise specified.
Note 4: One LSB is equal to V
REF
divided by 4096. For example, when
V
REF
= 5V, 1LSB = 5V/4096 = 1.22mV.
Note 5: Linearity error is specified between the actual end points of the
A/D transfer curve. The deviation is measured from the center of the
quantization band.
Note 6: Recommended operating conditions.
Note 7: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
The ● denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
5
LTC1292/LTC1297
12927fb
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
LTC1297 Supply Current (Power
Shutdown) vs CLK Frequency
REFERENCE VOLTAGE (V)
0
LINEARITY (LSB = 1/4096 × V
REF
)
0.75
1.00
1.25
4
LTC1292/7 G06
0.50
0.25
01235
V
CC
= 5V
Change in Gain vs Temperature
* AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS THE
FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 1MHz VALUE IS FIRST DETECTED (NOTE 9).
CLK FREQUENCY (kHz)
0
SUPPLY CURRENT (µA)
15
20
25
800
LTC1292/7 G04
10
5
0200 400 600 1000
V
CC
= 5V
V
REF
= 5V
CS HIGH
CMOS LOGIC LEVELS
Change in Linearity vs
Reference Voltage
Unadjusted Offset Voltage vs
Reference Voltage
REFERENCE VOLTAGE (V)
1
0.5
0.6
5
LTC1292/7 G05
0.4
0.3
0.1 234
0.2
0.9
0.8
OFFSET (LSB = 1/4096 × V
REF
)
0.7
V
OS
= 0.125mV
V
CC
= 5V
V
OS
= 0.250mV
Change in Gain vs
Reference Voltage Change in Offset vs Temperature
AMBIENT TEMPERATURE (°C)
–50
MAGNITUDE OF OFFSET CHANGE (LSB)
0.3
0.4
0.5
50
LTC1292/7 G08
0.2
0.1
0–25 025 75 125100
VCC = 5V
VREF = 5V
CLK = 1MHz
Change in Linearity vs
Temperature
AMBIENT TEMPERATURE (°C)
–50
MAGNITUDE OF LINEARITY CHANGE (LSB)
0.3
0.4
0.5
50
LTC1292/7 G09
0.2
0.1
0–25 025 75 125100
VCC = 5V
VREF = 5V
CLK = 1MHz
DOUT Delay Time vs Temperature
REFERENCE VOLTAGE (V)
0
–1.2
CHANGE IN GAIN (LSB = 1/4096 × VREF)
–1.0
–0.8
–0.6
–0.4
–0.2
0
1234
LTC1292/7 G07
5
VCC = 5V
AMBIENT TEMPERATURE (°C)
–50
MAGNITUDE OF GAIN CHANGE (LSB)
0.3
0.4
0.5
50
LTC1292/7 G10
0.2
0.1
0–25 025 75 125100
VCC = 5V
VREF = 5V
CLK = 1MHz
AMBIENT TEMPERATURE (°C)
–50
MINIMUM CLK FREQUENCY (MHz)
0.15
0.20
0.25
50
LTC1292/7 G11
0.10
0.05
–25 025 75 125100
VCC = 5V
Minimum Clock Rate for
0.1 LSB Error*
AMBIENT TEMPERATURE (°C)
–50
DOUT DELAY TIME FROM CLK↓ (ns)
150
200
250
50
LTC1292/7 G12
100
0–25 025 75 125100
VCC = 5V
50
MSB FIRST DATA
LSB FIRST DATA
6
LTC1292/LTC1297
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CCHARA TERISTICS
UW
ATYPICALPER
FORCE
100
0.2
MAXIMUM CLK FREQUENCY* (MHz)
0.4
0.6
0.8
1.0
1k 10k 100k
LTC1292/7G13
0
VCC = 5V
VREF = 5V
CLK = 1MHz
RSOURCE– (Ω)
+
–
+IN
–IN
+VIN
RSOURCE
Maximum Filter Resistor vs
Cycle Time
PI FU CTIO S
U
UU
* MAXIMUM CLK FREQUENCY REPRESENTS THE
CLK FREQUENCY AT WHICH A 0.1LSB SHIFT IN
THE ERROR AT ANY CODE TRANSITION FROM ITS
1MHz VALUE IS FIRST DETECTED.
** MAXIMUM R
FILTER
REPRESENTS THE FILTER
RESISTOR VALUE AT WHICH A 0.1LSB CHANGE IN
FULL SCALE ERROR FROM ITS VALUE AT
R
FILTER
= 0Ω IS FIRST DETECTED.
CYCLE TIME (µs)
10
MAXIMUM R
FILTER
** (Ω)
100
1k
10k
10 1k 10k
LTC1292/7 G14
1100
+
–
+V
IN
C
FILTER
≥1µF
R
FILTER
Maximum Clock Rate vs
Source Resistance
R
SOURCE
+ (Ω)
100
1
S & H AQUISITION TIME TO 0.02% (µs)
10
100
1000 10000
LTC1292/7 G15
+
–
+V
IN
R
SOURCE
V
REF
= 5V
V
CC
= 5V
T
A
= 25°C
0V TO 5V INPUT STEP
Sample-and-Hold Acquisition
Time vs Source Resistance
Input Channel Leakage Current vs
Temperature
AMBIENT TEMPERATURE (°C)
–50
0
INPUT CHANNEL LEAKAGE CURRENT (nA)
100
300
400
500
1000
700
–10 30 50 130
LTC1292/7 G16
200
800
900
600
–30 10 70 90 110
ON CHANNEL
OFF CHANNEL
GUARANTEED
Noise Error vs Reference Voltage
REFERENCE VOLTAGE (V)
0
0
PEAK-TO-PEAK NOISE ERROR (LSB)
0.25
0.75
1.00
1.25
245
2.25
0.50
13
1.50
1.75
2.00
LTC1292/7 G17
LTC1292/LTC1297
NOISE = 200µV
P-P
CS (Pin 1): Chip Select Input. A logic low on this input
enables the LTC1292/LTC1297. Power shutdown is acti-
vated on the LTC1297 when CS is brought high.
+IN, –IN (Pin 2, 3): Analog Inputs. These inputs must be
free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
V
REF
(Pin 5): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to GND.
D
OUT
(Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the serial
data transfer.
V
CC
(Pin 8):
Positive Supply. This supply must be kept free
of noise and ripple by bypassing directly to the analog
ground plane.
7
LTC1292/LTC1297
12927fb
Load Circuit for tdis and ten
Load Circuit for tdDO, tr and tf
On and Off Channel Leakage Current Voltage Waveforms for DOUT Delay Time, tdDO
W
IDAGRA
BLOCK
TEST CIRCUITS
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
Voltage Waveforms for tdis
INPUT
SHIFT
REGISTER
COMP
SAMPLE
AND
HOLD
12-BIT
CAPACITIVE
DAC
OUTPUT
SHIFT
REGISTER
12-BIT
SAR
CONTROL
AND
TIMING
V
CC
8
ANALOG
INPUT MUX
2
3
V
REF
5
GND
4
–IN
+IN
D
OUT
6
1
CLK
7
CS
LTC1292/7 BD
DOUT
1.4V
3kΩ
100pF
TEST POINT
LTC1292/7 TC03
D
OUT
3k
100pF
TEST POINT
5V t
dis
WAVEFORM 2, t
en
t
dis
WAVEFORM 1
LTC1292/7 TC02
5V
A
A
I
OFF
I
ON
POLARITY
OFF CHANNEL
ON CHANNEL
LTC1292/7 TC01
CLK
D
OUT
0.8V
t
dDO
0.4V
2.4V
LTC1292/7 TC04
D
OUT
0.4V
2.4V
t
r
t
f
LTC1292/7 TC05
D
OUT
WAVEFORM 1
(SEE NOTE 1)
2.0V
t
dis
90%
10%
D
OUT
WAVEFORM 2
(SEE NOTE 2)
CS
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1292/7 TC06
8
LTC1292/LTC1297
12927fb
TEST CIRCUITS
Voltage Waveforms for ten
The LTC1292/LTC1297 are data acquisition components
which contain the following functional blocks:
1. 12-Bit Succesive Approximation Capacitive A/D
Converter
2. Differential Input
3. Sample-and-Hold (S/H)
4. Synchronous, Half-Duplex Serial Interface
5. Control and Timing Logic
DIGITAL CONSIDERATIONS
Serial Interface
The LTC1292/LTC1297 communicate with microproces-
sors and other external circuitry via a synchronous, half-
duplex, three-wire serial interface (see Operating Se-
quence). The clock (CLK) synchronizes the data transfer
with each bit being transmitted on the falling CLK edge.
The LTC1292/LTC1297 do not require a configuration
input word and have no D
IN
pin. They are permanently
configured to have a single differential input and to per-
form a unipolar conversion. A falling CS initiates data
transfer. To allow the LTC1297 to recover from the power
shutdown mode, t
suCS
has to be met. Then the first CLK
pulse enables D
OUT
. After one null bit, the A/D conversion
result is output on the D
OUT
line with a MSB-first sequence
followed by a LSB-first sequence. With the half-duplex
serial interface the D
OUT
data is from the current conver-
sion. This provides easy interface to MSB-first or LSB-first
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
serial ports. Bringing CS high resets the LTC1292/LTC1297
for the next data exchange and puts the LTC1297 into its
power shutdown mode.
Table 1. Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1292/LTC1297**
D
OUT
0.8V
t
en
B11
CS
CLK
LTC1292/7 TC07
PART NUMBER TYPE OF INTERFACE
Motorola
MC6805S2, S3 SPI
MC68HC11 SPI
MC68HC05 SPI
RCA CDP68HC05 SPI
HitachiHD6305 SCI Synchronous
HD6301 SCI Synchronous
HD63701 SCI Synchronous
HD6303 SCI Synchronous
HD64180 SCI Synchronous
National Semiconductor
COP400 Family MICROWIRE
†
COP800 Family MCROWIRE/PLUS
†
NS8050U MICROWIRE/PLUS
HPC16000 Family MICROWIRE/PLUS
Texas Instruments
TMS7002 Serial Port
TMS7042 Serial Port
TMS70C02 Serial Port
TMS70C42 Serial Port
TMS32011* Serial Port
TMS32020* Serial Port
TMS370C050 SPI
* Requires external hardware
** Contact factory for interface information for processors not on this list
†
MICROWIRE and MICROWIRE/PLUS are trademarks of National
Semiconductor Corp.
9
LTC1292/LTC1297
12927fb
LTC1292 Operating Sequence
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Motorola SPI (MC68HC11)
The MC68HC11 has been chosen as an example of an MPU
with a dedicated serial port. This MPU transfers data MSB
first and in 8-bit increments. A dummy D
IN
word sent to the
data register starts the SPI process. With two 8-bit transfers,
the A/D result is read into the MPU (Figure 1). For the
LTC1292 the first 8-bit transfer clocks B11 through B8 of
the A/D conversion result into the processor. The second
8-bit transfer clocks the remaining bits B7 through B0 into
Microprocessor Interfaces
The LTC1292/LTC1297 can interface directly (without
external hardware) to most popular microprocessors’
(MPU) synchronous serial formats (see Table 1). If an
MPU without a dedicated serial port is used, then three of
the MPU’s parallel port lines can be programmed to form
the serial link to the LTC1292/LTC1297. Included here are
one serial interface example and one example showing a
parallel port programmed to form the serial interface.
Figure 1. Data Exchange Between LTC1292 and MC68HC11
CLK
tCYC
CS
B11 B10B9B8
B7
B6
B5B4
B3
B2
B1
B0B1B2
B3
B4
B5B6
B7
B8
B9B10 B11
tCONV
DOUT
Hi-Z
tSMPL tSMPL
LTC1292/7 AI01
LTC1297 Operating Sequence
CLK
CS
D
OUT
MPU
RECEIVED WORD
LTC1292/7 F01
B7 B6 B5 B4 B3 B2 B1 B0 B1
B8
B9
B10
B11
BYTE 2
B10 B9 B8B11
O
?
??
1ST TRANSFER 2ND TRANSFER
BYTE 1
B2 B1 B0
B3B4
B6
B7 B5
CLK
t
CYC
CS
B11 B10B9B8
B7
B6
B5B4
B3
B2
B1
B0B1B2
B3
B4
B5B6
B7
B8
B9B10 B11
t
CONV
D
OUT
Hi-Z
t
SMPL
LTC1292/7 AI02
t
suCS
POWER SHUTDOWN MODE
10
LTC1292/LTC1297
12927fb
the MPU. The data is right-justified in the two memory
locations (Figure 2). This was made possible by delaying
the falling edge of CS till after the second CLK. ANDing the
first byte with 0F
HEX
clears the four most significant bits.
This operation was not included in the code. It can be
inserted in the data gathering loop or outside the loop
when the data is processed.
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LABEL MNEMONIC OPERAND COMMENTS
LDAA #$50 CONFIGURATION DATA FOR SPCR
STAA $1028 LOAD DATA INTO SPCR ($1028)
LDAA #$1B CONFIG. DATA FOR PORT D DDR
STAA $1009 LOAD DATA INTO PORT D DDR
LDAA #$00 LOAD DUMMY DIN WORD INTO
ACC A
STAA $50 LOAD DUMMY DIN DATA INTO $50
LOOP LDX #$1000 LOAD INDEX REGISTER X WITH
$1000
LDAB #$00 LOAD ACC B WITH $00
LDAA $50 LOAD DUMMY DIN INTO ACC A
FROM $50
STAA $102A LOAD DUMMY DIN INTO SPI,
START SCK
NOP DELAY CS FALL TIME TO RIGHT
JUSTIFY DATA
MC68HC11 CODE for LTC1292 Interface
STAB $08, X D0 GOES LOW (CS GOES LOW)
NOP 6 NOPS FOR TIMING
LDAA $1029 CHECK SPI STATUS REG
LDAA $102A LOAD LTC1292 MSBs INTO ACC A
STAA $61 STORE MSBs IN $61
STAA $102A LOAD DUMMY DIN INTO SPI,
START SCK
NOPS 6 NOPS FOR TIMING
BSET $08,X,$01 D0 GOES HIGH (CS GOES HIGH)
LDAA $1029 CHECK SPI STATUS REGISTER
LDAA $102A LOAD LTC1292 LSBs IN ACC
STAA $62 STORE LSBs IN $62
JMP LOOP START NEXT CONVERSION
LABEL MNEMONIC OPERAND COMMENTS
BYTE 2
B3B7 B6 B5 B4 B2 B0
B1
B10 B9 B8B11
OO
OO BYTE 1
D
OUT
FROM LTC1292 STORED ON MC68HC11 RAM
LOCATION #61
LOCATION #62
MSB
LTC1292/7 F02
CLK
D
OUT
LTC1292
CS
ANALOG
INPUTS
DO
SCK
MISO
MC68HC11
Figure 2. Hardware and Software Interface to Motorola MC68HC11 Microcontroller
Figure 3. Data Exchange Between LTC1297 and MC68HC11
For the LTC1297 (Figure 3) a delay must be introduced to
accommodate the setup time, t
suCS
, before the dummy
D
IN
word is sent to the data register. The first 8-bit transfer
clocks B11 through B6 of the A/D conversion result into
the processor. The second 8-bit transfer clocks the re-
maining bits B5 through B0 into the MPU. Note B1 and B2
from the LSB-first data word have also been clocked in.
CLK
CS
D
OUT
MPU
RECEIVED WORD
LTC1292/7 F03
B7 B6 B5 B4 B3 B2 B1 B0 B1
B8
B9
B10
B11
BYTE 2
B8 B7 B6B9
B10
0
?B11
1ST TRANSFER 2ND TRANSFER
BYTE 1
B0 B1 B2
B1B2
B4
B5 B3
B2 B3
11
LTC1292/LTC1297
12927fb
on two port lines and the D
OUT
signal is read on a third port
line. After a falling CLK edge each data bit is loaded into the
carry bit and then rotated into the accumulator. Once the
first 8 MSBs have been shifted into the accumulator they
are loaded into register R2. The last four bits are shifted in
the same way and loaded into register R3. The output data
is left-justified in registers R2 and R3 (Figure 5).
For the LTC1297 four NOPs need to be inserted in the 8051
code after CS goes low to allow the LTC1297 to wake up
from power shutdown (t
suCS
).
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LABEL MNEMONIC OPERAND COMMENTS
LDAA #$50 CONFIGURATION DATA FOR SPCR
STAA $1028 LOAD DATA INTO SPCR ($1028)
LDAA #$1B CONFIG. DATA FOR PORT D DDR
STAA $1009 LOAD DATA INTO PORT D DDR
LDAA #$00 LOAD DUMMY DIN WORD INTO
ACC A
STAA $50 LOAD DUMMY DIN DATA INTO $0
LOOP LDX #$1000 LOAD INDEX REGISTER X WITH
$1000
LDAB #$00 LOAD ACC B WITH $00
LDAA $50 LOAD DIN INTO ACC FROM $50
BCLR $08,X,$01 D0 GOES LOW (CS GOES LOW)
NOP 3 NOP FOR t
suCS
TIMING
NOP
NOP
STAA $102A LOAD DUMMY DIN INTO SPI,
START CLK
LABEL MNEMONIC OPERAND COMMENTS
MC68HC11 CODE for LTC1297 Interface
LOOP1 LDAA $1029 CHECK SPI STATUS REG
BPL LOOP1 CHECK IF TRANSFER IS DONE
LDAA $102A LOAD LTC1297 MSBs INTO ACC A
STAA $61 STORE MSBs IN $61
STAA $102A LOAD DUMMY DIN INTO SPI,
START SCK
LOOP2 LDAA $1029 CHECK SPI STATUS RES
BPL LOOP2 CHECK IF TRANSFER IS DONE
BSET $08X,$01 D0 GOES HIGH (CS GOES HIGH)
LDAA $102A LOAD LTC1297 LSBs INTO ACC A
STAA $62 STORE LSBs IN $62
ROR $61 ROTATE RIGHT WITH CARRY
ROR $62 NEEDED TO RIGHT JUSTIFY
ROR $61 THE DATA IN $61 AND $62
ROR $62
JMP LOOP START NEXT CONVERSION
BYTE 2
B3B7 B6 B5 B4 B2 B0
B1
B10 B9 B8B11
OO
OO BYTE 1
D
OUT
FROM LTC1297 STORED ON MC68HC11 RAM
LOCATION #61
LOCATION #62
MSB
LTC1292/7 F04
CLK
D
OUT
LTC1297
CS
ANALOG
INPUTS
DO
SCK
MISO
MC68HC11
Figure 4. Hardware and Software Interface to Motorola MC68HC11 Microcontroller
The data is right- justified in the two memory locations by
rotating right twice (Figure 4). ANDing the first byte with
0F
HEX
clears the four most significant bits. This operation
was not included in the code. It can be inserted in the data
gathering loop or outside the loop when the data is
processed.
Interfacing to the Parallel Port of the Intel 8051 Family
The Intel 8051 has been chosen to show the interface
between the LTC1292/LTC1297 and parallel port
microprocessors. The signals CS and CLK are generated
12
LTC1292/LTC1297
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Figure 5. Hardware and Software Interface to Intel 8051 Processor
LABEL MNEMONIC OPERAND COMMENTS
MOV P1,#02h BIT 1 PORT 1 SET AS INPUT
CLR P1.3 CLK GOES LOW
SETB P1.4 CS GOES HIGH
CONT CLR P1.4 CS GOES LO
NOP 4 NOP FOR LTC1297 t
suCS
(Wakeup
NOP Time) (Not Needed for LTC1292)
NOP
NOP
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
MOV R4,#08H LOAD COUNTER
LOOP MOV C,P1.1 READ DATA BIT INTO CARRY
RLC A ROTATE DATA BIT INTO ACC
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
DJNZ R4,LOOP NEXT BIT
MOV R2,A STORE MSBs IN R2
MOV C,P1.1 READ DATA BIT INTO CARRY
CLR A CLEAR ACC
RLC A ROTATE DATA BIT (B3) INTO ACC
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
MOV C,P1.1 READ DATA BIT INTO CARRY
RLC A ROTATE DATA BIT (B2) INTO ACC
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
MOV C,P1.1 READ DATA BIT INTO CARRY
RLC A ROTATE DATA BIT (B1) INTO ACC
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
MOV C,P1.1 READ DATA BIT INTO CARRY
SETB P1.4 CS GOES HIGH
RRC A ROTATE DATA BIT (B0) INTO ACC
RRC A ROTATE RIGHT INTO ACC
RRC A ROTATE RIGHT INTO ACC
RRC A ROTATE RIGHT INTO ACC
MOV R3,A STORE LSBs IN R3
AJMP CONT START NEXT CONVERSION
LABEL MNEMONIC OPERAND COMMENTS
8051 CODE
Sharing the Serial Interface
The LTC1292/LTC1297 can share the same two-wire
serial interface with other peripheral components or other
LTC1292/LTC1297s (Figure 6). In this case, the CS signals
decide which LTC1292 is being addressed by the MPU.
ANALOG CONSIDERATIONS
Grounding
The LTC1292/LTC1297 should be used with an analog
ground plane and single point grounding techniques. Do
not use wire wrapping techniques to breadboard and
evaluate the device. To achieve the optimum performance
DOUT FROM LTC1292/LTC1297 STORED IN 8051 RAM
B3 B2 B0
B1 OO
OO
R3
B7 B6 B5 B4
B10 B9 B8B11
R2
MSB
ANALOG
INPUTS CLK
DOUT
LTC1292
LTC1297 CS P1.4
P1.3
P1.1
8051
LTC1292/7 F05
CS
DOUT B11 B7
B8
B9
B10 B4
B5B6 B3 B2 B1 B0
CLK
13
LTC1292/LTC1297
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Figure 6. Several LTC1292/LTC1297s Sharing One 2-Wire Serial Interface
LTC1292
LTC1297
CS CS
CS
2
2
22
2-WIRE SERIAL
INTERFACE TO OTHER
PERIPHERALS OR
LTC1292/LTC1297s
210
OUTPUT PORT
SERIAL DATA
MPU LTC1292
LTC1297 LTC1292
LTC1297
LTC1292/7 F06
+–+–+–
Figure 7. Example Ground Plane
for the LTC1292/LTC1297
1
2
3
45
6
7
8
22µF
TANTALUM
V
CC
LTC1292/7 F07
LTC1292
LTC1297
0.1µF
CS
V
CC
HORIZONTAL: 10µs/DIV
minimum and the V
CC
supply should have a low output
impedance such as obtained from a voltage regulator
(e.g., LT323A). For high frequency bypassing a 0.1µF
ceramic disk placed in parallel with the 22µF is
recommended. Again the leads should be kept to a
minimum. Figures 8 and 9 show the effects of good and
poor V
CC
bypassing.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1292/
LTC1297 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. If large source resistances are used or if slow
settling op amps drive the inputs, take care to insure that
the transients caused by the current spikes settle completely
before the conversion begins.
use a PC board. The ground pin (Pin 4) should be tied
directly to the ground plane with minimum lead length (a
low profile socket is fine). Figure 7 shows an example of
an ideal LTC1292/LTC1297 ground plane design for a two-
sided board. Of course this much ground plane will not
always be possible, but users should strive to get as close
to this ideal as possible.
Bypassing
For good performance, V
CC
must be free of noise and
ripple. Any changes in the V
CC
voltage with respect to
ground during a conversion cycle can induce errors or
noise in the output code. V
CC
noise and ripple can be kept
below 0.5mV by bypassing the V
CC
pin directly to the
analog ground plane with a minimum of 22µF tantalum
capacitor and with leads as short as possible. The lead
from the device to the V
CC
supply also should be kept to a
HORIZONTAL: 10µs/DIV
Figure 8. Poor VCC Bypassing. Noise and
Ripple Can Cause A/D Errors Figure 9. Good VCC Bypassing Keeps
Noise and Ripple on VCC Below 1mV
VERTICAL: 0.5mV/DIV
VERTICAL: 0.5mV/DIV
14
LTC1292/LTC1297
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Source Resistance
The analog inputs of the LTC1292/LTC1297 look like a
100pF capacitor (C
IN
) in series with a 500Ω resistor (R
ON
)
(Figures 10a and 10b). C
IN
gets switched between (+) and
(–) inputs once during each conversion cycle. Large
external source resistors and capacitances will slow the
settling of the inputs. It is important that the overall RC
time constant is short enough to allow the analog inputs to
settle completely within the allowed time.
“+” Input Settling
The input capacitor for the LTC1292 is switched onto the
“+” input during the sample phase (t
SMPL
, see Figures 11a,
11b and 11c). The sample period can be as short as t
WHCS
+ 1/2 CLK cycle or as long as t
WHCS
+ 1 1/2 CLK cycles
before a conversion starts. This variability depends on
where CS falls relative to CLK. The voltage on the “+” input
must settle completely within the sample period. Minimizing
R
SOURCE
+ and C1 will improve the settling time. If large “+”
input source resistance must be used, the sample time can
be increased by using a slower CLK frequency. With the
minimum possible sample time of 3.0µs, R
SOURCE
+ < 2.0k
and C1 < 20pF will provide adequate settling time.
The sample period for the LTC1297 starts on the falling
edge of CS and ends on the falling edge of the first CLK
Figure 11a. Setup Time (tsuCS) Is Met for the LTC1292
“+” and “–” Input Settling Windows
(Figure 12). The length of the sample period is t
suCS
+0.5
CLK cycles. Again, the voltage on the “+” input must settle
completely within the sample period. If large “+” input
source resistance must be used, the sample time can be
increased by using a slower CLK frequency or by increasing
Figure 10a. Analog Input Equivalent Circuit for the LTC1292
Figure 10b. Analog Input Equivalent Circuit for the LTC1297
CS↑RON
500Ω
tWHCS
+ 0.5 CLK
CIN
100pF
LTC1292
“+”
INPUT
RSOURCE +
VIN +
C1
“–”
INPUT
RSOURCE –
VIN –
C2
LTC1292/7 F10a
CS↓R
ON
500Ω
t
suCS
+ 0.5 CLK
C
IN
100pF
LTC1297
“+”
INPUT
R
SOURCE
+
V
IN
+
C1
“–”
INPUT
R
SOURCE
–
V
IN
–
C2
LTC1292/7 F10b
D
OUT
CLK
B11
HI-Z B9
B10
LTC1292/7 F11a
CS
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
t
SUCS
t
WHCS
t
SMPL
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
15
LTC1292/LTC1297
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Figure 11b. Setup Time (tsuCS) Is Met for the LTC1292
Figure 11c. Setup Time (tsuCS) Is Not Met for the LTC1292
t
suCS
. With the minimum possible sample time of 6µs,
R
SOURCE
+ < 5k and C1 < 20pF will provide adequate
settling time. In general for both the LTC1292 and LTC1297
keep the product of the total resistance and the total
capacitance less than t
SMPL
/9. If this condition can not be
met, then make C1 > 0.47µF (see RC Input Filtering
section).
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figures 11a,
11b, 11c and 12). During the conversion, the “+” input
voltage is effectively “held” by the sample-and-hold and
will not affect the conversion result. It is critical that the
D
OUT
CLK
B11
HI-Z B9
B10
LTC1292/7 F11b
CS
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
t
WHCS
t
SMPL
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
D
OUT
CLK
B11
HI-Z B10
LTC1292/7 F11c
CS
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
t
WHCS
t
SMPL
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
16
LTC1292/LTC1297
12927fb
Figure 12. “+” and “–” Input Settling Windows for the LTC1297
“–” input voltage be free of noise and settle completely
during the first CLK cycle of the conversion. Minimizing
R
SOURCE
– and C2 will improve settling time. If large “–”
input source resistance must be used the time can be
extended by using a slower CLK frequency. At the maximum
CLK frequency of 1MHz, R
SOURCE
– < 250
Ω
and C2 < 20pF
will provide adequate settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settles within the allowed time
(see Figures 11a, 11b, 11c and 12). Again the “+” and “–
” input sampling times can be extended as described
above to accommodate slower op amps. Most op amps
including the LT1797 and LT1677 single supply op amps
can be made to settle well even with the minimum settling
windows of 3.0µs for the LTC1292 or 6.0µs for the
LTC1297 (“+” input) and 1µs (“–” input) that occurs at the
maximum clock rate of 1MHz. Figures 13 and 14 show
examples of both adequate and poor op amp settling.
VERTICAL: 5mV/DIV
HORIZONTAL: 500ns/DIV
HORIZONTAL: 20µs/DIV
Figure 13. Adequate Settling of Op Amp Driving Analog Input
VERTICAL: 5mV/DIV
Figure 14. Poor Op Amp Settling Can Cause A/D Errors
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DOUT
CLK
B11
HI-Z B10
LTC1292/7 F12
CS
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
tWHCS
tSMPL
(+) INPUT MUST SETTLE
DURING THIS TIME
(+) INPUT
(–) INPUT
tsuCS
17
LTC1292/LTC1297
12927fb
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 15. For large values of C
F
(e.g., 1µF) the
capacitive input switching currents are averaged into a net
DC current. A filter should be chosen with a small resistor
and large capacitor to prevent DC drops across the resistor.
The magnitude of the DC current is approximately I
DC
=
100pF × V
IN
/t
CYC
and is roughly proportional to V
IN
. When
running the LTC1292(LTC1297) at the minimum cycle
time of 16.5µs (20µs), the input current equals 30µA
(25µA) at V
IN
= 5V. Here a filter resistor of 4Ω (5Ω) will
cause 0.1LSB of full scale error. If a large filter resistor
must be used, errors can be reduced by increasing the
cycle time as shown in the typical performance
characteristics curve Maximum Filter Resistor vs Cycle
Time.
Figure 15. RC Input Filtering
curve of S&H Acquisition Time vs Source Resistance). The
input voltage is sampled during the t
SMPL
time as shown
in Figure 11. The sampling interval begins at the rising
edge of CS for the LTC1292, and at the falling edge of CS
for the LTC1297, and continues until the falling edge of the
CLK before the conversion begins. On this falling edge the
S&H goes into the hold mode and the conversion begins.
Differential Input
With a differential input the A/D no longer converts a single
voltage but converts the difference between two voltages.
The voltage on the +IN pin is sampled and held and can be
rapidly time-varying as in single-ended mode. The voltage
on the –IN pin must remain constant and be free of noise
and ripple throughout the conversion time. Otherwise the
differencing operation will not be done accurately. The
conversion time is 12 CLK cycles. Therefore a change in
the –IN input voltage during this interval can cause
conversion errors. For a sinusoidal voltage on the –IN
input this error would be:
VfV
f
ERROR MAX IN PEAK CLK
( ) (– )
=
()
212
π
Where f
(–IN)
is the frequency of the –IN input voltage,
V
PEAK
is its peak amplitude and f
CLK
is the frequency of the
CLK. Usually V
ERROR
will not be significant. For a 60Hz
signal on the –IN input to generate a 0.25LSB error
(300µV) with the converter running at CLK = 1MHz, its
peak value would have to be 66mV. Rearranging the above
equation the maximum sinusoidal signal that can be
digitized to a given accuracy is given as:
fV
V
f
IN MAX ERROR MAX
PEAK
CLK
(– ) ()
=π
212
For 0.25LSB error (300µV) the maximum input sinusoid
with a 5V peak amplitude that can be digitized is 0.8Hz.
Reference Input
The voltage on the reference input of the LTC1292/
LTC1297 determine the voltage span of the A/D con-
verter. The reference input has transient capacitive
Input Leakage Current
Input leakage currents also can create errors if the source
resistance gets too large. For example, the maximum input
leakage specification of 1µA flowing through a source
resistance of 1k will cause a voltage drop of 1mV or
0.8LSB. This error will be much reduced at lower
temperatures because leakage drops rapidly (see typical
performance characteristics curve Input Channel Leakage
Current vs Temperature).
SAMPLE-AND-HOLD
Single-Ended Input
The LTC1292/LTC1297 provide a built-in sample-and-
hold (S&H) function on the +IN input for signals acquired
in the single-ended mode (–IN pin grounded). The sample-
and-hold allows the LTC1292/LTC1297 to convert rapidly
varying signals (see typical performance characteristics
R
FILTER
C
FILTER
LTC1292/7 F15
LTC1292
LTC1297
“+”
“–”
I
DC
V
IN
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Figures 17 and 18 show examples of both adequate and
poor settling. Using a slower CLK will allow more time
for the reference to settle. Even at the maximum CLK
rate of 1MHz most references and op amps can be
made to settle within the 1µs bit time. For example the
LT1790 will settle adequately.
Reduced Reference Operation
The effective resolution of the LTC1292/LTC1297 can
be increased by reducing the input span of the con-
verter. The LTC1292/LTC1297 exhibit good linearity
over a range of reference voltages (see typical perfor-
mance characteristics curves of Change in Linearity vs
Reference Voltage). Care must be taken when operat-
ing at low values of VREF because of the reduced LSB
step size and the resulting higher accuracy requirement
placed on the converter. Offset and noise are factors
that must be considered when operating at low VREF
values. The internal reference for VREF has been tied to
the GND pin. Any voltage drop from the GND pin to the
ground plane will cause a gain error.
Offset with Reduced VREF
The offset of the LTC1292/LTC1297 has a larger effect
on the output code when the A/D is operated with a
reduced reference voltage. The offset (which is typi-
cally a fixed voltage) becomes a larger fraction of an
LSB as the size of the LSB is reduced. The typical
performance characteristics curve of Unadjusted Off-
set Error vs Reference Voltage shows how offset in
LSBs is related to reference voltage for a typical value
of VOS. For example a VOS of 0.1mV, which is 0.1LSB
with a 5V reference becomes 0.4LSB with a 1.25V
reference. If this offset is unacceptable, it can be
corrected digitally by the receiving system or by offset-
ting the –IN input to the LTC1292/LTC1297.
Noise with Reduced VREF
The total input referred noise of the LTC1292/LTC1297
can be reduced to approximately 200µVP-P using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This
noise is insignificant with a 5V reference input but will
become a larger fraction of an LSB as the size of the LSB
switching currents due to the switched-capacitor con-
version technique (see Figure 16). During each bit test
of the conversion (every CLK cycle) a capacitive current
spike will be generated on the reference pin by the A/D.
These current spikes settle quickly and do not cause a
problem. If slow settling circuitry is used to drive the
reference input, take care to insure that transients
caused by these current spikes settle completely during
each bit test of the conversion.
R
ON
8pF TO 40pF
LTC1292
LTC1297
REF
+
R
OUT
V
REF
EVERY
CLK CYCLE
14
13
REF
–
LTC1292/7 F16
Figure 16. Reference Input Equivalent Circuit
HORIZONTAL: 1µs/DIV
Figure 17. Adequate Reference Settling (LT1027)
HORIZONTAL: 10µs/DIV
Figure 18. Poor Reference Settling Can Cause A/D Errors
VERTICAL: 0.5mV/DIV
VERTICAL: 0.5mV/DIV
19
LTC1292/LTC1297
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is reduced. The typical performance characteristics
curve of Noise Error vs Reference Voltage shows the
LSB contribution of this 200µV of noise.
For operation with a 5V reference, the 200µV noise is
only 0.16LSB peak-to-peak. Here the LTC1292/LTC1297
noise will contribute virtually no uncertainty to the
output code. For reduced references, the noise may
become a significant fraction of an LSB and cause
undesirable jitter in the output code. For example, with
a 1.25V reference, this 200µV noise is 0.64LSB peak-
to-peak. This will reduce the range of input voltages
over which a stable output code can be achieved by
0.64LSB. Now, averaging readings may be necessary.
This noise data was taken in a very clean test fixture.
Any setup induced noise (noise or ripple on VCC, VREF
or VIN) will add to the internal noise. The lower the
reference voltage used, the more critical it becomes to
have a noise-free setup.
Gain Error Due to Reduced VREF
The gain error of the LTC1292/LTC1297 is very good
over a wide range of reference voltages. The error
component that is seen in the typical performance
characteristics curve Change in Gain Error vs Refer-
ence Voltage is due to the voltage drop on the GND pin
from the device to the ground plane. To minimize this
error the LTC1292/LTC1297 should be soldered di-
rectly onto the PC board. The internal reference point
for VREF is tied to GND. Any voltage drop in the GND pin
will make the reference voltage, internal to the device,
less than what is applied externally (Figure 19). This
drop is typically 420µV due to the product of the pin
resistance (RPIN) and the LTC1292/LTC1297 supply
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This is the effective number of bits (ENOB). For the
example shown in Figures 20a and 20b, N = 11.8 bits
and 9.9 bits, respectively. Figure 21 shows a plot of
ENOB as a function of input frequency. The 2nd har-
monic distortion term accounts for the degradation of
the ENOB as fIN approaches fS/2.
Figure 22 shows an FFT plot of the output spectrum for
two tones applied to the input of the A/D. Nonlinearities
in the A/D will cause distortion products at the sum and
difference frequencies of the fundamentals and prod-
ucts of the fundamentals. This is classically referred to
as intermodulation distortion (IMD).
LTC1292
LTC1297
REF+
R
PIN
I
CC
DAC
REF– V
REF
GND
LTC1292/7 F19
±
REFERENCE
VOLTAGE
current. For example, with VREF = 1.25V this will result
in a gain error change of –1.0LSB from the gain error
measured with VREF = 5V.
LTC1292 AC Characteristics
Two commonly used figures of merit for specifying the
dynamic performance of the A/Ds in digital signal
processing applications are the Signal-to-Noise Ratio
(SNR) and the “Effective Number of Bits (ENOB).” SNR
is the ratio of the RMS magnitude of the fundamental to
the RMS magnitude of all the non-fundamental signals
up to the Nyquist frequency (half the sampling fre-
quency). The theoretical maximum SNR for a sine wave
input is given by:
SNR = (6.02N + 1.76dB)
where N is the number of bits. Thus the SNR depends
on the resolution of the A/D. For an ideal 12-bit A/D the
SNR is equal to 74dB. Fast Fourier Transform (FFT)
plots of the output spectrum of the LTC1292 are shown
in Figures 20a and 20b. The input (fIN) frequencies are
1kHz and 28kHz with the sampling frequency (fS) at
58.8 kHz. The SNRs obtained from the plots are 73.0dB
and 61.5dB.
By rewriting the SNR expression it is possible to obtain
the equivalent resolution based on the SNR measure-
ment.
NSNR dB
=
–.
.
176
602
Figure 19. Parasitic Resistance in GND Pin
20
LTC1292/LTC1297
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Figure 20a. fIN = 1kHz, fS = 58.8kHz, SNR = 73.0dB
Figure 20b. fIN = 28kHz, fS = 58.8kHz, SNR = 61.5dB
Figure 21. LTC1292 ENOB vs Input Frequency
Figure 22. fIN1 = 5.1kHz, fIN2 = 5.6kHz, fS = 58.8kHz
Overvoltage Protection
Applying signals to the LTC1292/LTC1297’s analog
inputs that exceed the positive supply or that go below
ground will degrade the accuracy of the A/D and possi-
bly damage the devices. For example this condition
would occur if a signal is applied to the analog inputs
before power is applied to the LTC1292/LTC1297. An-
other example is the input source is operating from
different supplies of larger value than the LTC1292/
LTC1297. These conditions should be prevented either
with proper supply sequencing or by use of external
circuitry to clamp or current limit the input source.
There are two ways to protect the inputs. In Figure 23
diode clamps from the inputs to VCC and GND are used.
The second method is to put resistors in series with the
analog inputs for current limiting. Limit the current to
15mA per channel. The +IN input can accept a resistor
value of 1k but the –IN input cannot accept more than
250Ω when clocked at its maximum clock frequency of
1MHz. If the LTC1292/LTC1297 are clocked at the
maximum clock frequency and 250Ω is not enough to
current limit the input source, then the clamp diodes are
recommended (Figures 24a and 24b). The reason for
the limit on the resistor value is that the MSB bit test is
affected by the value of the resistor placed at the –IN
input (see discussion on Analog Inputs and the typical
performance characteristics Maximum CLK Frequency
vs Source Resistance).
FREQUENCY (kHz)
0
–60
–40
–20
15 25
LTC1292/7 F20a
–80
–100
510 20 30
–120
–140
MAGNITUDE (dB)
0
FREQUENCY (kHz)
0
–60
–40
–20
15 25
LTC1292/7 F22
–80
–100
510 20 30
–120
–140
MAGNITUDE (dB)
0
FREQUENCY (kHz)
0
–60
–40
–20
15 25
LTC1292/7 F20b
–80
–100
510 20 30
–120
–140
MAGNITUDE (dB)
0
FREQUENCY (kHz)
0
EFFECTIVE NUMBER OF BITS
9.5
10.0
10.5
60 100
LT1292/7 F21
9.0
8.5
8.0 20 40 80
11.0
11.5
12.0
fS = 58.8kHz
21
LTC1292/LTC1297
12927fb
If VCC and VREF are not tied together, then VCC should
be turned on first, then VREF. If this sequence cannot be
met, connecting a diode from VREF to VCC is recom-
mended (see Figure 25).
Because a unique input protection structure is used on
the digital input pins, the signal levels on these pins can
exceed the device VCC without damaging the device.
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Figure 26. “Quick Look” Circuit for the LTC1292
5V
LTC1292/7 F23
1N4148 DIODES
V
CC
CLK
D
OUT
V
REF
CS
+IN
–IN
GND
LTC1292
LTC1297
5V
LTC1292/7 F24
1N4148 DIODES
1k
V
CC
CLK
D
OUT
V
REF
CS
+IN
–IN
GND
LTC1292
LTC1297
Figure 24b. Overvoltage Protection with
Diode Clamps and Current Limiting Resistor
Figure 23. Overvoltage Protection with Clamp Diodes
5V
LTC1292/7 F25
1N4148
5V
V
CC
CLK
D
OUT
V
REF
CS
+IN
–IN
GND
LTC1292
LTC1297
Figure 25. Separate VCC and VREF Supplies
5V
LTC1292/7 F24a
250Ω
1k
V
CC
CLK
D
OUT
V
REF
CS
+IN
–IN
GND
LTC1292
LTC1297
Figure 24a. Overvoltage Protection with
Current Limiting Resistors
TO OSCILLOSCOPE
CD4520
LTC1292/7 F26
Q1
RESET
VDD
EN
CLK
Q2
Q3
Q4
0.1µF
VIN
f/32 +5V
CLOCK IN
1MHz
22µF
CLK
EN
Q2
Q3
Q4
VSS
Q1
RESET
VCC
CLK
DOUT
VREF
CS
+IN
–IN
GND
LTC1292
22
LTC1292/LTC1297
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LSB
(B0) LSB-FIRST DATA
(B1)
MSB
(B11)
NULL
BIT
VERTICAL: 5V/DIV
HORIZONTAL: 2µs/DIV
CLK
CS
DOUT
A “Quick Look” Circuit for the LTC1297
A circuit similar to the one used for the LTC1292 can be
used for the LTC1297(Figure 28). A one shot has been
generated with NAND gates, a resistor and capacitor to
satisfy the setup time tsuCS. This can be eliminated if a
slower clock is used. When CS goes low the one shot is
triggered. This turns off the clock to the LTC1297 for a
fixed time to meet tsuCS. Once the clock starts DOUT is
shifted out one bit at a time. CS is driven at 1/64 the
clock rate by the 74HC393. The output data from the
DOUT pin can be viewed on an oscilloscope that is set to
trigger on the falling edge of CS. See Figure 29.
CS
CLK
DOUT
NULL
BIT MSB
(B11)
LSB-FIRST DATA
(B1)
LSB
(B0)
VERTICAL: 5V/DIV
HORIZONTAL: 5µs/DIV
Figure 29. Scope Trace of the LTC1297 “Quick Look”
Circuit Showing A/D Output 101010101010 (AAAHEX)
Figure 27. Scope Trace of the LTC1292 “Quick Look”
Circuit Showing A/D Output 101010101010 (AAAHEX)
Figure 28. “Quick Look” Circuit for the LTC1297
TO OSCILLOSCOPE
LTC1292/7 F28
0.1µF
VIN
f/64
5V
340Ω
22µF
TANTALUM
VCC
CLK
DOUT
VREF
CS
+IN
–IN
GND
LTC1297 74HC393
A1
CLR1
1QA
1QB
1QC
1QD
GND
VCC
A2
CLR2
2QA
2QB
2QC
2QD
+
f
0.02µF
CLOCK IN 1MHz
A “Quick Look” Circuit for the LTC1292
Users can get a quick look at the function and timing of
the LTC1292 by using the “Quick Look” circuit in Figure
26. VREF is tied to VCC. VIN is applied to the +IN input
and the –IN input is tied to the ground plane. CS is driven
at 1/32 the clock rate by the CD4520 and DOUT outputs
the data. The output data from the DOUT pin can be
viewed on an oscilloscope that is set up to trigger on the
falling edge of CS (Figure 27). Note the LSB data is
partially clocked out before CS goes high.
23
LTC1292/LTC1297
12927fb
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Opto-Isolated Temperature Monitor
Amplification of sensor outputs is often required to
generate a signal large enough to be properly digitized.
For example, a J-type thermocouple provides only
52µV/°C. The 5µV offset of the LTC1050 chopper op
amp generates less than 0.1°C error (Figure 31). Cold
junction compensation is provided by the LT1025A.
(For more detail see LTC Design Note 5).
In the opto-isolated interface two signals are generated
from one. This allows a two-wire interface to the
LTC1292. A long high signal (>1ms) on the CLK IN input
allows the 0.1µF capacitor to discharge taking CS high.
This resets the A/D for the next conversion. When CLK
IN starts toggling, CS goes low and stays there until the
next extended CLK IN high time. See Figure 30.
5V/DIV
A
CLK IN
CS
DATA OUT
20µs/DIV
+
1 F
TYPE J
J
R
GND
LT1025A
VIN H
2
2
3
–
+
LTC1050
7
4
6
+
µ
0.33 Fµ
178k
0.1%
3.4k
0.1%
2k
0.1%
47Ω
+
1 Fµ
GND
LTC1292
VCC
–IN
+IN
CS
CLK
DOUT
VREF
+
4.7 Fµ
3Ω
+
0.1 Fµ
10k
1N4148
8
7
6
5
1
2
3
4
+
22 FµLT1019-2.5
500k
1
21k CLK IN
3
4
500k
3
4
5k
DATA
OUT
1
26
1k
4N28s
1N4148
0°C – 500°C TEMPERATURE RANGE
ISOLATED
5V
45
+
–
A
6
100k
74C14
5V
5V
5k
LTC1292/7 F31
1N4148
Figure 31. Opto-Isolated Temperature Monitor
Figure 30. Opto-Isolated Temperature
Monitor Digital Waveforms
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24
LTC1292/LTC1297
12927fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LT/CPI 0202 1.5K REV B • PRINTED IN USA
LINEAR T ECHNOLOGY CORPORATION 1994
PACKAGE DESCRIPTIO
U
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1286 12-Bit, Micropower ADC in SO-8 12.5ksps, 1.3mW
LTC1402 12-Bit, 2.2Msps Serial ADC Unipolar (5V) or Bipolar (±5V), 90mW, 16-Pin SSOP Package
LTC1404 12-Bit, 600ksps Serial ADC in SO-8 Unipolar (5V) or Bipolar (±5V), 75mW
LTC1860 12-Bit, 250ksps Serial ADC in MSOP 4.25mW, Auto Shutdown-10µW at 1ksps
LTC1864 16-Bit, 250ksps Serial ADC in MSOP 4.25mW, Auto Shutdown-10µW at 1ksps
J8 1298
0.014 – 0.026
(0.360 – 0.660)
0.015 – 0.060
(0.381 – 1.524)
0.125
3.175
MIN
0.100
(2.54)
BSC
0.300 BSC
(0.762 BSC)
0.008 – 0.018
(0.203 – 0.457) 0° – 15°
0.045 – 0.065
(1.143 – 1.651)
0.045 – 0.068
(1.143 – 1.727)
FULL LEAD
OPTION
0.023 – 0.045
(0.584 – 1.143)
HALF LEAD
OPTION
CORNER LEADS OPTION
(4 PLCS)
0.200
(5.080)
MAX
0.005
(0.127)
MIN
0.405
(10.287)
MAX
0.220 – 0.310
(5.588 – 7.874)
1234
8765
0.025
(0.635)
RAD TYP
NOTE: LEAD DIMENSIONS APPLY TO SOLDER
DIP/PLATE OR TIN PLATE LEADS
N8 1098
0.100
(2.54)
BSC
0.065
(1.651)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.020
(0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.125
(3.175)
MIN 12 34
8765
0.255 ± 0.015*
(6.477 ± 0.381)
0.400*
(10.160)
MAX
0.009 – 0.015
(0.229 – 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.325 +0.035
–0.015
+0.889
–0.381
8.255
()
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
OBSOLETE PACKAGE
