M45PE80-VMW6TG - MICRON TECHNOLOGY

December 2008 Rev 11 1/48

M45PE80

8 Mbit, low voltage, Page-Erasable Serial Flash memory

with byte alterability and a 75 MHz SPI bus interface

Features

SPI bus compatible serial interface

75 MHz clock rate (maximum)

2.7 V to 3.6 V single supply voltage

8 Mbit of Page-Erasable Flash memory

Page size: 256 bytes:

– Page Write in 11 ms (typical)

– Page Program in 0.8 ms (typical)

– Page Erase in 10 ms (typical)

Sector Erase (64 Kbytes)

Hardware Write protection of the bottom sector

(64 Kbytes)

Electronic signature

– JEDEC standard two-byte signature

(4014h)

Unique ID code (UID) with 16 bytes read only,

available upon customer request only on T9HX

process technology parts

Deep Power-down mode 1 μA (typical)

More than 100 000 Write cycles

More than 20 years’ data retention

Packages

– RoHS compliant

VFQFPN8 (MP)

6 × 5 mm (MLP8)

SO8W (MW)

208 mils width

QFN8L (MS)

MLP8 6 x 5 mm

SO8N (MN)

150 mils width

www.numonyx.com

Contents M45PE80
2/48   
Contents
Summary description  . . . . . . . . . . .  . . .  . . . . . . . . .  . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . .  . . . . .  . . .  . . . . . . . . .  . . . . . . . . . . . . . . . . . 8
1 Serial Data Output (Q)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
3 Serial Clock (C)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
4 Chip Select (S)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
5 Reset (Reset)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
6 Write Protect (W)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
SPI modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating features   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1 Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . .  12
2 An easy way to modify data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
3 A fast way to modify data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
4 Polling during a Write, Program or Erase cycle  . . . . . . . . . . . . . . . . . . . .  13
5 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
6 Active Power, Stand-by Power and Deep Power-Down modes  . . . . . . . .  13
7 Status Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
8 Protection modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
Memory organization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1 Write Enable (WREN)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
2 Write Disable (WRDI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
3 Read Identification (RDID)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
4 Read Status Register (RDSR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
4.1 WIP bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

M45PE80 Contents
 3/48
4.2 WEL bit   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
6 Read Data Bytes at Higher Speed (FAST_READ)  . . . . . . . . . . . . . . . . . .  22
7 Page Write (PW)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23
8 Page Program (PP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
9 Page Erase (PE)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
10 Sector Erase (SE)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
11 Deep Power-down (DP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
12 Release from Deep Power-down (RDP)   . . . . . . . . . . . . . . . . . . . . . . . . .  30
Power-up and Power-down   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC and AC parameters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Part numbering  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

List of tables M45PE80
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List of tables
Table 1. Signal names  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Memory organization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Status Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Power-Up timing and VWI threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 9. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 12. AC characteristics (33 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 13. AC characteristics (50 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 14. AC characteristics (75 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 15. Reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Timings after a Reset Low pulse  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 17. VFQFPN8 (MLP8)8-lead Very thin Fine Pitch Quad Flat Package No lead,
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, mechanical data. . . . . . . . 42
Table 19. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. QFN8L (MLP8) 8-lead dual flat package no lead, 6 x 5 mm package mechanical data. . . 44
Table 21. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 22. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

M45PE80 List of figures
 5/48
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Read Identification (RDID) instruction sequence and data-out sequence  . . . . . . . . . . . . . 20
Figure 9. Read Status Register (RDSR) instruction sequence and data-out sequence  . . . . . . . . . . 21
Figure 10. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 22
Figure 11. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Page Write (PW) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Page Program (PP) instruction sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. Page Erase (PE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Release from Deep Power-down (RDP) instruction sequence. . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. Power-up timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. Write Protect setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22. Output timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 23. Reset ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 24. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 25. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package outline . . . . . . . . 42
Figure 26. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline  . . . . . . . . . . . 43
Figure 27. QFN8L (MLP8) 8-lead, dual flat package no lead, 6 × 5 mm, package outline  . . . . . . . . . 44

Summary descriptio n M45PE8 0

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1 Summary description

The M45PE80 is a 8 Mbit (1 Mbit × 8 bit) Serial Paged Flash Memory accessed by a high

speed SPI-compatible bus.

The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or

Page Program instruction. The Page Write instruction consists of an integrated Page Erase

cycle followed by a Page Program cycle.

The memory is organized as 16 sectors, each containing 256 pages. Each page is 256

bytes wide. Thus, the whole memory can be viewed as consisting of 4096 pages, or 1 048

576 bytes.

The memory can be erased a page at a time, using the Page Erase instruction, or a sector

at a time, using the Sector Erase instruction.

In order to meet environmental requirements, Numonyx offers the M45PE80 in RoHS

compliant packages, which are also Lead-free.

Figure 1. Logic diagra m

Table 1. Signal names

Signal name Function Direction

C Serial Clock Input

D Serial Data Input Input

Q Serial Data Output Output

S Chip Select Input

W Write Protect Input

Reset Reset Input

VCC Supply Voltage

VSS Ground

Reset

AI06810B

VCC

M45PE80

VSS

M45PE80 Summary description

7/48

Figure 2. VFQFPN and SO connections

1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to

VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.

2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.

AI06811B

5WS VCC

VSS

Reset

M45PE80

Signal description M45PE80

8/48

2 Signal description

2.1 Serial Dat a Output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (C).

2.2 Serial Data Input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be programmed. Values are latched on the rising edge of Serial

Clock (C).

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S)

When this input signal is High, the device is deselected and Serial Data Output (Q) is at high

impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the

device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip

Select (S) Low enables the device, placing it in the active power mode.

After Power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

2.5 Reset (Reset)

The Reset (Reset) input provides a hardware reset for the memory.

When Reset (Reset) is driven High, the memory is in the normal operating mode.

When Reset (Reset) is driven Low, the device enters the Reset mode. In this mode, the

output Q is high impedance:

If an internal operation (Write, Erase or Program cycle) is in progress when Reset (Reset) is

driven Low, the device enters the Reset mode and any on-going Write, Program or Erase

cycle is aborted. The addressed data may be lost.

2.6 Writ e Pr otect (W)

This input signal puts the device in the Hardware Protected mode, when Write Protect (W) is

connected to VSS, causing the first 256 pages of memory to become read-only by protecting

them from write, program and erase operations. When Write Protect (W) is connected to

VCC, the first 256 pages of memory behave like the other pages of memory.

M45PE80 Signal description

9/48

2.7 VCC supply voltage

VCC is the supply voltage.

2.8 VSS ground

VSS is the reference for the VCC supply voltage.

SPI modes M45PE80

10/48

3 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of

the two following modes:

CPOL=0, CPHA=0

CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 4, is the clock polarity when the

bus master is in Stand-by mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0)

C remains at 1 for (CPOL=1, CPHA=1)

Figure 3. Bus mas ter and memory de vi ces on the SPI bus

1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only

one device is selected at a time, so only one device drives the Serial Data Output (Q) line at

a time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure

that the M45PE80 is not selected if the Bus Master leaves the S line in the high impedance

state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at

the same time (for example, when the Bus Master is reset), the clock line (C) must be

connected to an external pull-down resistor so that, when all inputs/outputs become high

impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and

C do not become High at the same time, and so, that the tSHCH requirement is met). The

typical value of R is 100 kΩ, assuming that the time constant R*Cp (Cp = parasitic

capacitance of the bus line) is shorter than the time during which the Bus Master leaves the

SPI bus in high impedance.

AI12836b

SPI Bus Master

SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WHOLD WHOLD WHOLD

RR R

VCC VCC VCC

VSS VSS VSS

M45PE80 SPI modes

11/48

Example: Cp = 50 pF, that is R*Cp = 5 μs <=> the application must ensure that the Bus

Master never leaves the SPI bus in the high impedance state for a time period shorter than

5μs.

Figure 4. SPI modes support ed

AI01438B

MSB

CPHA

CPOL

MSB

Ope rating features M45PE80

12/48

4 Operating features

4.1 Sharing the overhead of modifying data

To write or program one (or more) data bytes, two instructions are required: Write Enable

(WREN), which is one byte, and a Page Write (PW) or Page Program (PP) sequence, which

consists of four bytes plus data. This is followed by the internal cycle (of duration tPW or tPP).

To share this overhead, the Page Write (PW) or Page Program (PP) instruction allows up to

256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at

a time, provided that they lie in consecutive addresses on the same page of memory.

4.2 An easy way to modify data

The Page Write (PW) instruction provides a convenient way of modifying data (up to 256

contiguous bytes at a time), and simply requires the start address, and the new data in the

instruction sequence.

The Page Write (PW) instruction is entered by driving Chip Select (S) Low, and then

transmitting the instruction byte, three address bytes (A23-A0) and at least one data byte,

and then driving Chip Select (S) High. While Chip Select (S) is being held Low, the data

bytes are written to the data buffer, starting at the address given in the third address byte

(A7-A0). When Chip Select (S) is driven High, the Write cycle starts. The remaining,

unchanged, bytes of the data buffer are automatically loaded with the values of the

corresponding bytes of the addressed memory page. The addressed memory page then

automatically put into an Erase cycle. Finally, the addressed memory page is programmed

with the contents of the data buffer.

All of this buffer management is handled internally, and is transparent to the user. The user

is given the facility of being able to alter the contents of the memory on a byte-by-byte basis.

For optimized timings, it is recommended to use the Page Write (PW) instruction to write all

consecutive targeted bytes in a single sequence versus using several Page Write (PW)

sequences with each containing only a few bytes (see Page W ri te (PW), Table 13: AC

characteristics (50 MHz operation), and Table 14.: AC characteristics (75 MHz operation)).

M45PE80 O p er atin g fe atures

13/48

4.3 A fast way to modify data

The Page Program (PP) instruction provides a fast way of modifying data up to 256

contiguous bytes at a time, provided that it involves only resetting bits to 0 that had

previously been set to 1. The following are times this use case might occur:

The designer is programming the device for the first time;

The designer knows that the page has already been erased by an earlier Page Erase

(PE) or Sector Erase (SE) instruction. This is useful, for example, when storing a fast

stream of data, having first performed the erase cycle when time was available;

The designer knows that the change involves only resetting bits to 0 that are still set to

1. When this method is possible, it has the additional advantage of minimizing the

number of unnecessary erase operations, and the extra stress incurred by each page.

For optimized timings, it is recommended to use the Page Program (PP) instruction to

program all consecutive targeted bytes in a single sequence versus using several Page

Program (PP) sequences with each containing only a few bytes (see Page Program (PP),

Tabl e 13: AC charac t eris ti c s (5 0 M H z ope r ation ), and Table 14.: AC characterist i c s (75 MHz

operation)).

4.4 Polling during a Write, Program or Erase cycle

A further improvement in the write, program or erase time can be achieved by not waiting for

the worst case delay (tPW, tPP

, tPE, or tSE). The Write In Progress (WIP) bit is provided in the

Status Register so that the application program can monitor its value, polling it to establish

when the previous cycle is complete.

4.5 Reset

An internal Power-On Reset circuit helps protect against inadvertent data writes. Addition

protection is provided by driving Reset (Reset) Low during the Power-on process, and only

driving it High when VCC has reached the correct voltage level, VCC(min).

4.6 Active Power, Stand-by Power and Deep Power-Down modes

When Chip Select (S) is Low, the device is enabled, and in the Active Power mode.

When Chip Select (S) is High, the device is disabled, but could remain in the Active Power

mode until all internal cycles have completed (Program, Erase, Write). The device then goes

in to the Stand-by Power mode. The device consumption drops to ICC1.

The Deep Power-down mode is entered when the specific instruction (the Enter Deep

Power-down Mode (DP) instruction) is executed. The device consumption drops further to

ICC2. The device remains in this mode until another specific instruction (the Release from

Deep Power-down Mode) is executed.

While in the Deep Power-down mode, the device ignores all Write, Program and Erase

instructions (see Deep Power-down (DP)). This can be used as an extra software protection

mechanism, when the device is not in active use, to protect the device from inadvertent

Write, Program or Erase instructions.

Ope rating features M45PE80

14/48

4.7 Status Register

The Status Register contains two status bits that can be read by the Read Status Register

(RDSR) instruction. See Se ction 6.4: Re ad Status Regi st er (RDSR) for a detailed

description of the Status Register bits.

4.8 Protection modes

The environments where non-volatile memory devices are used can be very noisy. No SPI

device can operate correctly in the presence of excessive noise. To help combat this, the

M45PE80 boasts the following data protection mechanisms:

Power-On Reset and an internal timer (tPUW) can provide protection against

inadvertent changes while the power supply is outside the operating specification.

Program, Erase and Write instructions are checked that they consist of a number of

clock pulses that is a multiple of eight, before they are accepted for execution.

All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state

by the following events:

– Power-up

– Reset (RESET) driven Low

– Write Disable (WRDI) instruction completion

– Page Write (PW) instruction completion

– Page Program (PP) instruction completion

– Page Erase (PE) instruction completion

– Sector Erase (SE) instruction completion

The Hardware Protected mode is entered when Write Protect (W) is driven Low,

causing the first 256 pages of memory to become read-only. When Write Protect (W) is

driven High, the first 256 pages of memory behave like the other pages of memory

The Reset (Reset) signal can be driven Low to protect the contents of the memory

during any critical time, not just during Power-up and Power-down.

In addition to the low power consumption feature, the Deep Power-down mode offers

extra software protection from inadvertent Write, Program and Erase instructions while

the device is not in active use.

M45PE80 Memory orga ni zation

15/48

5 Memory organization

The memory is organized as:

4096 pages (256 bytes each).

1 048 576 bytes (8 bits each)

16 sectors (512 Kbits, 65536 bytes each)

Each page can be individually:

programmed (bits are programmed from 1 to 0)

erased (bits are erased from 0 to 1)

written (bits are changed to either 0 or 1)

The device is Page or Sector Erasable (bits are erased from 0 to 1).

Table 2. Memory organization

Sector Address range

15 F0000h FFFFFh

14 E0000h EFFFFh

13 D0000h DFFFFh

12 C0000h CFFFFh

11 B0000h BFFFFh

10 A0000h AFFFFh

9 90000h 9FFFFh

8 80000h 8FFFFh

7 70000h 7FFFFh

6 60000h 6FFFFh

5 50000h 5FFFFh

4 40000h 4FFFFh

3 30000h 3FFFFh

2 20000h 2FFFFh

1 10000h 1FFFFh

0 00000h 0FFFFh

Memory organization M45 PE80

16/48

Figure 5. Block diagram

AI0681

WControl Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter 256 Byte

Data Buffer

256 Bytes (Page Size)

X Decoder

Y Decoder

Status

00000h

FFFFFh

000FFh

Reset

10000h

First 256 Pages can

be made read-only

M45PE80 Instructions

17/48

6 Instructions

All instructions, addresses, and data are shifted in and out of the device, most significant bit

first.

Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select

(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most

significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of

Serial Clock (C). The instruction set is listed in Table 3.

Every instruction sequence starts with a one-byte instruction code. Depending on the

instruction, this might be followed by address bytes, or by data bytes, or by both or none.

In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read)

or Read Status Register (RDSR) instruction, the shifted-in instruction sequence is followed

by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out

sequence is being shifted out.

In the case of a Page Write (PW), Page Program (PP), Page Erase (PE), Sector Erase (SE),

Write Enable (WREN), Write Disable (WRDI), Deep Power-down (DP) or Release from

Deep Power-down (RDP) instruction, Chip Select (S) must be driven High exactly at a byte

boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S)

must driven High when the number of clock pulses after Chip Select (S) being driven Low is

an exact multiple of eight.

All attempts to access the memory array during a Write cycle, Program cycle or Erase cycle

are ignored, and the internal Write cycle, Program cycle or Erase cycle continues

unaffected.

Table 3. In struct ion set

Instruction Description One -byte i nstruction

code Address

bytes Dummy

bytes Data

bytes

WREN Write Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

RDID Read Identification 1001 1111 9Fh 0 0 1 to 3

RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞

READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ Read Data Bytes at Higher

Speed 0000 1011 0Bh 3 1 1 to ∞

PW Page Write 0000 1010 0Ah 3 0 1 to 256

PP Page Program 0000 0010 02h 3 0 1 to 256

PE Page Erase 1101 1011 DBh 3 0 0

SE Sector Erase 1101 1000 D8h 3 0 0

DP Deep Power-down 1011 1001 B9h 0 0 0

RDP Release from Deep

Power-down 1010 1011 ABh 0 0 0

Instructions M45PE80

18/48

6.1 Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 6) sets the Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page

Program (PP), Page Erase (PE), and Sector Erase (SE) instruction.

The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

Figu r e 6. Writ e Enable ( WREN) instruction seq uence

6.2 Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 7) resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under the following conditions:

Power-up

Write Disable (WRDI) instruction completion

Page Write (PW) instruction completion

Page Program (PP) instruction completion

Page Erase (PE) instruction completion

Sector Erase (SE) instruction completion

Fig u re 7. Write Disable (WRDI ) instru ction sequence

AI02281E

21 34567

High Impedance

Instruction

AI03750D

21 34567

High Impedance

Instruction

M45PE80 Instructions

19/48

6.3 Read Identification (RDID)

The Read Identification (RDID) instruction allows the device identification data to be read as

explained here, with the data values shown in Table 4. : Read Id entification (RDI D) data-ou t

sequence.

Manufacturer identification (1 byte): Numonyx value assigned by JEDEC.

Device identification (2 bytes): assigned by the device manufacturer.

– The first byte indicates the memory type.

– The second byte indicates the memory capacity of the device.

Unique ID code (UID) (17 bytes): available upon customer request.(1)

– The first byte contains the length of the data that is contained in the UID.

– The remaining 16 bytes are available upon customer request and contain the

optional Customized Factory Data (CFD) content. The CFD bytes are read-only

and can be programmed with customer data upon customer demand. If a

customer does not make a request, the device is shipped with all CFD bytes

programmed to zero (00h).

Any Read Identification (RDID) instruction performed while an Erase or Program cycle is in

progress is not decoded, and has no effect on the cycle that is in progress.

The device is first selected by driving Chip Select (S) Low. Then, the 1-byte instruction code

for the instruction is shifted in.

After this the 20-bytes stored in memory are shifted out on Serial Data output (Q), including

the 3-bytes of manufacturer and device identification information, the 1-byte CFD length,

and the 16 bytes of CFD content. Each bit of these 20-bytes is shifted out during the falling

edge of Serial Clock (C). The instruction sequence is shown in Fi gur e 8: R ea d Id enti fic at i on

(RDID) in st ruction sequenc e and data-out sequence.

The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at

any time during data output. When Chip Select (S) is driven High, the device is put in the

Stand-by Power mode. Once in the Stand-by Power mode, the device waits to be selected,

so that it can receive, decode and execute instructions.

1. UID available on T9HX process technology parts.

Table 4. Read Identifi cation (RDID ) da ta-o u t sequence

Manufacturer

Identification

Device Identi fication UID

Memory Type Memory Capacity CFD length CFD content

20h 40h 14h 10h 16 bytes

Instructions M45PE80

20/48

Figure 8. Read Identification (RDID) i nstruction sequence and data-out sequenc e

6.4 Re ad St atus Registe r (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Program, Erase or Write cycle is in

progress. When one of these cycles is in progress, it is recommended to check the Write In

Progress (WIP) bit before sending a new instruction to the device. It is also possible to read

the Status Register continuously, as shown in Figure 9.

The status bits of the Status Register are as follows:

6.4.1 WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write, Program

or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is

in progress.

6.4.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable

Latch is reset and no Write, Program or Erase instruction is accepted.

21 3456789101112131415

Instruction

AI06809

Manufacturer Identification

High Impedance

MSB

15 1413 3210

Device Identification

MSB

16 16 18 28 29 30 31

Table 5. Status Register Form at

b7 b0

0 0 0 0 0 0 WEL(1)

1. WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is

automatically set and reset by the internal logic of the device).

WIP(1)

M45PE80 Instructions

21/48

Figure 9. Read Status Register (R D SR) instruct i on sequence and data-out

sequence

6.5 Read Data Bytes (READ )

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read

Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being

latched-in during the rising edge of Serial Clock (C). Then the memory contents at that

address is shifted out on Serial Data Output (Q), each bit being shifted out at a maximum

frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown

in Figure 10.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes (READ) instruction. When the highest

address is reached, the address counter rolls over to 000000h, allowing the read sequence

to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip

Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)

instruction, while an Erase, Program or Write cycle is in progress, is rejected without having

any effects on the cycle that is in progress.

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status Register Out

High Impedance

MSB

76543210

Status Register Out

MSB

Instructions M45PE80

22/48

Fig u re 10. Read Data Bytes (READ) instruction sequence and data-out sequence

1. Address bits A23 to A20 are Don’t Care.

6.6 Re ad Data Bytes at Higher Sp eed (FAST_READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read

Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-

A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).

Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each

bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 11.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)

instruction. When the highest address is reached, the address counter rolls over to

000000h, allowing the read sequence to be continued indefinitely.

The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving

Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any

Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or

Write cycle is in progress, is rejected without having any effects on the cycle that is in

progress.

AI03748D

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

High Impedance Data Out 1

Instruction 24-Bit Address

MSB

Data Out 2

M45PE80 Instructions

23/48

Figure 11. Read Data B ytes at Higher Speed (FAST_ REA D) instruc tion se quenc e

and data-out sequence

1. Address bits A23 to A20 are Don’t Care.

6.7 Page Write (PW)

The Page Write (PW) instruction allows bytes to be written in the memory. Before it can be

accepted, a Write Enable (WREN) instruction must previously have been executed. After

the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable

Latch (WEL).

The Page Write (PW) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, three address bytes and at least one data byte on Serial Data Input (D).

The rest of the page remains unchanged if no power failure occurs and the device is not

reset during the write cycle.

The Page Write (PW) instruction performs a page erase cycle even if only one byte is

updated.

If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding

the addressed page boundary roll over, and are written from the start address of the same

page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 12.

AI04006

21 345678910 28293031

2221 3210

High Impedance

Instruction 24 BIT ADDRESS

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy Byte

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

Instructions M45PE80

24/48

If more than 256 bytes are sent to the device, previously latched data are discarded and the

last 256 data bytes are guaranteed to be written correctly within the same page. If less than

256 Data bytes are sent to device, they are correctly written at the requested addresses

without having any effects on the other bytes of the same page.

For optimized timings, it is recommended to use the Page Write (PW) instruction to write all

consecutive targeted bytes in a single sequence versus using several Page Write (PW)

sequences with each containing only a few bytes (see Table 13: AC char acte ri stics (5 0 MH z

operation) and Table 14.: AC c haract eristics (75 MHz operation)).

Chip Select (S) must be driven High after the eighth bit of the last data byte has been

latched in, otherwise the Page Write (PW) instruction is not executed.

As soon as Chip Select (S) is driven High, the self-timed Page Write cycle (whose duration

is tPW) is initiated. While the Page Write cycle is in progress, the Status Register may be

read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is

1 during the self-timed Page Write cycle, and is 0 when it is completed. At some unspecified

time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.

A Page Write (PW) instruction applied to a page that is Hardware Protected is not executed.

Any Page Write (PW) instruction, while an Erase, Program or Write cycle is in progress, is

rejected without having any effects on the cycle that is in progress.

Figu re 12. Page Write (PW) in structi on seq uence

1. Address bits A23 to A20 are Don’t Care

2. 1 ≤ n ≤ 256

AI04045

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte n

765432 0

MSB MSB

MSB MSB MSB

M45PE80 Instructions

25/48

6.8 Page Program (PP)

The Page Program (PP) instruction allows bytes to be programmed in the memory

(changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN)

instruction must previously have been executed. After the Write Enable (WREN) instruction

has been decoded, the device sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by

the instruction code, three address bytes and at least one data byte on Serial Data Input (D).

If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding

the addressed page boundary roll over, and are programmed from the start address of the

same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select

(S) must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 13.

If more than 256 bytes are sent to the device, previously latched data are discarded and the

last 256 data bytes are guaranteed to be programmed correctly within the same page. If less

than 256 Data bytes are sent to device, they are correctly programmed at the requested

addresses without having any effects on the other bytes of the same page.

For optimized timings, it is recommended to use the Page Program (PP) instruction to

program all consecutive targeted bytes in a single sequence versus using several Page

Program (PP) sequences with each containing only a few bytes (see Table 13: AC

characteristics (50 MHz operation) and Table 14.: AC charac teristic s (75 MH z operati on)).

Chip Select (S) must be driven High after the eighth bit of the last data byte has been

latched in, otherwise the Page Program (PP) instruction is not executed.

As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose

duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register

may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress

(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At

some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is

reset.

A Page Program (PP) instruction applied to a page that is Hardware Protected is not

executed.

Any Page Program (PP) instruction, while an Erase, Program or Write cycle is in progress,

is rejected without having any effects on the cycle that is in progress.

Instructions M45PE80

26/48

Figure 13. Page Program (PP ) i nst ruct ion sequence

1. Address bits A23 to A20 are Don’t Care

2. 1 ≤ n ≤ 256

AI04044

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte n

765432 0

MSB MSB

MSB MSB MSB

M45PE80 Instructions

27/48

6.9 Page Erase (PE)

The Page Erase (PE) instruction sets to 1 (FFh) all bits inside the chosen page. Before it

can be accepted, a Write Enable (WREN) instruction must previously have been executed.

After the Write Enable (WREN) instruction has been decoded, the device sets the Write

Enable Latch (WEL).

The Page Erase (PE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, and three address bytes on Serial Data Input (D). Any address inside the

Page is a valid address for the Page Erase (PE) instruction. Chip Select (S) must be driven

Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 14.

Chip Select (S) must be driven High after the eighth bit of the last address byte has been

latched in, otherwise the Page Erase (PE) instruction is not executed. As soon as Chip

Select (S) is driven High, the self-timed Page Erase cycle (whose duration is tPE) is initiated.

While the Page Erase cycle is in progress, the Status Register may be read to check the

value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-

timed Page Erase cycle, and is 0 when it is completed. At some unspecified time before the

cycle is complete, the Write Enable Latch (WEL) bit is reset.

A Page Erase (PE) instruction applied to a page that is Hardware Protected is not executed.

Any Page Erase (PE) instruction, while an Erase, Program or Write cycle is in progress, is

rejected without having any effects on the cycle that is in progress.

Figure 14. Page Erase (PE ) instruction sequence

1. Address bits A23 to A20 are Don’t Care.

24 Bit Address

AI04046

21 3456789 293031

Instruction

23 22 2 0

MSB

Instructions M45PE80

28/48

6.10 Sector Erase (SE)

The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it

can be accepted, a Write Enable (WREN) instruction must previously have been executed.

After the Write Enable (WREN) instruction has been decoded, the device sets the Write

Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, and three address bytes on Serial Data Input (D). Any address inside the

Sector (see Table 2) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

Chip Select (S) must be driven High after the eighth bit of the last address byte has been

latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip

Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is

initiated. While the Sector Erase cycle is in progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified

time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.

A Sector Erase (SE) instruction applied to a sector that contains a page that is Hardware

Protected is not executed.

Any Sector Erase (SE) instruction, while an Erase, Program or Write cycle is in progress, is

rejected without having any effects on the cycle that is in progress.

Fig ur e 15. Sect or E r ase (SE) instruction sequence

1. Address bits A23 to A20 are Don’t Care.

24 Bit Address

AI03751D

21 3456789 293031

Instruction

23 22 2 0

MSB

M45PE80 Instructions

29/48

6.11 Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction is the only way to put the device in the

lowest consumption mode (the Deep Power-down mode). It can also be used as an extra

software protection mechanism, while the device is not in active use, since in this mode, the

device ignores all Write, Program and Erase instructions.

Driving Chip Select (S) High deselects the device, and puts the device in the Standby mode

(if there is no internal cycle currently in progress). But this mode is not the Deep Power-

down mode. The Deep Power-down mode can only be entered by executing the Deep

Power-down (DP) instruction, to reduce the standby current (from ICC1 to ICC2, as specified

in Table 11).

To exit from Deep Power-down mode, the Release from Deep Power-down (RDP)

instruction must be issued. No other instruction must be issued while

the device is in this mode.

The Deep Power-down mode automatically stops at Power-down, and the device always

Powers-up in the Standby mode.

The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed

by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 16.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as

Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced

to ICC2 and the Deep Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in

progress, is rejected without having any effects on the cycle that is in progress.

Figu r e 16. Deep P o wer-do wn (DP) ins truction sequ ence

AI03753D

21 345670tDP

Deep Power-down Mode

Stand-by Mode

Instruction

Instructions M45PE80

30/48

6.12 Release from Deep Power-down (RDP)

To exit from Deep Power-down mode, the Release from Deep Power-down (RDP)

instruction must be issued. No other instruction must be issued while the device is in this

mode.

The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S)

Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be

driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 17.

The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select

(S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven

Low, cause the instruction to be rejected, and not executed.

After Chip Select (S) has been driven High, followed by a delay, tRDP

, the device is put in the

Standby mode. Chip Select (S) must remain High at least until this period is over. The

device waits to be selected, so that it can receive, decode and execute instructions.

Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write

cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 17. Release from Deep Power-down (RDP) instruction sequence

AI06807

21 345670t

RDP

Stand-by Mode

Deep Power-down Mode

QHigh Impedance

Instruction

M45PE80 Power- up and Power-down

31/48

7 Power-up and Power-down

At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must

follow the voltage applied on VCC) until VCC reaches the correct value:

VCC(min) at Power-up, and then for a further delay of tVSL

VSS at Power-down

A safe configuration is provided in Section 3: SPI modes.

To avoid data corruption and inadvertent write operations during power up, a Power On

Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less

than the POR threshold value, VWI – all operations are disabled, and the device does not

respond to any instruction.

Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program

(PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of tPUW has

elapsed after the moment that VCC rises above the VWI threshold. However, the correct

operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No

Write, Program or Erase instructions should be sent until the later of:

tPUW after VCC passed the VWI threshold

tVSL after VCC passed the VCC(min) level

These values are specified in Table 6.

If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be

selected for READ instructions even if the tPUW delay is not yet fully elapsed.

As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration

of the Power-up and Power-down phases.

At Power-up, the device is in the following state:

The device is in the Standby mode (not the Deep Power-down mode).

The Write Enable Latch (WEL) bit is reset.

The Write In Progress (WIP) bit is reset.

Normal precautions must be taken for supply rail decoupling, to stabilize the VCC feed. Each

device in a system should have the VCC rail decoupled by a suitable capacitor close to the

package pins. (Generally, this capacitor is of the order of 100 nF).

At Power-down, when VCC drops from the operating voltage, to below the POR threshold

value, VWI, all operations are disabled and the device does not respond to any instruction.

(The designer needs to be aware that if a Power-down occurs while a Write, Program or

Erase cycle is in progress, some data corruption can result.)

Power-up and Power- down M45PE80

32/48

Figure 18. Powe r-up tim i ng

Table 6. Powe r-U p timing and VWI threshol d

Symbol Parameter Min. Max. Unit

tVSL(1)

1. These parameters are characterized only, over the temperature range –40°C to +85°C.

VCC(min) to S low 30 μs

tPUW(1) Time delay before the first Write, Program or Erase instruction 1 10 ms

VWI(1) Write inhibit voltage 1.5 2.5 V

VCC

AI04009C

VCC(min)

VWI

Reset State

of the

Device

Chip Selection Not Allowed

Program, Erase and Write Commands are Rejected by the Device

tVSL

tPUW

tim

Read Access allowed Device fully

accessible

VCC(max)

M45PE80 Ini tia l delive r y s tate

33/48

8 Initial delivery state

The device is delivered with the memory array erased: all bits are set to 1 (each byte

contains FFh). All usable Status Register bits are 0.

9 Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. Refer also to the Numonyx SURE Program

and other relevant quality documents.

Table 7. Absolute ma ximum ra tings

Symbol Parameter Min. Max. Unit

TSTG Storage temperature –65 150 °C

TLEAD Lead temperature during soldering See (1)

1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx RoHS

complian 7191395 specification, and the European directive on Restrictions on Hazardous Substances

(RoHS) 2002/95/EU.

°C

VIO Input and output voltage (with respect to Ground) –0.6 VCC + 0.6 V

VCC Supply voltage –0.6 4.0 V

VESD Electrostatic Discharge Voltage (Human Body Model)(2)

2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

–2000 2000 V

DC and AC parameters M45PE80

34/48

10 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC Characteristic tables that

follow are derived from tests performed under the Measurement Conditions summarized in

the relevant tables. Designers should check that the operating conditions in their circuit

match the measurement conditions when relying on the quoted parameters.

1. Output Hi-Z is defined as the point where data out is no longer driven.

Fig ur e 19. AC me asurement I/ O wavefo rm

Table 8. Operating conditions

Symbol Parameter Min. Max. Unit

VCC Supply voltage 2.7 3.6 V

TAAmbient operating temperature –40 85 °C

Table 9. AC measur em ent conditions

Symbol Parameter Min. Max. Unit

CLLoad capacitance 30 pF

Input rise and fall times 5 ns

Input pulse voltages 0.2VCC to 0.8VCC V

Input and output timing reference voltages 0.3VCC to 0.7VCC V

Table 10. Capacitance (1)

1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 33 MHz.

Symbol Parameter Test Condition Min. Max. Unit

COUT Output capacitance (Q) VOUT = 0 V 8 pF

CIN Input capacitance (other pins) VIN = 0 V 6 pF

AI00825B

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

M45PE80 DC and AC paramete rs

35/48

Table 11. DC cha r acter istics

Symbol Parameter Test condition

(in addition to those in Table 8)Min. Max. Unit

ILI Input leakage current ± 2 μA

ILO Output leakage current ± 2 μA

ICC1

Standby current (Standby

and Reset modes) S = VCC, VIN = VSS or VCC 50 μA

ICC2 Deep Power-down current S = VCC, VIN = VSS or VCC 10 μA

ICC3

Operating current

(FAST_READ)

C = 0.1VCC / 0.9.VCC at 33 MHz,

Q = open 4

C = 0.1VCC / 0.9.VCC at 75 MHz,

Q = open 12

ICC4 Operating current (PW) S = VCC 15 mA

ICC5 Operating current (SE) S = VCC 15 mA

VIL Input low voltage – 0.5 0.3VCC V

VIH Input high voltage 0.7VCC VCC+0.4 V

VOL Output low voltage IOL = 1.6 mA 0.4 V

VOH Output high voltage IOH = –100 μAV

CC–0.2 V

DC and AC parameters M45PE80

36/48

Table 12. AC characteristics (33 MHz operation)

Test conditions specified in Table 8 and Table 9

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfC

Clock frequency for the following instructions:

FAST_READ, PW, PP, PE, SE, DP, RDID,

RDP, WREN, WRDI, RDSR

D.C. 33 MHz

fRClock frequency for READ instructions D.C. 20 MHz

tCH(1) tCLH Clock High time 13 ns

tCL(1) tCLL Clock Low time 13 ns

Clock slew rate(2) (peak to peak) 0.03 V/ns

tSLCH tCSS S active setup time (relative to C) 10 ns

tCHSL S not active hold time (relative to C) 10 ns

tDVCH tDSU Data In setup time 3 ns

tCHDX tDH Data In hold time 5 ns

tCHSH S active hold time (relative to C) 5 ns

tSHCH S not active setup time (relative to C) 5 ns

tSHSL tCSH S deselect time 200 ns

tSHQZ(2) tDIS Output Disable time 12 ns

tCLQV tVClock Low to Output Valid 12 ns

tCLQX tHO Output hold time 0 ns

tTHSL Top Sector Lock setup time 50 ns

tSHTL Top Sector Lock hold time 100 ns

tDP(2) S to Deep Power-down 3 μs

tRDP(2) S High to Standby Power mode 30 μs

tPW(3)

Page Write cycle time (256 bytes) 11

25 ms

Page Write cycle time (n bytes) 10.2+

n*0.8/256

tPP(3)

Page Program cycle time (256 bytes) 1.2

5ms

Page Program cycle time (n bytes) 0.4+

n*0.8/256

tPE Page Erase cycle time 10 20 ms

tSE Sector Erase cycle time 1 5 s

1. tCH + tCL must be greater than or equal to 1/ fC

2. Value guaranteed by characterization, not 100% tested in production.

3. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence

including all the bytes versus several sequences of only a few bytes. (1 ≤ n ≤ 256)

M45PE80 DC and AC paramete rs

37/48

Table 13. AC characteristics (50 MHz operation)

Test conditions specified in Table 8 an d Table 9

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfC

Clock frequency for the following instructions:

FAST_READ, PW, PP, PE, SE, DP, RDP,

WREN, WRDI, RDSR, RDID

D.C. 50 MHz

fRClock frequency for READ instructions D.C. 33 MHz

tCH(1) tCLH Clock High time 9 ns

tCL(1) tCLL Clock Low time 9 ns

Clock slew rate(2) (peak to peak) 0.1 V/ns

tSLCH tCSS S active setup time (relative to C) 5 ns

tCHSL S not active hold time (relative to C) 5 ns

tDVCH tDSU Data in setup time 2 ns

tCHDX tDH Data in hold time 5 ns

tCHSH S active hold time (relative to C) 5 ns

tSHCH S not active setup time (relative to C) 5 ns

tSHSL tCSH S deselect time 100 ns

tSHQZ(2) tDIS Output disable time 8 ns

tCLQV tVClock Low to Output Valid 8 ns

tCLQX tHO Output hold time 0 ns

tWHSL Write Protect setup time 50 ns

tSHWL Write Protect hold time 100 ns

tDP(2) S to Deep Power-down 3 μs

tRDP(2) S High to Standby mode 30 μs

tRLRH(2) tRST Reset pulse width 10 μs

tRHSL tREC Reset recovery time 3 μs

tSHRH

Chip should have been deselected before

Reset is de-asserted 10 ns

tPW(3) Page Write cycle time (256 bytes) 11 23 ms

tPP(3) Page Program cycle time (256 bytes) 0.8 3ms

Page Program cycle time (n bytes) int(n/8) × 0.025

tPE Page Erase cycle time 10 20 ms

tSE Sector Erase cycle time 1 5 s

1. tCH + tCL must be greater than or equal to 1/ fC

2. Value guaranteed by characterization, not 100% tested in production.

3. n = number of bytes to program. int(A) corresponds to the upper integer part of A. Examples: int(1/8) = 1, int(16/8) = 2,

int(17/8) = 3.

DC and AC parameters M45PE80

38/48

Table 14. AC characteristics (75 MHz operation)

Test conditions specified in Table 8 an d Table 9

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfC

Clock frequency for the following instructions:

FAST_READ, RDLR, PW, PP, WRLR, PE, SE,

SSE, DP, RDP, WREN, WRDI, RDSR, WRCR

D.C. 75 MHz

fRClock frequency for READ instructions D.C. 33 MHz

tCH(1) tCLH Clock High time 6 ns

tCL(1) tCLL Clock Low time 6 ns

Clock slew rate(2)(2) (peak to peak) 0.1 V/ns

tSLCH tCSS S active setup time (relative to C) 5 ns

tCHSL S not active hold time (relative to C) 5 ns

tDVCH tDSU Data in setup time 2 ns

tCHDX tDH Data in hold time 5 ns

tCHSH S active hold time (relative to C) 5 ns

tSHCH S not active setup time (relative to C) 5 ns

tSHSL tCSH S deselect time 100 ns

tSHQZ(2) tDIS Output disable time 8 ns

tCLQV tVClock Low to Output Valid under 30 pF / 10 pF 8/6 ns

tCLQX tHO Output hold time 0 ns

tWHSL(3) Write Protect setup time 20 ns

tSHWL(3) Write Protect hold time 100 ns

tDP(2) S to Deep Power-down 3 μs

tRDP(2) S High to Standby mode 30 μs

tWWrite status register cycle time 3 15 μs

tPW(4) Page Write cycle time (256 bytes) 11 23 ms

tPP(4) Page Program cycle time (256 bytes) 0.8 3ms

Page Program cycle time (n bytes) int(n/8) × 0.025(5)

tPE Page Erase cycle time 10 20 ms

tSE Sector Erase cycle time 1 5 s

1. tCH + tCL must be greater than or equal to 1/ fC

2. Value guaranteed by characterization, not 100% tested in production.

3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

4. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence

including all the Bytes versus several sequences of only a few Bytes (1 . n . 256).

5. int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.

M45PE80 DC and AC paramete rs

39/48

Figure 20. S e rial input timing

Figure 21. Write Protect s etup and hold timing

Figure 22. Output timing

AI01447C

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

High Impedance

tWHSL tSHWL

AI07439

AI01449e

LSB OUT

ADDR.LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

DC and AC parameters M45PE80

40/48

Fig ur e 23. Re set ac wavefo rms

Table 15. Rese t condit ions

Test conditions specified in Table 8 an d Table 9

Symbol Alt. Parameter Conditions Min. Typ. Max. Unit

tRLRH(1)

1. Value guaranteed by characterization, not 100% tested in production.

tRST Reset Pulse Width 10 μs

tSHRH

Chip Select High to

Reset High

Chip should have been

deselected before Reset is

de-asserted

10 ns

Table 16. Ti mings after a Reset Low pul se(1)

1. All the values are guaranteed by characterization, and not 100% tested in production.

Test conditions specified in Table 8 and Table 9

Symbol Alt. Parameter Conditions:

Reset pulse occurred Min. Typ. Max. Unit

tRHSL tREC

Reset

Recovery

time

While decoding an instruction(2):

WREN, WRDI, RDID, RDSR,

READ, Fast_Read, PW, PP, PE,

SE, DP, RDP

2. S remains Low while Reset is Low.

30 μs

Under completion of an Erase or

Program cycle of a PW, PP, PE, SE

operation

300 μs

Device deselected (S High) and in

Standby mode 0μs

AI06808

Reset tRLRH

tRHSLtSHRH

M45PE80 Packag e mechanical

41/48

11 Package mechanical

Figure 24. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Pac kag e No lead,

6 × 5 mm, pa ckage out line

1. Drawing is not to scale.

2. The circle in the top view of the package indicates the position of pin 1.

Table 17. VFQFPN8 (MLP8)8-l ead Very thin F ine Pitch Quad F lat Package No lead,

6 × 5 mm, package mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 0.85 0.80 1.00 0.0335 0.0315 0.0394

A1 0.00 0.05 0.0000 0.0020

A2 0.65 0.0256

A3 0.20 0.0079

b 0.40 0.35 0.48 0.0157 0.0138 0.0189

D 6.00 0.2362

D1 5.75 0.2264

D2 3.40 3.20 3.60 0.1339 0.1260 0.1417

E 5.00 0.1969

E1 4.75 0.1870

E2 4.00 3.80 4.30 0.1575 0.1496 0.1693

e 1.27 – – 0.0500 – –

R1 0.10 0.00 0.0039 0.0000

L 0.60 0.50 0.75 0.0236 0.0197 0.0295

Θ12° 12°

aaa 0.15 0.0059

bbb 0.10 0.0039

ddd 0.05 0.0020

70-M

AA3

eE2

ddd

bbb

CAB

aaa CAA

aaa CB

0.10 CA

0.10 CB

Package mechanical M45PE80

42/48

Figure 25. SO8 wide – 8 lead Plastic Sma ll Out line, 20 8 mils body width, package

outline

1. Drawing is not to scale.

2. The circle in the top view of the package indicates the position of pin 1.

Table 18. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, mechanical

data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 2.50 0.098

A1 0.00 0.25 0.000 0.010

A2 1.51 2.00 0.059 0.079

b 0.40 0.35 0.51 0.016 0.014 0.020

c 0.20 0.10 0.35 0.008 0.004 0.014

CP 0.10 0.004

D 6.05 0.238

E 5.02 6.22 0.198 0.245

E1 7.62 8.89 0.300 0.350

e 1.27 – – 0.050 – –

k 0° 10° 0° 10°

L 0.50 0.80 0.020 0.031

N8 8

6L_ME

LA1 k

M45PE80 Packag e mechanical

43/48

Fig ur e 26. SO8N - 8 lead Plastic Small Outline, 150 mils bo d y width, packag e o u tline

1. Drawing is not to scale.

Table 19. SO8N - 8 lead Plastic Sma ll Outline, 150 mils body width, pa ckage

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.75 0.069

A1 0.10 0.25 0.004 0.010

A2 1.25 0.049

b 0.28 0.48 0.011 0.019

c 0.17 0.23 0.007 0.009

ccc 0.10 0.004

D 4.90 4.80 5.00 0.193 0.189 0.197

E 6.00 5.80 6.20 0.236 0.228 0.244

E1 3.90 3.80 4.00 0.154 0.150 0.157

e 1.27 – – 0.050 – –

h 0.25 0.50 0.010 0.020

k0°8°0°8°

L 0.40 1.27 0.016 0.050

L1 1.04 0.041

SO-A

ccc

h x 45˚

0.25 mm

GAUGE PLANE

Package mechanical M45PE80

44/48

Fig ur e 27. QFN8L (MLP8 ) 8-lead, du al flat packa g e n o l ead, 6 × 5 mm, pack age

outline

1. Drawing is not to scale.

Table 20. QFN 8L (MLP8) 8-lead du al flat pack ag e no lead , 6 x 5 mm package

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 0.90 0.80 1.00 0.035 0.031 0.039

A1 0.02 0.00 0.05 0.001 0.000 0.002

A3 0.20 0.008

b 0.40 0.35 0.48 0.016 0.014 0.019

D 6.00 0.236

D2 3.00 2.80 3.20 0.118 0.110 0.126

E 5.00 0.197

E2 3.00 2.80 3.20 0.118 0.110 0.126

e 1.27 0.050

L 0.60 0.50 0.75 0.024 0.020 0.030

0.08

5X_ME

AA3 A1 E2/2

0PIN 1 ID OPTION

M45PE80 Par t number ing

45/48

12 Part numbering

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest Numonyx Sales Office.

The category of second Level Interconnect is marked on the package and on the inner box

label, in compliance with JEDEC Standard JESD97. The maximum ratings related to

soldering conditions are also marked on the inner box label.

Table 21. Ordering information scheme

Example: M45PE80 – V MP 6 T G

Device Type

M45PE = Page-Erasable Serial Flash Memory

Device Function

80 = 8 Mbit (1 Mbit x 8)

Operating Voltage

V = VCC = 2.7 to 3.6V

Package

MW = SO8W (208 mils width)

MP = VFQFPN8 6 × 5 mm (MLP8)

MN = SO8N (150 mils width)

MS = QFN 8L 6 x 5 mm, pitch1.2 mm

Device Grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

Option

blank = Standard Packing

T = Tape & Reel Packing

Plating Technology

P or G = RoHS compliant

Reference M45PE80
46/48   
13 Reference
AN1995: Serial Flash Memory Device Marking.
14 Revision history
         
Table 22. Doc um ent revision history
Date Version Changes
10-Feb-2003 1.0 Document written
02-Apr-2003 1.1 VFQFPN8 (MLP) package added
08-Apr-2003 1.2 Document promoted to Product Preview
05-May-2003 1.3 Document promoted to Preliminary Data
04-Jun-2003 1.4
Description corrected of entering Hardware Protected mode (W must be 
driven, and cannot be left unconnected). Document Revision History for 
05-May-2003 corrected.
26-Nov-2003 2.0
VIO(min) extended to –0.6V, and tPP(typ) improved to 1.2ms. Table of 
contents, SO16 package, warning about exposed paddle on MLP8, and 
Pb-free options added. Change of naming for VDFPN8 package. 
Document promoted to full datasheet
23-Jan-2004 3.0 SO16 pin-out corrected
28-May-2004 4.0 Soldering temperature information clarified for RoHS compliant devices. 
Device Grade clarified
10-May-2005 5.0
SO16 wide package replaced by SO8 wide package.
Active Power, Stand-by Power and Deep Power-Down modes, Read 
Identification (RDID), Dee p Power-down (DP), and R elease fr om Deep 
Power-down (RDP)  descriptions updated.
Table 21: Ordering information scheme updated. 
Figure 22:  Output timing updated.
4-Oct-2005 6.0
Added Table 12: AC cha r acteristics (33 MHz operation). An easy way to 
modi fy  data, A fast way to m odify data, P age Write (PW) and Page 
Program (PP ) sections updated to explain optimal use of Page Write and 
Page Program instructions. Updated ICC3 values in Table 11: DC 
characteristics. Updated Table 21: Ordering information scheme RoHS 
information added.
14-Feb-2006 7
X process technology added (see S ection 2. 5: Reset (Reset), Table 14: 
Reset timings fo r U process technology d evices and Table 15: Reset 
timi ngs for X proc ess technology devices). MLP package renamed as 
VFQFPN8, MLP silhouette modified on  pag e 1. TLEAD removed from 
Table 7: Absolute maximum ratings.
T able 5: Status Register Format moved from Sec tion 4 .7: S t atus  Reg iste r 
to Section 6.4: Read Status Register (RDSR). Blank option removed 
under Plat i ng Technol ogy in Table 21: Ordering information scheme.

M45PE80 Revision history
 47/48
15-Dec-2006 8
50 MHz frequency added, Tab le 13: AC characteristics (50 MHz 
operation) added. Small text changes.
Section 2. 5: Reset (Rese t) updated. VCC supply voltage and VSS 
ground descriptions added.
Figure 3: Bus master and memory devices  on t he SPI bus modified and 
explanatory text added.
Behavior of WIP bit specified at Power-up in Section 7: Power-up and 
Power-down.
VIO max modified and TLEAD added in Table 7: Absolute maxi mum 
ratings.
Table 15: Reset conditions and Tabl e 16 : Ti m i ng s  aft e r a R es e t Low 
pulse updated.
SO8N package added (T9HX technology only), SO8W and VFQFPN8 
package specifications updated (see Section 11 : Package mech anica l).
10-Dec-2007 9 Applied Numonyx branding.
11-Nov-2008 10
Added frequency up to 75 MHz frequency, including Table 14 .: AC 
chara cteristics (75 MHz operation);
Added new package, including Figure 27.: QFN 8L (MLP8) 8- l ead, dual 
flat package no lead, 6 × 5 mm, pa ckage outli ne and Table 20.: QF N 8L 
(MLP8) 8-lead dual fl at package no lead, 6 x 5 mm package mechanical 
data;
Added UID/CFD protection.
12-Dec-2008 11 Added the “UID columns” to Table 4. : Read Ident ificat ion (RDID ) data-o ut 
sequence.
Table 22. Doc um ent revision history
Date Version Changes

M45PE80

48/48

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