Low Cost, High Performance
Voltage Feedback, 325 MHz Amplifier
Data Sheet AD8057/AD8058
Rev. E Document Feedback
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FEATURES
Low cost single (AD8057) and dual (AD8058)
High speed
325 MHz, −3 dB bandwidth (G = +1)
1000 V/μs slew rate
Gain flatness: 0.1 dB to 28 MHz
Low noise
7 nV/√Hz
Low power
5.4 mA/amplifier typical supply current at 5 V
Low distortion
−85 dBc at 5 MHz, RL = 1 kΩ
Wide supply range from 3 V to 12 V
Small packaging
AD8057 is available in an 8-lead SOIC and 5-lead SOT-23
AD8058 is available in an 8-lead SOIC and an 8-lead MSOP
APPLICATIONS
Imaging
DVD/CD
Photodiode preamp
Analog-to-digital driver
Professional cameras filters
CONNECTION DIAGRAMS
+IN
+VS
–VS
AD8057
1
2
3
5
4–IN
VOUT
(Not to Scale)
01064-001
Figure 1. RT-5 (SOT-23)
8
7
6
5
1
2
3
4
NC
–IN
+IN
NC
+V
S
V
OUT
NC
–
V
S
AD8057
(Not to Scale)
NC = NO CONNE C T
01064-002
Figure 2. R-8 (SOIC)
OUT1
–IN1
+IN1
–V
S
+V
S
OUT2
–IN2
+IN2
1
2
3
4
8
7
6
5
(Not to Scale)
AD8058
01064-003
Figure 3. RM-8 (MSOP) and R-8 (SOIC)
GENERAL DESCRIPTION
The AD8057 (single) and AD8058 (dual) are very high perfor-
mance amplifiers with a very low cost. The balance between
cost and performance make them ideal for many applications.
The AD8057 and AD8058 reduce the need to qualify a variety
of specialty amplifiers. The AD8057 and AD8058 are voltage
feedback amplifiers with the bandwidth and slew rate normally
found in current feedback amplifiers. The AD8057 and AD8058
are low power amplifiers having low quiescent current and a wide
supply range from 3 V to 12 V. They have noise and distortion
performance required for high end video systems as well as dc
performance parameters rarely found in high speed amplifiers.
The AD8057 and AD8058 are available in standard SOIC
packaging as well as tiny 5-lead SOT-23 (AD8057) and 8-lead
MSOP (AD8058) packages. These amplifiers are available in the
industrial temperature range of −40°C to +85°C.
FRE QUENCY (MHz)
1100010
GAIN (dB)
100
5
4
–5
3
2
1
0
–1
–2
–3
–4
G = +2
G = +10
G = +5
G = +1
01064-004
Figure 4. Small Signal Frequency Response
AD8057/AD8058 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagrams ...................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ..............................................6
Test Circuits ..................................................................................... 12
Applications Information .............................................................. 13
Driving Capacitive Loads .......................................................... 13
Video Filter .................................................................................. 13
Differential Analog-to-Digital Driver ..................................... 14
Layout .......................................................................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
3/14—Rev. D to Rev. E
Change to Figure 48 .........................................................................14
9/13—Rev. C to Rev. D
Changes to Output Voltage Swing Parameter, Table 3 ................. 4
Updated Outline Dimensions ........................................................ 15
Changes to Ordering Guide ........................................................... 16
10/10—Rev. B to Rev. C
Updated Format .................................................................. Universal
Change to Third-Order Intercept Parameter, Table 1 ................. 3
Changes to Input Common-Mode Voltage Range Parameter,
Table 2 ................................................................................................ 4
Changes to Figure 32 ...................................................................... 10
Changes to Figure 35 ...................................................................... 11
Changes to Figure 41 and Figure 42 ............................................. 12
Changes to Figure 44 and Figure 45 ............................................. 13
Changes to Ordering Guide .......................................................... 16
8/03—Rev. A to Rev. B
Renumbered Figures and TPCs ........................................ Universal
Changes to Ordering Guide ............................................................. 4
Change to Figure 8 ......................................................................... 12
Update Outline Dimensions ......................................................... 14
Rev. E | Page 2 of 16
Data Sheet AD8057/AD8058
SPECIFICATIONS
At TA = 25°C, VS = ±5 V, RL = 100 Ω, RF = 0 Ω, gain = +1, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, V
O
= 0.2 V p-p
325
MHz
G = –1, VO = 0.2 V p-p 95 MHz
G = +1, VO = 2 V p-p 175 MHz
Bandwidth for 0.1 dB Flatness G = +1, VO = 0.2 V p-p 30 MHz
Slew Rate G = +1, VO = 2 V step, RL = 2 kΩ 850 V/µs
G = +1, V
O
= 4 V step, R
L
= 2 kΩ
1150
V/µs
Settling Time to 0.1% G = +2, VO = 2 V step 30 ns
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
f
C
= 5 MHz, V
O
= 2 V p-p, R
L
= 1 kΩ
–85
dBc
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ –62 dBc
SFDR f = 5 MHz, VO = 2 V p-p, RL = 150 Ω –68 dB
Third-Order Intercept f = 5 MHz, VO = 2 V p-p −35 dBm
Crosstalk, Output to Output f = 5 MHz, G = +2 −60 dB
Input Voltage Noise f = 100 kHz 7 nV/√Hz
Input Current Noise
f = 100 kHz
0.7
pA/√Hz
Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.01 %
NTSC, G = +2, RL = 1 kΩ 0.02 %
Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.15 Degrees
NTSC, G = +2, RL = 1 kΩ 0.01 Degrees
Overload Recovery
V
IN
= 200 mV p-p, G = +1
30
ns
DC PERFORMANCE
Input Offset Voltage 1 5 mV
T
MIN
to T
MAX
2.5
mV
Input Offset Voltage Drift 3 μV/°C
Input Bias Current 0.5 2.5 µA
TMIN to TMAX 3.0 µA
Input Offset Current ±0.75 µA
Open-Loop Gain VO = ±2.5 V, RL = 2 kΩ 50 55 dB
VO = ±2.5 V, RL = 150 Ω 50 52 dB
INPUT CHARACTERISTICS
Input Resistance
10
MΩ
Input Capacitance +Input 2 pF
Input Common-Mode Voltage Range RL = 1 kΩ −4.0 +4.0 V
Common-Mode Rejection Ratio VCM = ±2.5 V 48 60 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 2 kΩ −4.0 +4.0 V
RL = 150 Ω ±3.9 V
Capacitive Load Drive 30% overshoot 30 pF
POWER SUPPLY
Operating Range ±1.5 ±5.0 ±6 V
Quiescent Current for AD8057 6.0 7.5 mA
Quiescent Current for AD8058 14.0 15 mA
Power Supply Rejection Ratio VS = ±5 V to ±1.5 V 54 59 dB
Rev. E | Page 3 of 16
AD8057/AD8058 Data Sheet
At TA = 25°C, VS = 5 V, R L = 100 Ω, RF = 0 Ω, gain = +1, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth G = +1, VO = 0.2 V p-p 300 MHz
G = +1, VO = 2 V p-p 155 MHz
Bandwidth for 0.1 dB Flatness
V
O
= 0.2 V p-p
28
MHz
Slew Rate G = +1, VO = 2 V step, RL = 2 kΩ 700 V/µs
Settling Time to 0.1% G = +2, VO = 2 V step 35 ns
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ –75 dBc
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ –54 dBc
Crosstalk, Output to Output f = 5 MHz, G = +2 −60 dB
Input Voltage Noise f = 100 kHz 7 nV/√Hz
Input Current Noise
f = 100 kHz
0.7
pA/√Hz
Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.05 %
NTSC, G = +2, RL = 1 kΩ 0.05 %
Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.10 Degrees
NTSC, G = +2, RL = 1 kΩ 0.02 Degrees
DC PERFORMANCE
Input Offset Voltage 1 5 mV
TMIN to TMAX 2.5 mV
Input Offset Voltage Drift 3 μV/°C
Input Bias Current 0.5 2.5 µA
TMIN to TMAX 3.0 µA
Input Offset Current 0.75 µA
Open-Loop Gain VO = ±1.5 V, RL = 2 kΩ to midsupply 50 55 dB
VO = ±1.5 V, RL = 150 Ω to midsupply 45 52 dB
INPUT CHARACTERISTICS
Input Resistance 10 MΩ
Input Capacitance +Input 2 pF
Input Common-Mode Voltage Range
R
L
= 1 kΩ
0.9 to 3.4
V
Common-Mode Rejection Ratio VCM = ±2.5 V 48 60 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
L
= 2 kΩ
0.9 to 3.8
V
RL = 150 Ω 1.2 to 3.4 V
Capacitive Load Drive 30% overshoot 30 pF
POWER SUPPLY
Operating Range 3 5.0 10 V
Quiescent Current for AD8057 5.4 7.0 mA
Quiescent Current for AD8058 13.5 14 mA
Power Supply Rejection Ratio 54 58 dB
Rev. E | Page 4 of 16
Data Sheet AD8057/AD8058
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage (+VS to –VS) 12.6 V
Internal Power Dissipation1
SOIC Package (R) 0.8 W
SOT-23-5 Package (RT) 0.5 W
MSOP Package (RM) 0.6 W
Input Voltage (Common Mode) ±VS
Differential Input Voltage ±4.0 V
Output Short-Circuit Duration
Observe power
derating curves
Storage Temperature Range (R) −65°C to +125°C
Operating Temperature Range (A Grade) −40°C to +85°C
Lead Temperature (Soldering 10sec) 300°C
1 Specification is for device in free air:
8-lead SOIC package: θJA = 160°C/W
5-lead SOT-23-5 package: θJA = 240°C/W
8-Lead MSOP package: θJA = 200°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8057/AD8058 is limited by the associated rise in junction
temperature. Exceeding a junction temperature of 175°C for
an extended period can result in device failure. Although the
AD8057/AD8058 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction temper-
ature (150°C) is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum power
derating curves.
AMBI ENT T E M P E RATURE ( °C)
2.0
1.5
0
MAXIMUM POWER DISSIPATIO N (W)
–50 –40 –30 –20 –10 010 20 30 40 50 60 70 80 90
1.0
0.5
T
J
= 150° C
8-L E AD SOI C
8-LEAD MSOP
SOT-23-5
01064-005
Figure 5. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. E | Page 5 of 16
AD8057/AD8058 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
LOAD RESISTANCE (Ω)
4.5
4.0
0100k10k10 100
OUTPUT VOLTAGE (V)
1k
2.5
1.5
1.0
0.5
3.5
3.0
2.0
(+) OUTPUT
VOLTAGE
ABS (–)
OUTPUT
01064-006
Figure 6. Output Swing vs. Load Resistance
–40 –30 –20 –10 010 20 30 40 50 60 70 8085
TEMPERATURE (°C)
–3.0
–6.5
–8.0
–I
SUPPLY
(mA)
–3.5
–6.0
–7.0
–7.5
–4.5
–5.5
–4.0
–5.0 –ISUPPLY @ ±1. 5V
–ISUPPLY @ ±5V
01064-007
Figure 7. −ISUPPLY vs. Temperature
TEMPERATURE (°C)
5.0
1.5
0
VOLTS (V)
4.5
2.0
1.0
0.5
3.5
2.5
4.0
3.0
+5V SWI NG R
L
= 150Ω
+2.5V S WI NG R
L
= 150Ω
+1.5V S WI NG R
L
= 150Ω
–40 –30 –20 –10 010 20 30 40 50 60 70 8085
01064-008
Figure 8. Positive Output Voltage Swing vs. Temperature
TEMPERATURE (°C)
0
–3.5
–5.0
VOLTS (V)
–0.5
–3.0
–4.0
–4.5
–1.5
–2.5
–1.0
–2.0
–40 –30 –20 –10 010 20 30 40 50 60 70 8085
–1.5V S WI NG RL = 150Ω
–2.5V S WI NG RL = 150Ω
–5V SW ING RL = 150Ω
01064-009
Figure 9. Negative Output Voltage Swing vs. Temperature
6
–2
–6
VOS (mV)
–4
2
0
4
VOS @ ±5V
VOS @ ±1.5V
–40 –30 –20 –10 010 20 30 40 50 60 70 8085
TEMPERATURE (°C)
01064-010
Figure 10. VOS vs. Temperature
3.5
1.5
0
A
VOL
(mV/V)
0.5
2.5
2.0
3.0
1.0
A
VOL
@ ±5V
A
VOL
@ ±2.5V
–40 –30 –20 –10 010 20 30 40 50 60 70 8085
TEMPERATURE (°C)
01064-011
Figure 11. Open-Loop Gain vs. Temperature
Rev. E | Page 6 of 16
Data Sheet AD8057/AD8058
0
–0.4
–0.6
IB(µA)
–0.5
–0.2
–0.3
–0.1
–0.8
–0.7
TEMPERATURE (°C)
–40 –30 –20 –10 010 20 30 40 50 60 70 8085
+IB@ ±5V
–IB@ ±5V
–IB@ ±1.5V +IB@ ±1.5V
+IB@ ±2.5V
–IB@ ±2.5V
01064-012
Figure 12. Input Bias Current vs. Temperature
4
PSRR (mV/V)
1
0
3
2
PSRR @ ±1.5V ±5V
–40 –30 –20 –10 010 20 30 40 50 60 70 8085
TEMPERATURE (°C)
01064-013
Figure 13. PSRR vs. Temperature
FREQUENCY (MHz)
0
–10
–600.1 1000110 100
PSRR (dB)
–20
–30
–50
–40
–PSRR V
S
= ±2. 5V
+PSRR V
S
= ±2. 5V
01064-014
Figure 14. PSRR vs. Frequency
100mV
20mV/DIV
–100mV 4ns/DIV
01064-016
Figure 15. Small Signal Step Response G = +1, RL = 1 kΩ, VS = ±5 V,
See Figure 41 for Test Circuit
5V
1V/DIV
–5V 4ns/DIV
01064-017
Figure 16. Large Signal Step Response G = +1,RL = 1 kΩ, VS = ±5.0 V,
See Figure 41 for Test Circuit
100mV
20mV/DIV
0V
–100mV 4ns/DIV
01064-019
Figure 17. Small Signal Step Response G = –1, RL = 1 kΩ,
See Figure 42 for Test Circuit
Rev. E | Page 7 of 16
AD8057/AD8058 Data Sheet
5V
1V/DIV
–5V 4ns/DIV
01064-020
Figure 18. Large Signal Step Response G = –1, RL = 1 kΩ ,
See Figure 42 for Test Circuit
FREQUENCY (MHz)
1100010
GAI N ( dB)
100
5
4
–5
3
2
1
0
–1
–2
–3
–4
G = +2
G = +10
G = +5
G = +1
01064-021
Figure 19. Small Signal Frequency Response, VOUT = 0.2 V p-p
FREQUENCY (MHz)
1100010
GAI N ( dB)
100
5
4
–5
3
2
1
0
–1
–2
–3
–4
G = +2
G = +10
G = +1
G = +5
01064-022
Figure 20. Large Signal Frequency Response, VOUT = 2 V p-p
FREQUENCY (MHz)
1100010
GAI N ( dB)
100
5
4
–5
3
2
1
0
–1
–2
–3
–4
G = –2
G = –10
G = –5
G = –1
01064-023
Figure 21. Large Signal Frequency Response
FREQUENCY (MHz)
1100010
GAI N ( dB)
100
0.5
0.4
–0.5
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
VOUT = 0. 2V
G = +2
RL = 1.0kΩ
RF = 1.0kΩ
01064-024
Figure 22. 0.1 dB Flatness G = +2
FREQUENCY (MHz)
1100010
DISTORTION (dBc)
100
–50
–60
–110
–70
–80
–90
–100
THD
SECOND
THIRD
01064-025
Figure 23. Distortion vs. Frequency, RL = 150 Ω
Rev. E | Page 8 of 16
Data Sheet AD8057/AD8058
V
OUT
(V p-p)
–40
–50
–80 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.00
DISTORTION (dBc)
–60
–70
20MHz
5MHz
01064-026
Figure 24. Distortion vs. VOUT at 20 MHz, 5 MHz, RL = 150 Ω, VS = ±5.0 V
VOUT (V p-p)
5.0
4.5
001 2 3 4
3.0
1.5
1.0
0.5
4.0
3.5
2.0
2.5
RISE TIME AND FALL TIME (ns)
RISE TIME
FALL TIME
01064-027
Figure 25. Rise Time and Fall Time vs. VOUT, G = +1, RL = 1 kΩ, RF = 0 Ω
V
OUT
(V p-p)
5
4
001234
RISE TIME AND FALL TIME (ns)
3
2
1
RISE TIME
FALL TIME
01064-028
Figure 26. Rise Time and Fall Time vs. VOUT, G = +2, RL = 100 Ω, RF = 402 Ω
0.4%
0.3%
0.2%
0.1%
0%
–0.1%
–0.2%
–0.3%
–0.4%
010 20 30 40 50 60
TIME (ns)
V
OUT
= –1V T O + 1V OR +1V TO –1V
G = +2
R
L
= 100Ω/1kΩ
01064-029
Figure 27. Settling Time
500mV/
DIV
0V
20ns/DIV
2.5V
V
S
= ±2. 5V
R
L
= 1kΩ
G = +1
INPUT SIGNAL
OUTPUT RESPONSE
01064-030
Figure 28. Input Overload Recovery, VS = ±2.5 V
1V/DIV
0V
20ns/DIV
5.0V
V
S
= ±5. 0V
R
L
= 1kΩ
G = +1
INPUT SIGNAL 5V
OUTPUT SIGNAL = 4.0V
01064-031
Figure 29. Output Overload Recovery, VS = ±5.0 V
Rev. E | Page 9 of 16
AD8057/AD8058 Data Sheet
FREQUENCY (MHz)
0
–10
–70
–60
0.1 100101
CMRR (dB)
–20
–30
–50
–40
01064-032
Figure 30. CMRR vs. Frequency
200mV/
DIV
20ns/DIV
1.8V VS = ± 2.5V
R1 = 1kΩ
G = +4
INPUT SIGNAL = 0.6V
OUTPUT SIGNAL 1.7V
01064-033
Figure 31. Output Overload Recovery, VS = ±2.5 V
500mV/
DIV
20ns/DIV
4.5V V
S
= ±5V
R1 = 1kΩ
G = +4
01064-034
Figure 32. Output Overload Recovery, VS = ±5.0 V
FREQUENCY (MHz)
0
–20
–1200.1
CROSS TAL K ( dB)
–60
–80
–100
–40
SIDE B DRIVE N
SIDE A DRIVE N
110 100
01064-035
Figure 33. Crosstalk (Output-to-Output) vs. Frequency
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
DIFFERENTIAL GAIN (%)
DIF FERE NTIAL PHAS E ( Degrees)
01064-036
VS = ±5. 0V
RL = 150Ω
0.015
0.010
0.005
0
–0.005
–0.010
–0.015
0.14
0.12
0.10
0.06
0.02
0.08
0.04
0
–0.02
VS = ± 5. 0V
RL = 150Ω
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
DIFFERENTIAL GAIN (%)
DIF FERE NTIAL PHAS E ( Degrees)
01064-037
VS
= ±5. 0V
R
L
= 1kΩ
0.015
0.010
0.005
0
–0.005
–0.010
–0.015
0.14
0.12
0.10
0.06
0.02
0.08
0.04
0
–0.02
V
S
= ±5. 0V
R
L
= 1kΩ
Figure 34. Differential Gain and Differential Phase One Back Terminated
Load (150 Ω) (Video Op Amps Only)
Rev. E | Page 10 of 16
Data Sheet AD8057/AD8058
FREQUENCY (MHz)
180
135
–90
0.01
PHASE ( Degrees)
45
0
–45
90
80
60
40
20
0
–20
OPEN-LOOP GAIN (dB)
0.1 110 100 1000
GAIN
01064-038
Figure 35. Open-Loop Gain and Phase vs. Frequency
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
DIFFERENTIAL GAIN (%)
DIF FERE NTIAL PHAS E ( Degrees)
01064-039
V
S
= +5V
R
L
= 150Ω
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
0.14
0.12
0.10
0.06
0.02
0.08
0.04
0
–0.02
V
S
= +5V
R
L
= 150Ω
Figure 36. Differential Gain and Differential Phase, RL = 150 Ω
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
DIFFERENTIAL GAIN (%)
DIF FERE NTIAL PHAS E ( Degrees)
01064-040
V
S
= +5V
R
L
= 1kΩ
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
0.14
0.12
0.10
0.06
0.02
0.08
0.04
0
–0.02
V
S
= +5V
R
L
= 1kΩ
Figure 37. Differential Gain and Differential Phase, RL = 1 kΩ
FREQUENCY ( Hz )
100
10
0.110 100 1k 10k 100k 1M 10M 100M
VNOISE (nV/√Hz)
1
01064-041
Figure 38. Voltage Noise vs. Frequency
FREQUENCY ( Hz )
100
10
0.110 100 1k 10k 100k 1M 10M 100M
INOISE (pA/√Hz)
1
01064-042
Figure 39. Current Noise vs. Frequency
100
10
ZOUT (Ω)
1
0.1 1FREQUENCY (MHz)
10 1000100
0.1
01064-043
Figure 40. Output Impedance vs. Frequency
Rev. E | Page 11 of 16
AD8057/AD8058 Data Sheet
TEST CIRCUITS
0.01µF
0.001µF
4.7µF
50Ω
V
IN
HP8130A
PULSE
GENERATOR
T
R
/T
F
= 1ns
AD8057
AD8058
0.001µF
0.01µF
4.7µF
1kΩ
+V
S
–V
S
V
OUT
01064-015
Figure 41. Test Circuit, G = +1, RL = 1 kΩ
0.01µF
0.001µF
4.7µF
–VS
+VS
VIN 1kΩ
50Ω
HP8130A
PULSE
GENERATOR
TR/TF = 1ns AD8057
AD8058 1kΩ
1kΩ
V
OUT
01064-018
0.001µF
0.01µF
4.7µF
Figure 42. Test Circuit, G = −1, RL = 1 kΩ
Rev. E | Page 12 of 16
Data Sheet AD8057/AD8058
APPLICATIONS INFORMATION
DRIVING CAPACITIVE LOADS
When driving a capacitive load, most op amps exhibit overshoot in
their pulse response. Figure 43 shows the relationship between
the capacitive load that results in 30% overshoot and the closed-
loop gain of an AD8058. It can be seen that, under the gain = +2
condition, the device is stable with capacitive loads of up to 69 pF.
In general, to minimize peaking or to ensure device stability for
larger values of capacitive loads, a small series resistor (RS) can
be added between the op amp output and the load capacitor
(CL) as shown in Figure 44.
For the setup shown in Figure 44, the relationship between RS
and CL was empirically derived and is shown in Table 4.
CLOSED-LOOP GAIN
500
400
051 2 3 4
C
L
(pF)
300
200
100
R
S
= 2.4Ω
R
S
= 0Ω
01064-044
Figure 43. Capacitive Load Drive vs. Closed-Loop Gain
–2.5V
RG
RF
RS
CL
VIN = 200mV p-p
AD8058
0.1µF 10µF
0.1µF
10µF
+2.5V
VOUT
FET PROBE
01064-045
Figure 44. Capacitive Load Drive Circuit
Table 4. Recommended Value for Resistors RS, RF, RG vs.
Capacitive Load, CL, Which Results in 30% Overshoot
Gain RF RG CL (RS = 0 Ω) CL (RS = 2.4 Ω)
1 100 Ω 11 pF 13 pF
2 100 Ω 100 Ω 51 pF 69 pF
3 100 Ω 50 Ω 104 pF 153 pF
4 100 Ω 33.2 Ω 186 pF 270 pF
5 100 Ω 25 Ω 245 pF 500 pF
10 100 Ω 11 Ω 870 pF 1580 pF
50ns/DIV
100mV
–100mV
200mV
–200mV
+OVERSHOOT
29.0%
100mV/DIV
01064-046
Figure 45. Typical Pulse Response with CL = 65 pF, Gain = +2, and VS = ±2.5
VIDEO FILTER
Some composite video signals that are derived from a digital
source contain some clock feedthrough that can cause problems
with downstream circuitry. This clock feedthrough is usually at
27 MHz, which is a standard clock frequency for both NTSC
and PAL video systems. A filter that passes the video band and
rejects frequencies at 27 MHz can be used to remove these fre-
quencies from the video signal.
Figure 46 shows a circuit that uses an AD8057 to create a single
5 V supply, 3-pole Sallen-Key filter. This circuit uses a single RC
pole in front of a standard 2-pole active section. To shift the dc
operating point to midsupply, ac coupling is provided by R4, R5,
and C4.
2
3
0.1µF +10µF
AD8057
7
4
6
+5V
+5V
R4
10kΩ
R5
10kΩ
C4
0.1µF
R3
49.9Ω
R2
499Ω
C1
100pF
R1
200Ω
R
F
1kΩ
C2
680pF
C3
36pF
01064-047
Figure 46. Low-Pass Filter for Video
Rev. E | Page 13 of 16
AD8057/AD8058 Data Sheet
Figure 47 shows a frequency sweep of this filter. The response is
down 3 dB at 5.7 MHz; therefore, it passes the video band with
little attenuation. The rejection at 27 MHz is 42 dB, which
provides more than a factor of 100 in suppression of the clock
components at this frequency.
FREQUENCY (MHz)
0
10
–10
–90
–70
–80
–60
100k 100M10M1M
LOG MAGNITUDE (dB)
–20
–30
–50
–40
01064-048
Figure 47. Video Filter Response
DIFFERENTIAL ANALOG-TO-DIGITAL DRIVER
As system supply voltages are dropping, many ADCs provide
differential analog inputs to increase the dynamic range of the
input signal while still operating on a low supply voltage.
Differential driving can also reduce second and other even-
order distortion products.
Analog Devices, Inc., offers an assortment of 12- and 14-bit
high speed converters that have differential inputs and can be
run from a single 5 V supply. These include the AD9220, AD9221,
AD9223, AD9224, and AD9225 at 12 bits, and the AD9240,
AD9241, and AD9243 at 14 bits. Although these devices can
operate over a range of common-mode voltages at their analog
inputs, they work best when the common-mode voltage at the
input is at the midsupply or 2.5 V.
Op amp architectures that require upwards of 2 V of headroom
at the output have significant problems when trying to drive
such ADCs while operating with a 5 V positive supply. The low
headroom output design of the AD8057 and AD8058 make
them ideal for driving these types of ADCs.
The AD8058 can be used to make a dc-coupled, single-ended-
to-differential driver for one of these ADCs. Figure 48 is a
schematic of such a circuit for driving an AD9225, 12-bit,
25 MSPS ADC.
2
3
0.1µF 10µF
0.1µF 10µF
0.1µF 10µF
+
8
1
+5V
1kΩ
AD8058
1kΩ
1kΩ
1kΩ
1kΩ
50Ω
50Ω
1kΩ
1kΩ
1kΩ 6
5
7
+
–5V
4
VIN
0V
VINB
VINA
AD9225
+5V
+
REF
+2.5V
AD8058
01064-049
Figure 48. Schematic Circuit for Driving AD9225
In this circuit, one of the op amps is configured in the inverting
mode whereas the other is in the noninverting mode. However,
to provide better bandwidth matching, each op amp is configured
for a noise gain of +2. The inverting op amp is configured for a
gain of −1 and the noninverting op amp is configured for a gain
of +2. Each of these produces a noise gain of +2, which is deter-
mined only by the inverse of the feedback ratio. The input signal to
the noninverting op amp is divided by two to normalize its level
and make it equal to the inverting output.
For 0 V input, the outputs of the op amps want to be at 2.5 V,
which is the midsupply level of the ADCs. This is accomplished by
first taking the 2.5 V reference output of the ADC and dividing it
by two by a pair of 1 kΩ resistors. The resulting 1.25 V is applied to
the positive input of each op amp. This voltage is then multiplied by
the gain of +2 of the op amps to provide a 2.5 V level at each output.
The assumption for this circuit is that the input signal is bipolar
with respect to ground and the circuit must be dc-coupled thereby
implying the existence of a negative supply elsewhere in the system.
This circuit uses −5 V as the negative supply for the AD8058.
Tying the negative supply of the AD8058 to ground causes a
problem at the input of the noninverting op amp. The input
common-mode voltage can only go to within 1 V of the negative
rail. Because this circuit requires that the positive inputs operate
with a 1.25 V bias, there is not enough room to swing this voltage
in the negative direction. The inverting stage does not have this
problem because its common-mode input voltage remains fixed
at 1.25 V. If dc coupling is not required, various ac coupling
techniques can be used to eliminate this problem.
LAYOUT
The AD8057 and AD8058 are high speed op amps for use in a
board layout that follows standard high speed design rules. Make
all signal traces as short and direct as possible. In particular, keep
the parasitic capacitance on the inverting input of each device
to a minimum to avoid excessive peaking and other undesirable
performance. Bypass the power supplies very close to the power pins
of the package with a 0.1 µF capacitor in parallel with a larger
(approximately 10 µF) tantalum capacitor. Connect these capacitors
to a ground plane that either is on an inner layer or fills the area
of the board that is not used for other signals.
Rev. E | Page 14 of 16
Data Sheet AD8057/AD8058
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 49. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 50. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
Rev. E | Page 15 of 16
AD8057/AD8058 Data Sheet
COMPLIANT TO JEDEC STANDARDS MO-178-AA
10°
5°
0°
SEATING
PLANE
1.90
BSC
0.95 BSC
0.60
BSC
5
1 2 3
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0.15 MAX
0.05 MIN
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.35 MIN
0.55
0.45
0.35
11-01-2010-A
Figure 51. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Notes
Temperature
Range Package Description
Package
Option Branding
AD8057AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8057AR-REEL −40°C to +85°C 8-Lead SOIC_N, 13” Tape and Reel R-8
AD8057AR-REEL7
−40°C to +85°C
8-Lead SOIC_N, 7” Tape and Reel
R-8
AD8057ARZ −40°C to +85°C 8-Lead SOIC_N R-8
AD8057ARZ-REEL −40°C to +85°C 8-Lead SOIC_N, 13” Tape and Reel R-8
AD8057ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7” Tape and Reel R-8
AD8057ACHIPS −40°C to +85°C Die Waffle Pak
AD8057ART-R2 −40°C to +85°C 5-Lead SOT-23 RJ-5 H7A
AD8057ART-REEL7 −40°C to +85°C 5-Lead SOT-23 RJ-5 H7A
AD8057ARTZ-R2 −40°C to +85°C 5-Lead SOT-23 RJ-5 H08
AD8057ARTZ-REEL −40°C to +85°C 5-Lead SOT-23 RJ-5 H08
AD8057ARTZ-REEL7 −40°C to +85°C 5-Lead SOT-23 RJ-5 H08
AD8057AR-EBZ −40°C to +85°C 8-Lead SOIC_N Evaluation Board
AD8057ART-EBZ
−40°C to +85°C
5-Lead SOT-23 Evaluation Board
AD8058AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8058AR-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7” Tape and Reel R-8
AD8058ARZ
−40°C to +85°C
8-Lead SOIC_N
R-8
AD8058ARZ-REEL −40°C to +85°C 8-Lead SOIC_N, 13” Tape and Reel R-8
AD8058ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7” Tape and Reel R-8
AD8058ACHIPS −40°C to +85°C Die Waffle Pak
AD8058ARM −40°C to +85°C 8-Lead MSOP RM-8 H8A
AD8058ARM-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 H8A
AD8058ARMZ-REEL7 2−40°C to +85°C 8-Lead MSOP RM-8 H8A
AD8058ARMZ 2−40°C to +85°C 8-Lead MSOP RM-8 H8A
AD8058ARMZ-REEL 2−40°C to +85°C 8-Lead MSOP RM-8 H8A
AD8058AR-EBZ −40°C to +85°C 8-Lead SOIC_N Evaluation Board
AD8058ARM-EBZ −40°C to +85°C 8-Lead MSOP Evaluation Board
1 Z = RoHS Compliant Part.
2 Bottom mark has # sign before date code.
©2010–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01064-0-3/14(E)
Rev. E | Page 16 of 16
