1
Precision Edge®
SY89874U
Micrel, Inc.
M9999-031208
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
■Integrated programmable clock divider and 1:2
fanout buffer
■Guaranteed AC performance over temperature and
voltage:
• > 2.5GHz fMAX
• < 250ps tr/tf
• < 15ps within device skew
■Low jitter design:
• < 10psPP total jitter
• < 1psRMS cycle-to-cycle jitter
■Unique input termination and VT pin for DC-coupled
and AC-coupled Inputs; CML, PECL, LVDS and
HSTL
■TTL/CMOS inputs for select and reset
■100k EP compatible LVPECL outputs
■Parallel programming capability
■Programmable divider ratios of 1, 2, 4, 8 and 16
■Low voltage operation 2.5V or 3.3V
■Output disable function
■–40°C to 85°C temperature range
■Available in 16-pin (3mm x 3mm) MLF® package
FEATURES
2.5GHz ANY DIFF. IN-TO-LVPECL
PROGRAMMABLE CLOCK DIVIDER/
FANOUT BUFFER WITH INTERNAL TERMINATION
Precision Edge®
SY89874U
APPLICATIONS
■SONET/SDH line cards
■Transponders
■High-end, multiprocessor sensors
Rev.: F Amendment: /0
Issue Date: March 2008
This low-skew, low-jitter device is capable of accepting a
high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or
HSTL clock input signal and dividing down the frequency
using a programmable divider ratio to create a frequency-
locked, lower speed version of the input clock. Available divider
ratios are 2, 4, 8 and 16, or straight pass-through. In a typical
622MHz clock system this would provide availability of
311MHz, 155MHz, 77MHz or 38MHz auxiliary clock
components.
The differential input buffer has a unique internal termination
design that allows access to the termination network through
a VT pin. This feature allows the device to easily interface to
different logic standards. A VREF-AC reference is included for
AC-coupled applications.
The /RESET input asynchronously resets the divider. In
the pass-through function (divide by 1) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /N).
FUNCTIONAL BLOCK DIAGRAM
TYPICAL PERFORMANCE
Precision Edge is a registered trademark of Micrel, Inc.
Micro
LeadFrame and MLF are trademarks of Amkor Technology, Inc.
IN
/IN
S0
S1
Q1
/Q1
Q0
/Q0
R0
R1
/RESET
V
T
V
REF-AC
S2
Divided
by
2, 4, 8
or 16
Enable
MUX
MUX
Enable
FF
Decoder
Divide-by-4
LVDS
622MHz
Clock In
OC-12 to OC-3
Translator/Divider
LVPECL
155.5MHz
Clock Out
622MHz In
/Q0
Q0
/IN
IN
155.5MHz Out
Precision Edge®
2
Precision Edge®
SY89874U
Micrel, Inc.
M9999-031208
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Pin Number Pin Name Pin Function
12, 9 IN, /IN Differential Input: Internal 50Ω termination resistors to VT input. Flexible input accepts any
differential input. See “Input Interface Applications” section.
1, 2, 3, 4 Q0, /Q0 Differential Buffered LVPECL Outputs: Divided by 1, 2, 4, 8 or 16. See “Truth Table.”
Q1, /Q1 Unused PECL outputs may be left floating with no impact on jitter performance.
16, 15, 5 S0, S1, S2 Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25kΩ pull-up
resistor. Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is VCC/2.
6 NC No Connect.
8 /RESET LVTTL/CMOS Logic Levels: Internal 25kΩ pull-up resistor. Logic HIGH if left unconnected.
/DISABLE Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a synchronous
disable/enable function. The reset and disable function occurs on the next high-to-low
clock input transition. Input threshold is VCC/2.
10 VREF-AC Reference Voltage: Equal to VCC–1.4V (approx.). Used for AC-coupled applications only.
Decouple the VREF-AC pin with a 0.01µF capacitor. See “Input Interface Applications” section.
11 VT Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, see
Figures 2a to 2f “Input Interface Applications” section.
7, 14 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitor.
13 GND Ground.
PIN DESCRIPTION
13141516
12
11
10
9
1
2
3
4
8765
Q0
/
Q0
Q1
/
Q1
IN
VT
VREF-AC
/IN
S0
S1
VCC
GND
S2
NC
VCC
/
RESET
16-Pin MLF® (MLF-16)
/RESET(1) S2 S1 S0 Outputs
1 0 X X Reference Clock (pass through)
1 1 0 0 Reference Clock ÷2
1 1 0 1 Reference Clock ÷4
1 1 1 0 Reference Clock ÷8
1 1 1 1 Reference Clock ÷16
0(1) 1 X X Q = LOW, /Q = HIGH
Clock Disable
Note 1. Reset/Disable function is asserted on the next clock input
(IN, /IN) high-to-low transition.
TRUTH TABLE
Ordering Information(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY89874UMI MLF-16 Industrial 874U Sn-Pb
SY89874UMITR(2) MLF-16 Industrial 874U Sn-Pb
SY89874UMG(3) MLF-16 Industrial 874U with NiPdAu
Pb-Free bar line indicator Pb-Free
SY89874UMGTR(2, 3) MLF-16 Industrial 874U with NiPdAu
Pb-Free bar line indicator Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
3
Precision Edge®
SY89874U
Micrel, Inc.
M9999-031208
hbwhelp@micrel.com or (408) 955-1690
Note 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng
conditions for extended periods may affect device reliability.
Note 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 3. Due to the limited drive capability use for input of the same package only.
Note 4. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the pcb.
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) .................................. –0.5V to +4.0V
Input Voltage (VIN) .................................. –0.5V to VCC+0.3
ECL Output Current (IOUT)
Continuous .........................................................50mA
Surge................................................................100mA
Input Current IN, /IN (IIN)..........................................±50mA
VT Current (IVT) ......................................................±100mA
VREF-AC Sink/Source Current (IVREF-AC), Note 3.......±2mA
Lead Temperature (soldering 20 sec.) ...................... 260°C
Storage Temperature (TS) .......................–65°C to +150°C
Operating Ratings(Note 2)
Supply Voltage (VCC) ................+3.3V ±10% or +2.5V ±5%
Ambient Temperature (TA).........................–40°C to +85°C
Package Thermal Resistance
MLF® (θJA)
Still-Air .............................................................60°C/W
500lfpm............................................................54°C/W
MLF® (ψJB), Note 4
Junction-to-Board ............................................32°C/W
TA= –40°C to +85°C; Unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VCC Power Supply 2.375 3.63 V
ICC Power Supply Current No load, max. VCC 50 75 mA
RIN Differential Input Resistance 90 100 110 Ω
(IN-to-/IN)
VIH Input High Voltage (IN, /IN) Note 3 0.1 –VCC+0.3 V
VIL Input Low Voltage (IN, /IN) Note 3 –0.3 –VIH–0.1 V
VIN Input Voltage Swing Notes 3, 4 0.1 –VCC V
VDIFF_IN Differential Input Voltage Swing Notes 3, 4, 5 0.2 –V
|IIN| Input Current (IN, /IN) Note 3 ––45 mA
VREF-AC Reference Voltage Note 6 VCC–1.525 VCC–1.425 VCC–1.325 V
Note 1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2. Specification for packaged product only.
Note 3. Due to the internal termination (see
“Input Structures”
) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply
a combination of voltages that causes the input current to exceed the maximum limit!
Note 4. See
“Timing Diagram”
for VIN definition. VIN (Max) is specified when VT is floating.
Note 5. See
“Typical Operating Characteristics”
section for VDIFF definition.
Note 6. Operating using VIN is limited to AC-coupled PECL or CML applications only. Connect directly to VT pin.
DC ELECTRICAL CHARACTERISTICS(Notes 1, 2)
VCC = 3.3V ±10% or 2.5V ±5%; TA = –40°C to +85°C, RL = 50Ω to VCC –2V; Unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VOH Output High Voltage VCC–1.145 VCC–1.020 VCC–0.895 V
VOL Output Low Voltage VCC–1.945 VCC–1.820 VCC–1.695 V
VOUT Output Voltage Swing 550 800 1050 mV
VDIFF_OUT Differential Output Voltage Swing 1.10 1.60 2.10 V
Note 1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2. Specification for packaged product only.
(100KEP) LVPECL DC ELECTRICAL CHARACTERISTICS(Notes 1, 2)
4
Precision Edge®
SY89874U
Micrel, Inc.
M9999-031208
hbwhelp@micrel.com or (408) 955-1690
VCC = 3.3V ±10% or 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
IIH Input HIGH Current –125 20 µA
IIL Input LOW Current –300 µA
Note 1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2. Specification for packaged product only.
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(Notes 1, 2)
5
Precision Edge®
SY89874U
Micrel, Inc.
M9999-031208
hbwhelp@micrel.com or (408) 955-1690
VCC = 3.3V ±10% or 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
fMAX Maximum Output Toggle Frequency Output Swing ≥ 400mV 2.5 GHz
Maximum Input Frequency Divide by 2, 4, 8, 16 3.2 GHz
tPD Differential Propagation Delay Input Swing < 400mV 540 650 790 ps
IN to Q Input Swing ≥ 400mV 480 600 730 ps
tSKEW Within-Device Skew (diff.) Note 3 715 ps
Q0–Q1
Part-to-Part Skew (diff.) Note 3 250 ps
tRR Reset Recovery Time Note 4 600 ps
Tjitter Cycle-to-Cycle Jitter Note 5 1ps
RMS
Total Jitter Note 6 10 psPP
tr,tfRise/Fall Time (20% to 80%) 70 150 250 ps
Note 1. Measured with 400mV input signal, 50% duty cycle, all outputs loaded with 50Ω to VCC–2V, unless otherwise stated.
Note 2. Specification for packaged product only.
Note 3. Skew is measured between outputs under identical transitions.
Note 4. See
“Timing Diagram.”
Note 5. Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc=Tn–Tn+1,
where T is the time between rising edges of the output signal.
Note 6. Total jitter definition: with an ideal clock input, of frequency ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by more
than the specified peak-to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS(Notes 1, 2)
TIMING DIAGRAM
VIN
/RESET
IN
/IN
/Q
Q
tPD
tRR
VCC/2
VIN Swing
VOUT Swing
6
Precision Edge®
SY89874U
Micrel, Inc.
M9999-031208
hbwhelp@micrel.com or (408) 955-1690
TYPICAL OPERATING CHARACTERISTICS
VCC = 3.3V, VIN = 400mV, TA = 25°C, unless otherwise stated.
0
100
200
300
400
500
600
700
800
900
0
500
1000
1500
2000
2500
3000
3500
QA AMPLITUDE (mV)
FREQUENCY (MHz)
QA Output Amplitude
vs. Frequency
0
100
200
300
400
500
600
700
800
900
0 200 400 600 800 1000 1200
PROPAGATION DELAY (ps)
INPUT SWING (mV)
IN to Q Propagation Delay
vs. Input Swing
400
500
600
700
800
-40 -20 0 20 40 60 80 100 120
PROPAGATION DELAY (ps)
TEMPERATURE (°C)
IN to Q Propagation Delay
vs. Temperature
622MHz Output
TIME (200ps/div.)
Output Swing
(100mV/div.)
/Q
Q
1.25GHz Output
TIME (200ps/div.)
Output Swing
(100mV/div.)
/Q
Q
2.5GHz Output
TIME (100ps/div.)
Output Swing
(100mV/div.)
/Q
Q
7
Precision Edge®
SY89874U
Micrel, Inc.
M9999-031208
hbwhelp@micrel.com or (408) 955-1690
INPUT BUFFER STRUCTURE
V
CC
GND
50Ω
50Ω
IN
V
T
/IN
1.86kΩ
1.86kΩ1.86kΩ
1.86kΩ
Figure 2a. Simplified Differential Input Buffer
VCC
GND
S0
S1
S2
/RESET
R25kΩ
R
Figure 2b. Simplified TTL/CMOS Input Buffer
DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING
VIN, VOUT
800mV
(typical)
1600mV (typical)
VDIFF_IN, VDIFF_OUT
Figure 1a. Single-Ended Swing Figure 1b. Differential Swing
8
Precision Edge®
SY89874U
Micrel, Inc.
M9999-031208
hbwhelp@micrel.com or (408) 955-1690
INPUT INTERFACE APPLICATIONS
CML IN
/IN
V
T
NC
GND
SY89874U
V
CC
V
CC
V
REF-AC
NC
Figure 3a. DC-Coupled CML
Input Interface
CML IN
/IN
V
T
GND
SY89874U
V
CC
V
CC
V
REF-AC
V
CC
0.01µF
Figure 3b. AC-Coupled CML
Input Interface
PECL IN
/IN
VT
GND SY89874U
V
CC
V
CC
V
REF-AC
NC
50Ω
* Bypass with 0.01µF to V
CC
0.01µF
V
CC
–2V*
V
CC
Figure 3c. DC-Coupled PECL
Input Interface
PECL IN
/IN
VT
GND
SY89874U
VCC
Rpd*
*Note. 3.3V = Rpd = 100Ω
2.5V = Rpd = 50Ω
Rpd*
VCC
GND VREF-AC
VCC
0.01µF
Figure 3d. AC-Coupled PECL
Input Interface
LVDS IN
/IN
VT
NC
GND
SY89874U
VCC VCC
VREF-AC
NC
Figure 3e. LVDS
Input Interface
HSTL IN
/IN
V
T
GND
SY89874U
V
CC
V
CC
GND
NC V
REF-AC
Figure 3f. HSTL
Input Interface
Part Number Function Data Sheet Link
SY89871U 2.5GHz Any Diff. In-to-LVPECL http://www.micrel.com/product-info/products/sy89871u.shtml
Programmable Clock Divider/Fanout Buffer
w/Internal Termination
MLF® Application Note http://www.amkor.com/products/notes_papers/mlf_appnote_0902.pdf
HBW Solutions New Products and Applications http://www.micrel.com/product-info/products/solutions.shtml
RELATED PRODUCT AND SUPPORT DOCUMENTATION
9
Precision Edge®
SY89874U
Micrel, Inc.
M9999-031208
hbwhelp@micrel.com or (408) 955-1690
LVPECL OUTPUT TERMINATION RECOMMENDATIONS
R2
82Ω
R2
82Ω
Z
O
= 50Ω
Z
O
= 50Ω
+3.3V +3.3V
V
t
= V
CC
—2V
R1
130ΩR1
130Ω
+3.3V
Figure 4a. Parallel Termination–Thevenin Equivalent
Note 1. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω
Z = 50Ω
Z = 50Ω
50Ω50Ω
50Ω
+3.3V +3.3V
“source”“destination”
Rb(Optional)
C1
0.01µF
Figure 4b. Three-Resistor “Y–Termination”
Note 1. Power-saving alternative to Thevenin termination.
Note 2. Place termination resistors as close to destination inputs as possible.
Note 3. Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 46Ω to 50Ω. For +2.5V systems Rb = 39Ω
Note 4. C1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches.
+3.3V +3.3V
Z
O
= 50Ω
R2
82Ω
+3.3V +3.3V
R1
130ΩR1
130Ω
R2
82Ω
V
t
= V
CC
—2V
Q
/Q
R3
1kΩ
R4
1.6kΩ
V
t
= V
CC
—1.3V
Figure 4d. Terminating Unused I/O
Note 1. Unused output (/Q) must be terminated to balance the output.
Note 2. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω, R3 = 1.25kΩ, R4 = 1.2kΩ.
10
Precision Edge®
SY89874U
Micrel, Inc.
M9999-031208
hbwhelp@micrel.com or (408) 955-1690
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heavy Copper Plane
Heavy Copper Plane
VEE
VEE
Heat Dissipation
PCB Thermal Consideration for 16-Pin MLF® Package
(Always solder, or equivalent, the exposed pad to the PCB)
16-PIN
Micro
LeadFrame® (MLF-16)
Package Notes:
Note 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form.
Note 2. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
