Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
1
SP202E/232E/233E/310E/312E
■Operates from Single +5V Power Supply
■Meets All RS-232D and ITU V.28
Specifications
■Operates with 0.1µF to 10µF Capacitors
■High Data Rate – 120Kbps Under Load
■Low Power Shutdown ≤1µA (Typical)
■3-State TTL/CMOS Receiver Outputs
■Low Power CMOS – 3mA Operation
■Improved ESD Specifications:
±15kV Human Body Model
±15kV IEC1000-4-2 Air Discharge
±8kV IEC1000-4-2 Contact Discharge
Number of RS232 No. of Receivers No. of External
Model Drivers Receivers Active in Shutdown 0.1µF Capacitors Shutdown WakeUp TTL Tri–State
SP202E 22 0 4 NoNoNo
SP232E 22 0 4 NoNoNo
SP233E 22 0 0 NoNoNo
SP310E 22 0 4 Yes No Yes
SP312E 22 2 4 Yes Yes Yes
High-P erf ormance RS-232
Line Drivers/Receivers
®
DESCRIPTION
SELECTION TABLE
The SP202E/232E/233E/310E/312E devices are a family of line driver and receiver pairs that
meet the specifications of RS-232 and V.28 serial protocols with enhanced ESD performance.
The ESD tolerance has been improved on these devices to over ±15KV for both Human Body
Model and IEC1000-4-2 Air Discharge Method. These devices are pin-to-pin compatible with
Sipex's SP232A/233A/310A/312A devices as well as popular industry standards. As with the
initial versions, the SP202E/232E/233E/310E/312E devices feature at least 120Kbps data rate
under load, 0.1µF charge pump capacitors, and overall ruggedness for commercial applications.
This family also features Sipex's BiCMOS design allowing low power operation without
sacrificing performance. The series is available in plastic DIP and SOIC packages operating over
the commercial and industrial temperature ranges.
V
CC
GND
T
1
OUT
R
1
IN
R
1
OUT
T
1
IN
T
2
IN
R
2
OUT
C
1
+
V+
C
1
-
C
2
+
C
2
-
V-
T
2
OUT
R
2
IN
SP202E
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Now Available in Lead Free Packaging
Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
2
This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect
reliability.
Vcc ................................................................................................................................................................. +6V
V+.................................................................................................................... (Vcc-0.3V) to +11.0V
V-............................................................................................................................................................ -11.0V
Input Voltages
TIN ......................................................................................................................... -0.3 to (Vcc +0.3V)
RIN ............................................................................................................................................................ ±15V
Output Voltages
TOUT .................................................................................................... (V+, +0.3V) to (V-, -0.3V)
ROUT ................................................................................................................ -0.3V to (Vcc +0.3V)
Short Circuit Duration
TOUT ......................................................................................................................................... Continuous
VCC=+5V±10%; 0.1µF charge pump capacitors; TMIN to TMAX unless otherwise noted.
PARAMETERS MIN. TYP. MAX. UNITS CONDITIONS
TTL INPUT
Logic Threshold
LOW 0.8 Volts TIN ; EN, SD
HIGH 2.0 Volts TIN ; EN, SD
Logic Pull-Up Current 15 200 µAT
IN = 0V
TTL OUTPUT
TTL/CMOS Output
Voltage, Low 0.4 Volts IOUT = 3.2mA; Vcc = +5V
Voltage, High 3.5 Volts IOUT = -1.0mA
Leakage Current **; TA = +25°0.05 ±10 µAEN = VCC, 0V≤VOUT ≤VCC
RS-232 OUTPUT
Output Voltage Swing ±5±6Volts All transmitter outputs loaded
with 3kΩ to Ground
Output Resistance 300 Ohms VCC = 0V; VOUT = ±2V
Output Short Circuit Current ±18 mA Infinite duration
Maximum Data Rate 120 240 Kbps CL = 2500pF, RL= 3kΩ
RS-232 INPUT
Voltage Range -15 +15 Volts
Voltage Threshold
LOW 0.8 1.2 Volts VCC = 5V, TA = +25°C
HIGH 1.7 2.8 Volts VCC = 5V, TA = +25°C
Hysteresis 0.2 0.5 1.0 Volts VCC = 5V, TA = +25°C
Resistance 3 5 7 kΩ
T
A
= +25°C, -15V ≤ V
IN
≤ +15V
DYNAMIC CHARACTERISTICS
Driver Propagation Delay 1.5 3.0 µsTTL to RS-232; CL = 50pF
Receiver Propagation Delay 0.1 1.0 µsRS-232 to TTL
Instantaneous Slew Rate 30 V/µsC
L = 10pF, RL= 3-7kΩ;
TA =+25°C
Transition Region Slew Rate 10 V/µsC
L = 2500pF, RL= 3kΩ;
measured from +3V to -3V
or -3V to +3V
Output Enable Time ** 400 ns SP310E and SP312E only
Output Disable Time ** 250 ns SP310E and SP312E only
POWER REQUIREMENTS
VCC Power Supply Current 3 5 mA No load, TA= +25°C; VCC = 5V
15 mA All transmitters RL = 3kΩ;
TA = +25°C
Shutdown Supply Current ** 1 5 µAV
CC = 5V, TA = +25°C
**SP310E and SP312E only
ELECTRICAL CHARACTERISTICS
Plastic DIP .......................................................................... 375mW
(derate 7mW/°C above +70°C)
Small Outline ...................................................................... 375mW
(derate 7mW/°C above +70°C)
ABSOLUTE MAXIMUM RATINGS
Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
3
PERFORMANCE CURVES
-55 -40 0 25 70 85 125
Temperature (°C)
0
5
10
15
20
25
30
V
CC
= 6V
V
CC
= 5V
V
CC
= 4V
V
CC
= 3V
I
CC
(mA)
051015 20
Load Current (mA)
0
6
8
10
12
V+ (Volts)
2
4
V
CC
= 5V
V
CC
= 4V
V
CC
= 6V
25 30 35 40
02468101214
Load Current (mA)
V– Voltage (Volts)
-3
-4
-5
-6
-7
-8
-9
-10
-11
V
CC
= 6V
V
CC
= 5V
V
CC
= 4V
R
2
OUT
R
2
IN
T
2
OUT
V-
C
2
-
C
2
+
C
1
–
C
1
+
C
2
+
C
2
–
T
2
IN
T
1
IN
R
1
OUT
R
1
IN
T
1
OUT
GND
V
CC
V+
GND
V–
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SP233ECT
20-PIN SOIC
V
CC
GND
T
1
OUT
R
1
IN
R
1
OUT
T
1
IN
T
2
IN
R
2
OUT
C
1
+
V+
C
1
-
C
2
+
C
2
-
V-
T
2
OUT
R
2
IN
SP232E
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHUTDOWN
V
CC
GND
T
1
OUT
R
1
IN
R
1
OUT
T
1
IN
T
2
IN
R
2
OUT
EN *
C
1
+
V+
C
1
-
C
2
+
C
2
-
V-
T
2
OUT
R
2
IN
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
SP312E
ON/OFF
V
CC
GND
T
1
OUT
R
1
IN
R
1
OUT
T
1
IN
T
2
IN
R
2
OUT
NC
*
C
1
+
V+
C
1
-
C
2
+
C
2
-
V-
T
2
OUT
R
2
IN
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
SP310E
V
CC
GND
T
1
OUT
R
1
IN
R
1
OUT
T
1
IN
T
2
IN
R
2
OUT
C
1
+
V+
C
1
-
C
2
+
C
2
-
V-
T
2
OUT
R
2
IN
SP202E
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHDN
V
CC
GND
T1OUT
R1IN
R1OUT
N.C.
T1IN
T2IN
N.C.
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
R2OUT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SP310E_A/312E_A
20-PIN SSOP
N.C./EN
* N.C. for SP310E_A, EN for SP312E_A
PINOUTS
4.5 4.75 5.0 5.25 5.5
V
CC
(Volts)
5.0
6.5
7.0
7.5
8.0
8.5
9.0
Load current = 0mA
T
A
= 25°C
V
OH
(Volts)
5.5
6.0
Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
4
Figure 1. Typical Circuit using the SP202E or SP232E.
FEATURES…
The SP202E/232E/233E/310E/312E devices
are a family of line driver and receiver pairs that
meet the specifications of RS-232 and V.28
serial protocols with enhanced ESD perfor-
mance. The ESD tolerance has been improved
on these devices to over ±15KV for both Human
Body Model and IEC1000-4-2 Air Discharge
Method. These devices are pin-to-pin compat-
ible with Sipex's 232A/233A/310A/312A
devices as well as popular industry standards.
As with the initial versions, the SP202E/232E/
233E/310E/312E devices feature10V/µs slew
rate, 120Kbps data rate under load, 0.1µF
charge pump capacitors, overall ruggedness
for commercial applications, and increased drive
current for longer and more flexible cable
configurations. This family also features Sipex's
BiCMOS design allowing low power operation
without sacrificing performance.
The SP202E/232E/233E/310E/312E devices
have internal charge pump voltage converters
which allow them to operate from a single +5V
supply. The charge pumps will operate with
polarized or non-polarized capacitors ranging
from 0.1 to 10 µF and will generate the ±6V
needed to generate the RS-232 output levels.
Both meet all EIA RS-232 and ITU V.28
specifications.
The SP310E provides identical features as the
SP232E with a single control line which
simultaneously shuts down the internal DC/DC
converter and puts all transmitter and receiver
outputs into a high impedance state. The SP312E
is identical to the SP310E with separate tri-state
and shutdown control lines.
THEORY OF OPERATION
The SP232E, SP233E, SP310E and SP312E
devices are made up of three basic circuit blocks –
1) a driver/transmitter, 2) a receiver and 3) a charge
pump. Each block is described below.
Driver/Transmitter
The drivers are inverting transmitters, which ac-
cept TTL or CMOS inputs and output the RS-232
signals with an inverted sense relative to the input
logic levels. Typically the RS-232output voltage
swing is ±6V. Even under worst case loading
conditions of 3kOhms and 2500pF, the output is
guaranteed to be ±5V, which is consistent with the
RS-232 standard specifications. The transmitter
outputs are protected against infinite short-circuits
to ground without degradation in reliability.
R
2
98
R INR OUT
2
R
1
12 13 R INR OUT
1
T2
10 7
T IN
2
T OUT
2
T1
11 14
T IN
1
T OUT
1
15GND
400k Ω
400k Ω
TTL/CMOS INPUTS
RS-232 OUTPUTS
3
1C +
C -
1
1
6
16
V
CC
V+
+
+
0.1 F
6.3V
µ
Charge Pump
+5V INPUT
2
V-
TTL/CMOS OUTPUTS
RS-232 INPUTS
2
1
5kΩ
0.1 F
16V
µ
5kΩ
5
4C +
C -
2
2
+
0.1 F
16V
µ
0.1 F 6.3V
µ
10 F 6.3V
µ
SP232E
+
+
*
*The negative terminal of the V+ storage capacitor can be tied
to either VCC or GND. Connecting the capacitor to VCC (+5V)
is recommended.
SP202E
Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
5
The instantaneous slew rate of the transmitter
output is internally limited to a maximum of 30V/
µs in order to meet the standards [EIA RS-232-D
2.1.7, Paragraph (5)]. However, the transition re-
gion slew rate of these enhanced products is typi-
cally 10V/µs. The smooth transition of the loaded
output from VOL to VOH clearly meets the mono-
tonicity requirements of the standard [EIA
RS-232-D 2.1.7, Paragraphs (1) & (2)].
Receivers
The receivers convert RS-232 input signals to
inverted TTL signals. Since the input is usually
from a transmission line, where long cable lengths
and system interference can degrade the signal, the
inputs have a typical hysteresis margin of 500mV.
This ensures that the receiver is virtually immune
to noisy transmission lines.
The input thresholds are 0.8V minimum and 2.4V
maximum, again well within the ±3V RS-232
requirements. The receiver inputs are also pro-
tected against voltages up to ±15V. Should an
input be left unconnected, a 5KOhm pulldown
resistor to ground will commit the output of the
receiver to a high state.
R
2
20 19 R INR OUT
2
R
1
34
R INR OUT
1
T
2
118
T IN
2
T OUT
2
T
1
25
T IN
1
T OUT
1
9
GND
400k Ω
400k Ω
TTL/CMOS INPUTS
RS-232 OUTPUTS
14
13 C +
C -
V-
V-
V+
1
1
11
7
V
CC
+5V INPUT
12
TTL/CMOS OUTPUTS
RS-232 INPUTS
2
1
5kΩ
5kΩ
17
10 C +
C +
C -
C -
2
2
GND
6
8
15
16
2
2
Do not make
connection to
these pins
Internal
-10V Power
Supply
Internal
+10V Power
Supply
SP233ECT
Figure 2. Typical Circuits using the SP233ECP and SP233ECT
Figure 3. Typical Circuits using the SP310E and SP312E
R
2
10 9 R INR OUT
2
R
1
13 14 R INR OUT
1
T2
11 8
T IN
2
T OUT
2
T1
12 15
T IN
1
T OUT
1
16GND
400k Ω
400k Ω
TTL/CMOS INPUTS
RS-232 OUTPUTS
4
2C +
C -
1
1
7
17
V
CC
V+
+
+
0.1 F
6.3V
µ
Charge Pump
+5V INPUT
3
V-
TTL/CMOS OUTPUTS
RS-232 INPUTS
2
1
5kΩ
5kΩ
6
5C +
C -
2
2
+
0.1 F
16V
µ
10 F 6.3V
µ
SP310E
+
18 ON/OFF
+
0.1 µF
16V
*
*The negative terminal of the V+ storage capacitor can be tied
to either V
CC
or GND. Connecting the capacitor to V
CC
(+5V)
is recommended.
0.1 µF
16V
R
2
10 9R INR OUT
2
R
1
13 14 R INR OUT
1
T
2
11 8
T IN
2
T OUT
2
T
1
12 15
T IN
1
T OUT
1
16GND
400k Ω
400k Ω
TTL/CMOS INPUTS
RS-232 OUTPUTS
4
2C +
C -
1
1
7
17
V
CC
V+
+
+
0.1 F
6.3V
µ
+5V INPUT
3
V-
TTL/CMOS OUTPUTS
RS-232 INPUTS
2
1
5kΩ
0.1 F
16V
µ
5kΩ
6
5C +
C -
2
2
+
0.1 F
16V
µ
Charge Pump
10 F 6.3V
µ
SP312E
+
18 SHUTDOWN
1
EN
+
0.1 F
16V
µ
*
*The negative terminal of the V+ storage capacitor can be tied
to either V
CC
or GND. Connecting the capacitor to V
CC
(+5V)
is recommended.
Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
6
VCC = +5V
–5V –5V
+5V
VSS Storage Capacitor
VDD Storage Capacitor
C1C2
C3
C4
+
+
++
–
–
––
Figure 4. Charge Pump — Phase 1
Figure 5. Charge Pump — Phase 2
VCC = +5V
–10V
VSS Storage Capacitor
VDD Storage Capacitor
C1C2
C3
C4
+
+
++
–
–
––
In actual system applications, it is quite possible
for signals to be applied to the receiver inputs
before power is applied to the receiver circuitry.
This occurs, for example, when a PC user attempts
to print, only to realize the printer wasn’t turned on.
In this case an RS-232 signal from the PC will
appear on the receiver input at the printer. When
the printer power is turned on, the receiver will
operate normally. All of these enhanced devices
are fully protected.
Charge Pump
The charge pump is a Sipex–patented design
(5,306,954) and uses a unique approach com-
pared to older less–efficient designs. The charge
pump still requires four external capacitors, but
uses a four–phase voltage shifting technique to
attain symmetrical power supplies. There is a
free–running oscillator that controls the four
phases of the voltage shifting. A description of
each phase follows.
Phase 1
— VSS charge storage —During this phase of
the clock cycle, the positive side of capacitors
C1 and C2 are initially charged to +5V. Cl+ is
then switched to ground and the charge in C1– is
transferred to C2–. Since C2+ is connected to
+5V, the voltage potential across capacitor C2 is
now 10V.
Phase 2
— VSS transfer — Phase two of the clock con-
nects the negative terminal of C2 to the VSS
storage capacitor and the positive terminal of C2
to ground, and transfers the generated –l0V to
C3. Simultaneously, the positive side of capaci-
tor C 1 is switched to +5V and the negative side
is connected to ground.
Phase 3
— VDD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C1 produces –5V in the negative
terminal of C1, which is applied to the negative
side of capacitor C2. Since C2+ is at +5V, the
voltage potential across C2 is l0V.
Phase 4
— VDD transfer — The fourth phase of the clock
connects the negative terminal of C2 to ground,
and transfers the generated l0V across C2 to C4,
the VDD storage capacitor. Again, simultaneously
with this, the positive side of capacitor C1 is
switched to +5V and the negative side is con-
nected to ground, and the cycle begins again.
Since both V+ and V– are separately generated
from VCC; in a no–load condition V+ and V– will
Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
7
Figure 6. Charge Pump Waveforms
+10V
a) C2+
GND
GND
b) C2–
–10V
Figure 7. Charge Pump — Phase 3
V
CC
= +5V
–5V
+5V
–5V
V
SS
Storage Capacitor
V
DD
Storage Capacitor
C
1
C
2
C
3
C
4
+
+
++
–
–
––
Figure 8. Charge Pump — Phase 4
V
CC
= +5V
+10V
V
SS
Storage Capacitor
V
DD
Storage Capacitor
C
1
C
2
C
3
C
4
+
+
++
–
–
––
be symmetrical. Older charge pump approaches
that generate V– from V+ will show a decrease in
the magnitude of V– compared to V+ due to the
inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 15kHz. The external capacitors can
be as low as 0.1µF with a 16V breakdown
voltage rating.
Shutdown (SD) and Enable (EN) for the
SP310E and SP312E
Both the SP310E and SP312E have a shutdown/
standby mode to conserve power in battery-pow-
ered systems. To activate the shutdown mode,
which stops the operation of the charge pump, a
logic “0” is applied to the appropriate control line.
For the SP310E, this control line is ON/OFF (pin
18). Activating the shutdown mode also puts the
Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
8
Table 1. Wake-up Function Truth Table.
SD EN Power
Up/Down Receiver
Outputs
0
0
1
1
0
1
0
1
Down
Down
Up
Up
Enable
Tri–state
Enable
Tri–state
SP310E transmitter and receiver outputs in a high
impedance condition (tri-stated). The shutdown
mode is controlled on the SP312E by a logic “0”
on the SHUTDOWN control line (pin 18); this also
puts the transmitter outputs in a tri–state mode.
The receiver outputs can be tri–stated separately
during normal operation or shutdown by a logic
“1” on the ENABLE line (pin 1).
Wake–Up Feature for the SP312E
The SP312E has a wake–up feature that keeps
all the receivers in an enabled state when the
device is in the shutdown mode. Table 1 defines
the truth table for the wake–up function.
With only the receivers activated, the SP312E
typically draws less than 5µA supply current.
In the case of a modem interfaced to a computer
in power down mode, the Ring Indicator (RI)
signal from the modem would be used to "wake
up" the computer, allowing it to accept data
transmission.
After the ring indicator signal has propagated
through the SP312E receiver, it can be used to
trigger the power management circuitry of the
computer to power up the microprocessor, and
bring the SD pin of the SP312E to a logic high,
taking it out of the shutdown mode. The receiver
propagation delay is typically 1µs. The enable
time for V+ and V– is typically 2ms. After V+ and
V– have settled to their final values, a signal can
be sent back to the modem on the data terminal
ready (DTR) pin signifying that the computer is
ready to accept and transmit data.
Pin Strapping for the SP233ECT
The SP233E packaged in the 20–pin SOIC pack-
age (SP233ECT) has a slightly different pinout
than the SP233E in other package configurations.
To operate properly, the following pairs of pins
must be externally wired together:
the two V– pins (pins 10 and 17)
the two C2+ pins (pins 12 and 15)
the two C2– pins (pins 11 and 16)
All other connections, features, functions and
performance are identical to the SP233E as
specified elsewhere in this data sheet.
ESD TOLERANCE
The SP202E/232E/233E/310E/312E devices
incorporates ruggedized ESD cells on all driver
output and receiver input pins. The ESD struc-
ture is improved over our previous family for
more rugged applications and environments sen-
sitive to electro-static discharges and associated
transients. The improved ESD tolerance is at
least ±15KV without damage nor latch-up.
There are different methods of ESD testing
applied: a) MIL-STD-883, Method 3015.7
b) IEC1000-4-2 Air-Discharge
c) IEC1000-4-2 Direct Contact
The Human Body Model has been the generally
accepted ESD testing method for semiconductors.
This method is also specified in MIL-STD-883,
Method 3015.7 for ESD testing. The premise of
this ESD test is to simulate the human body’s
potential to store electro-static energy and
discharge it to an integrated circuit. The
simulation is performed by using a test model as
shown in Figure 9. This method will test the IC’s
capability to withstand an ESD transient during
normal handling such as in manufacturing areas
where the ICs tend to be handled frequently.
The IEC-1000-4-2, formerly IEC801-2, is
generally used for testing ESD on equipment and
systems. For system manufacturers, they must
guarantee a certain amount of ESD protection
since the system itself is exposed to the outside
environment and human presence. The premise
Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
9
R
C
C
S
R
S
SW1 SW2
R
C
Device
Under
Test
DC Power
Source
C
S
R
S
SW1 SW2
Figure 9. ESD Test Circuit for Human Body Model
R
S
and
R
V
add up to 330Ω for IEC1000-4-2.
R
S
and
R
V
add up to 330Ω for IEC1000-4-2.
Contact-Discharge Module
R
V
R
C
C
S
R
S
SW1 SW2
R
C
Device
Under
Test
DC Power
Source
C
S
R
S
SW1 SW2
R
V
Contact-Discharge Module
Figure 10. ESD Test Circuit for IEC1000-4-2
with IEC1000-4-2 is that the system is required
to withstand an amount of static electricity when
ESD is applied to points and surfaces of the
equipment that are accessible to personnel during
normal usage. The transceiver IC receives most
of the ESD current when the ESD source is
applied to the connector pins. The test circuit for
IEC1000-4-2 is shown on Figure 10. There are
two methods within IEC1000-4-2, the Air
Discharge method and the Contact Discharge
method.
With the Air Discharge Method, an ESD voltage
is applied to the equipment under test (EUT)
through air. This simulates an electrically charged
person ready to connect a cable onto the rear of
the system only to find an unpleasant zap just
before the person touches the back panel. The
high energy potential on the person discharges
through an arcing path to the rear panel of the
system before he or she even touches the system.
This energy, whether discharged directly or
through air, is predominantly a function of the
Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
10
SP202E HUMAN BODY IEC1000-4-2
Family MODEL Air Discharge Direct Contact Level
Driver Outputs ±15kV ±15kV ±8kV 4
Receiver Inputs ±15kV ±15kV ±8kV 4
Figure 11. ESD Test Waveform for IEC1000-4-2
t=0ns t=30ns
0A
15A
30A
t ➙
i ➙
Table 2. Transceiver ESD Tolerance Levels
discharge current rather than the discharge
voltage. Variables with an air discharge such as
approach speed of the object carrying the ESD
potential to the system and humidity will tend to
change the discharge current. For example, the
rise time of the discharge current varies with the
approach speed.
The Contact Discharge Method applies the ESD
current directly to the EUT. This method was
devised to reduce the unpredictability of the
ESD arc. The discharge current rise time is
constant since the energy is directly transferred
without the air-gap arc. In situations such as
hand held systems, the ESD charge can be directly
discharged to the equipment from a person already
holding the equipment. The current is transferred
on to the keypad or the serial port of the equipment
directly and then travels through the PCB and
finally to the IC.
The circuit models in Figures 9 and 10 represent
the typical ESD testing circuit used for all three
methods. The CS is initially charged with the DC
power supply when the first switch (SW1) is on.
Now that the capacitor is charged, the second
switch (SW2) is on while SW1 switches off. The
voltage stored in the capacitor is then applied
through RS, the current limiting resistor, onto the
device under test (DUT). In ESD tests, the SW2
switch is pulsed so that the device under test
receives a duration of voltage.
For the Human Body Model, the current limiting
resistor (RS) and the source capacitor (CS) are
1.5kΩ an 100pF, respectively. For IEC-1000-4-
2, the current limiting resistor (RS) and the source
capacitor (CS) are 330Ω an 150pF, respectively.
The higher CS value and lower RS value in the
IEC1000-4-2 model are more stringent than the
Human Body Model. The larger storage capacitor
injects a higher voltage to the test point when
SW2 is switched on. The lower current limiting
resistor increases the current charge onto the test
point.
Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
11
D
E1 E
INDEX AREA
D
2x2
E1
N
12
Seating Plane
A2 A
A1
b
SEE DETAIL “A”
(b)
c
WITH LEAD FINISH
BASE METAL
L1
L
Seaing Plane
Ø
2 NX R R1
DETAIL A
- - 2.0
0.05 - -
Dimensions in (mm)
20 PIN SSOP
JEDEC MO-150
(AE) Variation
1.65 1.75 1.85
0.22 - 0.38
0.09 - 0.25
0.55 0.75 0.95
0º 4º 8º
A
A1
A2
b
c
D
E
E1
L
L1
Ø
MIN NOM MAX
7.40 7.80 8.20
5.00 5.30 5.60
1.25 REF
6.90 7.20 7.50
e
A
A
Section A-A
20 PIN SSOP
PACKAGE: 20 PIN SSOP
Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
12
Ø
Ø1
1.65
TOP VIEW
SECTION B-B
16 PIN NSOIC
b
c
WITH PLATING
BASE METAL
b
DIMENSIONS
in
(mm)
16 Pin NSOIC
(JEDEC MS-012,
AC - VARIATION)
A
A1
A2
b
c
L
e
E1
E
L2
L1
1.35
0.40
0.31 0.51
SYMBOL MIN NOM MAX
0.10 - 0.25
1.75
1.25
0.17 0.25
6.00 BSC
3.90 BSC
1.27 BSC1.27
1.04 REF
0.25 BSC
0º
5º 8º
15º
L1
L
Ø
Ø1
Ø1
Seating Plane
Gauge Plane
L2
VIEW C
AA2
A1
SIDE VIEW
E
E/2
E1
INDEX AREA
(D/2 X E1/2)
E1/2
D
SEE VIEW C
1
-
-
-
-
-
-
-
Seating Plane
B
B
e
D9.90 BSC
PACKAGE: 16 PIN NSOIC
Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
13
Ø
Ø1
2.55
TOP VIEW
16 PIN SOIC WIDE
c
WITH PLATING
BASE METAL
b
DIMENSIONS IN
(mm)
16 Pin SOIC (WIDE)
(JEDEC MS-013,
AA - VARIATION)
A
A1
A2
b
c
L
e
E1
E
L2
L1
2.35
10.30 BSC
0.40
0.31 0.51
SYMBOL MIN NOM MAX
0.10 - 0.30
D
2.65
2.05
0.20 0.33
10.30 BSC
7.50 BSC
1.27 BSC1.27
1.40 REF
0.25 BSC
0º
5º 8º
15º
L1
L
Ø
Ø1
Ø1
Seating Plane
Gauge Plane
L2
VIEW C
AA2
A1
SIDE VIEW
e
E
E/2
E1
b
INDEX AREA
(D/2 X E1/2)
E1/2
D
SEE VIEW C
123
SECTION B-B
-
-
-
-
-
-
-
B
B
Seating Plane
PACKAGE: 16 PIN WSOIC
Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
14
N
123
INDEX
AREA
eA
eB
E
C
b
- - .210
.015 -
Dimensions in inches
18 PIN PDIP
JEDEC MS-001
(AC) Variation
.115 .130 .195
.014 .018 .022
.045 .060 .070
.240 .250 .280
A
A1
A2
b
c
D1
E
E1
e
eA
eB
.115 .130 .150
L
MIN NOM MAX
b2
b3 .030 .039 .045
D
.008
.010 .014
.880 .900 .920
.005
.300 .310 .325
.100 BSC
.300 BSC
.430
D1
-
--
--
N/2
18 pin PDIP
E
E1
D
A
LA2
A1
b
b2
e
b3
c
PACKAGE: 18 PIN PDIP
Date: 7/19/04 SP202E Series High Performance RS232 Transceivers © Copyright 2004 Sipex Corporation
15
Part Number Temperature Range Topmark Package
SP202ECN.............................0°C to +70°C.................................SP202ECN........................................................................16–pin NSOIC
SP202ECN/TR.......................0°C to +70°C.................................SP202ECN........................................................................16–pin NSOIC
SP202ECP.............................0°C to +70°C.................................SP202ECP.........................................................................16–pin PDIP
SP202ECT.............................0°C to +70°C.................................SP202ECT.........................................................................16–pin WSOIC
SP202ECT/TR.......................0°C to +70°C.................................SP202ECT.........................................................................16–pin WSOIC
SP202EEN..........................–40°C to +85°C................................SP202EEN.........................................................................16–pin NSOIC
SP202EEN/TR....................–40°C to +85°C................................SP202EEN.........................................................................16–pin NSOIC
SP202EEP..........................–40°C to +85°C................................SP202EEP.........................................................................16–pin PDIP
SP202EET..........................–40°C to +85°C................................SP202EET..........................................................................16–pin WSOIC
SP202EET/TR.....................–40°C to +85°C................................SP202EET..........................................................................16–pin WSOIC
SP232ECN.............................0°C to +70°C................................SP232ECN..........................................................................16–pin NSOIC
SP232ECN/TR.......................0°C to +70°C................................SP232ECN..........................................................................16–pin NSOIC
SP232ECP.............................0°C to +70°C.................................SP232ECP.........................................................................16–pin PDIP
SP232ECT.............................0°C to +70°C.................................SP232ECT..........................................................................16–pin WSOIC
SP232ECT/TR.......................0°C to +70°C.................................SP232ECT..........................................................................16–pin WSOIC
SP232EEN..........................–40°C to +85°C................................SP232EEN..........................................................................16–pin NSOIC
SP232EEN/TR....................–40°C to +85°C................................SP232EEN..........................................................................16–pin NSOIC
SP232EEP..........................–40°C to +85°C................................SP232EEP..........................................................................16–pin PDIP
SP232EET..........................–40°C to +85°C................................SP232EET...........................................................................16–pin WSOIC
SP232EET/TR.....................–40°C to +85°C................................SP232EET...........................................................................16–pin WSOIC
SP233ECT............................0°C to +70°C.................................SP233ECT...........................................................................20–pin WSOIC
SP233ECT/TR......................0°C to +70°C.................................SP233ECT...........................................................................20–pin WSOIC
SP233EET..........................–40°C to +85°C................................SP233EET...........................................................................20–pin WSOIC
SP233EET/TR.....................–40°C to +85°C................................SP233EET...........................................................................20–pin WSOIC
SP310ECP............................0°C to +70°C.................................SP310ECP.........................................................................18–pin PDIP
SP310ECT............................0°C to +70°C.................................SP310ECT..........................................................................18–pin WSOIC
SP310ECT/TR......................0°C to +70°C.................................SP310ECT..........................................................................18–pin WSOIC
SP310ECA............................0°C to +70°C.................................SP310ECA..........................................................................20–pin SSOP
SP310ECA/TR......................0°C to +70°C.................................SP310ECA..........................................................................20–pin SSOP
SP310EEP..........................–40°C to +85°C................................SP310EEP..........................................................................18–pin PDIP
SP310EET..........................–40°C to +85°C................................SP310EET...........................................................................18–pin WSOIC
SP310EET/TR.....................–40°C to +85°C................................SP310EET...........................................................................18–pin WSOIC
SP310EEA..........................–40°C to +85°C................................SP310EEA...........................................................................20–pin SSOP
SP310EEA/TR.....................–40°C to +85°C................................SP310EEA...........................................................................20–pin SSOP
SP312ECP............................0°C to +70°C.................................SP312ECP..........................................................................18–pin PDIP
SP312ECT............................0°C to +70°C.................................SP312ECT...........................................................................18–pin WSOIC
SP312ECT/TR......................0°C to +70°C.................................SP312ECT...........................................................................18–pin WSOIC
SP312ECA............................0°C to +70°C.................................SP312ECA...........................................................................20–pin SSOP
SP312ECA/TR......................0°C to +70°C.................................SP312ECA...........................................................................20–pin SSOP
SP312EEP..........................–40°C to +85°C................................SP312EEP...........................................................................18–pin PDIP
SP312EET..........................–40°C to +85°C................................SP312EET............................................................................18–pin WSOIC
SP312EET/TR.....................–40°C to +85°C................................SP312EET............................................................................18–pin WSOIC
SP312EEA..........................–40°C to +85°C................................SP312EEA............................................................................20–pin SSOP
SP312EEA/TR.....................–40°C to +85°C................................SP312EEA............................................................................20–pin SSOP
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP312EEA/TR = standard; SP312EEA-L/TR = lead free
/TR = Tape and Reel
Pack quantity is 1,500 for SSOP or WSOIC and 2,500 for NSOIC.
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
ORDERING INFORMATION
DATE REVISION DESCRIPTION
6/2/04 A Incorporated new package drawings with JEDEC reference.
7/19/04 A Added typical output voltage swing value (±6V).
REVISION HISTORY