FAN7930CMX-G - FAIRCHILD SEMICONDUCTOR

To learn more about ON Semiconductor, please visit our website at

www.onsemi.com

Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers

will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor

product management systems do not have the ability to manage part nomenclature that utilizes an underscore

(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain

device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated

device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please

email any questions regarding the system integration to Fairchild_questions@onsemi.com.

Is Now Part of

ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number

of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right

to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and speciﬁcally disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON

Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON

Semiconductor data sheets and/or speciﬁcations can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s

technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA

Class 3 medical devices or medical devices with a same or similar classiﬁcation in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended

or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its ofﬁcers, employees, subsidiaries, afﬁliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out

of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor

is an Equal Opportunity/Afﬁrmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

April 2013

FAN3216 / FAN3217 • Rev. 1.0.3

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

FAN3216 / FAN3217

Dual 2-A, High-Speed, Low-Side Gate Drivers

Features

 Industry-Standard Pinouts

 4.5-V to 18-V Operating Range

 3-A Peak Sink/Source at VDD = 12 V

 2.4-A Sink / 1.6-A Source at VOUT = 6 V

 Inverting Configuration (FAN3216) and

Non-Inverting Configuration (FAN3217)

 Internal Resistors Turn Driver Off If No Inputs

 12-ns / 9-ns Typical Rise/Fall Times (1 nF Load)

 20-ns Typical Propagation Delay Time Matched

within 1 ns to the Other Channel

 TTL Input Thresholds

 MillerDrive™ Technology

 Double Current Capability by Paralleling Channels

 Standard SOIC-8 Package

 Rated from –40°C to +125°C Ambient

 Automotive Qualified to AEC-Q100 (F085 Versions)

Applications

 Switch-Mode Power Supplies

 High-Efficiency MOSFET Switching

 Synchronous Rectifier Circuits

 DC-to-DC Converters

 Motor Control

 Automotive-Qualified Systems (F085 Versions)

Description

The FAN3216 and FAN3217 dual 2 A gate drivers are

designed to drive N-channel enhancement-mode

MOSFETs in low-side switching applications by

providing high peak current pulses during the short

switching intervals. They are both available with TTL

input thresholds. Internal circuitry provides an under-

voltage lockout function by holding the output LOW until

the supply voltage is within the operating range. In

addition, the drivers feature matched internal

propagation delays between A and B channels for

applications requiring dual gate drives with critical

timing, such as synchronous rectifiers. This also

enables connecting two drivers in parallel to effectively

double the current capability driving a single MOSFET.

The FAN3216/17 drivers incorporate MillerDrive™

architecture for the final output stage. This bipolar-

MOSFET combination provides high current during the

Miller plateau stage of the MOSFET turn-on / turn-off

process to minimize switching loss, while providing rail-

to-rail voltage swing and reverse current capability.

The FAN3216 offers two inverting drivers and the

FAN3217 offers two non-inverting drivers. Both are

offered in a standard 8-pin SOIC package.

Figure 1. FAN3216 Pin Configuration Figure 2. FAN3217 Pin Configuration

FAN3216 / FAN3217 • Rev. 1.0.3 2

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Ordering Information

Part Number Logic Input

Threshold Package Packing

Method Quantity

per Reel

FAN3216TMX Dual Inverting Channels TTL

SOIC-8 Tape & Reel 2,500

FAN3216TMX_F085(1) Dual Inverting Channels TTL SOIC-8 Tape & Reel 2,500

FAN3217TMX Dual Non-Inverting Channels TTL SOIC-8 Tape & Reel 2,500

FAN3217TMX_F085(1) Dual Non-Inverting Channels TTL SOIC-8 Tape & Reel 2,500

All standard Fairchild Semiconductor products are RoHS compliant and many are also “Green” or going green. Green means

the products are RoHS compliant AND they have limits on additional substances of Chlorine, Bromine and Antimony. For additional

information on Fairchild’s “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

Note:

1. Qualified to AEC-Q100

Package Outlines

Figure 3. SOIC-8 (Top View)

Thermal Characteristics(2)

Package ΘJL(3) ΘJT(4) ΘJA(5) ΨJB(6) ΨJT(7) Unit

8-Pin Small Outline Integrated Circuit (SOIC) 40 31 89 43 3.0 °C/W

Notes:

2. Estimates derived from thermal simulation; actual values depend on the application.

3. Theta_JL (ΘJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads

(including any thermal pad) that are typically soldered to a PCB.

4. Theta_JT (ΘJT): Thermal resistance between the semiconductor junction and the top surface of the package,

assuming it is held at a uniform temperature by a top-side heatsink.

5. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,

and airflow. The value given is for natural convection with no heatsink using a 2S2P board, as specified in

JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.

6. Psi_JB (ΨjB): Thermal characterization parameter providing correlation between semiconductor junction

temperature and an application circuit board reference point for the thermal environment defined in Note 5. For

the SOIC-8 package, the board reference is defined as the pcb copper adjacent to pin 6.

7. Psi_JT (ΨjT): Thermal characterization parameter providing correlation between the semiconductor junction

temperature and the center of the top of the package for the thermal environment defined in Note 5.

FAN3216 / FAN3217 • Rev. 1.0.3 3

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Pin Configurations

Figure 4. FAN3216 Figure 5. FAN3217

Pin Definitions

Pin Name Pin Description

1 NC

No Connect. This pin can be grounded or left floating.

2 INA

Input to Channel A.

3 GND

Ground. Common ground reference for input and output circuits.

4 INB

Input to Channel B.

(FAN3216) OUTB Gate Drive Output B (inverted from the input): Held LOW unless required input is

present and VDD is above UVLO threshold.

(FAN3217) OUTB Gate Drive Output B: Held LOW unless required input(s) are present and VDD is above

UVLO threshold.

6 VDD

Supply Voltage. Provides power to the IC.

(FAN3216) OUTA Gate Drive Output A (inverted from the input): Held LOW unless required input is

present and VDD is above UVLO threshold.

(FAN3217) OUTA Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above

UVLO threshold.

8 NC

No Connect. This pin can be grounded or left floating.

Output Logic

FAN3216 (x=A or B) FAN3217 (x=A or B)

INx OUTx INx OUTx

0 1 0

(

)

(

)

0 1 1

Note:

8. Default input signal if no external connection is made.

FAN3216 / FAN3217 • Rev. 1.0.3 4

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Block Diagrams

Figure 6. FAN3216 Block Diagram

Figure 7. FAN3217 Block Diagram

FAN3216 / FAN3217 • Rev. 1.0.3 5

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VDD VDD to PGND -0.3 20.0 V

VIN INA and INB to GND GND - 0.3 VDD + 0.3 V

VOUT OUTA and OUTB to GND GND - 0.3 VDD + 0.3 V

TL Lead Soldering Temperature (10 Seconds) +260 ºC

TJ Junction Temperature -55 +150 ºC

TSTG Storage Temperature -65 +150 ºC

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. Unit

VDD Supply Voltage Range 4.5 18.0 V

VIN Input Voltage INA and INB 0 VDD V

TA Operating Ambient Temperature -40 +125 ºC

FAN3216 / FAN3217 • Rev. 1.0.3 6

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Electrical Characteristics

Unless otherwise noted, VDD=12 V, TJ=-40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol Parameter Conditions Min. Typ. Max. Unit

Supply

VDD Operating Range 4.5 18.0 V

IDD Supply Current, Inputs Not Connected 0.75 1.20 mA

VON Turn-On Voltage INA=VDD, INB=0 V 3.45 3.90 4.35 V

VOFF Turn-Off Voltage INA=VDD, INB=0 V 3.25 3.70 4.15 V

FAN3216TMX_F085, FAN3217TMX_F085 (Automotive-Qualified Versions)

VON Turn-On Voltage(11) INA=VDD, INB=0 V 3.40 3.90 4.60 V

VOFF Turn-Off Voltage(11) INA=VDD, INB=0 V 3.20 3.70 4.30 V

Inputs

VIL_T INx Logic Low Threshold 0.8 1.2 V

VIH_T INx Logic High Threshold 1.6 2.0 V

VHYS_T TTL Logic Hysteresis Voltage 0.2 0.4 0.8 V

FAN3216TMX, FAN3217TMX

IIN+ Non-inverting Input Current IN from 0 to VDD -1.0 175 µA

IIN- Inverting Input Current IN from 0 to VDD -175.0 1.0 µA

FAN3216TMX_F085, FAN3217TMX_F085 (Automotive-Qualified Versions)

IINx_T Non-inverting Input Current(11) IN=0 V -1.5 1.5 µA

IINx_T Non-inverting Input Current(11) IN=VDD 90 120 175.0 µA

IINx_T Inverting Input Current(11) IN=0 V -175.0 -120 -90 µA

IINx_T Inverting Input Current(11) IN=VDD -1.5 1.5 µA

Outputs

ISINK OUT Current, Mid-Voltage, Sinking(9) OUTx at VDD/2,

CLOAD=0.22 µF, f=1 kHz 2.4 A

ISOURCE OUT Current, Mid-Voltage, Sourcing(9) OUTx at VDD/2,

CLOAD=0.1 µF, f=1 kHz -1.6 A

IPK_SINK OUT Current, Peak, Sinking(9) C

LOAD=0.1 µF, f=1 kHz 3 A

IPK_SOURCE OUT Current, Peak, Sourcing(9) C

LOAD=0.1 µF, f=1 kHz -3 A

tRISE Output Rise Time(10) C

LOAD=1000 pF 12 22 ns

tFALL Output Fall Time(10) C

LOAD=1000 pF 9 17 ns

tD1, tD2 Output Propagation Delay, TTL Inputs(10) 0 – 5 VIN, 1V/ns Slew Rate 10 19 34 ns

Propagation Matching Between Channels INA=INB, OUTA and OUTB

at 50% Point 1 2 ns

IRVS Output Reverse Current Withstand(9) 500 mA

Continued on the following page…

FAN3216 / FAN3217 • Rev. 1.0.3 7

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Electrical Characteristics (Continued)

Unless otherwise noted, VDD=12 V, TJ=-40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol Parameter Conditions Min. Typ. Max. Unit

Outputs (continued)

FAN3216TMX_F085, FAN3217TMX_F085 (Automotive-Qualified Versions)

tD1, tD2 Output Propagation Delay, TTL Inputs(11) 0 – 5 VIN, 1 V/ns Slew Rate 4.5 19.0 34.0 ns

Propagation Matching Between

Channels(11)

INA=INB, OUTA and OUTB

at 50% Point 2 4 ns

VOH High Level Output Voltage(11) VOH =VDD –VOUT, IOUT=-1 mA 15 35 mV

VOL Low Level Output Voltage(11) IOUT=1 mA 10 25 mV

Notes:

9. Not tested in production.

10. See Timing Diagrams of Figure 8 and Figure 9.

11. Apply to only F085 Version

Figure 8. Non-Inverting Timing Diagram Figure 9. Inverting Timing Diagram

FAN3216 / FAN3217 • Rev. 1.0.3 8

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Typical Performance Characteristics

Typical characteristics are provided at TA=25°C and VDD=12 V unless otherwise noted.

Figure 10. IDD (Static) vs. Supply Voltage(12) Figure 11. IDD (Static) vs. Temperature(12)

Figure 12. IDD (No-Load) vs. Frequency Figure 13. IDD (1 nF Load) vs. Frequency

Figure 14. Input Th resholds vs. Supply Voltage Figure 15. Input Thresholds vs. Temperature

FAN3216 / FAN3217 • Rev. 1.0.3 9

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Typical Performance Characteristics

Typical characteristics are provided at TA=25°C and VDD=12 V unless otherwise noted.

Figure 16. UVLO Threshold vs. Temperature

Figure 17. Propagation Delay vs. Supply Voltage Figure 18. Propagation Delay vs. Supply Voltage

Figure 19. Propagation Delays vs. Tempera t ure Figure 20. Propagation Delays vs. Temperature

FAN3216 / FAN3217 • Rev. 1.0.3 10

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Typical Performance Characteristics

Typical characteristics are provided at TA=25°C and VDD=12 V unless otherwise noted.

Figure 21. Fall Time vs. Supply Voltage Figure 22. Rise Time vs. Supply Voltage

Figure 23. Rise and Fall Times vs. Temperature

Figure 24. Rise/Fall Waveforms with 2.2 nF Load Figure 25. Rise/Fall Waveforms wi th 10 nF Load

FAN3216 / FAN3217 • Rev. 1.0.3 11

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Typical Performance Characteristics

Typical characteristics are provided at TA=25°C and VDD=12 V unless otherwise noted.

Figure 26. Quasi-Static Source Current

with VDD=12 V(13) Figure 27. Quasi-Static Sink Current with VDD=12 V(13)

Figure 28. Quasi-Static Source Current

with VDD=8 V(13) Figure 29. Quasi-Static Sink Current with VDD=8 V(13)

Notes:

12. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high; static IDD increases

by the current flowing through the corresponding pull-up/down resistor shown in Figure 6 and Figure 7.

13. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the

current-measurement loop.

Test Circuit

Figure 30. Quasi-Static IOUT

VOUT Test Circuit

FAN3216 / FAN3217 • Rev. 1.0.3 12

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Applications Information

Input Thresholds

The FAN3216 and the FAN3217 drivers consist of two

identical channels that may be used independently at

rated current or connected in parallel to double the

individual current capacity.

The input thresholds meet industry-standard TTL-logic

thresholds independent of the VDD voltage, and there is

a hysteresis voltage of approximately 0.4 V. These

levels permit the inputs to be driven from a range of

input logic signal levels for which a voltage over 2 V is

considered logic HIGH. The driving signal for the TTL

inputs should have fast rising and falling edges with a

slew rate of 6 V/µs or faster, so a rise time from 0 to

3.3 V should be 550 ns or less. With reduced slew rate,

circuit noise could cause the driver input voltage to

exceed the hysteresis voltage and retrigger the driver

input, causing erratic operation.

Static Supply Current

In the IDD (static) typical performance characteristics

shown in Figure 10 and Figure 11, each curve is

produced with both inputs floating and both outputs

LOW to indicate the lowest static IDD current. For other

states, additional current flows through the 100kΩ

resistors on the inputs and outputs shown in the block

diagram of each part (see Figure 6 and Figure 7). In

these cases, the actual static IDD current is the value

obtained from the curves plus this additional current.

MillerDrive™ Gate Drive Technology

FAN3216 and FAN3217 gate drivers incorporate the

MillerDrive™ architecture shown in Figure 31. For the

output stage, a combination of bipolar and MOS devices

provide large currents over a wide range of supply

voltage and temperature variations. The bipolar devices

carry the bulk of the current as OUT swings between 1/3

to 2/3 VDD and the MOS devices pull the output to the

HIGH or LOW rail.

The purpose of the MillerDrive™ architecture is to

speed up switching by providing high current during the

Miller plateau region when the gate-drain capacitance of

the MOSFET is being charged or discharged as part of

the turn-on / turn-off process.

For applications with zero voltage switching during the

MOSFET turn-on or turn-off interval, the driver supplies

high peak current for fast switching even though the

Miller plateau is not present. This situation often occurs

in synchronous rectifier applications because the body

diode is generally conducting before the MOSFET is

switched ON.

The output pin slew rate is determined by VDD voltage

and the load on the output. It is not user adjustable, but

a series resistor can be added if a slower rise or fall time

at the MOSFET gate is needed.

Figure 31. MillerDrive™ Output Architecture

Under-Voltage Lockout

The FAN321x startup logic is optimized to drive ground-

referenced N-channel MOSFETs with an under-voltage

lockout (UVLO) function to ensure that the IC starts up

in an orderly fashion. When VDD is rising, yet below the

3.9 V operational level, this circuit holds the output

LOW, regardless of the status of the input pins. After the

part is active, the supply voltage must drop 0.2 V before

the part shuts down. This hysteresis helps prevent

chatter when low VDD supply voltages have noise from

the power switching. This configuration is not suitable

for driving high-side P-channel MOSFETs because the

low output voltage of the driver would turn the P-channel

MOSFET on with VDD below 3.9 V.

VDD Bypass Capacitor Guidelines

To enable this IC to turn a device ON quickly, a local

high-frequency bypass capacitor, CBYP, with low ESR and

ESL should be connected between the VDD and GND

pins with minimal trace length. This capacitor is in

addition to bulk electrolytic capacitance of 10 µF to 47 µF

commonly found on driver and controller bias circuits.

A typical criterion for choosing the value of CBYP is to

keep the ripple voltage on the VDD supply to ≤ 5%. This

is often achieved with a value ≥ 20 times the equivalent

load capacitance CEQV, defined here as QGATE/VDD.

Ceramic capacitors of 0.1 µF to 1 µF or larger are

common choices, as are dielectrics, such as X5R and

X7R, with good temperature characteristics and high

pulse current capability.

If circuit noise affects normal operation, the value of

CBYP may be increased, to 50-100 times the CEQV, or

CBYP may be split into two capacitors. One should be a

larger value, based on equivalent load capacitance, and

the other a smaller value, such as 1-10 nF mounted

closest to the VDD and GND pins to carry the higher-

frequency components of the current pulses. The

bypass capacitor must provide the pulsed current from

both of the driver channels and, if the drivers are

switching simultaneously, the combined peak current

sourced from the CBYP would be twice as large as when

a single channel is switching.

FAN3216 / FAN3217 • Rev. 1.0.3 13

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Layout and Connection Guidelines

The FAN3216 and FAN3217 gate drivers incorporate

fast-reacting input circuits, short propagation delays,

and powerful output stages capable of delivering current

peaks over 2 A to facilitate voltage transition times from

under 10 ns to over 150 ns. The following layout and

connection guidelines are strongly recommended:

 Keep high-current output and power ground paths

separate from logic input signals and signal ground

paths. This is especially critical for TTL-level logic

thresholds at driver input pins.

 Keep the driver as close to the load as possible to

minimize the length of high-current traces. This

reduces the series inductance to improve high-

speed switching, while reducing the loop area that

can radiate EMI to the driver inputs and

surrounding circuitry.

 If the inputs to a channel are not externally

connected, the internal 100 kΩ resistors indicated

on block diagrams command a low output. In noisy

environments, it may be necessary to tie inputs of

an unused channel to VDD or GND using short

traces to prevent noise from causing spurious

output switching.

 Many high-speed power circuits can be susceptible

to noise injected from their own output or other

external sources, possibly causing output re-

triggering. These effects can be obvious if the

circuit is tested in breadboard or non-optimal circuit

layouts with long input or output leads. For best

results, make connections to all pins as short and

direct as possible.

 FAN3216 and FAN3217 are pin-compatible with

many other industry-standard drivers.

 The turn-on and turn-off current paths should be

minimized, as discussed in the following section.

Figure 32 shows the pulsed gate drive current path

when the gate driver is supplying gate charge to turn the

MOSFET on. The current is supplied from the local

bypass capacitor, CBYP, and flows through the driver to

the MOSFET gate and to ground. To reach the high

peak currents possible, the resistance and inductance in

the path should be minimized. The localized CBYP acts

to contain the high peak current pulses within this driver-

MOSFET circuit, preventing them from disturbing the

sensitive analog circuitry in the PWM controller.

Figure 32. Current Path for MOSFET Turn-On

Figure 33 shows the current path when the gate driver

turns the MOSFET OFF. Ideally, the driver shunts the

current directly to the source of the MOSFET in a small

circuit loop. For fast turn-off times, the resistance and

inductance in this path should be minimized.

Figure 33. Current Path for MOSFET Turn-Off

FAN3216 / FAN3217 • Rev. 1.0.3 14

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Operational Waveforms

At power-up, the driver output remains LOW until the

VDD voltage reaches the turn-on threshold. The

magnitude of the OUT pulses rises with VDD until

steady-state VDD is reached. The non-inverting

operation illustrated in Figure 34 shows that the output

remains LOW until the UVLO threshold is reached, then

the output is in-phase with the input.

Figure 34. Non-Inverting Startup Waveforms

The inverting configuration of startup waveforms are

shown in Figure 35. With IN+ tied to VDD and the input

signal applied to IN–, the OUT pulses are inverted with

respect to the input. At power-up, the inverted output

remains LOW until the VDD voltage reaches the turn-on

threshold, then it follows the input with inverted phase.

Figure 35. Inverting Startup Waveforms

FAN3216 / FAN3217 • Rev. 1.0.3 15

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Thermal Guidelines

Gate drivers used to switch MOSFETs and IGBTs at

high frequencies can dissipate significant amounts of

power. It is important to determine the driver power

dissipation and the resulting junction temperature in the

application to ensure that the part is operating within

acceptable temperature limits.

The total power dissipation in a gate driver is the sum of

two components, PGATE and PDYNAMIC:

PTOTAL = PGATE + PDYNAMIC (1)

Gate Driving Loss: The most significant power loss

results from supplying gate current (charge per unit

time) to switch the load MOSFET on and off at the

switching frequency. The power dissipation that

results from driving a MOSFET at a specified gate-

source voltage, VGS, with gate charge, QG, at

switching frequency, fSW, is determined by:

PGATE = QG • VGS • fSW • n (2)

where n is the number of driver channels in use (1 or 2).

Dynamic Pre-Drive / Shoot-through Current: A power

loss resulting from internal current consumption under

dynamic operating conditions, including pin pull-up /

pull-down resistors, can be obtained using the graphs

in Typical Performance Characteristics to determine

the current IDYNAMIC drawn from VDD under actual

operating conditions:

PDYNAMIC = IDYNAMIC • VDD • n (3)

Once the power dissipated in the driver is determined,

the driver junction rise with respect to circuit board can

be evaluated using the following thermal equation,

assuming ψJB was determined for a similar thermal

design (heat sinking and air flow):

TJ = PTOTAL • ψJB + TB (4)

where:

TJ = driver junction temperature;

ψJB = (psi) thermal characterization parameter

relating temperature rise to total power

dissipation; and

TB = board temperature in location as defined in

the Thermal Characteristics table.

In the forward converter with synchronous rectifier

shown in the typical application diagrams, the

FDMS8660S is a reasonable MOSFET selection. The

gate charge for each SR MOSFET would be 60 nC with

VGS = VDD = 7V. At a switching frequency of 500 kHz,

the total power dissipation is:

PGATE = 60 nC • 7 V • 500 kHz • 2 = 0.42 W (5)

PDYNAMIC = 3 mA • 7 V • 2 = 0.042 W (6)

PTOTAL = 0.46 W (7)

The SOIC-8 has a junction-to-board thermal

characterization parameter of ψJB = 43°C/W. In a

system application, the localized temperature around

the device is a function of the layout and construction of

the PCB along with airflow across the surfaces. To

ensure reliable operation, the maximum junction

temperature of the device must be prevented from

exceeding the maximum rating of 150°C; with 80%

derating, TJ would be limited to 120°C. Rearranging

Equation 4 determines the board temperature required

to maintain the junction temperature below 120°C:

TB = TJ - PTOTAL • ψJB (8)

TB = 120°C – 0.46 W • 43°C/W = 100°C (9)

FAN3216 / FAN3217 • Rev. 1.0.3 16

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Typical Application Diagrams

Figure 36. Forward Converter

with Synchronous Rectification Figure 37. Primary-Side Dual Driver

in a Push-Pull Converter

Figure 38. Phase-Shifted Full-Bridge with Two Gate Drive Transformers (Simplified)

FAN3216 / FAN3217 • Rev. 1.0.3 17

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Table 1. Related Products

Type Part

Number Gate Drive(14)

(Sink/Src) Input

Threshold Logic Package

Single 1 A FAN3111C +1.1 A / -0.9 A CMOS Single Channel of Dual-Input/Single-Output SOT23-5, MLP6

Single 1 A FAN3111E +1.1 A / -0.9 A External(15) Single Non-Inverting Channel with External Reference SOT23-5, MLP6

Single 2 A FAN3100C +2.5 A / -1.8 A CMOS Single Channel of Two-Input/One-Output SOT23-5, MLP6

Single 2 A FAN3100T +2.5 A / -1.8 A TTL Single Channel of Two-Input/One-Output SOT23-5, MLP6

Single 2 A FAN3180 +2.4 A / -1.6 A TTL Single Non-Inverting Channel + 3.3-V LDO SOT23-5

Dual 2 A FAN3216T +2.4 A / -1.6 A TTL Dual Inverting Channels SOIC8

Dual 2 A FAN3217T +2.4 A / -1.6 A TTL Dual Non-Inverting Channels SOIC8

Dual 2 A FAN3226C +2.4 A / -1.6 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8

Dual 2 A FAN3226T +2.4 A / -1.6 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8

Dual 2 A FAN3227C +2.4 A / -1.6 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8

Dual 2 A FAN3227T +2.4 A / -1.6 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8

Dual 2 A FAN3228C +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8

Dual 2 A FAN3228T +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8

Dual 2 A FAN3229C +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8

Dual 2 A FAN3229T +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8

Dual 2 A FAN3268T +2.4 A / -1.6 A TTL 20 V Non-Inverting Channel (NMOS) and Inverting

Channel (PMOS) + Dual Enables SOIC8

Dual 2 A FAN3278T +2.4 A / -1.6 A TTL 30 V Non-Inverting Channel (NMOS) and Inverting

Channel (PMOS) + Dual Enables SOIC8

Dual 4 A FAN3213T +2.5 A / -1.8 A TTL Dual Inverting Channels SOIC8

Dual 4 A FAN3214T +2.5 A / -1.8 A TTL Dual Non-Inverting Channels SOIC8

Dual 4 A FAN3223C +4.3 A / -2.8 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8

Dual 4 A FAN3223T +4.3 A / -2.8 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8

Dual 4 A FAN3224C +4.3 A / -2.8 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8

Dual 4 A FAN3224T +4.3 A / -2.8 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8

Dual 4 A FAN3225C +4.3 A / -2.8 A CMOS Dual Channels of Two-Input/One-Output SOIC8, MLP8

Dual 4 A FAN3225T +4.3 A / -2.8 A TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8

Single 9 A FAN3121C +9.7 A / -7.1 A CMOS Single Inverting Channel + Enable SOIC8, MLP8

Single 9 A FAN3121T +9.7 A / -7.1 A TTL Single Inverting Channel + Enable SOIC8, MLP8

Single 9 A FAN3122T +9.7 A / -7.1 A CMOS Single Non-Inverting Channel + Enable SOIC8, MLP8

Single 9 A FAN3122C +9.7 A / -7.1 A TTL Single Non-Inverting Channel + Enable SOIC8, MLP8

Dual 12 A FAN3240 +12.0 A TTL Dual-Coil Relay Driver, Timing Config. 0 SOIC8

Dual 12 A FAN3241 +12.0 A TTL Dual-Coil Relay Driver, Timing Config. 1 SOIC8

Notes:

14. Typical currents with OUTx at 6 V and VDD=12 V.

15. Thresholds proportional to an externally supplied reference voltage.

FAN3216 / FAN3217 • Rev. 1.0.3 18

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

Physical Dimensions

8°

0°

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08AREV13

LAND PATTERN RECOMMENDATION

SEATING PLANE

0.10 C

GAGE PLANE

x 45°

DETAIL A

SCALE: 2:1

PIN ONE

INDICATOR

MBA0.25

5.60

0.65

1.75

1.27

6.20

5.80

3.81

4.00

3.80

5.00

4.80

(0.33)

1.27

0.51

0.33

0.25

0.10

1.75 MAX

0.25

0.19

0.36

0.50

0.25

R0.10

0.90

0.406 (1.04)

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

Figure 39. 8-Lead Small Outline Integrated Circuit (SOIC)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN3216 / FAN3217 • Rev. 1.0.3 19

FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers

www.onsemi.com

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

www.onsemi.com

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative