841S01BGI www.icst.com/products/hiperclocks.html JUNE 12, 2006
1
Integrated
Circuit
Systems, Inc.
ICS841S01I
PCI EXPRESS™ C LOCK GENERATOR
PRELIMINARY
GENERAL DESCRIPTION
The ICS841S01I is a PLL-based clock generator
specifically designed for PCI_Express™Clock
Generation applications. This device generates
a 100MHz HCSL clock. The device offers a HCSL
(Host Clock Signal Level) clock output from a
clock input reference of 25MHz. The input reference may be
derived from an external source or by the addition of a 25MHz
crystal to the on-chip crystal oscillator. An external reference
may be applied to the XTAL_IN pin with the XTAL_OUT pin
left floating.
The device offers spread spectrum clock output for reduced
EMI applications. An I2C bus interface is used to enable or
disable spread spectrum operation as well as select either a
down spread value of -0.35% or -.5%.
The ICS841S01I is available in both standard and lead-free
16-Lead TSSOP packages.
HiPerClockS™
ICS
FEATURES
•One 0.7V current mode differential HCSL output pair
•Crystal oscillator interface, 25MHz
•Output frequency: 100MHz
•Period jitter: TBD
•Output skew: 150ps (maximum)
•Cycle-to-cyle jitter: 50ps (maximum)
•I2C support with readback capabilities up to 400kHz
•Spread Spectrum for electromagnetic interference (EMI)
reduction
•3.3V operating supply mode
•-40°C to 85°C ambient operating temperature
•Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM PIN ASSIGNMENT
VSS_SRC
VDD_SRC
SRCT0
SRCC0
VDD_SRC
VSS_SRC
IREF
VSSA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD_SRC
SDATA
SCLK
XTAL_OUT
XTAL_IN
VDD_REF
VSS_REF
VDDA
ICS841S01I
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
Divider
Network
PLL
OSC
I2C
Logic
SRCT0
SRCC0
SCLK
IREF
XTAL_IN
XTAL_OUT
SDATA
Pullup
Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
841S01BGI www.icst.com/products/hiperclocks.html JUNE 12, 2006
2
Integrated
Circuit
Systems, Inc.
ICS841S01I
PCI EXPRESS™ C LOCK GENERATOR
PRELIMINARY
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
6,1V
CRS_SS
rewoP.stuptuoCRSrofdnuorG
61,5,2V
CRS_DD
rewoP.stuptuoCRSrofylppusrewoP
4,30CCRS,0TCRStuptuO.slevelecafretniLSCH.riaptuptuolaitnereffiD
7FERItupnI
574(
rotsisernoisicerpdexifA Ωasedivorpdnuorgotnipsihtmorf)
0TCRS,0CCRSedom-tnerruclaitnereffidrofdesutnerru
cecnerefer
.stuptuokcolc
8V
ASS
rewoP.nipdnuorggolanA
9V
ADD
rewoP.LLProfylppusrewoP
01V
FER_SS
rewoPecafretnilatsyrcrofdnuorG
11V
FER_DD
rewoP.ecafretnilatsyrcrofylppusrewoP
,21
31 TUO_LATX,NI_LATXtupnI .tupniehtsiNI_LATX.ecafretnirotallicsolat
syrC
.tuptuoehtsiTUO_LATX
41KLCStupnIpulluP
tub,rotsiserpulluplanretninasahnipsihT.KLCSelbitapmocsuBMS
.edom
nwodrewopniecnadepmihgihnisi
.slevelecafretniLTTVL/SOMCVL
51ATADSpulluP
,rotsiserpulluplanretninasahnipsih
T.ATADSelbitapmocsuBMS
.edomnwodrewopniecnadepmihgihnisitub
.slevelecafretniLTTVL/SOMCVL
:ETON pulluP .seu
lavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
C
TUO
ecnaticapaCniPtuptuO35Fp
L
NI
ecnatcudnIniP 7Hn
841S01BGI www.icst.com/products/hiperclocks.html JUNE 12, 2006
3
Integrated
Circuit
Systems, Inc.
ICS841S01I
PCI EXPRESS™ C LOCK GENERATOR
PRELIMINARY
To enhance the flexibility and function of the clock synthe-
sizer, a two-signal serial interface is provided. Through the
Serial Data Interface, various device functions, such as
individual clock output buffers, can be individually enabled
or disabled. The registers associated with the Serial Data
Interface initialize to their default setting upon power-up,
and therefore, use of this interface is optional. Clock device
register changes are normally made upon system initial-
ization, if any are required. The interface cannot be used
during system operation for power management functions.
SERIAL DATA INTERFACE
The clock driver serial protocol accepts byte write, byte
read, block write, and block read operations from the con-
troller. For block write/read operation, the bytes must be
accessed in sequential order from lowest to highest byte
(most significant bit first) with the ability to stop after any
complete byte has been transferred. For byte write and byte
read operations, the system controller can access individu-
ally indexed bytes. The offset of the indexed byte is en-
coded in the command code, as described in Table 3A.
The block write and block read protocol is outlined in Table
3B, while Table 3C outlines the corresponding byte write
and byte read protocol. The slave receiver address is
11010010 (D2h).
DATA PROTOCOL
TABLE 3A. COMMAND CODE DEFINITION
TIBnoitpircseD
7 .noitarepoetirwetybrodaeretyB=1,noitarepoetirwkcolbrodaerkcolB=0
5:6.ecivedsseccaot"00"ot
tes,sserddatcelespihC
0:4 ebtsumstibeseht,snoitarepoetirwkcolbrodaerkcolbroF.noitarepoetirwetybrodaeret
ybroftesffoetyB
."00000"
TABLE 3B. BLOCK READ AND BLOCK W RITE PROTOCOL
TIBetirWkcolB=noitpircseDTIBdaeRkcolB=noitpircseD
1tratS1tratS
8:2stib7-sserddaevalS8:2stib7-sserddaevalS
9etirW9eti
rW
01evalsmorfegdelwonkcA01evalsmorfegdelwonkcA
81:11stib8-edoCdnammoC81:11stib8-edoCdnammoC
91evalsmorfegdelwo
nkcA91evalsmorfegdelwonkcA
72:02stib8-tnuoCetyB02tratstaepeR
82evalsmorfegdelwonkcA72:12stib7-sserddaevalS
63:92s
tib8-1etybataD821=daeR
73evalsmorfegdelwonkcA92evalsmorfegdelwonkcA
54:83stib8-2etybataD73:03stib8-evalsmorftnu
oCetyB
64evalsmorfegdelwonkcA83egdelwonkcA
segdelwonkcAevalS/etyBataD64:93stib8-evalsmorf1etyBataD
stib8-Nety
BataD74egdelwonkcA
evalsmorfegdelwonkcA55:84stib8-evalsmorf2etyBataD
potS65egdelwonkcA
segdelwonkcA/evalSmorfs
etyBataD
stib8-evalsmorfNetyBataD
egdelwonkcAtoN
841S01BGI www.icst.com/products/hiperclocks.html JUNE 12, 2006
4
Integrated
Circuit
Systems, Inc.
ICS841S01I
PCI EXPRESS™ C LOCK GENERATOR
PRELIMINARY
TABLE 3C. BYTE READ AND BYTE W RITE PROTOCOL
TIBetirWetyB=noitpircseDTIBdaeRetyB=noitpircseD
1tratS1tratS
8:2stib7-sserddaevalS8:2stib7-sserddaevalS
9etirW9etirW
01evalsmorfegdelwonkcA01evalsmorfegdelwonkcA
81:11stib8-edoCdnammoC81:11stib8-edoCdnammoC
91evalsmorfegdelwonk
cA91evalsmorfegdelwonkcA
72:02stib8-etybataD02tratstaepeR
82evalsmorfegdelwonkcA72:12stib7-sserddaevalS
92potS82dae
R
92evalsmorfegdelwonkcA
73:03stib8-evalsmorfataD
83egdelwonkcAtoN
93potS
TABLE 4A. BYTE 0:CONTROL REGISTER 0
CONTROL REGISTERS
TIBpuP@emaNnoitpircseD
70 devreseRdevreseR
61 devreseRdevreseR
51 devreseRdevreseR
41 devreseRdevreseR
31 devreseRdevreseR
21 0]C/T[C
RS
elbanEtuptuO0]C/T[CRS
)Z-iH(elbasiD=0
elbanE=1
10 devreseRdevreseR
00 devreseRdevreseR
841S01BGI www.icst.com/products/hiperclocks.html JUNE 12, 2006
5
Integrated
Circuit
Systems, Inc.
ICS841S01I
PCI EXPRESS™ C LOCK GENERATOR
PRELIMINARY
TABLE 4B. BYTE 1:CONTROL REGISTER 1
TIBpuP@emaNnoitpircseD
70 devreseRdevreseR
60 devreseRdevreseR
50 devreseRdevreseR
40 devreseRdevreseR
30 devreseRdevreseR
20 devrese
RdevreseR
10 devreseRdevreseR
00 devreseRdevreseR
TABLE 4D. BYTE 3:CONTROL REGISTER 3
TIBpuP@emaNnoitpircseD
71 devreseRdevreseR
60 devreseRdevreseR
51 devreseRdevreseR
40 devreseRdevreseR
31 devreseRdevreseR
21 devrese
RdevreseR
11 devreseRdevreseR
01 devreseRdevreseR
TABLE 4F. BYTE 5:CONTROL REGISTER 5
TIBpuP@emaNnoitpircseD
70 devreseRdevreseR
60 devreseRdevreseR
50 devreseRdevreseR
40 devreseRdevreseR
30 devreseRdevreseR
20 devrese
RdevreseR
10 devreseRdevreseR
00 devreseRdevreseR
TABLE 4C. BYTE 2:CONTROL REGISTER 2
TIBpuP@emaNnoitpircseD
71 C/TCRS noitceleSmurtcepSdaerpS
%05.0-=1,%53.0-=0
61 devreseRdevreseR
51 devreseRdevreseR
40 devres
eRdevreseR
31 devreseRdevreseR
20 CRS elbanEmurtcepSdaerpSCRS
nOdaerpS=1,ffOdaerpS=0
11 devreseRdevreseR
01 devreseRdevrese
R
TABLE 4E. BYTE 4:CONTROL REGISTER 4
TIBpuP@emaNnoitpircseD
70 devreseRdevreseR
60 devreseRdevreseR
50 devreseRdevreseR
40 devreseRdevreseR
30 devreseRdevreseR
20 devrese
RdevreseR
10 devreseRdevreseR
01 devreseRdevreseR
841S01BGI www.icst.com/products/hiperclocks.html JUNE 12, 2006
6
Integrated
Circuit
Systems, Inc.
ICS841S01I
PCI EXPRESS™ C LOCK GENERATOR
PRELIMINARY
TABLE 4G. BYTE 6:CONTROL REGISTER 6
TIBpuP@emaNnoitpircseD
70 LES_TSET tceleSetats-irTroN/FER
N/FER=1,Z-iH=0
60 EDOM_TSET lortnoCyrtnEedoMkcolCTSET
edoM
Z-iHroN/FER=1,noitarepOlamroN=0
50 devreseRdevreseR
41 devreseRdevreseR
30 devreseRdevreseR
20 devreseRdevreseR
11 devreseRdev
reseR
01 devreseRdevreseR
TABLE 4H. BYTE 7:CONTROL REGISTER 7
TIBpuP@emaNnoitpircseD
70 3tiBedoCnoisiveR
60 2tiBedoCnoisiveR
50 1tiBedoCnoisiveR
40 0tiBedoCnoisiveR
30 3tiBDIrodneV
20 2tiBDI
rodneV
10 1tiBDIrodneV
01 0tiBDIrodneV
OUTPUT DRIVER CURRENT
The ICS841S01I outputs are HCSL current drive with the
current being set with a resistor from IREF to ground. For a
50Ω pc board trace, the drive current would typically be set
with a RREF of 475Ω which products an IREF of 2.32mA. The
IREF is multiplied by a current mirror to an output drive of
6*2.32mA or 13.92mA. See Figure 1 for current mirror and
output drive details.
FIGURE 1. HCSL CURRENT MIRROR AND OUTPUT DRIVE
IREF
RREF RL
RL
841S01BGI www.icst.com/products/hiperclocks.html JUNE 12, 2006
7
Integrated
Circuit
Systems, Inc.
ICS841S01I
PCI EXPRESS™ C LOCK GENERATOR
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD_REF + 0.5 V
Outputs, VO-0.5V to VDD_SRC + 0.5V
Package Thermal Impedance, θJA 89°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V±5%, TA = -40°C TO 85°C
TABLE 5B. DC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
SUBMSHI
egatloVhgiHtupnIKLCS,ATADS2.2V
V
SUBMSLI
egatloVwoLtupnIKLCS,ATADS 0.1V
I
HI
tnerruChgiHtupnIKLCS,ATADSV
DD
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnIKLCS,ATADSV
DD
V,V564.3=
NI
V0=051-Aµ
I
HO
tnerruCtuptuO 41Am
I
ZO
tnerruCegakaeLecnadepmIhgiH 01-01Aµ
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
FER_DD
egatloVylppuSrewoP 531.33.3564.3V
V
ADD
egatloVylppuSgolanAV
FER_DD
I–
ADD
01* Ω3.3V
FER_DD
V
V
CRS_DD
egatloVylppuStuptuO531.33.3564.3V
I
DD
tnerruCylppuScimanyDycneuqerFdnadaoL.xaMtA004Am
I
ADD
tnerruCylppuSgolanA DBTAm
841S01BGI www.icst.com/products/hiperclocks.html JUNE 12, 2006
8
Integrated
Circuit
Systems, Inc.
ICS841S01I
PCI EXPRESS™ C LOCK GENERATOR
PRELIMINARY
TABLE 6. AC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
ferfycneuqerF 52zHM
klcsycneuqerFKLCS 004zHk
1ETON;ecnareloT
ycneuqerF
LATX05mpp
lanretxE
ecnerefeR 0mpp
cdo2ETON;elcyCytuDCCRS/TCRS 5455%
)o(kst2ETON;wekSkcolCC/TCRSotC/TCRS 05
1sp
t
DOIREP
3ETON;doirePegarevA 0799.93350.01sn
t)cc(tij2ETON;rettiJelcyC-ot-elcyCC/TCRS 05sp
t)rep(tijSMR,rettiJdoireP DBTs
p
t
R
t/
F
4ETON;emiTllaF/esiRCCRS/TCRS%08ot%02571007sp
t
MFR
5ETON;gnihctaMemiTllaF/esiR 02%
t
CD
6ETON;elcyCytuDNI_LATX 5.745.25%
Δt
R
t/
F
noitairaVemiTllaF/esiR 521sp
V
HGIH
hgiHegatloV 066058vm
V
WOL
woLegatloV 051-vm
V
XO
egatloVrevossorCtuptuOgniwSV7.0@052055Vm
V
SVO
egatloVtoohsrevOmumixaM V
HGIH
3.0+V
V
SDU
egatloVtoohsrednUmuminiM 3.0-V
V
BR
egatloVkcaBgniR 2.0V
.latsyrcdednemmocerhtiW:1ETON
VtniopgnissorctaderusaeM:2ETON
XO
.
VtniopgnissorctaderusaeM:3ETON
XO
.zHM001ta
VmorfderusaeM:4ETON
LO
VotV571.0=
HO
.V525.0=
t(*2fonoitcarfasadenimreteD:5ETON
R
t–
F
t(/)
R
t+
F
.)
nihtiwebtonlliwelcycytudkcolcFERehttub%07/03otpuselcycytudtupnihtiwylbaileretarepolliwecivedehT:6ETON
noitacificeps
841S01BGI www.icst.com/products/hiperclocks.html JUNE 12, 2006
9
Integrated
Circuit
Systems, Inc.
ICS841S01I
PCI EXPRESS™ C LOCK GENERATOR
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
PERIOD JITTER
CYCLE-TO-CYCLE JITTER3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
HCSL OUTPUT RISE/FALL T IME
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
t
PW
tPERIOD
t
PW
t
PERIOD
odc = x 100%
SRCT0
SRCC0
➤
➤
➤
➤
SRCT0
SRCC0
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
tcycle n tcycle n+1
OUTPUT DUTY CYCLE/PULSE W IDTH/PERIOD
t
sk(o)
nSRCx
SRCx
nSRCy
SRCy
VOH
VREF
VOL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Histogram
HSCL
33Ω
100Ω Differential
33Ω
475Ω49.9Ω
Measurement
Point
49.9Ω
Measurement
Point
0V
3.3V±5%
GND
VDD_REF,
VDD_SRC
3.3V±5%
VDDA
841S01BGI www.icst.com/products/hiperclocks.html JUNE 12, 2006
10
Integrated
Circuit
Systems, Inc.
ICS841S01I
PCI EXPRESS™ C LOCK GENERATOR
PRELIMINARY
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The ICS841S01I pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. VDD_REF, VDDA,
and VDD_SRC should be individually connected to the power
supply plane through vias, and bypass capacitors should
be used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VDDA. The 10Ω resis-
tor can also be replaced by a ferrite bead.
POWER SUPPLY FILTERING T ECHNIQUES
FIGURE 2. POWER SUPPLY FILTERING
10Ω
VDDA
10μF
.01μF
3.3V
.01μF
VDD_REF
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
HCSL OUTPUT
All unused HCSL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
USING THE ON-BOARD CRYSTAL OSCILLATOR
The ICS841S01I features a fully integrated Pierce oscillator
to minimize system implementation costs. The ICS841S01I
may be operated with a 25MHz crystal and without addi-
tional components. Recommended operation for the crystal
should be of a parallel resonant type and a load specification
of CL = 18pF. See Table 7 for complete crystal specifications.
If more precise frequency control is desired, the addition of
capacitors from each of the XTAL_IN and XTAL_OUT pins
to ground may be used to trim the frequency as shown in
Figure 3.
TABLE 7. RECOMMENDED CRYSTAL SPECIFICATIONS
retemaraPeulaV
tuClatsyrCtuCTAlatnemadnuF
ecnanoseRecnanoseRlellaraP
C(ecnaticapaCtnuhS
L
)Fp7-5
C(ecnaticapaCdaoL
O
)Fp81
)RSE(ecnatsiseRseireStnelaviuqE05-02 Ω
FIGURE3. CRYSTAL OSCILLATOR W ITH T RIM CAPACITOR
The crystal and optional trim capacitors should be located as
close to the ICS841S01I XTAL_IN and XTAL_OUT pins as
possible to avoid any board level parasitic.
XT AL_IN
XTAL_OUT
25MHz
TBD
TBD
841S01BGI www.icst.com/products/hiperclocks.html JUNE 12, 2006
11
Integrated
Circuit
Systems, Inc.
ICS841S01I
PCI EXPRESS™ C LOCK GENERATOR
PRELIMINARY
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS841S01I is: 1874
TABLE 8. θJAVS. AIR FLOW T ABLE FOR 16 LEAD TSSOP
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 118.2°C/W 106.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 89.0°C/W 81.8°C/W 78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
841S01BGI www.icst.com/products/hiperclocks.html JUNE 12, 2006
12
Integrated
Circuit
Systems, Inc.
ICS841S01I
PCI EXPRESS™ C LOCK GENERATOR
PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
LOBMYS sretemilliM
muminiMmumixaM
N61
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D09.401.5
ECISAB04.6
1E03.405.4
eCISAB56.0
L5
4.057.0
α°0°8
aaa--01.0
841S01BGI www.icst.com/products/hiperclocks.html JUNE 12, 2006
13
Integrated
Circuit
Systems, Inc.
ICS841S01I
PCI EXPRESS™ C LOCK GENERATOR
PRELIMINARY
TABLE 10. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be
registered in certain jurisdictions.
rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT
IGB10S148SCIIB10S148SCIPOSSTdaeL61ebutC°58otC°04-
TI
GB10S148SCIIB10S148SCIPOSSTdaeL61leer&epat0052C°58otC°04-
FLIGB10S148SCILIB10S14POSST"eerF-daeL"daeL61ebutC°58
otC°04-
TFLIGB10S148SCILIB10S14POSST"eerF-daeL"daeL61leer&epat0052C°58otC°04-
.tnailpmocSHoReradnanoitarugi
fnoceerF-bPehterarebmuntrapehtotxiffus"FL"nahtiwderedroeratahtstraP:ETON
