REV. A
a
ADT7460
*
dB
COOL
™
Remote Thermal
Controller and Fan Controller
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
FEATURES
Controls and Monitors up to 4 Fan Speeds
1 On-Chip and 2 Remote Temperature Sensors
Dynamic T
MIN
Control Mode Optimizes System Acoustics
Intelligently
Automatic Fan Speed Control Mode Controls System
Cooling Based on Measured Temperature
Enhanced Acoustic Mode Dramatically Reduces User
Perception of Changing Fan Speeds
Thermal Protection Feature via THERM Output
Monitors Performance Impact of Intel
®
Pentium
®
4
Processor Thermal Control Circuit via THERM Input
2-Wire and 3-Wire Fan Speed Measurement
Limit Comparison of All Monitored Values
Meets SMBus 2.0 Electrical Specifications
(Fully SMBus 1.1 Compliant)
APPLICATIONS
Low Acoustic Noise PCs
Networking and Telecommunications Equipment
FUNCTIONAL BLOCK DIAGRAM
BAND GAP
REFERENCE
10-BIT
ADC
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
GND
SERIAL BUS
INTERFACE
SCL SDA
ADDRESS
POINTER
REGISTER
ADT7460
VALUE AND
LIMIT
REGISTERS
LIMIT
COMPARATORS
PWM
CONFIGURATION
REGISTERS
INTERRUPT
STATUS
REGISTERS
BAND GAP
TEMP. SENSOR
V
CC
TO ADT7460
INTERRUPT
MASKING
SMBALERT
V
CC
D1+
D1–
D2+
D2–
+2.5V
IN
SMBUS
ADDRESS
SELECTION
ADDR EN
ADDR
SELECT
THERMAL
PROTECTION
PERFORMANCE
MONITORING
THERM
PWM
REGISTERS
AND
CONTROLLERS
PWM1
PWM2
PWM3
ACOUSTIC
ENHANCEMENT
CONTROL
AUTOMATIC
FAN SPEED
CONTROL
DYNAMIC
T
MIN
CONTROL
FAN SPEED
COUNTER
TACH1
TACH2
TACH3
TACH4
GENERAL DESCRIPTION
The ADT7460 dBCOOL controller is a thermal monitor and
multiple PWM fan controller for noise-sensitive applications
requiring active system cooling. It can monitor the temperature
of up to two remote sensor diodes, plus its own internal tempera-
ture. It can measure and control the speed of up to four fans so
that they operate at the lowest possible speed for minimum
acoustic noise. The automatic fan speed control loop optimizes fan
speed for a given temperature. A unique dynamic T
MIN
control
mode enables the system thermals/acoustics to be intelligently
managed. The effectiveness of the system’s thermal solution can
be monitored using the THERM input. The ADT7460 also
provides critical thermal protection to the system using the
bidirectional THERM pin as an output to prevent system or
component overheating.
*Protected by U.S. Patent Nos. 6,188,189; 6,169,442; 6,097,239; 5,982,221; and 5,867,012. Other patents pending.
REV. A–2–
ADT7460–SPECIFICATIONS
1, 2, 3, 4
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage 3.0 5.0 5.5 V
Supply Current, I
CC
3mAInterface Inactive, ADC Active
20 mAStandby Mode
TEMPERATURE-TO-DIGITAL CONVERTER
Local Sensor Accuracy ±1.5 C0C T
A
70C
±3C–40C T
A
+120C
Resolution 0.25 C
Remote Diode Sensor Accuracy ±1.5 C
0
C T
A
70
C; 0
C T
D
120
C
±2.5 C
0
C T
A
105
C; 0
C T
D
120
C
±3C
0
C T
A
120
C; 0
C T
D
120
C
Resolution 0.25 C
Remote Sensor Source Current 180 mAHigh Level
11 mALow Level
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error, TUE ±1.5 %
Differential Nonlinearity, DNL ±1LSB 8 Bits
Power Supply Sensitivity ±0.1 %/V
Conversion Time (Voltage Input) 11.38 13 ms Averaging Enabled
Conversion Time (Local Temperature) 12.09 13.50 ms Averaging Enabled
Conversion Time (Remote Temperature) 25.59 28 ms Averaging Enabled
Total Monitoring Cycle Time 120.17 134.50 ms Averaging Enabled (Incl. Delay
5
)
Total Monitoring Cycle Time 13.51 15 ms Averaging Disabled
Input Resistance 80 140 200 kW
FAN RPM-TO-DIGITAL CONVERTER
Accuracy ±7%0C T
A
70C
±11 % 0C T
A
105C
±13 % –40C T
A
+120C
Full-Scale Count 65,535
Nominal Input RPM 109 RPM Fan Count = 0xBFFF
329 RPM Fan Count = 0x3FFF
5000 RPM Fan Count = 0x0438
10000 RPM Fan Count = 0x021C
Internal Clock Frequency 82.8 90.0 97.2 kHz
OPEN-DRAIN DIGITAL OUTPUTS,
PWM1–PWM3, XTO
Current Sink, I
OL
8.0 mA
Output Low Voltage, V
OL
0.4 V I
OUT
= –8.0 mA, V
CC
= 3.3 V
High Level Output Current, I
OH
0.1 1 mAV
OUT
= V
CC
OPEN-DRAIN SERIAL DATA
BUS OUTPUT (SDA)
Output Low Voltage, V
OL
0.4 V I
OUT
= –4.0 mA, V
CC
= 3.3 V
High Level Output Current, I
OH
0.1 1 mAV
OUT
= V
CC
SMBUS DIGITAL INPUTS
(SCL, SDA)
Input High Voltage, V
IH
2.0 V
Input Low Voltage, V
IL
0.4 V
Hysteresis 500 mV
DIGITAL INPUT LOGIC LEVELS
(TACH INPUTS)
Input High Voltage, V
IH
2.0 V
5.5 V Maximum Input Voltage
Input Low Voltage, V
IL
+0.8 V
–0.3 V Minimum Input Voltage
Hysteresis 0.5 V p-p
(TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.)
REV. A
ADT7460
–3–
Parameter Min Typ Max Unit Test Conditions/Comment
DIGITAL INPUT LOGIC LEVELS
(THERM)
Input High Voltage, V
IH
1.7 V
Input Low Voltage, V
IL
0.8 V
DIGITAL INPUT CURRENT
Input High Current, I
IH
–1 mAV
IN
= V
CC
Input Low Current, I
IL
+1 mAV
IN
= 0
Input Capacitance, C
IN
5pF
SERIAL BUS TIMING
Clock Frequency, f
SCLK
10 100 kHz See Figure 1
Glitch Immunity, t
SW
50 ns See Figure 1
Bus Free Time, t
BUF
4.7 msSee Figure 1
Start Setup Time, t
SU;STA
4.7 msSee Figure 1
Start Hold Time, t
HD;STA
4.0 msSee Figure 1
SCL Low Time, t
LOW
4.7 msSee Figure 1
SCL High Time, t
HIGH
4.0 50 msSee Figure 1
SCL, SDA Rise Time, t
R
1000 ns See Figure 1
SCL, SDA Fall Time, t
F
300 msSee Figure 1
Data Setup Time, t
SU;DAT
250 ns See Figure 1
Data Hold Time, t
HD;DAT
300 ns See Figure 1
Detect Clock Low Timeout, t
TIMEOUT
15 35 ms Can Be Optionally Disabled
NOTES
1
All voltages are measured with respect to GND, unless otherwise specified.
2
Typicals are at T
A
= 25∞C and represent the most likely parametric norm.
3
Logic inputs will accept input high voltages up to V
MAX
even when the device is operating down to V
MIN
.
4
Timing specifications are tested at logic levels of V
IL
= 0.8 V for a falling edge and V
IH
= 2.0 V for a rising edge.
5
The delay is the time between the round robin finishing one set of measurements and starting the next.
Specifications subject to change without notice.
P
S
t
SU;DAT
t
HIGH
t
F
t
HD;DAT
t
R
t
LOW
t
SU;STO
PS
SCL
SDA
t
HD;STA
t
HD;STA
t
SU;STA
t
BUF
Figure 1. Diagram for Serial Bus Timing
REV. A–4–
ADT7460
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (V
CC
) . . . . . . . . . . . . . . . . . . . . . 6.5 V
Voltage on Any Other Input or Output Pin . . . . –0.3 V to +6.5 V
Input Current at Any Pin . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Maximum Junction Temperature (T
J
max) . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature . . . . . . . . . . . . . . . . . . . 220°C
Lead Temperature (soldering 10 sec) . . . . . . . . . . . . . 300°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADT7460 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
THERMAL CHARACTERISTICS
16-Lead QSOP Package:
θ
JA
= 150°C/W, θ
JC
= 39°C/W
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
ADT7460ARQ –40⬚C to +120⬚C16-Lead QSOP RQ-16
ADT7460ARQ-REEL
–40⬚C to +120⬚C16-Lead QSOP RQ-16
ADT7460ARQ-REEL7
–40⬚C to +120⬚C16-Lead QSOP RQ-16
EVAL-ADT7460EB
REV. A
ADT7460
–5–
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
2GND Ground Pin for the ADT7460.
3V
CC
Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required. V
CC
is also
monitored through this pin. The ADT7460 can also be powered from a 5 V supply. Setting Bit 7 of
Configuration Register 1 (Reg. 0x40) rescales the V
CC
input attenuators to correctly measure a 5 V supply.
4TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. Can be reconfigured as an
analog input (AIN3) to measure the speed of 2-wire fans.
5PWM2 Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulsewidth modulated output to control Fan 2 speed.
SMBALERT Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal
out-of-limit conditions.
6TACH1 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. Can be reconfigured as an
analog input (AIN1) to measure the speed of 2-wire fans.
7TACH2 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. Can be reconfigured as an
analog input (AIN2) to measure the speed of 2-wire fans.
8PWM3 Digital I/O (Open Drain). Pulsewidth modulated output to control Fan 3/4 speed. Requires 10 kΩ typical pull-up.
ADDRESS If pulled low on power-up, this places the ADT7460 into address select mode, and the state of Pin 9 will
ENABLE determine the ADT7460’s slave address.
9TACH4 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. Can be reconfigured as an
analog input (AIN4) to measure the speed of 2-wire fans.
ADDRESS If in address select mode, this pin determines the SMBus device address.
SELECT
THERM Alternatively, the pin may be reconfigured as a bidirectional THERM pin. Can be used to time and monitor asser-
tions on the THERM input. For example, can be connected to the PROCHOT output of Intel’s Pentium 4
processor or to the output of a trip point temperature sensor. Can be used as an output to signal
overtemperature conditions.
10 D2– Cathode Connection to Second Thermal Diode.
11 D2+ Anode Connection to Second Thermal Diode.
12 D1– Cathode Connection to First Thermal Diode.
13 D1+ Anode Connection to First Thermal Diode.
14 +2.5V
IN
Analog Input. Monitors 2.5 V supply, typically a chipset voltage.
SMBALERT Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal
out-of-limit conditions.
15 PWM1/XTO Digital Output (Open Drain). Pulsewidth modulated output to control Fan 1 speed. Requires 10 kΩ typical pull-up.
16 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pull-up.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
ADT7460
TACH2
TACH1
PWM2/SMBALERT
TACH3
SDA
SCL
GND
VCC
PWM3/ADDRESS ENABLE TACH4/ADDRESS SELECT/THERM
D2–
D2+
D1–
PWM1/XTO
+2.5VIN/SMBALERT
D1+
REV. A–6–
ADT7460
FUNCTIONAL DESCRIPTION
General Description
The ADT7460 is a thermal monitor and multiple fan controller
for any system requiring monitoring and cooling. The device
communicates with the system via a serial System Management
Bus(SMBus). The serial bus controller has an optional address
line for device selection (Pin 9), a serial data line for reading and
writing addresses and data (Pin 16), and an input line for the
serial clock (Pin 1). All control and programming functions of
the ADT7460 are performed over the serial bus. In addition, two of
the pins can be reconfigured as an SMBALERT output to indicate
out-of-limit conditions.
Measurement Inputs
The device has three measurement inputs, one for voltage and
two for temperature. It can also measure its own supply voltage
and can measure ambient temperature with its on-chip tem-
perature sensor.
Pin 14 is an analog input with an on-chip attenuator and is
configured to monitor 2.5 V.
Power is supplied to the chip via Pin 3, and the system also
monitors V
CC
through this pin. In PCs, this pin is normally
connected to a 3.3 V standby supply. This pin can, however, be
connected to a 5 V supply and monitor it without overranging.
Remote temperature sensing is provided by the D1 and D2
inputs, to which diode-connected, external temperature-sensing
transistors, such as a 2N3904 or CPU thermal diode, may be
connected.
The ADC also accepts input from an on-chip band gap tem-
perature sensor that monitors system ambient temperature.
Sequential Measurement
When the ADT7460 monitoring sequence is started, it cycles
sequentially through the measurement of 2.5 V input and the
temperature sensors. Measured values from these inputs are
stored in value registers. These can be read out over the serial
bus, or can be compared with programmed limits stored in the
limit registers. The results of out-of-limit comparisons are stored
in the Status registers, which can be read over the serial bus to
flag out-of-limit conditions.
ADT7460 Address Selection
Pin 8 is the dual function PWM3/ADDRESS ENABLE pin. If Pin
8 is pulled low on power-up, the ADT7460 will read the state of
Pin 9 (TACH4/ADDRESS SELECT/
THERM
) to determine the
ADT7460’s slave address. If Pin 8 is high on power-up, then
the ADT7460 will default to SMBus slave address 0x2E. This
function is described in more detail later.
INTERNAL REGISTERS OF THE ADT7460
A brief description of the ADT7460’s principal internal registers
is given below. More detailed information on the function of
each register is given in Tables IV to XLI.
Configuration Registers
The configuration registers provide control and configuration of
the ADT7460, including alternate pinout functionality.
Address Pointer Register
This register contains the address that selects one of the other
internal registers. When writing to the ADT7460, the first byte
of data is always a register address, which is written to the
address pointer register.
Status Registers
These registers provide the status of each limit comparison and
are used to signal out-of-limit conditions on the temperature,
voltage, or fan speed channels. If Pin 14 is configured as
SMBALERT, then this pin will assert low whenever an unmasked
status bit gets set.
Interrupt Mask Registers
These registers allow each interrupt status event to be masked
when Pin 14 is configured as an SMBALERT output.
Value and Limit Registers
The results of analog voltage input, temperature, and fan
speed measurements are stored in these registers, along with
their limit values.
Offset Registers
These registers allow each temperature channel reading to be
offset by a twos complement value written to these registers.
T
MIN
Registers
These registers program the starting temperature for each fan
under automatic fan speed control.
T
RANGE
Registers
These registers program the temperature-to-fan speed control
slope in automatic fan speed control mode for each PWM output.
Operating Point Registers
These registers define the target operating temperatures for each
thermal zone when running under dynamic T
MIN
control. This
function allows the cooling solution to adjust dynamically in
response to measured temperature and system performance.
Enhance Acoustics Registers
These registers allow each PWM output controlling fan to be
tweaked to enhance the system’s acoustics.
REV. A
Typical Performance Characteristics–ADT7460
–7–
LEAKAGE RESISTANCE – M⍀
REMOTE TEMPERATURE ERROR – ⴗC
15
10
–201 3.3 100.0
10.0 30.0
0
–5
–10
–15
5DXP TO GND
DXP TO V
CC
(3.3V)
TPC 1. Remote Temperature
Error vs. Leakage Resistance
TEMPERATURE – C
LOCAL TEMPERATURE ERROR – C
–3
–40 10 110
60
1
0
–2
–1
3
2
LOW LIMIT
HIGH LIMIT
–3 SIGMA
+3 SIGMA
TPC 4. Local Temperature Error vs.
Actual Temperature
1.9
1.8
1.8
1.7
1.7
1.6
1.6
1.5
1.5
1.4
1.4
2.5
2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4
5.5
SUPPLY VOLTAGE – V
SUPPLY CURRENT – mA
TPC 7. Supply Current vs.
Supply Voltage
DXP–DXN CAPACITANCE – nF
REMOTE TEMPERATURE ERROR – ⴗC
3
1
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
2.2 3.3 4.7 10.0 22.0 47.0
–30
–33
–36
REMOTE TEMPERATURE
ERROR (ⴗC)
TPC 2. Remote Temperature Error
vs. Capacitance between D+ and D–
FREQUENCY – Hz
REMOTE TEMPERATURE ERROR – ⴗC
14
12
–2.0
100k 550k 50M
5M
6
4
0
2
10
8
100mV
250mV
TPC 5. Remote Temperature Error
vs. Power Supply Noise Frequency
FREQUENCY – Hz
REMOTE TEMPERATURE ERROR – ⴗC
16
60k
14
12
10
8
6
4
2
0
–2.0
110k 1M 10M 50M
10mV
20mV
TPC 8. Remote Temperature Error
vs. Differential Mode Noise
Frequency
TEMPERATURE – C
REMOTE TEMPERATURE ERROR – C
3
–40
2
1
0
–1
–2
–3 10 60 110
–3 SIGMA
+3 SIGMA
LOW LIMIT
HIGH LIMIT
TPC 3. Remote Temperature Error
vs. Actual Temperature
FREQUENCY – Hz
LOCAL TEMPERATURE ERROR – ⴗC
12.5
10.0
–5.0
100k 550k 50M
5M
5.0
2.5
–2.5
0
7.5
100mV
250mV
TPC 6. Local Temperature Error vs.
Power Supply Noise Frequency
FREQUENCY – Hz
REMOTE TEMPERATURE ERROR – ⴗC
40
10k
35
30
25
20
15
10
5
0
–5
–10 100k 1M 10M
20mV
40mV
100mV
TPC 9. Remote Temperature Error
vs. Common-Mode Noise
Frequency
REV. A–8–
ADT7460
GND
TACH2
PWM3
TACH3
D1+
D1–
SMBALERT
ADT7460
SCL
SDA
THERM
D2+
D2–
TACH1
PWM1
FRONT
CHASSIS
FAN
REAR
CHASSIS
FAN
AMBIENT
TEMPERATURE
PROCHOT
Figure 2. Recommended Implementation
RECOMMENDED IMPLEMENTATION
Configuring the ADT7460 as in Figure 2 allows the systems
designer the following features:
∑Two PWM outputs for fan control of up to three fans (the
front and rear chassis fans are connected in parallel).
∑Three TACH fan speed measurement inputs.
∑V
CC
measured internally through Pin 3.
∑CPU temperature measured using Remote 1 temperature
channel.
∑Ambient temperature measured through Remote 2
temperature channel.
∑Bidirectional THERM pin. Allows Intel Pentium 4
PROCHOT
monitoring and can function as an
overtemperature
THERM output.
∑SMBALERT system interrupt output.
REV. A
ADT7460
–9–
SERIAL BUS INTERFACE
Control of the ADT7460 is carried out using the serial System
Management bus (SMBus). The ADT7460 is connected to this
bus as a slave device, under the control of a master controller.
The ADT7460 has a 7-bit serial bus address. When the device
is powered up with Pin 8 (PWM3/ADDRESS ENABLE) high,
the ADT7460 will have a default SMBus address of 0101110 or
0x2E. If more than one ADT7460 is to be used in a system,
then each ADT7460 should be placed in address select mode by
strapping Pin 8 low on power-up. The logic state of Pin 9 then
determines the device’s SMBus address. The logic state of these
pins is sampled upon power-up.
The device address is sampled and latched on the first valid
SMBus transaction, more precisely, on the low to high transition
at the beginning of the eighth SCL pulse, when the serial address
byte matches the selected slave address. The selected slave
address is chosen using the ADDRESS ENABLE/ADDRESS
SELECT pins. Any attempted changes in the address will have
no effect after this.
Table I. Address Select Mode
Pin 8 State Pin 9 State Address
0Low (10 kW to GND) 0101100 (0x2C)
0High (10 kW Pull-Up) 0101101 (0x2D)
1Don’t Care 0101110 (0x2E)
(Default)
ADT7460
9
8
ADDR_SEL
PWM3/ADDR_EN
V
CC
10k⍀
ADDRESS = 0x2E
Figure 3. Default SMBus Address = 0x2E
ADT7460
9
8
ADDR_SEL
PWM3/ADDR_EN
10k⍀
ADDRESS = 0x2C
Figure 4. SMBus Address = 0x2C (Pin 9 = 0)
The facility to make hardwired changes to the SMBus slave
address allows the user to avoid conflicts with other devices shar-
ing the same serial bus, for example, if more than one ADT7460
is used in a system.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start condi-
tion, defined as a high to low transition on the serial data line
SDA while the serial clock line SCL remains high. This indicates
that an address/data stream will follow. All slave peripherals
connected to the serial bus respond to the start condition and
shift in the next eight bits, consisting of a 7-bit address (MSB
first) plus a R/W bit, which determines the direction of the
data transfer, i.e., whether data will be written to or read from
the slave device.
ADT7460
ADDR_SEL
PWM3/ADDR_EN
ADDRESS = 0x2D
9
8
VCC
10k⍀
Figure 5. SMBus Address = 0x2D (Pin 9 = 1)
ADT7460
9
8
ADDR_SEL
PWM3/ADDR_EN
VCC
10k⍀
DO NOT LEAVE ADDR_EN
UNCONNECTED! CAN
CAUSE UNPREDICTABLE
ADDRESSES
NC
CARE SHOULD BE TAKEN TO ENSURE THAT PIN 8
(PWM3/ADDR_EN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 8
FLOATING COULD CAUSE THE ADT7460 TO POWER UP WITH AN
UNEXPECTED ADDRESS.
NOTE THAT IF THE ADT7460 IS PLACED INTO ADDRESS SELECT
MODE, PINS 8 AND 9 CAN BE USED AS THE ALTERNATE FUNC-
TIONS (PWM3, TACH4/THERM) ONLY IF THE CORRECT CIRCUIT IS
MUXED IN AT THE CORRECT TIME
Figure 6. Unpredictable SMBus Address if Pin 8 Is
Unconnected
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowl-
edge Bit. All other devices on the bus now remain idle while
the selected device waits for data to be read from or written
to it. If the R/W bit is a 0, then the master will write to the
slave device.If the R/W bit is a 1, the master will read from
the slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an Acknowledge Bit
from the slave device. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, as a low to high transition when the
clock is high may be interpreted as a stop signal. The number
of data bytes that can be transmitted over the serial bus in a
single read or write operation is limited only by what the
master and slave devices can handle.
3. When all data bytes have been read or written, stop conditions
are established. In write mode, the master will pull the data
line high during the 10th clock pulse to assert a stop condition.
In read mode, the master device will override the acknowl-
edge bit by pulling the data line high during the low period
before the ninth clock pulse. This is known as No Acknowledge.
The master will then take the data line low during the low
period before the 10th clock pulse, then high during the
10th clock pulse to assert a stop condition.
REV. A–10–
ADT7460
R/W
0
SCL
SDA 10
11A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7460
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
19
1
ACK. BY
ADT7460
9
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7460
STOP BY
MASTER
FRAME 3
DATA
BYTE
19
SCL (CONTINUED)
SDA (CONTINUED)
Figure 7. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
In the case of the ADT7460, write operations contain either one
or two bytes, and read operations contain one byte and perform
the following functions:
To write data to one of the device data registers or read data
from it, the address pointer register must be set so that the
correct data register is addressed, then data can be written into
that register or read from it. The first byte of a write operation
always contains an address that is stored in the address pointer
register. If data is to be written to the device, then the write
operation contains a second data byte that is written to the
register selected by the address pointer register.
This is illustrated in Figure 7. The device address is sent over
the bus followed by R/W being set to 0. This is followed by two
data bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the address pointer
register. The second data byte is the data to be written to the
internal data register.
REV. A
ADT7460
–11–
When reading data from a register, there are two possibilities:
1. If the ADT7460’s address pointer register value is unknown
or not the desired value, it is first necessary to set it to the
correct value before data can be read from the desired data
register. This is done by performing a write to the ADT7460
as before, but only the data byte containing the register address
is sent as data is not to be written to the register. This is
shown in Figure 8.
A read operation is then performed consisting of the serial
bus address, R/W bit set to 1, followed by the data byte read
from the data register. This is shown in Figure 9.
2. If the address pointer register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register, so Figure 8 can be omitted.
Notes
1. It is possible to read a data byte from a data register without
first writing to the address pointer register if the address
pointer register is already at the correct value. However, it is
not possible to write data to a register without writing to the
address pointer register because the first data byte of a write
is always written to the address pointer register.
2. In Figures 7 to 9, the serial bus address is shown as the
default value 01011(A1)(A0), where A1 and A0 are set by
the address select mode function previously defined.
3. In addition to supporting the Send Byte and Receive Byte
protocols, the ADT7460 also supports the Read Byte protocol
(see System Management Bus specifications Rev. 2.0 for
more information).
4. If it is required to perform several read or write operations in
succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
R/W
0
SCL
SDA 10
11A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7460
STOP BY
MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
19
1
ACK. BY
ADT7460
9
Figure 8. Writing to the Address Pointer Register Only
R/W
0
SCL
SDA 10
11A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
NO ACK. BY
MASTER
STOP BY
MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
DATA BYTE FROM ADT7460
19
1
ACK. BY
ADT7460
9
Figure 9. Reading Data from a Previously Selected Register
REV. A–12–
ADT7460
ADT7460 WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADT7460 are discussed below. The following abbreviations are
used in the diagrams:
S – START
P– STOP
R– READ
W – WRITE
A– ACKNOWLEDGE
A–NO ACKNOWLEDGE
The ADT7460 uses the following SMBus write protocols:
Send Byte
In this operation, the master device sends a single command
byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7460, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This is illustrated in Figure 10.
SSLAVE
ADDRESS WA
12 3 4 56
AP
REGISTER
ADDRESS
Figure 10. Setting a Register Address for Subsequent
Read
If it is required to read data from the register immediately after
setting up the address, the master can assert a repeat start con-
dition immediately after the final ACK and carry out a single
byte read without asserting an intermediate stop condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end the
transaction.
This is illustrated in Figure 11.
SSLAVE
ADDRESS WA
12 3 4 56
ADATA AP
78
REGISTER
ADDRESS
Figure 11. Single Byte Write to a Register
ADT7460 READ OPERATIONS
The ADT7460 uses the following SMBus read protocols:
Receive Byte
This is useful when repeatedly reading a single register. The
register address needs to have been set up previously. In this
operation, the master device receives a single byte from a slave
device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA and the trans-
action ends.
In the ADT7460, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation.
SSLAVE
ADDRESS WA
12 3 4 56
AP
REGISTER
ADDRESS
Figure 12. Single Byte Read from a Register
ALERT RESPONSE ADDRESS
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as an interrupt output or
can be used as an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
procedure occurs:
1. SMBALERT is pulled low.
2. Master initiates a read operation and sends the alert response
address (ARA = 0001 100). This is a general call address
that must not be used as a specific device address.
3. The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known, and it can
be interrogated in the usual way.
4. If more than one device’s SMBALERT output is low, the
one with the lowest device address will have priority in
accordance with normal SMBus arbitration.
5. Once the ADT7460 has responded to the alert response
address, the master must read the status registers and the
SMBALERT will be cleared only if the error condition has
gone away.
REV. A
ADT7460
–13–
SMBus Timeout
The ADT7460 includes an SMBus timeout feature. If there is
no SMBus activity for 35 ms, the ADT7460 assumes that the bus
is locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it
can be disabled.
CONFIGURATION REGISTER 1 (REG. 0x40)
<6> TODIS = 0; SMBus Timeout Enabled (Default)
<6> TODIS = 1; SMBus Timeout Disabled
VOLTAGE MEASUREMENT INPUT
The ADT7460 has one external voltage measurement channel.
It can also measure its own supply voltage, V
CC
.
Pin 14 may be configured to measure a 2.5 V supply. The V
CC
supply voltage measurement is carried out through the V
CC
pin
(Pin 3). Setting Bit 7 of Configuration Register 1 (Reg. 0x40)
allows a 5 V supply to power the ADT7460 and be measured
without overranging the V
CC
measurement channel. The 2.5 V
input can be used to monitor a chipset supply voltage in
computer systems.
ANALOG-TO-DIGITAL CONVERTER
All analog inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter. This has a resolu-
tion of 10 bits. The basic input range is 0 V to 2.25 V, but the
input has built-in attenuators to allow measurement of 2.5 V
without any external components. To allow for the tolerance of
the supply voltage, the ADC produces an output of 3/4 full scale
(decimal 768 or 300 hex) for the nominal input voltage and so
has adequate headroom to deal with overvoltages.
INPUT CIRCUITRY
The internal structure for the 2.5 V analog input is shown in
Figure 13. The input circuit consists of an input protection diode,
an attenuator, plus a capacitor to form a first order low-pass
filter that gives the input immunity to high frequency noise.
VOLTAGE MEASUREMENT REGISTERS
Reg. 0x20 2.5 V Reading = 0x00 Default
2.5 V LIMIT REGISTERS
Associated with the 2.5 V measurement channel is a high and
low limit register. Exceeding the programmed high or low limit
causes the appropriate status bit to be set. Exceeding either limit
can also generate SMBALERT interrupts.
Reg. 0x44 2.5 V Low Limit = 0x00 Default
Reg. 0x45 2.5 V High Limit = 0xFF Default
30pF
45k⍀
94k⍀
2.5VIN
Figure 13. Structure of Analog Inputs
Table II shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 711 ms and averages 16 conversions to reduce noise;
ameasurement takes nominally 11.38 ms.
REV. A–14–
ADT7460
Table II. 10-Bit A/D Output Code vs. V
IN
Input Voltage A/D Output
+5V
IN
V
CC
(3.3V
IN
)*+2.5V
IN
Decimal Binary (10 Bits)
<0.0065 <0.0042 <0.0032 0 00000000 00
0.0065–0.0130 0.0042–0.0085 0.0032–0.0065 1 00000000 01
0.0130–0.0195 0.0085–0.0128 0.0065–0.0097 2 00000000 10
0.0195–0.0260 0.0128–0.0171 0.0097–0.0130 3 00000000 11
0.0260–0.0325 0.0171–0.0214 0.0130–0.0162 4 00000001 00
0.0325–0.0390 0.0214–0.0257 0.0162–0.0195 5 00000001 01
0.0390–0.0455 0.0257–0.0300 0.0195–0.0227 6 00000001 10
0.0455–0.0521 0.0300–0.0343 0.0227–0.0260 7 00000001 11
0.0521–0.0586 0.0343–0.0386 0.0260–0.0292 8 00000010 00
∑
∑
∑
1.6675–1.6740 1.1000–1.1042 0.8325–0.8357 256 (1/4 scale) 01000000 00
∑
∑
∑
3.3300–3.3415 2.2000–2.2042 1.6650–1.6682 512 (1/2 scale) 10000000 00
∑
∑
∑
5.0025–5.0090 3.3000–3.3042 2.4975–2.5007 768 (3/4 scale) 11000000 00
∑
∑
∑
6.5983–6.6048 4.3527–4.3570 3.2942–3.2974 1013 11111101 01
6.6048–6.6113 4.3570–4.3613 3.2974–3.3007 1014 11111101 10
6.6113–6.6178 4.3613–4.3656 3.3007–3.3039 1015 11111101 11
6.6178–6.6244 4.3656–4.3699 3.3039–3.3072 1016 11111110 00
6.6244–6.6309 4.3699–4.3742 3.3072–3.3104 1017 11111110 01
6.6309–6.6374 4.3742–4.3785 3.3104–3.3137 1018 11111110 10
6.6374–6.4390 4.3785–4.3828 3.3137–3.3169 1019 11111110 11
6.6439–6.6504 4.3828–4.3871 3.3169–3.3202 1020 11111111 00
6.6504–6.6569 4.3871–4.3914 3.3202–3.3234 1021 11111111 01
6.6569–6.6634 4.3914–4.3957 3.3234–3.3267 1022 11111111 10
>6.6634 >4.3957 >3.3267 1023 11111111 11
*The V
CC
output codes listed assume that V
CC
is 3.3 V. If V
CC
input is reconfigured for 5 V operation (by setting Bit 7 of Configuration Register 1), then the V
CC
output codes are the same as for the 5 V
IN
column.
REV. A
ADT7460
–15–
ADDITIONAL ADC FUNCTIONS FOR VOLTAGE
MEASUREMENTS
A number of other functions are available on the ADT7460 to
offer the systems designer increased flexibility:
Turn-Off Averaging
For each voltage measurement read from a value register, 16
readings have actually been made internally and the results
averaged before being placed into the value register. There may
be an instance where you would like to speed up conversions.
Setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns aver-
aging off. This effectively gives a reading 16 times faster (711 ms),
but the reading may be noisier.
Bypass Voltage Input Attenuator
Setting Bit 5 of Configuration Register 2 (Reg. 0x73) removes
the attenuation circuitry from the 2.5 V
input. This allows the
user to directly connect external sensors or rescale the analog
voltage measurement inputs for other applications. The input
range of the ADC without the attenuators is 0 V to 2.25 V.
Single-Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7460 into single-channel ADC conversion mode. In this
mode, the ADT7460 can be made to read a single voltage chan-
nel only. If the internal ADT7460 clock is used, the selected
input will be read every 711 ms. The appropriate ADC channel
is selected by writing to Bits <7:5> of the TACH1 Minimum
High Byte Register (0x55).
Bits <7:5> Reg. 0x55 Channel Selected
000 2.5 V
010 V
CC
Configuration Register 2 (Reg. 0x73)
<4> = 1 Averaging Off
<5> = 1 Bypass Input Attenuators
<6> = 1 Single-Channel Convert Mode
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> Selects ADC Channel for Single-Channel Convert Mode
TEMPERATURE MEASUREMENT SYSTEM
Local Temperature Measurement
The ADT7460 contains an on-chip band gap temperature sensor
whose output is digitized by the on-chip 10-bit ADC. The 8-bit
MSB temperature data is stored in the local temperature Register
(Address 0x26). As both positive and negative temperatures can be
measured, the temperature data is stored in twos complement
format, as shown in Table III. Theoretically, the temperature sensor
and ADC can measure temperatures from –128C to +127C
with a resolution of 0.25C. However, this exceeds the operating
temperature range of the device, so local temperature measure-
ments outside this range are not possible.
Remote Temperature Measurement
The ADT7460 can measure the temperature of two remote diode
sensors or diode-connected transistors connected to Pins 12 and
13, or 10 and 11.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about –2 mV/C. Unfortunately, the absolute
value of V
BE
varies from device to device and individual calibra-
tion is required to null this out, so the technique is unsuitable
for mass production. The technique used in the ADT7460 is to
measure the change in V
BE
when the device is operated at two
different currents.
This is given by
DVKTqN
BE
=¥
()
ln
where:
K is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvins.
N is the ratio of the two currents.
Figure 14 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows the
external sensor as a substrate transistor, provided for temperature
monitoring on some microprocessors. It could equally well be a
discrete transistor, such as a 2N3904.
D+
D–
REMOTE
SENSING
TRANSISTOR
IN ⴛ I I
BIAS
V
DD
V
OUT+
TO ADC
V
OUT–
BIAS
DIODE LOW PASS
FILTER
fC
= 65kHz
THERMDA
THERMDC
CPU
Figure 14. Signal Conditioning for Remote Diode Temperature Sensors
REV. A–16–
ADT7460
If a discrete transistor is used, the collector will not be grounded,
and should be linked to the base. If a PNP transistor is used, the
base is connected to the D– input and the emitter to the D+ input.
If an NPN transistor is used, the emitter is connected to the
D– input and the base to the D+ input. Figures 15a and 15b
show how to connect the ADT7460 to an NPN or PNP transistor
for temperature measurement. To prevent ground noise from
interfering with the measurement, the more negative terminal of
the sensor is not referenced to ground but is biased above ground
by an internal diode at the D– input.
To measure DV
BE
, the sensor is switched between operating cur-
rents of I and N I. The resulting waveform is passed through
a 65 kHz low-pass filter to remove noise and to a chopper-
stabilized amplifier that performs the functions of amplification
and rectification of the waveform to produce a dc voltage
proportional to DV
BE
. This voltage is measured by the ADC to
give a temperature output in 10-bit, twos complement format. To
further reduce the effects of noise, digital filtering is performed
by averaging the results of 16 measurement cycles. A remote
temperature measurement takes nominally 25.5 ms. The results
of remote temperature measurements are stored in 10-bit, twos
complement format, as illustrated in Table III. The extra resolu-
tion for the temperature measurements is held in the Extended
Resolution Register 2 (Reg. 0x77). This gives temperature readings
with a resolution of 0.25C.
Table III. Temperature Data Format
Temperature Digital Output (10-Bit)*
–128C1000 0000 00
–125C1000 0011 00
–100C1001 1100 00
–75C1011 0101 00
–50C1100 1110 00
–25C1110 0111 00
–10C1111 0110 00
0C0000 0000 00
+10.25C0000 1010 01
+25.5C0001 1001 10
+50.75C0011 0010 11
+75C0100 1011 00
+100C0110 0100 00
+125C0111 1101 00
+127C0111 1111 00
*Bold denotes 2 LSBs of measurement in Extended
Resolution Register 2 (Reg. 0x77) with 0.25C resolution.
ADT7460
2N3904
NPN D+
D–
Figure 15a. Measuring Temperature Using an
NPN Transistor
2N3906
PNP
ADT7460
D+
D–
Figure 15b. Measuring Temperature Using a
PNP Transistor
Nulling Out Temperature Errors
As CPUs run faster, it is getting more difficult to avoid high fre-
quency clocks when routing the D+, D– traces around a system
board. Even when recommended layout guidelines are followed,
there may still be temperature errors attributed to noise being
coupled onto the D+/D– lines. High frequency noise generally has
the effect of giving temperature measurements that are too high
by a constant amount. The ADT7460 has temperature offset reg-
isters at Addresses 0x70, 0x72 for the Remote 1 and Remote 2
temperature channels. By doing a one-time calibration of the system,
one can determine the offset caused by system board noise and
null it out using the offset registers. The offset registers automati-
cally add a twos complement 8-bit reading to every temperature
measurement. The LSB adds 0.25∞C offset to the temperature
reading so the 8-bit register effectively allows temperature offsets
of up to 32C with a resolution of 0.25C. This ensures that
the readings in the temperature measurement registers are as
accurate as possible.
Temperature Offset Registers
Reg. 0x70 Remote 1 Temp Offset = 0x00 (0∞C Default)
Reg. 0x71 Local Temp Offset = 0x00 (0∞C Default)
Reg. 0x72 Remote 2 Temp Offset = 0x00 (0∞C Default)
REV. A
ADT7460
–17–
TEMPERATURE MEASUREMENT REGISTERS
Reg. 0x25 Remote 1 Temperature = 0x80 Default
Reg. 0x26 Local Temperature = 0x80 Default
Reg. 0x27 Remote 2 Temperature = 0x80 Default
Reg. 0x77 Extended Resolution 2 = 0x00 Default
<7:6> TDM2 = Remote 2 Temperature LSBs
<5:4> LTMP = Local Temperature LSBs
<3:2> TDM1 = Remote 1 Temperature LSBs
Temperature Measurement Limit Registers
Associated with each temperature measurement channel are
high and low limit registers. Exceeding the programmed high or
low limit causes the appropriate status bit to be set. Exceeding
either limit can also generate SMBALERT interrupts.
Reg. 0x4E Remote 1 Temp Low Limit = 0x81 Default
Reg. 0x4F Remote 1 Temp High Limit = 0x7F Default
Reg. 0x50 Local Temp Low Limit = 0x81 Default
Reg. 0x51 Local Temp High Limit = 0x7F Default
Reg. 0x52 Remote 2 Temp Low Limit = 0x81 Default
Reg. 0x53 Remote 2 Temp High Limit = 0x7F Default
Reading Temperature from the ADT7460
It is important to note that temperature can be read from the
ADT7460 as an 8-bit value (with 1∞C resolution), or as a 10-bit
value (with 0.25∞C resolution). If only 1∞C resolution is
required, the temperature readings can be read back at any time
and in no particular order.
If the 10-bit measurement is required, this involves a 2-register
read for each measurement. The Extended Resolution Register
(Reg. 0x77) should be read first. This causes all temperature
reading registers to be frozen until all temperature reading regis-
ters have been read from. This prevents an MSB reading from
being updated while its 2 LSBs are being read, and vice versa.
ADDITIONAL ADC FUNCTIONS FOR TEMPERATURE
MEASUREMENT
A number of other functions are available on the ADT7460 to
offer the systems designer increased flexibility:
Turn-Off Averaging
For each temperature measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value register. Sometimes
it may be necessary to take a very fast measurement, e.g., of
CPU temperature. Setting Bit 4 of Configuration Register 2
(Reg. 0x73) turns averaging off. This takes a reading every
15.5 ms. Each remote temperature measurement takes 4 ms and
the local temperature measurement takes 1.4 ms.
SINGLE-CHANNEL ADC CONVERSIONS
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7460 into single-channel ADC conversion mode. In this
mode, the ADT7460 can be made to read a single temperature
channel only. The appropriate ADC channel is selected by writing
to Bits <7:5> of TACH1 Minimum High Byte Register (0x55).
Bits <7:5> Reg. 0x55 Channel Selected
101 Remote 1 Temp
110 Local Temp
111 Remote 2 Temp
Configuration Register 2 (Reg. 0x73)
<4> = 1 Averaging Off
<6> = 1 Single-Channel Convert Mode
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> Selects ADC Channel for Single-Channel Convert Mode
Overtemperature Events
Overtemperature events on any of the temperature channels can
be detected and dealt with automatically in automatic fan speed
control mode. Registers 0x6A–0x6C are the THERM limits.
When a temperature exceeds its THERM limit, all fans will run
at 100% duty cycle. The fans will stay running at 100% until the
temperature drops below THERM – Hysteresis (this can be
disabled by setting the BOOST bit in Configuration Register 3,
Bit 2, Register 0x78). The hysteresis value for that THERM
limit is the value programmed into Registers 0x6D, 0x6E
(hysteresis registers). The default hysteresis value is 4∞C.
FANS
THERM LIMIT
TEMP
100%
HYSTERESIS = (ⴗC)
Figure 16. THERM Limit Operation
REV. A–18–
ADT7460
LIMITS, STATUS REGISTERS, AND INTERRUPTS
Limit Values
Associated with each measurement channel on the ADT7460
are high and low limits. These can form the basis of system
status monitoring: a status bit can be set for any out-of-limit
condition and detected by polling the device. Alternatively,
SMBALERT interrupts can be generated to flag a processor or
microcontroller of out-of-limit conditions.
8-Bit Limits
The following is a list of 8-bit limits on the ADT7460:
Voltage Limit Registers
Reg. 0x44 2.5 V Low Limit = 0x00 Default
Reg. 0x45 2.5 V High Limit = 0xFF Default
Reg. 0x48 V
CC
Low Limit = 0x00 Default
Reg. 0x49 V
CC
High Limit = 0xFF Default
Temperature Limit Registers
Reg. 0x4E Remote 1 Temp Low Limit = 0x81 Default
Reg. 0x4F Remote 1 Temp High Limit = 0x7F Default
Reg. 0x6A Remote 1 THERMTHERM
THERMTHERM
THERM Limit = 0x64 Default
Reg. 0x50 Local Temp Low Limit = 0x81 Default
Reg. 0x51 Local Temp High Limit = 0x7F Default
Reg. 0x6B Local THERMTHERM
THERMTHERM
THERM Limit = 0x64 Default
Reg. 0x52 Remote 2 Temp Low Limit = 0x81 Default
Reg. 0x53 Remote 2 Temp High Limit = 0x7F Default
Reg. 0x6C Remote 2 THERMTHERM
THERMTHERM
THERM Limit = 0x64 Default
THERM Limit Register
Reg. 0x7A THERM Timer Limit = 0x00 Default
16-Bit Limits
The fan TACH measurements are 16-bit results. The fan TACH
limits are also 16 bits, consisting of a high byte and low byte.
Since fans running under speed or stalled are normally the only
conditions of interest, only high limits exist for fan TACHs.
Since fan TACH period is actually being measured, exceeding
the limit indicates a slow or stalled fan.
Fan Limit Registers
Reg. 0x54 TACH1 Minimum Low Byte = 0xFF Default
Reg. 0x55 TACH1 Minimum High Byte = 0xFF Default
Reg. 0x56 TACH2 Minimum Low Byte = 0xFF Default
Reg. 0x57 TACH2 Minimum High Byte = 0xFF Default
Reg. 0x58 TACH3 Minimum Low Byte = 0xFF Default
Reg. 0x59 TACH3 Minimum High Byte = 0xFF Default
Reg. 0x5A TACH4 Minimum Low Byte = 0xFF Default
Reg. 0x5B TACH4 Minimum High Byte = 0xFF Default
Out-of-Limit Comparisons
Once all limits have been programmed, the ADT7460 can be
enabled for monitoring. The ADT7460 will measure all param-
eters in round-robin format and set the appropriate status bit for
out-of-limit conditions. Comparisons are done differently depending
on whether the measured value is being compared to a high or
low limit.
HIGH LIMIT: > COMPARISON PERFORMED
LOW LIMIT: < OR = COMPARISON PERFORMED
NO INT
LOW LIMIT
TEMP >
LOW LIMIT
Figure 17. Temperature > Low Limit: No
INT
REV. A
ADT7460
–19–
INT
LOW LIMIT
TEMP =
LOW LIMIT
Figure 18. Temperature = Low Limit:
INT
Occurs
NO INT
HIGH LIMIT
TEMP =
HIGH LIMIT
Figure 19. Temperature = High Limit: No
INT
HIGH LIMIT
INT
TEMP >
HIGH LIMIT
Figure 20. Temperature > High Limit:
INT
Occurs
Analog Monitoring Cycle Time
The analog monitoring cycle begins when a 1 is written to the
start bit (Bit 0) of Configuration Register 1 (Reg 0x40). The ADC
measures each analog input in turn and as each measurement
is
completed, the result is automatically stored in the
appropri-
ate value register. This round-robin monitoring cycle continues
unless disabled by writing a 0 to Bit 0 of Configuration Register 1.
As the ADC will normally be left to free-run in this manner, the
time taken to monitor all the analog inputs will normally not be
of interest, as the most recently measured value of any input can
be read out at any time.
For applications where the monitoring cycle time is important,
it can easily be calculated.
The total number of channels measured is
∑Two supply voltage inputs (2.5 V and V
CC
)
∑Local temperature
∑Two remote temperatures
As mentioned previously, the ADC performs round-robin conver-
sions and takes 11.38 ms for each voltage measurement, 12 ms
for a local temperature reading, and 25.5 ms for each remote
temperature reading.
The total monitoring cycle time for averaged voltage and tempera-
ture monitoring is, therefore, nominally
21138 12 225 5 85 76¥
()
++¥
()
=...ms
The round robin starts again 35 ms later. Therefore, all channels
are measured approximately every 120 ms.
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.
Status Registers
The results of limit comparisons are stored in Status Registers 1
and 2. The status register bit for each channel reflects the status
of the last measurement and limit comparison on that channel. If
a measurement is within limits, the corresponding status register
bit will be cleared to 0. If the measurement is out-of-limits, the
corresponding status register bit will be set to 1.
The state of the various measurement channels may be polled by
reading the status registers over the serial bus. In Bit 7 (OOL)
of Status Register 1 (Reg. 0x41), 1 means that an out-of-limit
event has been flagged in Status Register 2. This means that you
need only read Status Register 2 when this bit is set. Alternatively,
Pin 5 or Pin 14 can be configured as an SMBALERT output. This
will automatically notify the system supervisor of an out-of-limit
condition. Reading the status registers clears the appropriate
status bit as long as the error condition that caused the interrupt
has cleared. Status register bits are “sticky.” Whenever a status
bit gets set, indicating an out-of-limit condition, it will remain
set even if the event that caused it has gone away (until read).
The only way to clear the status bit is to read the status register
after the event has gone away. Interrupt status mask registers
(Reg. 0x74, 0x75) allow individual interrupt sources to be masked
from causing an SMBALERT. However, if one of these masked
interrupt sources goes out-of-limit, its associated status bit will
get set in the interrupt status registers.
REV. A–20–
ADT7460
OOL = 1 DENOTES A PARAMETER
MONITORED THROUGH STATUS REG 2
IS OUT-OF-LIMIT
Figure 21. Status Register 1
Status Register 1 (Reg. 0x41)
Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and
Status Register 2 should be read.
Bit 6 (R2T) = 1, Remote 2 temp high or low limit has been
exceeded.
Bit 5 (LT) = 1, Local temp high or low limit has been exceeded.
Bit 4 (R1T) = 1, Remote 1 temp high or low limit has been
exceeded.
Bit 3 = Unused
Bit 2 (V
CC
) = 1, V
CC
high or low limit has been exceeded.
Bit 1
= Unused
Bit 0 (2.5 V) = 1, 2.5 V high or low limit has been exceeded.
F4P = 1, FAN4 OR THERM
TIMER IS OUT-OF-LIMIT
Figure 22. Status Register 2
Status Register 2 (Reg. 0x42)
Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs.
Bit 6 (D1) = 1, indicates an open or short on D2+/D2– inputs.
Bit 5 (F4P) = 1, indicates Fan 4 has dropped below minimum
speed. Alternatively, indicates that THERM timer limit has
been exceeded if the THERM timer function is used.
Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below minimum
speed.
Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below minimum
speed.
Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below minimum
speed.
Bit 1 (OVT) = 1, indicates that a THERM overtemperature
limit has been exceeded.
Bit 0
= Unused
SMBALERT Interrupt Behavior
The ADT7460 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. It is
important to note how the SMBALERT output and status bits
behave when writing interrupt handler software.
“STICKY”
STATUS
BIT
HIGH LIMIT
TEMPERATURE
SMBALERT
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
Figure 23.
SMBALERT
and Status Bit Behavior
Figure 23 shows how the SMBALERT output and “sticky” status
bits behave. Once a limit is exceeded, the corresponding status
bit gets set to 1. The status bit remains set until the error condi-
tion subsides and the status register gets read. The status bits
are referred to as “sticky” since they remain set until read by
software. This ensures that an out-of-limit event cannot be
missed if software is polling the device periodically. Note that
the SMBALERT output remains low for the entire duration that
a reading is out-of-limit and until the status register has been
read. This has implications on how software handles the interrupt.
HANDLING SMBALERT INTERRUPTS
To prevent the system from being tied up servicing interrupts, it
is recommend to handle the SMBALERT interrupt as follows:
1. Detect the SMBALERT assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt source.
4. Mask the interrupt source by setting the appropriate mask bit
in the interrupt mask registers (Reg. 0x74, 0x75).
5. Take the appropriate action for a given interrupt source.
6. Exit the interrupt handler.
7. Periodically poll the status registers. If the interrupt status bit
has cleared, reset the corresponding interrupt mask bit to 0.
This will cause the SMBALERT output and status bits to
behave as shown in Figure 24.
“STICKY”
STATUS
BIT
HIGH LIMIT
TEMPERATURE
SMBALERT
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT
CLEARED
(SMBALERT REARMED)
Figure 24. How Masking the Interrupt Source Affects
SMBALERT
Output
REV. A
ADT7460
–21–
Masking Interrupt Sources
Interrupt Mask Registers 1 and 2 are located at Addresses 0x74
and 0x75. These allow individual interrupt sources to be masked
out to prevent SMBALERT interrupts. Note that masking an
interrupt source only prevents the SMBALERT output from
being asserted; the appropriate status bit will get set as normal.
Interrupt Mask Register 1 (Reg. 0x74)
Bit 7 (OOL) = 1, masks SMBALERT for any alert condition
flagged in Status Register 2.
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature.
Bit 5 (LT) = 1, masks SMBALERT for local temperature.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature.
Bit 3 = Unused
Bit 2 (V
CC
) = 1, masks SMBALERT for V
CC
channel.
Bit 1 = Unused
Bit 0 (2.5 V) = 1, masks SMBALERT for 2.5 V channel.
Interrupt Mask Register 2 (Reg. 0x75)
Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (FAN4) = 1, masks SMBALERT for Fan 4 failure. If the
TACH4 pin is being used as the THERM input, this bit masks
SMBALERT for a THERM event.
Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1, masks SMBALERT for overtemperature
(exceeding THERM limits).
Bit 0 = Unused
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by default. Pin 5
or Pin 14 can be reconfigured as an SMBALERT output to
signal out-of-limit conditions.
Configuring Pin 5 as SMBALERT Output
Register Bit Setting
Config Reg 4 (Reg. 0x7D) <0> AL2.5V = 1
Configuring Pin 14 as SMBALERT Output
Register Bit Setting
Config Reg 4 (Reg. 0x7D) <0> AL2.5V = 1
To Assign THERM Functionality to Pin 9
Pin 9 can be configured as the THERM pin on the ADT7460.
To configure Pin 9 as the THERM pin, set the THERM ENABLE
Bit (Bit 1) in Configuration Register 3 (Address = 0x78) = 1.
THERM as an Input
When configured as an input, the THERM pin allows the user to
time assertions on the pin. This can be useful for connecting to
the PROCHOT output of a CPU to gauge system performance.
See this data sheet for more information on timing THERM
assertions and generating SMBALERTs based on THERM.
The user can also set up the ADT7460 so when the THERM pin
is driven low externally the fans will run at 100%. The fans will
run at 100% for the duration of the THERM pin being pulled low.
This is done by setting the BOOST bit (Bit 2) in Configuration
Register 3 (Address = 0x78) to 1. This works only if the fan is
already running, for example, in manual mode when the
current duty cycle is above 0x00 or in automatic mode when
the temperature is above T
MIN
. If the temperature is below
T
MIN
or if the duty cycle in manual mode is set to 0x00, then
pulling the THERM low externally will have no effect. See
Figure 25 for more information.
TMIN
THERM
T
HERM ASSERTED LOW AS
AN INPUT. FANS DO NOT GO
TO 100% SINCE TEMPERATURE
IS BELOW T MIN.
THERM ASSERTED LOW AS AN
INPUT. FANS GO TO 100% SINCE
TEMPERATURE IS ABOVE T MIN AND
FANS ARE ALREADY RUNNING.
Figure 25. Asserting
THERM
Low as an Input in
Automatic Fan Speed Control Mode
THERM Timer
The ADT7460 has an internal timer to measure THERM
assertion time. For example, the THERM input may be connected
to
the PROCHOT output of a Pentium 4 CPU and measure
system performance. The THERM input may also be connected
to the output of a trip point temperature sensor.
The timer is started on the assertion of the ADT7460’s THERM
input and stopped on the negation of the pin. The timer counts
THERM times cumulatively, i.e., the timer resumes counting
on the next THERM assertion. The THERM timer will continue
to accumulate THERM assertion times until the timer is read
(it is cleared on read) or until it reaches full scale. If the counter
reaches full scale, it will stop at that reading until cleared.
The 8-bit THERM timer register (Reg. 0x79) is designed such
that Bit 0 will get set to 1 on the first THERM assertion. Once
the cumulative THERM assertion time has exceeded 45.52 ms,
Bit 1 of the THERM timer gets set and Bit 0 becomes the LSB
of the timer with a resolution of 22.76 ms.
Figure 26 illustrates how the THERM timer behaves as the
THERM input is asserted and negated. Bit 0 gets set on the first
THERM assertion detected. This bit remains set until such time
as the cumulative THERM assertions exceed 45.52 ms. At this
time, Bit 1 of the THERM timer gets set, and Bit 0 is cleared.
Bit 0 now reflects timer readings with a resolution of 22.76 ms.
REV. A–22–
ADT7460
THERM
TIMER
(REG. 0x79)
THERM
00000010
76543210
THERM ASSERTED
22.76ms
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM ASSERTED
45.52ms
00000101
76543210THERM ASSERTED 113.8ms
(91.04ms + 22.76ms)
THERM
TIMER
(REG. 0x79)
T
HERM TIMER
(REG. 0x79)
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
00000001
76543210
Figure 26. Understanding the
THERM
Timer
When using the
THERM
timer, be aware of the following:
∑After a
THERM
timer read (Reg. 0x79)
a) The contents of the timer get cleared on read.
b) The F4P bit (Bit 5) of Status Register 2 needs to be
cleared (assuming the
THERM
limit has been exceeded).
76543210
22.76ms
45.52ms
THERM
91.04ms
182.08ms
364.16ms
728.32ms
1.457s
2.914s
IN OUT
RESET
LATCH
STATUS REGISTER 2
CLEARED
ON READ
F4P BIT (BIT 5)
MASK REGISTER 2
(REG. 0x75)
1 = MASK
SMBALERT
F4P BIT (BIT 5)
THERM TIMER CLEARED ON READ
COMPARATOR
THERM
TIMER
(REG. 0x79)
7
6
543
2
1
0
22.76ms
45.52ms
91.04ms
182.08ms
364.16ms
728.32ms
1.457s
2.914s
THERM LIMIT
(REG. 0x7A)
Figure 27. Functional Diagram of ADT7460’s
THERM
Monitoring Circuitry
∑If the
THERM
timer is read during a
THERM
assertion
a) The contents of the timer are cleared.
b) Bit 0 of the
THERM
timer is set to 1 (since a
THERM
assertion is occurring).
c) The
THERM
timer increments from zero.
d) If the
THERM
limit (Reg. 0x7A) = 0x00, then the
F4P bit gets set.
Generating SMBALERT Interrupts from THERM Events
The ADT7460 can generate SMBALERTs when a program-
mable THERM limit has been exceeded. This allows the
systems designer to ignore brief, infrequent
THERM
assertions,
while capturing longer
THERM
events. Register 0x7A is the
THERM
limit register. This 8-bit register allows a limit from 0
seconds (first
THERM
assertion) to 5.825 seconds to be set
before an SMBALERT is generated. The
THERM
timer value is
compared with the contents of the
THERM
limit Register. If the
THERM
timer value exceeds the
THERM
limit value, then the
F4P bit (Bit 5) of Status Register 2 gets set, and an SMBALERT
is generated. Note that the F4P bit (Bit 5) of Mask Register 2
(Reg. 0x75) will mask out SMBALERTs if this bit is set to 1,
although the F4P bit of Interrupt Status Register 2 will still get set
if the
THERM
limit is exceeded.
Figure 27 is a Functional Block Diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM limit register (Reg. 0x7A) causes SMBALERT to
be generated on the first THERM assertion. A THERM limit
value of 0x01 generates an SMBALERT once cumulative THERM
assertions exceed 45.52 ms.
REV. A
ADT7460
–23–
Configuring the Desired THERM Behavior
1. Configure the THERM input.
Setting Bit 1 (
THERM ENABLE
) of Configuration Register
3 (Reg. 0x78)
enables the THERM monitoring function.
2. Select the desired fan behavior for THERM events.
Setting
Bit
2 (BOOST bit) of Configuration Register 3
(Reg. 0x78) causes all fans to run at 100% duty cycle whenever
THERM gets asserted. This allows fail-safe system cooling.
If this bit = 0, the fans will run at their current settings and
will not be affected by THERM events.
3. Select whether THERM events should generate
SMBALERT interrupts.
Bit 5 (F4P) of Mask Register 2 (Reg. 0x75), when set,
masks out SMBALERTs when the THERM limit value gets
exceeded. This bit should be cleared if SMBALERTs based
on THERM events are required.
4. Select a suitable THERM limit value.
This value determines whether an SMBALERT is generated
on the first THERM assertion, or only if a cumulative THERM
assertion time limit is exceeded. A value of 0x00 causes an
SMBALERT to be generated on the first THERM assertion.
5. Select a THERM monitoring time.
This is how often OS or BIOS level software checks the
THERM timer. For example, BIOS could read the THERM
timer once an hour to determine the cumulative THERM
assertion time. If, for example, the total THERM assertion
time is <22.76 ms in Hour 1, >182.08 ms in Hour 2, and
>5.825 s in Hour 3, this can indicate that system perfor-
mance is degrading significantly since THERM is asserting
more frequently on an hourly basis.
Alternatively, OS or BIOS level software can time-stamp when
the system is powered on. If an SMBALERT is generated
due to the THERM limit being exceeded, another time-stamp
can be taken. The difference in time can be calculated for a
fixed THERM limit time. For example, if it takes one week
for a THERM limit of 2.914 s to be exceeded and the next
time it takes only one hour, then this is an indication of a
serious degradation in system performance.
Configuring the ADT7460 THERM Pin as an Output
In addition to the ADT7460 being able to monitor THERM as
an input, the ADT7460 can optionally drive THERM low as an
output. The user can preprogram system critical thermal limits.
If the temperature exceeds a thermal limit by 0.25∞C, THERM
will assert low. If the temperature is still above the thermal limit
on the next monitoring cycle, THERM will stay low. THERM
will remain asserted low until the temperature is equal to or
below the thermal limit. Since the temperature for that channel
is only measured every monitoring cycle, once THERM asserts
it is guaranteed to remain low for at least one monitoring cycle.
The THERM pin can be configured to assert low if the Remote 1,
local, or Remote 2 temperature THERM limits get exceeded by
0.25∞C. The THERM limit registers are at Locations 0x6A,
0x6B, and 0x6C, respectively. Setting Bit 3 of registers 0x5F,
0x60, and 0x61 enables the THERM output feature for the
Remote 1, local, and Remote 2 temperature channels, respectively.
Figure 28 shows how the THERM pin asserts low as an output
in the event of a critical overtemperature.
THERM LIMIT
+0.25ⴗC
THERM LIMIT
TEMP
THERM
ADT7460
MONITORING
CYCLE
Figure 28. Asserting
THERM
as an Output, Based on
Tripping
THERM
Limits
FAN DRIVE USING PWM CONTROL
The ADT7460 uses pulsewidth modulation (PWM) to control
fan speed. This relies on varying the duty cycle (or on/off ratio)
of a square wave applied to the fan to vary the fan speed. The
external circuitry required to drive a fan using PWM control is
extremely simple. A single NMOSFET is the only drive device
required. The specifications of the MOSFET depend on the
maximum current required by the fan being driven. Typical
notebook fans draw a nominal 170 mA, and so SOT devices can
be used where board space is a concern. In desktops, fans can
typically draw 250 mA–300 mA each. If you drive several fans
in parallel from a single PWM output or drive larger server fans,
the MOSFET will need to handle the higher current requirements.
The only other stipulation is that the MOSFET should have a
gate voltage drive, V
GS
< 3.3 V for direct interfacing to the
PWM_OUT pin. V
GS
can be greater than 3.3 V as long as the
pull-up on the gate is tied to 5 V. The MOSFET should also
have a low on resistance to ensure that there is not significant
voltage drop across the FET. This would reduce the voltage
applied across the fan and therefore the maximum operating
speed of the fan.
Figure 29 shows how a 3-wire fan may be driven using PWM
control.
ADT7460
TACH/AIN
PWM
4.7k⍀
10k⍀
10k⍀
10k⍀
3.3V
12V12V
12V
FAN
Q1
NDT3055L
TACH
1N4148
Figure 29. Driving a 3-Wire Fan Using an
N-Channel MOSFET
Figure 29 uses a 10 kW pull-up resistor for the TACH signal. This
assumes that the TACH signal is open-collector from the fan. In
all cases, the TACH signal from the fan must be kept below 5 V
maximum to prevent damaging the ADT7460. If in doubt as to
whether the fan used has an open-collector or totem pole
TACH output, use one of the input signal conditioning circuits
shown in the Fan Speed Measurement section of the data sheet.
REV. A–24–
ADT7460
ADT7460
PWM3
2.2k⍀
1k⍀
3.3V
Q1
MMBT3904
3.3V
10⍀
TACH3
Q2
MMBT2222
10⍀
TACH4
12V
Q3
MMBT2222
1N4148
Figure 31. Interfacing Two Fans in Parallel to the PWM3 Output Using Low Cost NPN Transistors
ADT7460
TACH4
10k⍀
TYPICAL
3.3V
TACH
TACH3
10k⍀
TYPICAL
3.3V
PWM3
10k⍀
TYPICAL
3.3V
+V
Q1
NDT3055L
5V OR
12V FAN
TACH
5V OR 12V
FAN
+V
1N4148
Figure 32. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N-Channel MOSFET
Figure 30 shows a fan drive circuit using an NPN transistor such
as a general-purpose MMBT2222. While these devices are inexpen-
sive, they tend to have much lower current handling capabilities
and higher on-resistance than MOSFETs. When choosing a
transistor, care should be taken to ensure that it meets the fan’s
current requirements.
Ensure that the base resistor is chosen such that the transistor is
saturated when the fan is powered on.
ADT7460
TACH/AIN
PWM
4.7k⍀
10k⍀
10k⍀
470⍀
3.3V
12V12V
12V
FAN
Q1
MMBT2222
1N4148
TACH
Figure 30. Driving a 3-Wire Fan Using an NPN Transistor
Driving Two Fans from PWM3
Note that the ADT7460 has four TACH inputs available for fan
speed measurement, but only three PWM drive outputs. If a fourth
fan is being used in the system, it should be driven from the PWM3
output in parallel with the third fan. Figure 31 shows how to drive
two fans in parallel using low cost NPN transistors. Figure 32
is the equivalent circuit using the NDT3055L MOSFET. Note
that since the MOSFET can handle up to 3.5 A, it is simply a
matter of connecting another fan directly in parallel with the first.
Care should be taken in designing drive circuits with transistors
and FETs to ensure that the PWM pins are not required to
source current and that they sink less than the 8 mA maximum
current specified on the data sheet.
Driving Up to Three Fans from PWM2
TACH measurements for fans are synchronized to particular
PWM channels, e.g., TACH1 is synchronized to PWM1. TACH3
and TACH4 are both synchronized to PWM3, so PWM3 can
drive two fans. Alternatively, PWM2 can be programmed to
synchronize TACH2, TACH3, and TACH4 to the PWM2
output. This allows PWM2 to drive two or three fans. In this
case, the drive circuitry looks the same as shown in Figures 30, 31,
and 32. The SYNC bit in Register 0x62 enables this function.
REV. A
ADT7460
–25–
ENHANCE ACOUSTICS REGISTER 1 (REG. 0x62)
<4> SYNC = 1, Synchronizes TACH2, TACH3, and TACH4
to PWM2.
Driving 2-Wire Fans
Figure 33 shows how a 2-wire fan may be connected to the
ADT7460. This circuit allows the speed of a 2-wire fan to be
measured, even though the fan has no dedicated TACH signal.
A series resistor, R
SENSE
, in the fan circuit converts the fan commu-
tation pulses into a voltage. This is ac-coupled into the ADT7460
through the 0.01 mF capacitor. On-chip signal conditioning allows
accurate monitoring of fan speed. The value of R
SENSE
chosen
depends upon the programmed input threshold and the current
drawn by the fan. For fans drawing approximately 200 mA, a 2 W
R
SENSE
value is suitable when the threshold is programmed as
40 mV. For fans that draw more current, such as larger desktop
or server fans, R
SENSE
may be reduced for the same programmed
threshold. The smaller the threshold programmed the better, since
more voltage will be developed across the fan and the fan will spin
faster. Figure 34 shows a typical plot of the sensing waveform at a
TACH/AIN pin. The most important thing is that the voltage spikes
(either negative going or positive going) are more than 40 mV
in amplitude. This allows fan speed to be reliably determined.
ADT7460
TACH/AIN
PWM
10k⍀
TYPICAL
3.3V
+V
Q1
NDT3055L
5V OR
12V FAN
RSENSE
2⍀
TYPICAL
0.01F
1N4148
Figure 33. Driving a 2-Wire Fan
Figure 34. Fan Speed Sensing Waveform at
TACH/AIN Pin
LAYING OUT 2-WIRE AND 3-WIRE FANS
Figure 35 shows how to lay out a common circuit arrangement for
2-wire and 3-wire fans. Some components will not be populated,
depending on whether a 2-wire or 3-wire fan is being used.
3.3V OR 5V
TACH/AIN
PWM
12V OR 5V
Q1
MMBT2222
R4
R5
R3
C1
R2
R1
FOR 3-WIRE FANS:
POPULATE R1, R2, R3
R4 = 0⍀
C1 = UNPOPULATED
FOR 2-WIRE FANS:
POPULATE R4, C1
R1, R2, R3 UNPOPULATED
1N4148
Figure 35. Planning for 2-Wire or 3-Wire Fans on a PCB
TACH Inputs
Pins 4, 6, 7, and 9 are open-drain TACH inputs intended for
fan speed measurement.
Signal conditioning in the ADT7460 accommodates the slow rise
and fall times typical of fan tachometer outputs. The maximum
input signal range is 0 V to 5 V, even where V
CC
is less than 5 V.
In the event that these inputs are supplied from fan outputs that
exceed 0 V to 5 V, either resistive attenuation of the fan signal
or diode clamping must be included to keep inputs within an
acceptable range.
Figures 36a to 36d show circuits for most common fan TACH
outputs.
If the fan TACH output has a resistive pull-up to V
CC
, it can be
connected directly to the fan input, as shown in Figure 36a.
12V
ADT7460
FAN SPEED
COUNTER
TACH
TACH
OUTPUT
PULL-UP
4.7k⍀
TYP
V
CC
Figure 36a. Fan with TACH Pull-Up to V
CC
If the fan output has a resistive pull-up to 12 V (or other voltage
greater than 5 V), the fan output can be clamped with a Zener
diode, as shown in Figure 36b. The Zener diode voltage should
be chosen so that it is greater than V
IH
of the TACH input but
less than 5 V, allowing for the voltage tolerance of the Zener.
Avalue of between 3 V and 5 V is suitable.
REV. A–26–
ADT7460
measured by gating an on-chip 90 kHz oscillator
into the input of
a 16-bit counter for N periods of the fan TACH
output (Figure 37),
so the accumulated count is actually pro
portional to the fan
tachometer period and inversely
proportional to the fan speed.
1
2
3
4
CLOCK
PWM
TACH
Figure 37. Fan Speed Measurement
N, the number of pulses counted, is determined by the settings
of Register 0x7B (fan pulses per revolution register). This
register contains two bits for each fan, allowing one, two
(default), three, or four TACH pulses to be counted.
Fan Speed Measurement Registers
The fan tachometer readings are 16-bit values consisting of a
2-byte read from the ADT7460.
Reg. 0x28 TACH1 Low Byte = 0x00 Default
Reg. 0x29 TACH1 High Byte = 0x00 Default
Reg. 0x2A TACH2 Low Byte = 0x00 Default
Reg. 0x2B TACH2 High Byte = 0x00 Default
Reg. 0x2C TACH3 Low Byte = 0x00 Default
Reg. 0x2D TACH3 High Byte = 0x00 Default
Reg. 0x2E TACH4 Low Byte = 0x00 Default
Reg. 0x2F TACH4 High Byte = 0x00 Default
Reading Fan Speed from the ADT7460
If fan speeds are being measured, this involves a 2-register read
for each measurement. The low byte should be read first. This
causes the high byte to be frozen until both high and low byte
registers have been read from. This prevents erroneous TACH
readings.
The fan tachometer reading registers report back the number of
11.11 ms period clocks (90 kHz oscillator) gated to the fan
speed counter, from the rising edge of the first fan TACH pulse
to the rising edge of the third fan TACH pulse (assuming two
pulses per revolution are being counted). Since the device is
essentially measuring the fan TACH period, the higher the
count value the slower the fan is actually running. A 16-bit fan
tachometer reading of 0xFFFF indicates either that the fan has
stalled or is running very slowly (<100 RPM).
HIGH LIMIT: > COMPARISON PERFORMED
Since the actual fan TACH period is being measured, exceeding
a fan TACH limit by 1 will set the appropriate status bit and
can be used to generate an SMBALERT.
ADT7460
FAN SPEED
COUNTER
TACH
TACH
OUTPUT
V
CC
ZD1*
*CHOOSE ZD1 VOLTAGE APPROX 0.8 ⴛ V
CC
12V
PULL-UP
4.7k⍀
TYP
Figure 36b. Fan with TACH Pull-Up to Voltage
> 5 V, e.g., 12 V, Clamped with Zener Diode
If the fan has a strong pull-up (less than 1 kW) to 12 V or a
totem-pole output, then a series resistor can be added to limit the
Zener current, as shown in Figure 36c. Alternatively, a resistive
attenuator may be used, as shown in Figure 36d.
R1 and R2 should be chosen such that:
22125 VV<¥ ++<VRRRR
PULLUP PULLUP
/( )
The fan inputs have an input resistance of nominally 160 kW to
ground, so this should be taken into account when calculating
resistor values.
With a pull-up voltage of 12 V and pull-up resistor less than 1 kW,
suitable values for R1 and R2 would be 100 kW and 47 kW. This
will give a high input voltage of 3.83 V.
5V OR 12V
ADT7460
FAN SPEED
COUNTER
TACH
TACH
OUTPUT
PULL-UP TYP
<1k⍀
OR
TOTEM POLE
VCC
FAN
ZD1
ZENER
*
*CHOOSE ZD1 VOLTAGE APPROX 0.8 ⴛ VCC
R1
10k⍀
Figure 36c. Fan with Strong TACH Pull-Up to > V
CC
or
Totem-Pole Output, Clamped with Zener and Resistor
12V
ADT7460
FAN SPEED
COUNTER
TACH
TACH
OUTPUT
<1k⍀
V
CC
R2*
*SEE TEXT
R1*
Figure 36d. Fan with Strong TACH Pull-Up to > V
CC
or Totem-Pole Output, Attenuated with R1/R2
Fan Speed Measurement
The fan counter does not count the fan TACH output pulses
directly because the fan speed may be less than 1000 RPM and
it would take several seconds to accumulate a reasonably large
and accurate count. Instead, the period of the fan revolution is
REV. A
ADT7460
–27–
Fan TACH Limit Registers
The fan TACH limit registers are 16-bit values consisting of
two bytes.
Reg. 0x54 TACH1 Minimum Low Byte = 0xFF Default
Reg. 0x55 TACH1 Minimum High Byte = 0xFF Default
Reg. 0x56 TACH2 Minimum Low Byte = 0xFF Default
Reg. 0x57 TACH2 Minimum High Byte = 0xFF Default
Reg. 0x58 TACH3 Minimum Low Byte = 0xFF Default
Reg. 0x59 TACH3 Minimum High Byte = 0xFF Default
Reg. 0x5A TACH4 Minimum Low Byte = 0xFF Default
Reg. 0x5B TACH4 Minimum High Byte = 0xFF Default
Fan Speed Measurement Rate
The fan TACH readings are normally updated once every second.
The FAST bit (Bit 3) of Configuration Register 3 (Reg. 0x78),
when set, updates the fan TACH readings every 250 ms.
If any of the fans are not being driven by a PWM channel but
are powered directly from 5 V or 12 V, its associated dc bit in
Configuration Register 3 should be set. This allows TACH
readings to be taken on a continuous basis for fans connected
directly to a dc source.
Calculating Fan Speed
Assuming a fan with a two pulses/revolution (and two pulses/
revolution being measured), fan speed is calculated by
Fan Speed (RPM) = (90,000
ⴛ
60)/Fan TACH Reading
where:
Fan TACH Reading = 16-Bit Fan Tachometer Reading
Example:
TACH1 High Byte (Reg. 0x29) = 0x17
TACH1 Low Byte (Reg. 0x28) = 0xFF
What is Fan 1 speed in RPM?
Fan 1 TACH Reading = 0x17FF = 6143 Decimal
RPM = (f ⫻ 60)/Fan 1 TACH Reading
RPM = (90000 ⫻ 60)/6143
Fan Speed = 879 RPM
Fan Pulses per Revolution
Different fan models can output either 1, 2, 3, or 4 TACH pulses
per revolution. Once the number of fan TACH pulses has been
determined, it can be programmed into the fan pulses per revolu-
tion register (Reg. 0x7B) for each fan. Alternatively, this register
can be used to determine the number or pulses/revolution output
by a given fan. By plotting fan speed measurements at 100% speed
with different pulses/revolution setting, the smoothest graph with
the lowest ripple determines the correct pulses/revolution value.
Fan Pulses per Revolution Register
<1:0> FAN1 Default = 2 Pulses per Revolution
<3:2> FAN2 Default = 2 Pulses per Revolution
<5:4> FAN3 Default = 2 Pulses per Revolution
<7:6> FAN4 Default = 2 Pulses per Revolution
00 = 1 Pulse per Revolution
01 = 2 Pulses per Revolution
10 = 3 Pulses per Revolution
11 = 4 Pulses per Revolution
2-Wire Fan Speed Measurements
The ADT7460 is capable of measuring the speed of 2-wire fans,
i.e., fans without TACH outputs. To do this, the fan must be
interfaced as shown in the Fan Drive Circuitry section of the
data sheet. In this case, the TACH inputs need to be repro-
grammed as analog inputs, AIN.
CONFIGURATION REGISTER 2 (REG. 0x73)
Bit 3 (AIN4) = 1, Pin 9 is reconfigured to measure the speed of
a 2-wire fan using an external sensing resistor and coupling
capacitor.
Bit 2 (AIN3) = 1, Pin 4 is reconfigured to measure the speed of
a 2-wire fan using an external sensing resistor and coupling
capacitor.
Bit 1 (AIN2) = 1, Pin 7 is reconfigured to measure the speed of
a 2-wire fan using an external sensing resistor and coupling
capacitor.
Bit 0 (AIN1) = 1, Pin 6 is reconfigured to measure the speed of
a 2-wire fan using an external sensing resistor and coupling
capacitor.
AIN Switching Threshold
Having configured the TACH inputs as AIN inputs for 2-wire
measurements, the user can select the sensing threshold for
the AIN signal.
CONFIGURATION REGISTER 4 (REG. 0x7D)
<3:2> AINL These two bits define the input threshold for
2-wire fan speed measurements.
00 = ⴞ20 mV
01 = ⴞ40 mV
10 = ⴞ80 mV
11 = ⴞ130 mV
Fan Spin-Up
The ADT7460 has a unique fan spin-up function. It will spin
the fan at 100% PWM duty cycle until two TACH pulses are
detected on the TACH input. Once two pulses have been
detected, the PWM duty cycle will go to the expected running
value, e.g., 33%. The advantage of this is that fans have dif-
ferent spin-up characteristics and will take different times to
overcome inertia. The ADT7460 runs the fans just fast enough
to overcome inertia and will be quieter on spin-up than fans
programmed to spin-up for a given spin-up time.
Fan Start-Up Timeout
To prevent false interrupts being generated as a fan spins up
(since it is below running speed), the ADT7460 includes a fan
start-up timeout function. This is the time limit allowed for two
TACH pulses to be detected on spin-up. For example, if 2 seconds
fan start-up timeout is chosen and no TACH pulses occur within
2 seconds of the start of spin-up, a fan fault is detected and flagged
in the interrupt status registers.
REV. A–28–
ADT7460
PWM1 CONFIGURATION (REG. 0x5C)
<2:0> SPIN These bits control the start-up timeout for PWM1.
000 = No Start-Up Timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
PWM2 CONFIGURATION (REG. 0x5D)
<2:0> SPIN These bits control the start-up timeout for PWM2.
000 = No Start-Up Timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
PWM3 CONFIGURATION (REG. 0x5E)
<2:0> SPIN These bits control the start-up timeout for PWM3.
000 = No Start-Up Timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
Disabling Fan Start-Up Timeout
Although fan start-up makes fan spin-ups much quieter than
fixed-time spin-ups, the option exists to use fixed spin-up times.
Bit 5 (FSPDIS) = 1 in Configuration Register 1 (Reg. 0x40)
disables the spin-up for two TACH pulses. Instead, the fan will
spin up for the fixed time as selected in Registers 0x5C–0x5E.
PWM Logic State
The PWM outputs can be programmed high for 100% duty cycle
(noninverted) or low for 100% duty cycle (inverted).
PWM1 Configuration (Reg. 0x5C)
<4> INV 0 = Logic High for 100% PWM Duty Cycle
1 = Logic Low for 100% PWM Duty Cycle
PWM2 Configuration (Reg. 0x5D)
<4> INV 0 = Logic High for 100% PWM Duty Cycle
1 = Logic Low for 100% PWM Duty Cycle
PWM3 Configuration (Reg. 0x5E)
<4> INV 0 = Logic High for 100% PWM Duty Cycle
1 = Logic Low for 100% PWM Duty Cycle
PWM Drive Frequency
The PWM drive frequency can be adjusted for the applica-
tion. Registers 0x5F–0x61 configure the PWM frequency for
PWM1–PWM3, respectively.
PWM1 FREQUENCY REGISTERS (REG. 0x5F–0x61)
<2:0> FREQ 000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (Default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
Fan Speed Control
The ADT7460 can control fan speed using two different modes.
The first is automatic fan speed control mode. In this mode, fan
speed is automatically varied with temperature and without CPU
intervention, once initial parameters are set up. The advantage of
this is, in the case of the system hanging, the user is guaranteed
that the system is protected from overheating. The automatic fan
speed control incorporates a feature called dynamic T
MIN
calibra-
tion. This feature reduces the design effort required to program
the automatic fan speed control loop. For more information and
how to program the automatic fan speed control loop and Dynamic
T
MIN
calibration, see the AN-613 Programming the automatic fan
speed control loop application note (http://www.analog.com/
Uploaded Files/Application_Notes/331085006AN613_0.pdf).
The second fan speed control method is manual fan speed control,
which is described in the next paragraph.
Manual Fan Speed Control
The ADT7460 allows the duty cycle of any PWM output to be
manually adjusted. This can be useful if you wish to change fan
speed in software or want to adjust PWM duty cycle output
for test purposes. Bits <7:5> of Registers 0x5C–0x5E (PWM
configuration) control the behavior of each PWM output.
PWM CONFIGURATION (REG. 0x5C–0x5E)
<7:5> BHVR 111 = Manual Mode
Once under manual control, each PWM output may be manu-
ally updated by writing to registers 0x30–0x32 (PWMx current
duty cycle registers).
Programming the PWM
Current Duty Cycle Registers
The PWM
current duty cycle registers are 8-bit registers that
allow the PWM duty cycle for each output to be set anywhere
from 0% (0x00) to 100% (0xFF) in steps of 0.39% (256 steps).
The value to be programmed into the PWM
MIN
register is
given by
Value decimal PWM
MIN
()
=039.
Example 1: For a PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 Decimal
Value = 128 Decimal or 0x80.
Example 2: For a PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85 Decimal
Value = 85 Decimal or 0x54.
REV. A
ADT7460
–29–
PWM DUTY CYCLE REGISTERS
Reg. 0x30 PWM1 Duty Cycle = 0xFF (100% Default)
Reg. 0x31 PWM2 Duty Cycle = 0xFF (100% Default)
Reg. 0x32 PWM3 Duty Cycle = 0xFF (100% Default)
By reading the PWMx current duty cycle registers, users can
keep track of the current duty cycle on each PWM output, even
when the fans are running in automatic fan speed control mode
or acoustic enhancement mode.
VARY PWM DUTY
CYCLE WITH 8-BIT
RESOLUTION
Figure 38. Control PWM Duty Cycle Manually
with a Resolution of 0.39%
OPERATING FROM 3.3 V STANDBY
The ADT7460 has been specifically designed to operate from a
3.3 V STBY supply. In computers that support S3 and S5
states, the core voltage of the processor will be lowered in these
states. If using the dynamic T
MIN
mode, lowering the core volt-
age of the processor would change the CPU temperature and
change
the dynamics of the system under dynamic T
MIN
con-
trol.
Likewise, when monitoring THERM, the THERM
timer
should be disabled during these states.
XOR TREE TEST MODE
The ADT7460 includes an XOR tree test mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying stimulus to the pins included in the XOR tree, it is
possible to detect opens or shorts on the system board. Figure 39
shows the signals that are exercised in the XOR tree test mode.
PWM1/XTO
PWM3
PWM2
TACH4
TACH3
TACH2
TACH1
Figure 39. XOR Tree Test
The XOR tree test is invoked by setting Bit 0 (XEN) of the XOR
tree test enable register (Reg. 0x6F).
POWER-ON DEFAULT
The ADT7460 does not monitor temperature and fan speed by
default on power-up. Monitoring of temperature and fan speed is
enabled by setting the start bit in configuration Register 1 (Bit 0,
Address 0x40) to 1. The fans will run at full speed on power-up.
This is because the BHVR bits (Bits <7:5>) in the PWMx configu-
ration registers are set to 100 (fans run full speed) by default.
REV. A–30–
ADT7460
Table IV. ADT7460 Registers
Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable?
0x20 R 2.5 V Reading 9 8 7 6 5 4 3 2 0x00
0x22 R V
CC
Reading 9 8 7 6 5 4 3 2 0x00
0x25 R Remote 1 Temperature 9 8 7 6 5 4 3 2 0x80
0x26 R Local Temperature 9 8 7 6 5 4 3 2 0x80
0x27 R Remote 2 Temperature 9 8 7 6 5 4 3 2 0x80
0x28 R TACH1 Low Byte 7 6 5 4 3 2 1 0 0x00
0x29 R TACH1 High Byte 15 14 13 12 11 10 9 8 0x00
0x2A R TACH2 Low Byte 7 6 5 4 3 2 1 0 0x00
0x2B R TACH2 High Byte 15 14 13 12 11 10 9 8 0x00
0x2C R TACH3 Low Byte 7 6 5 4 3 2 1 0 0x00
0x2D R TACH3 High Byte 15 14 13 12 11 10 9 8 0x00
0x2E R TACH4 Low Byte 7 6 5 4 3 2 1 0 0x00
0x2F R TACH4 High Byte 15 14 13 12 11 10 9 8 0x00
0x30 R/W PWM1 Current Duty Cycle 7 6 5 4 3 2 1 0 0xFF
0x31 R/W PWM2 Current Duty Cycle 7 6 5 4 3 2 1 0 0xFF
0x32 R/W PWM3 Current Duty Cycle 7 6 5 4 3 2 1 0 0xFF
0x33 R/W Remote 1 Operating Point 7 6 5 4 3 2 1 0 0x64 YES
0x34 R/W Local Temp Operating Point 7 6 5 4 3 2 1 0 0x64 YES
0x35 R/W Remote 2 Operating Point 7 6 5 4 3 2 1 0 0x64 YES
0x36 R/W Dynamic T
MIN
Control Reg. 1 R2T LT R1T
PHTR2 PHTL
PHTR1
V
CC
RES
CYR2 0x00 YES
0x37 R/W Dynamic T
MIN
Control Reg. 2 CYR2 CYR2 CYL CYL CYL CYR1 CYR1 CYR1 0x00 YES
0x3D R Device ID Register 7 6 5 4 3 2 1 0 0x27
0x3E R Company ID Number 7 6 5 4 3 2 1 0 0x41
0x3F R Revision Number VER VER VER VER STP STP STP STP 0x62
0x40 R/W Configuration Register 1 V
CC
TODIS FSPDIS RES FSPD RDY LOCK STRT 0x00 YES
0x41 R Interrupt Status Register 1 OOL R2T LT R1T RES V
CC
RES 2.5V 0x00
0x42 R Interrupt Status Register 2 D2 D1 5 FAN3 FAN2 FAN1 OVT RES 0x00
0x44 R/W 2.5 V Low Limit 7 6 5 4 3 2 1 0 0x00
0x45 R/W 2.5 V High Limit 7 6 5 4 3 2 1 0 0xFF
0x48 R/W V
CC
Low Limit 7 6 5 4 3 2 1 0 0x00
0x49 R/W V
CC
High Limit 7 6 5 4 3 2 1 0 0xFF
0x4E R/W Remote 1 Temp Low Limit 7 6 5 4 3 2 1 0 0x81
0x4F R/W Remote 1 Temp High Limit 7 6 5 4 3 2 1 0 0x7F
0x50 R/W Local Temp Low Limit 7 6 5 4 3 2 1 0 0x81
0x51 R/W Local Temp High Limit 7 6 5 4 3 2 1 0 0x7F
0x52 R/W Remote 2 Temp Low Limit 7 6 5 4 3 2 1 0 0x81
0x53 R/W Remote 2 Temp High Limit 7 6 5 4 3 2 1 0 0x7F
0x54 R/W TACH1 Minimum Low Byte 7 6 5 4 3 2 1 0 0xFF
0x55 R/W TACH1 Minimum High Byte 15 14 13 12 11 10 9 8 0xFF
0x56 R/W TACH2 Minimum Low Byte 7 6 5 4 3 2 1 0 0xFF
0x57 R/W TACH2 Minimum High Byte 15 14 13 12 11 10 9 8 0xFF
0x58 R/W TACH3 Minimum Low Byte 7 6 5 4 3 2 1 0 0xFF
0x59 R/W TACH3 Minimum High Byte 15 14 13 12 11 10 9 8 0xFF
0x5A R/W TACH4 Minimum Low Byte 7 6 5 4 3 2 1 0 0xFF
0x5B R/W TACH4 Minimum High Byte 15 14 13 12 11 10 9 8 0xFF
REV. A
ADT7460
–31–
Table IV. ADT7460 Registers (continued)
Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable?
0x5C R/W PWM1 Configuration Register BHVR BHVR BHVR INV SLOW SPIN SPIN SPIN 0x62 YES
0x5D R/W PWM2 Configuration Register BHVR BHVR BHVR INV SLOW SPIN SPIN SPIN 0x62 YES
0x5E R/W PWM3 Configuration Register BHVR BHVR BHVR INV SLOW SPIN SPIN SPIN 0x62 YES
0x5F R/W Remote 1 T
RANGE
/PWM 1 Freq. RANGE RANGE RANGE RANGE THRM FREQ FREQ FREQ 0xC4 YES
0x60 R/W Local T
RANGE
/PWM 2 Freq RANGE RANGE RANGE RANGE THRM FREQ FREQ FREQ 0xC4 YES
0x61 R/W Remote 2 T
RANGE
/PWM 3 Freq. RANGE RANGE RANGE RANGE THRM FREQ FREQ FREQ 0xC4 YES
0x62 R/W Enhance Acoustics Reg. 1 MIN3 MIN2 MIN1 SYNC EN1 ACOU ACOU ACOU 0x00 YES
0x63 R/W Enhance Acoustics Reg. 2 EN2 ACOU2 ACOU2 ACOU2 EN3 ACOU3 ACOU3 ACOU3 0x00 YES
0x64 R/W PWM1 Min Duty Cycle 7 6 5 4 3 2 1 0 0x80 YES
0x65 R/W PWM2 Min Duty Cycle 7 6 5 4 3 2 1 0 0x80 YES
0x66 R/W PWM3 Min Duty Cycle 7 6 5 4 3 2 1 0 0x80 YES
0x67 R/W Remote 1 Temp T
MIN
765 432 100x5A YES
0x68 R/W Local Temp T
MIN
765 432 100x5A YES
0x69 R/W Remote 2 Temp T
MIN
765 432 100x5A YES
0x6A R/W Remote 1 THERM Limit 7 6 5 4 3 2 1 0 0x64 YES
0x6B R/W Local THERM Limit 7 6 5 4 3 2 1 0 0x64 YES
0x6C R/W Remote 2 THERM Limit 7 6 5 4 3 2 1 0 0x64 YES
0x6D R/W Remote 1 Local Hysteresis HYSR1 HYSR1 HYSR1 HYSR1 HYSL HYSL HYSL HYSL 0x44 YES
0x6E R/W Remote 2 Temp Hysteresis HYSR2 HYSR2 HYSR2 HYSR2 RES RES RES RES 0x40 YES
0x6F R/W XOR Tree Test Enable RES RES RES RES RES RES RES XEN 0x00 YES
0x70 R/W Remote 1 Temperature Offset 7 6 5 4 3 2 1 0 0x00 YES
0x71 R/W Local Temperature Offset 7 6 5 4 3 2 1 0 0x00 YES
0x72 R/W Remote 2 Temperature Offset 7 6 5 4 3 2 1 0 0x00 YES
0x73 R/W Configuration Register 2 SHDN CONV ATTN AVG AIN4 AIN3 AIN2 AIN1 0x00 YES
0x74 R/W Interrupt Mask Register 1 OOL R2T LT R1T RES V
CC
RES 2.5V 0x00
0x75 R/W Interrupt Mask Register 2 D2 D1 F4P FAN3 FAN2 FAN1 OVT RES 0x00
0x76 R/W Extended Resolution 1 RES RES V
CC
V
CC
RES RES 2.5V 2.5V 0x00
0x77 R/W Extended Resolution 2 TDM2 TDM2 LTMP LTMP TDM1 TDM1 RES RES 0x00
0x78 R/W Configuration Register 3 DC4 DC3 DC2 DC1 FAST BOOST THERM ALERT 0x00 YES
ENABLE
0x79 R THERM Status Register TMR TMR TMR TMR TMR TMR TMR ASRT/ 0x00
TMR
0x7A R/W THERM Limit Register LIMT LIMT LIMT LIMT LIMT LIMT LIMT LIMT 0x00
0x7B R/W Fan Pulses per Revolution FAN4 FAN4 FAN3 FAN3 FAN2 FAN2 FAN1 FAN1 0x55
0x7D R/W Configuration Register 4 RES RES RES RES AINL AINL RES AL2.5V 0x00 YES
0x7E R Test Register 1 DO NOT WRITE TO THESE REGISTERS 0x00 YES
0x7F R Test Register 2 DO NOT WRITE TO THESE REGISTERS 0x00 YES
REV. A–32–
ADT7460
Table V. Voltage Reading Registers (Power-On Default = 0x00)
Register Address R/W Description
0x20 Read-Only 2.5 V Reading (8 MSBs of reading)
0x22 Read-Only V
CC
Reading: Measures V
CC
through the V
CC
pin (8 MSBs of Reading)
These voltage readings are in twos complement format.
If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) should be read first. Once the extended
resolution registers get read, the associated MSB reading registers get frozen until read. Both the extended resolution registers and the MSB registers get frozen.
Table VI. Temperature Reading Registers (Power-On Default = 0x80)
Register Address R/W Description
0x25 Read-Only Remote 1 Temperature Reading* (8 MSBs of Reading)
0x26 Read-Only Local Temperature Reading (8 MSBs of Reading)
0x27 Read-Only Remote 2 Temperature Reading* (8 MSBs of Reading)
These temperature readings are in twos complement format.
*Note that a reading of 0x80 in a temperature reading register indicates a diode fault (open or short) on that channel. If the extended resolution bits of these readings are
also being read, the extended resolution registers (Reg. 0x76, 0x77) should be read first. Once the extended resolution registers get read, all associated MSB reading
registers get frozen until read. Both the extended resolution registers and the MSB registers get frozen.
Table VII. Fan Tachometer Reading Registers (Power-On Default = 0x00)
Register Address R/W Description
0x28 Read-Only TACH1 Low Byte
0x29 Read-Only TACH1 High Byte
0x2A Read-Only TACH2 Low Byte
0x2B Read-Only TACH2 High Byte
0x2C Read-Only TACH3 Low Byte
0x2D Read-Only TACH3 High Byte
0x2E Read-Only TACH4 Low Byte
0x2F Read-Only TACH4 High Byte
These registers count the number of 11.11 ms periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2).
The number of TACH pulses used to count can be changed using the fan pulses per revolution register (Reg. 0x7B). This allows the fan speed to be accurately
measured. Since a valid fan tachometer reading requires that two bytes are read, the low byte MUST be read first. Both the low and high bytes are then frozen until
read. At power-on, these registers contain 0x0000 until such time as the first valid fan TACH measurement is read in to these registers. This prevents false interrupts
from occurring while the fans are spinning up.
A count of 0xFFFF indicates that a fan is: 1. Stalled or Blocked (object jamming the fan)
2. Failed (internal circuitry destroyed)
3. Not Populated (The ADT7460 expects to see a fan connected to each TACH.
If a fan is not connected to that TACH, its TACH minimum high and low byte
should be set to 0xFFFF.)
4. Alternate Function, e.g., TACH4 reconfigured as THERM pin
5. 2-Wire Instead of 3-Wire Fan
REV. A
ADT7460
–33–
Table VIII. Current PWM Duty Cycle Registers (Power-On Default = 0xFF)
Register Address R/W Description
0x30 Read/Write PWM1 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
0x31 Read/Write PWM2 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
0x32 Read/Write PWM3 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7460 reports the PWM duty
cycles back through these registers. The PWM duty cycle values will vary according to temperature in automatic fan speed control mode. During fan startup, these
registers report back 0x00. In software mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers.
Table IX. Operating Point Registers (Power-On Default = 0x64)
Register Address R/W*Description
0x33 Read/Write Remote 1 Operating Point Register (Default = 100C)
0x34 Read/Write Local Temp Operating Point Register (Default = 100C)
0x35 Read/Write Remote 2 Operating Point Register (Default = 100C)
These registers set the target operating point for each temperature channel when the dynamic T
MIN
control feature is enabled.
The fans being controlled will be adjusted to maintain temperature about an operating point.
*These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers will fail.
REV. A–34–
ADT7460
Table X. Register 0x36 – Dynamic T
MIN
Control Register 1 (Power-On Default = 0x00)
Bit Name R/W*Description
<0> CYR2 Read/Write MSB of 3-Bit Remote 2 Cycle Value. The other two bits of the code reside in Dynamic T
MIN
Control Register 2 (Reg. 0x37). These three bits define the delay time between making sub-
sequent T
MIN
adjustments in the control loop, in terms of number of monitoring cycles.
The system will have associated thermal time constants that need to be found to optimize
the response of fans and the control loop.
<1> Reserved Read-Only Reserved for future use.
<2> PHTR1 Read/Write PHTR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point
register if THERM gets asserted. The operating point will contain the temperature at
which THERM is asserted. This allows the system to run as quietly as possible without
system performance being affected. PHTR1 = 0 ignores any THERM assertions on the
THERM pin. The Remote 1 operating point register will reflect its programmed value.
<3> PHTL Read/Write PHTL = 1 copies the local channel’s current temperature to the local operating point
register if THERM gets asserted. The operating point will contain the temperature at
which THERM is asserted. This allows the system to run as quietly as possible without
system performance being affected. PHTL = 0 ignores any THERM assertions on the
THERM pin. The local temp operating point register will reflect its programmed value
.
<4> PHTR2 Read/Write PHTR2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point
register if THERM gets asserted. The operating point will contain the temperature at
which THERM is asserted. This allows the system to run as quietly as possible without
system performance being affected. PHTR2 = 0 ignores any THERM assertions on the
THERM pin. The Remote 2 operating point register will reflect its programmed value.
<5> R1T Read/Write R1T = 1 enables
dynamic
T
MIN
control on the Remote 1
temperature channel. The chosen
T
MIN
value will be dynamically adjusted based on the current temperature, operating point,
and high and low limits for this zone. R1T = 0 disables dynamic T
MIN
control. The T
MIN
value chosen will not be adjusted and the channel will behave as described in the
Automatic Fan Control section.
<6> LT Read/Write LT = 1 enables dynamic T
MIN
control on the local temperature channel. The chosen
T
MIN
value will be dynamically adjusted based on the current temperature, operating
point, and high and low limits for this zone. LT = 0 disables dynamic T
MIN
control. The
T
MIN
value chosen will not be adjusted and the channel will behave as described in the
Automatic Fan Control section.
<7> R2T Read/Write
R2T = 1 enables dynamic T
MIN
control on the Remote 2 temperature channel. The
chosen T
MIN
value will be dynamically adjusted based on the current temperature,
operating point, and high and low limits for this zone. R2T = 0 disables dynamic T
MIN
control. The T
MIN
value chosen will not be adjusted and the channel will behave as
described in the Automatic Fan Control section.
*This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register will fail.
REV. A
ADT7460
–35–
Table XI. Register 0x37 – Dynamic T
MIN
Control Register 2 (Power-On Default = 0x00)
Bit Name R/W*Description
<2:0>
CYR1 Read/Write 3-Bit Remote 1 Cycle Value. These three bits define the delay time between making
subsequent T
MIN
adjustments in the control loop for the Remote 1 channel, in terms
of number of monitoring cycles. The system will have associated thermal time constants
that need to be found to optimize the response of fans and the control loop.
Bits Decrease Cycle Increase Cycle
000 4 Cycles (0.5 s) 8 Cycles (1 s)
001 8 Cycles (1 s) 16 Cycles (2 s)
010 16 Cycles (2 s) 32 Cycles (4 s)
011 32 Cycles (4 s) 64 Cycles (8 s)
100 64 Cycles (8 s) 128 Cycles (16 s)
101 128 Cycles (16 s) 256 Cycles (32 s)
110 256 Cycles (32 s) 512 Cycles (64 s)
111 512 Cycles (64 s) 1024 Cycles (128 s)
<5:3>
CYL Read/Write 3-Bit Local Temp Cycle Value. These three bits define the delay time between making
subsequent T
MIN
adjustments in the control loop for local temperature channel, in terms
of number of monitoring cycles. The system will have associated thermal time constants
that need to be found to optimize the response of fans and the control loop.
Bits Decrease Cycle Increase Cycle
000 4 Cycles (0.5 s) 8 Cycles (1 s)
001 8 Cycles (1 s) 16 Cycles (2 s)
010 16 Cycles (2 s) 32 Cycles (4 s)
011 32 Cycles (4 s) 64 Cycles (8 s)
100 64 Cycles (8 s) 128 Cycles (16 s)
101 128 Cycles (16 s) 256 Cycles (32 s)
110 256 Cycles (32 s) 512 Cycles (64 s)
111 512 Cycles (64 s) 1024 Cycles (128 s)
<7:6> CYR2 Read/Write 2 LSBs of 3-Bit Remote 2 Cycle Value. The MSB of the 3-bit code resides in Dynamic
T
MIN
Control Register 1 (Reg. 0x36). These three bits define the delay time between making
subsequent T
MIN
adjustments in the control loop for the Remote 2 channel, in terms of
number of monitoring cycles. The system will have associated thermal time constants that
need to be found to optimize the response of fans and the control loop.
Bits Decrease Cycle Increase Cycle
000 4 Cycles (0.5 s) 8 Cycles (1 s)
001 8 Cycles (1 s) 16 Cycles (2 s)
010 16 Cycles (2 s) 32 Cycles (4 s)
011 32 Cycles (4 s) 64 Cycles (8 s)
100 64 Cycles (8 s) 128 Cycles (16 s)
101 128 Cycles (16 s) 256 Cycles (32 s)
110 256 Cycles (32 s) 512 Cycles (64 s)
111 512 Cycles (64 s) 1024 Cycles (128 s)
*This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register will fail.
REV. A–36–
ADT7460
Table XII. Register 0x40 – Configuration Register 1 (Power-On Default = 0x00)
Bit Name R/W Description
<0> STRT Read/Write Logic 1 enables monitoring and PWM control outputs based on the limit settings pro-
grammed. Logic 0 disables monitoring and PWM control based on the default power-up
limit settings. Note that the limit values programmed are preserved even if a Logic 0 is
written to this bit and the default settings are enabled. This bit becomes read-only and
cannot be changed once Bit 1 (lock bit) has been written. All limit registers should be
programmed by BIOS before setting this bit to 1. (Lockable.)
<1> LOCK Write Once Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable
registers become read-only and cannot be modified until the ADT7460 is powered down
and powered up again. This prevents rogue programs such as viruses from modifying
critical system limit settings. (Lockable.)
<2> RDY Read-Only This bit gets set to 1 by the ADT7460 to indicate that the device is fully powered-up
and ready to begin systems monitoring.
<3> FSPD Read/Write When set to 1, this runs all fans at full speed. Power-on default = 0. This bit does not
get locked at any time.
<4> RES Read-Only Reserved for future use.
<5> FSPDIS Read/Write Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs will go
high for the entire fan spin-up timeout selected.
<6> TODIS Read/Write When this bit is set to 1, the SMBus timeout feature is disabled. This allows the
ADT7460 to be used with SMBus controllers that cannot handle SMBus
timeouts. (Lockable.)
<7> V
CC
Read/Write When this bit is set to 1, the ADT7460 rescales its V
CC
pin to measure a 5 V supply. If
this bit is 0, the ADT7460 measures V
CC
as a 3.3 V supply. (Lockable.)
Table XIII. Register 0x41 – Interrupt Status Register 1 (Power-On Default = 0x00)
Bit Name R/W Description
<0> 2.5V Read-Only A one indicates the 2.5 V
high or low limit has been exceeded. This bit gets cleared on
a read of the status register only if the error condition has subsided.
<1> RES Read-Only Reserved for future use.
<2> V
CC
Read-Only A one indicates the V
CC
high or low limit has been exceeded. This bit gets cleared on a
read of the status register only if the error condition has subsided.
<3> RES Read-Only Reserved for future use.
<4> R1T Read-Only A one indicates the Remote 1 low or high temperature limit has been exceeded. This bit
gets cleared on a read of the Status Register only if the error condition has subsided.
<5> LT Read-Only A one indicates the local low or high temperature limit has been exceeded. This bit gets
cleared on a read of the Status Register only if the error condition has subsided.
<6> R2T Read-Only A one indicates the Remote 2 low or high temperature limit has been exceeded. This bit
gets cleared on a read of the Status Register only if the error condition has subsided.
<7> OOL Read-Only A one indicates that an out-of-limit event has been latched in Status Register 2. This bit
is a logical OR of all status bits in Status Register 2. Software can test this bit in isolation
to determine whether any of the voltage, temperature, or fan speed readings represented
by Status Register 2 are out-of-limit. This saves the need to read Status Register 2 every
interrupt or polling cycle.
REV. A
ADT7460
–37–
Table XIV. Register 0x42 – Interrupt Status Register 2 (Power-On Default = 0x00)
Bit Name R/W Description
<0> RES Read-Only Reserved for future use.
<1> OVT Read-Only A one indicates that one of the THERM overtemperature limits has been exceeded.
This bit gets cleared on a read of the status register when the temperature drops below
THERM – T
HYST
.
<2> FAN1 Read-Only A one indicates that Fan 1 has dropped below minimum speed or has stalled.
This bit does NOT get set when the PWM1 output is off.
<3> FAN2 Read-Only A one indicates that Fan 2 has dropped below minimum speed or has stalled.
This bit does NOT get set when the PWM2 output is off.
<4> FAN3 Read-Only A one indicates that Fan 3 has dropped below minimum speed or has stalled.
This bit does NOT get set when the PWM3 output is off.
<5> F4P Read-Only A one indicates that Fan 4 has dropped below minimum speed or has stalled.
This bit does NOT get set when the PWM3 output is off.
Read-Only If Pin 9 is configured as the THERM timer input for THERM monitoring, then this bit
gets set when the THERM assertion time exceeds the limit programmed in the THERM
Limit Register (Reg. 0x7A).
<6> D1 Read-Only A one indicates either an open or short circuit on the Thermal Diode 1 inputs.
<7> D2 Read-Only A one indicates either an open or short circuit on the Thermal Diode 2 inputs.
Table XV. Voltage Limit Registers
Register Address R/W Description Power-On Default
0x44 Read/Write 2.5 V Low Limit 0x00
0x45 Read/Write 2.5 V High Limit 0xFF
0x48 Read/Write V
CC
Low Limit 0x00
0x49 Read/Write V
CC
High Limit 0xFF
Setting the Configuration Register 1 lock bit has no effect on these registers.
High Limits: An interrupt is generated when a value exceeds its high limit (> comparison).
Low Limits: An interrupt is generated when a value is equal to or below its low limit ( £ comparison).
Table XVI. Temperature Limit Registers
Register Address R/W Description Power-On Default
0x4E Read/Write Remote 1 Temp Low Limit 0x81
0x4F Read/Write Remote 1 Temp High Limit 0x7F
0x50 Read/Write Local Temp Low Limit 0x81
0x51 Read/Write Local Temp High Limit 0x7F
0x52 Read/Write Remote 2 Temp Low Limit 0x81
0x53 Read/Write Remote 2 Temp High Limit 0x7F
Exceeding any of these temperature limits by 1C will cause the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock bit
has no effect on these registers.
High Limits: An interrupt is generated when a value exceeds its high limit (> comparison).
Low Limits: An interrupt is generated when a value is equal to or below its low limit ( £ comparison).
REV. A–38–
ADT7460
Table XVII. Fan Tachometer Limit Registers
Register Address R/W Description Power-On Default
0x54 Read/Write TACH1 Minimum Low Byte 0xFF
0x55 Read/Write TACH1 Minimum High Byte 0xFF
0x56 Read/Write TACH2 Minimum Low Byte 0xFF
0x57 Read/Write TACH2 Minimum High Byte 0xFF
0x58 Read/Write TACH3 Minimum Low Byte 0xFF
0x59 Read/Write TACH3 Minimum High Byte 0xFF
0x5A Read/Write TACH4 Minimum Low Byte 0xFF
0x5B Read/Write TACH4 Minimum High Byte 0xFF
Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit will be set in Interrupt Status
Register 2 to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers.
Table XVIII. PWM Configuration Registers
Register Address R/W*Description Power-On Default
0x5C Read/Write PWM1 Configuration 0x62
0x5D Read/Write PWM2 Configuration 0x62
0x5E Read/Write PWM3 Configuration 0x62
Bit Name R/W Description
<2:0> SPIN Read/Write These bits control the start-up timeout for PWMx. The PWM output stays high until
two valid TACH rising edges are seen from the fan. If there is not a valid TACH signal
during the fan TACH measurement directly after the fan start-up timeout period, then
the TACH measurement will read 0xFFFF and Status Register 2 reflects the fan fault. If
the TACH minimum high and low byte contains 0xFFFF or 0x0000, then the Status
Register 2 bit will not get set, even if the fan has not started.
000 = No Start-Up timeout
001 = 100 ms
010 = 250 ms (Default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
<3> SLOW Read/Write SLOW = 1 makes the ramp rates for acoustic enhancement four times longer.
<4> INV Read/Write This bit inverts the PWM output. The default is 0, which corresponds to a logic high
output for 100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty
cycle corresponds to a logic low output.
<7:5> BHVR Read/Write These bits assign each fan to a particular temperature sensor for localized cooling.
000 = Remote 1 temp controls PWMx (automatic fan control mode).
001 = Local temp controls PWMx (automatic fan control mode).
010 = Remote 2 temp controls PWMx (automatic fan control mode).
011 = PWMx runs full speed (default).
100 = PWMx is disabled.
101 = Fastest Speed Calculated by Local and Remote 2 Temp Control PWMx
110 = Fastest Speed Calculated by all three Temp Channels Control PWMx
111 = Manual Mode. PWM duty cycle registers (Reg. 0x30–0x32) become writable.
*These registers become read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to these registers will fail.
REV. A
ADT7460
–39–
Table XIX. TEMP T
RANGE
/PWM Frequency Registers
Register Address R/W*Description Power-On Default
0x5F Read/Write Remote 1 T
RANGE
/PWM1 Frequency 0xC4
0x60 Read/Write Local Temp T
RANGE
/PWM2 Frequency 0xC4
0x61 Read/Write Remote 2 T
RANGE
/PWM3 Frequency 0xC4
Bit Name R/W Description
<2:0> FREQ Read/Write These bits control the PWMx frequency.
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (Default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
<3> THRM Read/Write THRM = 1 causes the THERM pin (Pin 9) to assert low as an output when this temperature
channel’s THERM limit has been exceeded by 0.25C. The THERM pin will remain
asserted until the temperature is equal to or below the THERM limit. The minimum time
that THERM asserts for is one monitoring cycle. This allows clock modulation of devices
that incorporate this feature. THRM = 0 makes the THERM pin act as an input only,
e.g., for Pentium 4 PROCHOT monitoring, when Pin 9 is configured as THERM.
<7:4> RANGE Read/Write These bits determine the PWM duty cycle versus temperature slope for automatic
fan control.
0000 = 2C
0001 = 2.5C
0010 = 3.33C
0011 = 4C
0100 = 5C
0101 = 6.67C
0110 = 8C
0111 = 10C
1000 = 13.33C
1001 = 16C
1010 = 20C
1011 = 26.67C
1100 = 32C (Default)
1101 = 40C
1110 = 53.33C
1111 = 80C
*These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers shall have no effect.
REV. A–40–
ADT7460
Table XX. Register 0x62 – Enhance Acoustics Register 1 (Power-On Default = 0x00)
Bit Name R/W*Description
<2:0> ACOU Read/Write These bits select the ramp rate applied to the PWM1 output. Instead of PWM1 jumping
instantaneously to its newly calculated speed, PWM1 will ramp gracefully at the rate
determined by these bits. This feature enhances the acoustics of the fan being driven by
the PWM1 output.
Time Slot Increase Time for 33% to 100%
000 = 1 35 s
001 = 2 17.6 s
010 = 3 18 s
011 = 5 7 s
100 = 8 4.4 s
101 = 12 3 s
110 = 24 1.6 s
111 = 48 0.8 s
<3> EN1 Read/Write When this bit is 1, acoustic enhancement is enabled on PWM1 output.
<4> SYNC Read/Write SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to
PWM3. This allows up to three fans to be driven from PWM3 output and their speeds to
be measured.
SYNC = 0, only TACH3 and TACH4 are synchronized to PWM3 output.
<5> MIN1 Read/Write
When the ADT7460 is in automatic fan control mode, this bit defines whether PWM1 is
off (0% duty cycle) or at PWM1 minimum duty cycle when the controlling temperature is
below its T
MIN
– Hysteresis value.
0 = 0% Duty Cycle below T
MIN
– Hysteresis
1 = PWM1 Minimum Duty Cycle below T
MIN
– Hysteresis
<6> MIN2 Read/Write When the ADT7460 is in automatic fan speed control mode, this bit defines whether
PWM2 is off (0% duty cycle) or at PWM2 minimum duty cycle when the controlling
temperature is below its T
MIN
– Hysteresis value.
0 = 0% Duty Cycle below T
MIN
– Hysteresis
1 = PWM2 Minimum Duty Cycle below T
MIN
– Hysteresis
<7> MIN3 Read/Write When the ADT7460 is in automatic fan speed control mode, this bit defines whether
PWM3 is off (0% duty cycle) or at PWM3 minimum duty cycle when the controlling
temperature is below its T
MIN
– Hysteresis value.
0 = 0% Duty Cycle below T
MIN
– Hysteresis
1 = PWM3 Minimum Duty Cycle below T
MIN
– Hysteresis
*This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register will have no effect.
REV. A
ADT7460
–41–
Table XXI. Register 0x63 – Enhance Acoustics Register 2 (Power-On Default = 0x00)
Bit Name R/W*Description
<2:0> ACOU3 Read/Write These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jumping
instantaneously to its newly calculated speed, PWM3 will ramp gracefully at the rate determined
by these bits. This effect enhances the acoustics of the fan being driven by the PWM3 output.
Time Slot Increase Time for 33% to 100%
000 = 1 35 s
001 = 2 17.6 s
010 = 3 1.8 s
011 = 5 7 s
100 = 8 4.4 s
101 = 12 3 s
110 = 24 1.6 s
111 = 48 0.8 s
<3> EN3 Read/Write When this bit is 1, acoustic enhancement is enabled on PWM3 output.
<6:4> ACOU2 Read/Write These bits select the ramp rate applied to the PWM2 output. Instead of PWM2 jumping
instantaneously to its newly calculated speed, PWM2 will ramp gracefully at the rate determined
by these bits. This effect enhances the acoustics of the fans being driven by the PWM2 output.
Time Slot Increase Time for 33% to 100%
000 = 1 35 s
001 = 2 17.6 s
010 = 3 11.8 s
011 = 5 7 s
100 = 8 4.4 s
101 = 12 3 s
110 = 24 1.6 s
111 = 48 0.8 s
<7> EN2 Read/Write When this bit is 1, acoustic enhancement is enabled on PWM2 output.
*This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register will have no effect.
REV. A–42–
ADT7460
Table XXII. PWM Min Duty Cycle Registers
Register Address R/W*Description Power-On Default
0x64 Read/Write PWM1 Min Duty Cycle 0x80 (50% duty cycle)
0x65 Read/Write PWM2 Min Duty Cycle 0x80 (50% duty cycle)
0x66 Read/Write PWM3 Min Duty Cycle 0x80 (50% duty cycle)
Bit Name Read/Write Description
<7:0> PWM Duty Read/Write These bits define the PWM
MIN
duty cycle for PWMx.
Cycle 0x00 = 0% Duty Cycle (Fan Off)
0x40 = 25% Duty Cycle
0x80 = 50% Duty Cycle
0xFF = 100% Duty Cycle (Fan Full Speed)
*These registers become read-only when the ADT7460 is in automatic fan control mode.
Table XXIII. T
MIN
Registers
Register Address R/W*Description Power-On Default
0x67 Read/Write Remote 1 Temp T
MIN
0x5A (90C)
0x68 Read/Write Local Temp T
MIN
0x5A (90C)
0x69 Read/Write Remote 2 Temp T
MIN
0x5A (90C)
These are the T
MIN
registers for each temperature channel. When the temperature measured exceeds T
MIN
, the appropriate fan will run at minimum speed and increase
with temperature according to T
RANGE
.
*These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers shall have no effect.
Table XXIV. THERM Limit Registers
Register Address R/W*Description Power-On Default
0x6A Read/Write Remote 1 THERM Limit 0x64 (100C)
0x6B Read/Write Local THERM Limit 0x64 (100C)
0x6C Read/Write Remote 2 THERM Limit 0x64 (100C)
If any temperature measured exceeds its THERM limit, all PWM outputs will drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool
the system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is
disabled. The PWM output will remain at 100% until the temperature drops below THERM Limit – Hysteresis. If the THERM pin is programmed as an output, then
exceeding these limits by 0.25C can cause the THERM pin to assert low as an output.
*These registers become read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to these registers will have no effect.
Table XXV. Temperature Hysteresis Registers
Register Address R/W*Description Power-On Default
0x6D Read/Write Remote 1 Local Temp Hysteresis 0x44
0x6E Read/Write Remote 2 Temp Hysteresis 0x40
Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its T
MIN
value,
the fan will remain running at PWM
MIN
duty cycle until the temperature = T
MIN
– Hysteresis. Up to 15C of hysteresis may be assigned to any temperature channel. The
hysteresis value chosen will also apply to that temperature channel if its THERM limit is exceeded. The PWM output being controlled will go to 100% if the THERM
limit is exceeded and will remain at 100% until the temperature drops below THERM – Hysteresis. For acoustic reasons, it is recommended that the hysteresis value
not be programmed less than 4C. Setting the hysteresis value lower than 4C will cause the fan to switch on and off regularly when the temperature is close to T
MIN
.
*These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers will have no effect.
REV. A
ADT7460
–43–
Table XXVI. XOR Tree Test Enable Register
Register Address R/W*Description Power-On Default
0x6F Read/Write XOR Tree Test Enable 0x00
<0> XEN If the XEN bit is set to 1, the device enters the XOR tree test mode. Clearing the bit
removes the device from the XOR Test Mode.
<7:1> RES Unused. Do not write to these bits.
*This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register will have no effect.
Table XXVII. Remote 1 Temperature Offset Register
Register Address R/W*Description Power-On Default
0x70 Read/Write Remote 1 Temperature Offset 0x00
<7:0> Read/Write Allows a twos complement offset value to be automatically added to or subtracted from
the Remote 1 temperature reading. This is to compensate for any
inherent system offsets
such as PCB trace resistance. LSB value = 0.25
o
C.
*This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register will have no effect.
Table XXVIII. Local Temperature Offset Register
Register Address R/W*Description Power-On Default
0x71 Read/Write Local Temperature Offset 0x00
<7:0> Read/Write Allows a twos complement offset value to be automatically added to or subtracted from
the local temperature reading. LSB value = 0.25
o
C.
*This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register will have no effect.
Table XXIX. Remote 2 Temperature Offset Register
Register Address R/W*Description Power-On Default
0x72 Read/Write Remote 2 Temperature Offset 0x00
<7:0> Read/Write Allows a twos complement offset value to be automatically added to or subtracted from
the Remote 2 temperature reading. This is to compensate for any inherent system offsets
such as PCB trace resistance. LSB value = 0.25
o
C.
*This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register will have no effect.
REV. A–44–
ADT7460
Table XXX. Register 0x73 – Configuration Register 2 (Power-On Default = 0x00)
Bit Name R/W*Description
0AIN1 Read/Write AIN1 = 0, Speed of 3-wire fans measured using the TACH output from the fan.
AIN1 = 1, Pin 6 is reconfigured to measure the speed of 2-wire fans using an external
sensing resistor and coupling capacitor.
AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D).
1AIN2 Read/Write AIN2 = 0, Speed of 3-wire fans measured using the TACH output from the fan.
AIN2 = 1, Pin 7 is reconfigured to measure the speed of 2-wire fans using an external
sensing resistor and coupling capacitor.
AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D).
2AIN3 Read/Write AIN3 = 0, Speed of 3-wire fans measured using the TACH output from the fan.
AIN3 = 1, Pin 4 is reconfigured to measure the speed of 2-wire fans using an external
sensing resistor and coupling capacitor.
AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D).
3AIN4 Read/Write AIN4 = 0, Speed of 3-wire fans measured using the TACH output from the fan.
AIN4 = 1, Pin 9 is reconfigured to measure the speed of 2-wire fans using an external
sensing resistor and coupling capacitor.
AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D).
4AVG Read/Write AVG = 1, Averaging on the temperature and voltage measurements is turned off. This
allows measurements on each channel to be made much faster.
5ATTN Read/Write ATTN = 1, the ADT7460 removes the attenuators from the 2.5 V input. The input can
be used for other functions such as connecting up external sensors.
6CONV Read/Write CONV = 1, the ADT7460 is put into a single-channel ADC conversion mode. In this
mode, the ADT7460 can be made to read continuously from one input only, e.g.,
Remote 1 temperature. It is also possible to start ADC conversions using an external
clock on Pin 6 by setting Bit 2 of Test Register 2 (Reg. 0x7F). This mode could be
useful if, for example, users wanted to characterize/profile CPU temperature quickly.
The appropriate ADC channel is selected by writing to Bits <7:5> of TACH1 min high
byte register (0x55).
Bits <7:5> Reg. 0x55 Channel Selected
000 2.5 V
010 V
CC
(3.3 V)
101 Remote 1 Temp
110 Local Temp
111 Remote 2 Temp
7SHDN Read/Write SHDN = 1, ADT7460 goes into shutdown mode. All PWM outputs assert low (or high
depending on state of INV bit) to switch off all fans. The PWM current duty cycle
registers read 0x00 to indicate that the fans are not being driven.
*This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register will have no effect.
REV. A
ADT7460
–45–
Table XXXI. Register 0x74 – Interrupt Mask Register 1 (Power-On Default <7:0> = 0x00)
Bit Name R/W Description
02.5V Read/Write A one masks SMBALERT for out-of-limit conditions on the 2.5 V channel.
1RES Read/Write Reserved for future use.
2V
CC
Read/Write A one masks SMBALERT for out-of-limit conditions on the V
CC
channel.
3RES Read/Write Reserved for future use.
4R1T Read/Write A one masks SMBALERT for out-of-limit conditions on the Remote 1
temperature channel.
5LT Read/Write A one masks SMBALERT for out-of-limit conditions on the Local
temperature channel.
6R2T Read/Write A one masks SMBALERT for out-of-limit conditions on the Remote 2
temperature channel.
7OOL Read/Write A one masks SMBALERT for any out-of-limit condition in Status Register 2.
Table XXXII. Register 0x75 – Interrupt Mask Register 2 (Power-On Default <7:0> = 0x00)
Bit Name R/W Description
0RES Read/Write Reserved for future use.
1OVT Read-Only A one masks SMBALERT for overtemperature THERM conditions.
2FAN1 Read/Write A one masks SMBALERT for a Fan 1 fault.
3FAN2 Read/Write A one masks SMBALERT for a Fan 2 fault.
4FAN3 Read/Write A one masks SMBALERT for a Fan 3 fault.
5F4P Read/Write A one masks SMBALERT for a Fan 4 Fault. If the TACH4 pin is being used as the
THERM input, this bit masks SMBALERT for a THERM timer event.
6D1 Read/Write A one masks SMBALERT for a diode open or short on Remote 1 channel.
7D2 Read/Write A one masks SMBALERT for a diode open or short on Remote 2 channel.
Table XXXIII. Register 0x76 – Extended Resolution Register 1
Bit Name R/W Description
<1:0> 2.5V Read-Only 2.5 V LSBs. Holds the 2 LSBs of the 10-bit 2.5 V measurement.
<3:2> RES Read/Write Reserved for future use.
<5:4> V
CC
Read-Only V
CC
LSBs. Holds the 2 LSBs of the 10-bit V
CC
measurement.
<7:6> RES Read/Write Reserved for future use.
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table XXXIV. Register 0x77 – Extended Resolution Register 2
Bit Name R/W Description
<1:0> RES Read/Write Reserved for future use.
<3:2> TDM1 Read-Only Remote 1 Temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1
temperature measurement.
<5:4> LTMP Read-Only Local Temperature LSBs. Holds the 2 LSBs of the 10-bit Local
temperature measurement.
<7:6> TDM2 Read-Only Remote 2 Temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2
temperature measurement.
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
REV. A–46–
ADT7460
Table XXXV. Register 0x78 – Configuration Register 3 (Power-On Default = 0x00)
Bit Name R/W*Description
<0> ALERT Read/Write ALERT = 1, Pin 5 (PWM2/SMBALERT) is configured as an SMBALERT interrupt
output to indicate out-of-limit error conditions.
<1> THERM Read/Write THERM ENABLE = 1 enables THERM monitoring functionality on Pin 9 when it is
ENABLE configured as THERM. When THERM is asserted, fans can be run at full speed (if the
BOOST bit is set) or a timer can be triggered to time how long THERM has been asserted for.
<2> BOOST Read/Write BOOST = 1, assertion of THERM will cause all fans to run at 100% duty cycle for
fail-safe cooling.
<3> FAST Read/Write FAST = 1 enables fast TACH measurements on all channels. This increases the
TACH measurement rate from once per second, to once every 250 ms (4ⴛ).
<4> DC1 Read/Write DC1 = 1 enables TACH measurements to be continuously made on TACH1.
<5> DC2 Read/Write DC2 = 2 enables TACH measurements to be continuously made on TACH2.
<6> DC3 Read/Write DC3 = 1 enables TACH measurements to be continuously made on TACH3.
<7> DC4 Read/Write DC4 = 1 enables TACH measurements to be continuously made on TACH4.
*This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register will have no effect.
Table XXXVI. Register 0x79 – THERM Status Register (Power-On Default = 0x00)
Bit Name R/W Description
<7:1> TMR Read-Only Times how long THERM input is asserted. These seven bits will read zero until the
THERM assertion time exceeds 45.52 ms.
<0> ASRT/TMR0 Read-Only Gets set high on the assertion of the THERM input. Cleared on read. If the THERM
assertion time exceeds 45.52 ms, this bit gets set and becomes the LSB of the 8-bit TMR
reading. This allows THERM assertion times from 45.52 ms to 5.82 s to be reported
back with a resolution of 22.76 ms.
Table XXXVII. Register 0x7A – THERM Limit Register (Power-On Default = 0x00)
Bit Name R/W Description
<7:0> LIMT Read/Write Sets maximum THERM assertion length allowed before an interrupt is generated. This
is an 8-bit limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms
to 5.82 s to be programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P)
of Interrupt Status Register 2 (Reg. 0x42) will be set. If the limit value is 0x00, then an
interrupt will be generated immediately on the assertion of the THERM input.
REV. A
ADT7460
–47–
Table XXXVIII. Register 0x7B – Fan Pulses per Revolution Register (Power-On Default = 0x55)
Bit Name R/W Description
<1:0> FAN1 Read/Write Sets number of pulses to be counted when measuring Fan1 speed. Can be used to
determine fan’s pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (Default)
10 = 3
11 = 4
<3:2> FAN2 Read/Write Sets number of pulses to be counted when measuring FAN2 speed. Can be used to
determine fan’s pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (Default)
10 = 3
11 = 4
<5:4> FAN3 Read/Write Sets number of pulses to be counted when measuring FAN3 speed. Can be used to
determine fan’s pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (Default)
10 = 3
11 = 4
<7:6> FAN4 Read/Write Sets number of pulses to be counted when measuring FAN4 speed. Can be used to
determine fan’s pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (Default)
10 = 3
11 = 4
Table XXXIX. Register 0x7D – Configuration Register 4 (Power-On Default = 0x00)
Bit Name R/W Description
<0> AL2.5V Read/Write AL2.5V = 1, Pin 14 (2.5V/SMBALERT) is configured as an SMBALERT interrupt
output to indicate out-of-limit error conditions. AL2.5V = 0, Pin 14 (2.5V/
SMBALERT
)
is configured as a 2.5 V measurement input.
<1> RES Read-Only Reserved for future use.
<3:2> AINL Read/Write These two bits define the input threshold for 2-wire fan speed measurements:
00 = 20 mV
01 = 40 mV
10 = 80 mV
11 = 130 mV
<7:4> RES Reserved for future use.
*This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register will have no effect.
REV. A–48–
ADT7460
Table XL. Register 0x7E – Manufacturer’s Test Register 1 (Power On-Default = 0x00)
Bit Name Read/Write Description
<7:0> RES Read-Only Manufacturer’s Test Register. These bits are reserved for manufacturer’s test purposes
and should NOT be written to under normal operation.
Table XLI. Register 0x7F – Manufacturer’s Test Register 2 (Power-On Default = 0x00)
Bit Name Read/Write Description
<7:0> RES Read-Only Manufacturer’s Test Register. These bits are reserved for manufacturer’s test purposes
and should NOT be written to under normal operation.
REV. A
ADT7460
–49–
OUTLINE DIMENSIONS
16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in millimeters
16 9
8
1
PIN 1
SEATING
PLANE
0.010
0.004 0.012
0.008
0.025
BSC 0.010
0.006
0.050
0.016
8ⴗ
0ⴗ
COPLANARITY
0.004
0.065
0.049
0.069
0.053
0.154
BSC
0.236
BSC
COMPLIANT TO JEDEC STANDARDS MO-137AB
0.193
BSC
REV. A–50–
ADT7460
Revision History
Location Page
6/03—Data Sheet changed from REV. 0 to REV. A.
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Updated the SERIAL BUS INTERFACE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Added the To Assign THERM Functionality to a Pin 9 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Added the THERM as an Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Renamed the Therm Input section to THERM Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Renumbered the figures after Figure 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Updated Step 1 in the Configuring the Desired THERM Behavior section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Updated the Fan Speed Control section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Added the POWER-ON DEFAULT section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Updated Table IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Updated Table XVIII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Updated Table XX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Updated Table XXXV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
–51–
C03228–0–6/03(A)
–52–
