CMOS 4-/8-Channel
Analog Multiplexers
ADG508A/ADG509A
Rev. D
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FEATURES
44 V supply maximum rating
VSS to VDD analog signal range
Single-/dual-supply specifications
Wide supply range: 10.8 V to 16.5 V
Extended plastic temperature range: −40°C to +85°C
Low power dissipation: 28 mW maximum
Low leakage: 20 pA typical
Available in 16-lead DIP/SOIC and 20-lead PLCC/LCC
packages
Superior alternative to
DG508A, HI-508
DG509A, HI-509
FUNCTIONAL BLOCK DIAGRAMS
ADG508A
S1
S8
D
A0 A1 A2 EN
DECODER
00051-001
Figure 1. ADG508A
ADG509A
S
1A
S
4A
DA
A0 A1 EN
DECODER
DB
S
1B
S
4B
00051-002
Figure 2. ADG509A
GENERAL DESCRIPTION
The ADG508A and ADG509A are CMOS monolithic analog
multiplexers with eight channels and dual four channels, respec-
tively. The ADG508A switches one of eight inputs to a common
output, depending on the state of three binary addresses and an
enable input. The ADG509A switches one of four differential
inputs to a common differential output, depending on the state
of two binary addresses and an enable input. Both devices have
TTL and 5 V CMOS logic-compatible digital inputs.
The ADG508A and ADG509A are designed on an enhanced
LC2MOS process that gives an increased signal capability of VSS
to VDD and enables operation over a wide range of supply voltages.
The devices can comfortably operate anywhere in the 10.8 V to
16.5 V single- or dual-supply range. These multiplexers also
feature high switching speeds and low RON.
PRODUCT HIGHLIGHTS
1. Single-/Dual-Supply Specifications with a Wide Tolerance.
The devices are specified in the 10.8 V to 16.5 V range for
both single and dual supplies.
2. Extended Signal Range. The enhanced LC2MOS processing
results in a high breakdown and an increased analog signal
range of VSS to VDD.
3. Break-Before-Make Switching. Switches are guaranteed
break-before-make so that input signals are protected
against momentary shorting.
4. Low Leakage. Leakage currents in the range of 20 pA make
these multiplexers suitable for high precision circuits.
ADG508A/ADG509A
Rev. D | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 5
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Typical Performance Characteristics ........................................... 10
Test Circuits ..................................................................................... 11
Single-Supply Octal DAC Application ........................................ 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 16
REVISION HISTORY
7/09—Rev. C to Rev. D
Changes to Table 4 ............................................................................ 8
3/07—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Table 3 ............................................................................ 6
Inserted Table 4 ................................................................................. 7
Inserted Table 6 ................................................................................. 8
Changes to Figure 24 ...................................................................... 12
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 15
ADG508A/ADG509A
Rev. D | Page 3 of 16
SPECIFICATIONS
DUAL SUPPLY
VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V, unless otherwise noted.
Table 1.
ADG508A/
ADG509A
K Version
ADG508A/
ADG509A
B Version
ADG508A/
ADG509A
T Version
Parameter +25°C
−40°C to
+85° +25°C
−40°C to
+85°C +25°C
−55°C to
+125°C Unit Comments
ANALOG SWITCH
Analog Signal Range VSS VSS VSS VSS VSS VSS V min
V
DD VDD VDD VDD VDD VDD V max
RON 280 280 280 Ω typ −10 V ≤ VS ≤ +10 V, IDS = 1 mA;
see Figure 14
450 600 450 600 450 600 Ω max
300 400 300 400 Ω max VDD = 15 V (±10%),
V
SS = −15 V (±10%)
300 400 Ω max VDD = 15 V (±5%),
V
SS = −15 V (±5%)
RON Drift 0.6 0.6 0.6 %/°C typ VS = 0, IDS = 1 mA
RON Match 5 5 5 % typ −10 V ≤ VS ≤ +10 V, IDS = 1 mA
IS (Off), Off Input Leakage 0.02 0.02 0.02 nA typ V1 = ±10 V, V2 = 10 V;
see
m
Figure 15
1 50 1 50 1 50 nA max
ID (Off), Off Output Leakage 0.04 0.04 0.04 nA typ V1 = ±10 V, V2 = 10 V;
see
m
Figure 16
ADG508A 1 100 1 100 1 100 nA max
ADG509A 1 50 1 50 1 50 nA max
ID (On), On Channel Leakage 0.04 0.04 0.04 nA typ V1 = V2 = ±10 V; see Figure 17
ADG508A 1 100 1 100 1 100 nA max
ADG509A 1 50 1 50 1 50 nA max
IDIFF, Differential Off Output
Leakage (ADG509A Only)
25 25 25 nA max
V1 = ±10 V, V2 = 10 V;
see
m
Figure 18
DIGITAL CONTROL
VINH, Input High Voltage 2.4 2.4 2.4 V min
VINL, Input Low Voltage 0.8 0.8 0.8 V max
IINL or IINH 1 1 1 μA max VIN = 0 to VDD
CIN Digital Input Capacitance 8 8 8 pF max
DYNAMIC CHARACTERISTICS
tTRANSITION1 200 200 200 ns typ V1 = ±10 V, V2 = 10 V;
see
m
Figure 19
300 400 300 400 300 400 ns max
tOPEN1 50 50 50 ns typ See Figure 20
25 10 25 10 25 10 ns min
tON (EN)1 200 200 200 ns typ See Figure 21
300 400 300 400 300 400 ns max
tOFF (EN)1 200 200 200 ns typ See Figure 21
300 400 300 400 300 400 ns max
OffF Isolation 68 68 68 dB typ VEN = 0.8 V, RL = 1 kΩ, CL = 15 pF,
VS = 7 V rms, f = 100 kHz
50 50 50 dB min
ADG508A/ADG509A
Rev. D | Page 4 of 16
ADG508A/
ADG509A
K Version
ADG508A/
ADG509A
B Version
ADG508A/
ADG509A
T Version
Parameter +25°C
−40°C to
+85° +25°C
−40°C to
+85°C +25°C
−55°C to
+125°C Unit Comments
CS (Off) 5 5 5 pF typ VEN = 0.8 V
CD (Off)
ADG508A 22 22 22 pF typ VEN = 0.8 V
ADG509A 11 11 11 pF typ
QINJ, Charge Injection 4 4 4 pC typ RS = 0 Ω, VS = 0; see Figure 22
POWER SUPPLY
IDD 0.6 0.6 0.6 mA typ VIN = VINL or VINH
1.5 1.5 1.5 mA max
ISS 20 20 20 μA typ VIN = VINL or VINH
0.2 0.2 0.2 mA max
Power Dissipation 10 10 10 mW typ
28 28 28 mW max
1 Sample tested at 25°C to ensure compliance.
ADG508A/ADG509A
Rev. D | Page 5 of 16
SINGLE SUPPLY
VDD = 10.8 V to 16.5 V, VSS = GND = 0 V, unless otherwise noted.
Table 2.
ADG508A/
ADG509A
K Version
ADG508A/
ADG509A
B Version
ADG508A/
ADG509A
T Version
Parameter +25°C
−40°C to
+85°C +25°C
−40°C to
+85°C +25°C
−55°C to
+125°C Unit Comments
ANALOG SWITCH
Analog Signal Range GND GND GND GND GND GND V min
V
DD VDD VDD VDD VDD VDD V max
RON 500 500 500 Ω typ GND ≤ VS ≤ 10 V, IDS = 0.5 mA;
see Figure 14
700 1000 700 1000 700 1000 Ω max
RON Drift 0.6 0.6 0.6 %/°C typ VS = 0, IDS = 0.5 mA
RON Match 5 5 5 % typ GND ≤ VS ≤ 10 V, IDS = 0.5 mA
IS (Off), Off Input Leakage 0.02 0.02 0.02 nA typ V1 = 10 V/GND, V2 = GND/10 V;
see Figure 15
1 50 1 50 1 50 nA max
ID (Off), Off Output Leakage 0.04 0.04 0.04 nA typ V1 = 10 V/GND, V2 = GND/10 V;
see Figure 16
ADG508A 1 100 1 100 1 100 nA max
ADG509A 1 50 1 50 1 50 nA max
ID (On), On Channel Leakage 0.04 0.04 0.04 nA typ V1 = V2 = 10 V/GND;
see Figure 17
ADG508A 1 100 1 100 1 100 nA max
ADG509A 1 50 1 50 1 50 nA max
IDIFF, Differential Off Output
Leakage (ADG509A Only)
25 25 25 nA max
V1 = 10 V/GND, V2 = GND/10 V;
see Figure 18
DIGITAL CONTROL
VINH, Input High Voltage 2.4 2.4 2.4 V min
VINL, Input Low Voltage 0.8 0.8 0.8 V max
IINL or IINH 1 1 1 μA max VIN = 0 to VDD
CIN Digital Input Capacitance 8 8 8 pF max
DYNAMIC CHARACTERISTICS
tTRANSITION1 300 300 300 ns typ V1 = 10 V/GND, V2 = GND/10 V;
see Figure 19
450 600 450 600 450 600 ns max
tOPEN1 50 50 50 ns typ See Figure 20
25 10 25 10 25 10 ns min
tON (EN)1 250 250 250 ns typ See Figure 21
450 600 450 600 450 600 ns max
tOFF (EN)1 250 250 250 ns typ See Figure 21
450 600 450 600 450 600 ns max
Off Isolation 68 68 68 dB typ VEN = 0.8 V, RL = 1kΩ, CL = 15 pF,
VS = 3.5 V rms, f = 100 kHz
50 50 50 dB min
CS (Off) 5 5 5 pF typ VEN = 0.8 V
CD (Off)
ADG508A 22 22 22 pF typ VEN = 0.8 V
ADG509A 11 11 11 pF typ
QINJ, Charge Injection 4 4 4 pC typ RS = 0 Ω, VS = 0 V; see Figure 22
ADG508A/ADG509A
Rev. D | Page 6 of 16
ADG508A/
ADG509A
K Version
ADG508A/
ADG509A
B Version
ADG508A/
ADG509A
T Version
Parameter +25°C
−40°C to
+85°C +25°C
−40°C to
+85°C +25°C
−55°C to
+125°C Unit Comments
POWER SUPPLY
IDD 0.6 0.6 0.6 mA typ VIN = VINL or VINH
1.5 1.5 1.5 mA max
Power Dissipation 10 10 10 mW typ
25 25 25 mW max
1 Sample tested at 25°C to ensure compliance.
ADG508A/ADG509A
Rev. D | Page 7 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Ratings
VDD to VSS 44 V
VDD to GND 32 V
VSS to GND –32 V
Analog Inputs1
Voltage at S, D VSS − 2 V to VDD + 2 V or 20 mA,
whichever occurs first
Continuous Current, S or D 20 mA
Pulsed Current S or D
1 ms Duration, 10% Duty Cycle 40 mA
Digital Inputs1
Voltage at A, EN VSS − 4 V to VDD + 4 V or 20 mA,
whichever occurs first
Power Dissipation (Any Package)
Up to 75°C 470 mW
Derates Above 75°C by 6 mW/°C
Operating Temperature
Commercial (K Version) −40°C to +85°C
Industrial (B Version) −40°C to +85°C
Extended (T Version) −55°C to +125°C
Storage Temperature Range −65°C to +150°C
1Overvoltage at A, EN, S, or D is clamped by diodes. Current should be limited
to the maximum rating shown in Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADG508A/ADG509A
Rev. D | Page 8 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
A0 1
EN 2
V
SS 3
S1 4
A116
A2
15
GND14
VDD
13
S2 5
S3 6
S4 7
S512
S611
S7
10
D8S89
ADG508A
TOP VIEW
(Not to Scale)
00051-003
Figure 3. ADG508A DIP, SOIC
4
V
SS
5
S1
6
NC
7
S2
8
S3
18
GND
17
V
DD
16
NC
15
S5
14
S6
19
A2
20
A1
1
NC
2
A0
3
EN
13
S7
12
S8
11
NC
10
D
9
S4
ADG508A
TOP VIEW
(Not to Scale)
NC = NO CONNECT
00051-004
Figure 4. ADG508A LCC
1201923
4
5
6
7
8
18
17
16
15
14
910 11 12 13
NC = NO CONNECT
V
SS
S1
NC
S2
S3
GND
V
DD
NC
S5
S6
EN
A0
NC
A1
A2
S4
D
NC
S8
S7
PIN 1
IDENTIFIER
ADG508A
TOP VIEW
(Not to Scale)
0
0051-005
Figure 5. ADG508A PLCC
Table 4. ADG508A Pin Function Description
Pin Number
DIP/SOIC PLCC/LCC Mnemonic Description
1 2 A0 Logic Control Input.
2 3 EN
Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.
3 4 VSS Most Negative Power Supply Potential in Dual Supplies. In single-supply applications,
it can be connected to ground.
4 5 S1 Source Terminal 1. Can be an input or an output.
5 7 S2 Source Terminal 2. Can be an input or an output.
6 8 S3 Source Terminal 3. Can be an input or an output.
7 9 S4 Source Terminal 4. Can be an input or an output.
8 10 D Drain Terminal. Can be an input or an output.
9 12 S8 Source Terminal 8. Can be an input or an output.
10 13 S7 Source Terminal 7. Can be an input or an output.
11 14 S6 Source Terminal 6. Can be an input or an output.
12 15 S5 Source Terminal 5. Can be an input or an output.
13 17 VDD Most Positive Power Supply Potential.
14 18 GND Ground (0 V) Reference.
15 19 A2 Logic Control Input.
16 20 A1 Logic Control Input.
N/A 1 NC No Connect.
N/A 6 NC No Connect.
N/A 11 NC No Connect.
N/A 16 NC No Connect.
Table 5. ADG508A Truth Table
A2 A1 A0 EN On Switch
X1 X
1 XX
1 0 None
0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8
1 X = don’t care.
ADG508A/ADG509A
Rev. D | Page 9 of 16
A0
1
EN
2
V
SS 3
S1A
4
A1
16
GND
15
V
DD
14
S1B
13
S2A
5
S3A
6
S4A
7
S2B
12
S3B
11
S4B
10
DA
8
DB
9
ADG509A
TOP VIEW
(Not to Scale)
00051-006
Figure 6. ADG509A DIP, SOIC
1201923
4
5
6
7
8
18
17
16
15
14
910 11 12 13
NC = NO CONNECT
V
SS
S1
A
NC
S2
A
S3
A
V
DD
S1B
NC
S2B
S3B
EN
A0
NC
A1
GND
S4A
DA
NC
DB
S4B
PIN 1
IDENTIFIER
ADG509A
TOP VIEW
(Not to Scale)
00051-008
Figure 7. ADG509A PLCC
Table 6. ADG509A Pin Function Description
Pin Number
DIP/SOIC PLCC/LCC Mnemonic Description
1 2 A0 Logic Control Input.
2 3 EN Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.
3 4 VSS Most Negative Power Supply Potential in Dual Supplies. In single-supply applications,
it can be connected to ground.
4 5 S1A Source Terminal 1A. Can be an input or an output.
5 7 S2A Source Terminal 2A. Can be an input or an output.
6 8 S3A Source Terminal 3A. Can be an input or an output.
7 9 S4A Source Terminal 4A. Can be an input or an output.
8 10 DA Drain Terminal A. Can be an input or an output.
9 12 DB Drain Terminal B. Can be an input or an output.
10 13 S4B Source Terminal 4B. Can be an input or an output.
11 14 S3B Source Terminal 3B. Can be an input or an output.
12 15 S2B Source Terminal 2B. Can be an input or an output.
13 17 S1B Source Terminal 1B. Can be an input or an output.
14 18 VDD Most Positive Power Supply Potential.
15 19 GND Ground (0 V) Reference.
16 20 A1 Logic Control Input.
N/A 1 NC No Connect.
N/A 6 NC No Connect.
N/A 11 NC No Connect.
N/A 16 NC No Connect.
Table 7. ADG509A Truth Table
A1 A0 EN On Switch Pair
X1 XX
1 0 None
0 0 1 1
0 1 1 2
1 0 1 3
1 1 1 4
1 X = don’t care.
ADG508A/ADG509A
Rev. D | Page 10 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V.
600
500
400
300
200
100
–15 –10 –5 0 5 10 15
700
0
–20 20
V
D
[V
S
](V)
R
ON
(Ω)
V
DD
=+5V
V
SS
= –5V
V
DD
= +10.8V
V
SS
= –10.8V
V
DD
= +15V
V
SS
= –15V
00051-009
Figure 8. RON as a Function of VD (VS): Dual-Supply Voltage, TA = 25°C
10
1
0.1
25 35 45 55 65 85 95 105 115
100
75 125
TEMPERATURE (°C)
LEAKAGE CURRENT (nA)
V
DD
= +16.5V
V
SS
= –16.5V
I
D
(ON)
I
D
(OFF)
I
S
(OFF)
00051-010
Figure 9. Leakage Current as a Function of Temperature
(Note: Leakage Currents Reduce as the Supply Voltages Reduce)
700
600
500
400
300
200
67891011121314
800
100
515
SUPPLY VOLTAGE (V)
tTRANSITION
(ns)
SINGLE
SUPPLY
DUAL
SUPPLY
00051-011
Figure 10. tTRANSITION vs. Supply Voltage: Dual and Single Supplies, TA = 25°C
(Note: For VDD and lVSSl < 10 V; V1 = VDD/VSS, V2 = VSS/VDD. (see Figure 19))
600
500
400
300
200
100
–15 –10 –5 0 5 10 15
700
0
–20 20
V
D
[V
S
](V)
R
ON
(Ω)
V
DD
=10.8V
V
SS
=0V
V
DD
=15V
V
SS
=0V
00051-012
Figure 11. RON as a Function of VD (VS) Single-Supply Voltage, TA = 25°C
1.8
1.7
1.6
1.9
1.5
678910111213145
SUPPLY VOLTAGE (V)
TRIGGER LEVEL (V)
00051-013
15
Figure 12. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply,
TA = 25°C
0.8
0.6
0.4
0.2
678910111213141516
1.0
0
5
SUPPLY VOLTAGE (V)
IDD (mA)
00051-014
17
Figure 13. IDD vs. Supply Voltage: Dual or Single Supply, TA = 25°C
ADG508A/ADG509A
Rev. D | Page 11 of 16
TEST CIRCUITS
Note: All digital input signal rise and fall times measured from 10% to 90% of 3 V. tR = tF = 20 ns.
R
ON
=V1/I
DS
V
S
SD
V1
I
DS
00051-015
Figure 14. RON
D
A
EN
GND
0.8V
IS(OFF)
V1 V2
VDD VSS
VDD VSS
00051-016
Figure 15. IS (Off)
I
D
(OFF)
D
A
EN
GND
0.8V
V1
V2
V
SS
V
DD
V
SS
V
DD
0
0051-017
Figure 16. ID (Off)
D
A
EN
GND
2.4V
ID(ON)V2
V
1
V
DD
V
SS
VDD VSS
00051-018
Figure 17. ID (On)
DA
EN
GND
0.8V
DB
V1 V2
V
SS
V
DD
V
SS
V
DD
A
A
ADG509A
00051-019
Figure 18. IDIFF = IDB (Off)
90%
0V
3V
90%
50%
OUTPUT
ADDRESS
DRIVE (V
IN
)
t
TRANSITION
t
TRANSITION
OUTPUT
ADG508A1
A2
A1
A0
50Ω
1MΩ
GND
S1
S2–S7
S8
D
35pF
V
IN
2.4V EN
V
DD
V
SS
V
DD
V
SS
V1
V2
1
SIMILAR CONNECTION FOR ADG509A.
00051-020
Figure 19. Switching Time of Multiplexer, tTRANSITION
ADG508A/ADG509A
Rev. D | Page 12 of 16
0
V
3
V
50% OUTPUT
ADDRESS
DRIVE (VIN)
t
OPEN
OUTPUT
ADG508A
1
A2
A1
A0
50Ω
1kΩ
GND
S1
S2–S7
S8
D
35pF
VIN
2.4V EN
V
DD
V
SS
VDD VSS
5V
1SIMILAR CONNECTION FOR ADG509A.
00051-021
Figure 20. Break-Before-Make Delay, tOPEN
ENABLE
DRIVE (V
IN
)
OUTPUT
10%
3V
0V 50%
90%
t
ON
(EN)
t
OFF
(EN)
OUTPUT
ADG508A
1
A2
A1
A0
50Ω1kΩ
GND
S1
S2–S8
D
35pF
V
IN
EN
V
DD
V
SS
V
DD
V
SS
5V
1
SIMILAR CONNECTION FOR ADG509A.
00051-022
Figure 21. Enable Delay, tON (EN), tOFF (EN)
3V
0V
IN
V
O
Q
INJ
=CL×ΔV
O
ΔV
O
DS1
EN
GND
CL
1nF
V
O
R
S
V
S
V
DD
V
SS
V
DD
V
SS
A0
A1
A2
ADG508A
1
1
SIMILAR CONNECTION FOR ADG509A.
50Ω
V
IN
0
0051-023
Figure 22. Charge Injection
ADG508A/ADG509A
Rev. D | Page 13 of 16
SINGLE-SUPPLY OCTAL DAC APPLICATION
The entire system operates from a single 15 V power supply.
The ADG508A is ideally suited for the application because it
has both low charge injection and IS (OFF) leakage current.
The following circuit shows the ADG508A connected as a demulti-
plexer to provide eight separate, digitally programmable voltages
(0 V to 10 V) from the AD7245A. The AD7245A is a complete
12-bit, voltage output DAC with output amplifier and Zener
voltage reference on a monolithic CMOS chip.
DB11
DB0
R
FB
V
DD
V
OUT
R
OFS
AD7245A
V
SS
DGND
AGND
CS
WR
LDAC
CLR
REF OUT
ADG508A
EN
D
GND
V
SS
S8
S1
V
DD
A0 A1 A2
+
1/4 TLC274
V
OUT1
15V
15
V
15
V
0.01µF
1/4 TLC274
V
OUT8
15V
0.01µF
10µF0.1µF
10Ω
00051-024
Figure 23. ADG508A in a Single-Supply Octal DAC Circuit
ADG508A/ADG509A
Rev. D | Page 14 of 16
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001-AB
073106-B
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
16
18
9
0.100 (2.54)
BSC
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 24. 16-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-16)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.840 (21.34) MAX
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
0
.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.310 (7.87)
0.220 (5.59)
0.005 (0.13) MIN 0.098 (2.49) MAX
0.100 (2.54) BSC
PIN 1
18
9
16
SEATING
PLANE
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
Figure 25. 16-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-16)
Dimensions shown in inches and (millimeters)
ADG508A/ADG509A
Rev. D | Page 15 of 16
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AC
10.00 (0.3937)
9.80 (0.3858)
16 9
8
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
060606-A
45°
Figure 26. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-16)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-047-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.020 (0.50)
R
BOTTOM
VIEW
(PINS UP)
0.021 (0.53)
0.013 (0.33) 0.330 (8.38)
0.290 (7.37)
0.032 (0.81)
0.026 (0.66)
0.056 (1.42)
0.042 (1.07) 0.20 (0.51)
MIN
0.120 (3.04)
0.090 (2.29)
3
4
19
18
8
9
14
13
TOP VIEW
(PINS DOWN)
0.395 (10.03)
0.385 (9.78) SQ
0.356 (9.04)
0.350 (8.89)SQ
0.048 (1.22 )
0.042 (1.07)
0.048 (1.22)
0.042 (1.07)
0.020
(0.51)
R
0.050
(1.27)
BSC
0.180 (4.57)
0.165 (4.19)
0.045 (1.14)
0.025 (0.64) R
PIN 1
IDENTIFIER
Figure 27. 20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
1
20 4
9
8
13
19
14
3
18
BOTTOM
VIEW
0.028 (0.71)
0.022 (0.56)
45° TYP
0.015 (0.38)
MIN
0.055 (1.40)
0.045 (1.14)
0.050 (1.27)
BSC
0.075 (1.91)
REF
0.011 (0.28)
0.007 (0.18)
R TYP
0.095 (2.41)
0.075 (1.90)
0.100 (2.54) REF
0.200 (5.08)
REF
0.150 (3.81)
BSC
0.075 (1.91)
REF
0.358 (9.09)
0.342 (8.69)
SQ
0.358
(9.09)
MAX
SQ
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
022106-A
Figure 28. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1)
Dimensions shown in inches and (millimeters)
ADG508A/ADG509A
Rev. D | Page 16 of 16
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG508AKN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADG508AKNZ1 −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADG508AKR −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG508AKR-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG508AKR-REEL7 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG508AKRZ1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG508AKRZ-REEL1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG508AKRZ-REEL71 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG508AKP −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20
ADG508AKP-REEL −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20
ADG508AKPZ1 −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20
ADG508AKPZ-REEL1 −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20
ADG508ABQ −40°C to +85°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16
ADG508ATQ −55°C to +125°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16
ADG508ATE −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier [LCC] E-20-1
ADG508ABCHIPS DIE
ADG508ATCHIPS DIE
ADG509AKN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADG509AKNZ1 −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADG509AKR −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG509AKR-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG509AKR-REEL7 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG509AKRZ-REEL1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG509AKRZ-REEL71 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG509AKP −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20
ADG509AKP-REEL −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20
ADG509AKPZ1 −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20
ADG509AKPZ-REEL1 −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20
ADG509ABQ −40°C to +85°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16
ADG509ATQ −55°C to +125°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16
ADG509ATQ/883B −55°C to +125°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16
ADG509ABCHIPS DIE
ADG509ATCHIPS DIE
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D00051-0-7/09(D)