SST39LF100-45-4C-WIE - Silicon Storage Technology

Data Sheet

S71129-04-000 11/03 363

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

1 Mbit (64K x16) Multi-Purpose Flash

SST39LF100 / SST39VF100

FEATURES:

• Organized as 64K x16

• Single Voltage Read and Write Operations

– 3.0-3.6V for SST39LF100

– 2.7-3.6V for SST39VF100

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

(typical values at 14 MHz)

– Active Current: 20 mA (typical)

– Standby Current: 3 µA (typical)

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Fast Read Access Time

– 45 ns for SST39LF1 00

– 70 ns for SST39VF 100

• Latched Address and Data

• Fast Erase and Word-Program

– Sector-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Word-Program Time: 14 µs (typical)

– Chip Rewrite Time: 1 second (typical)

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard Command Sets

• Packages Available

– 40-lead TSOP (10mm x 14mm)

– 48-ball TFBGA (6mm x 8mm)

PRODUCT DESCRIPTION

The SST39LF/VF100 devices are 64K x16 CMOS Multi-

Purpose Flash (MPF) manufactured with SST’ s proprietary,

high performance CMOS SuperFlash technology. The

split-gate cell design and thick-oxide tunneling injector

attain better reliability and manufacturability compared with

alternate approaches. The SST39LF/VF100 write (Pro-

gram or Erase) with a s ingle voltage power su pply of 3. 0-

3.6V and 2.7-3.6V, respectively.

Featuring high performance Word-Program, the

SST39LF/VF100 devices provide a typical Word-Program

time of 14 µsec. The devices use Toggle Bit or Dat a# Poll-

ing to det ect the completion of the Prog r am or Er ase ope r-

ation. To protect against inadvertent write, the SST39LF/

VF100 have on-chip hardware and software data protec-

tion schemes. Designed, manufactured, and tested for a

wide spectrum of applications, the SST39LF/VF100 are

offered with a guaranteed typical endurance of 10,000

cycles. Dat a retention is r ated at greate r than 100 ye ars.

The SST39LF/VF100 devices are suited for applications

that require convenient and economical updating of pro-

gram, configuration, or data memory. For all system appli-

cations, the SST39LF/VF100 significantly improve

per formanc e and reliab ility, whil e low ering pow er consu mp-

tion. T he SST 39LF/ VF100 inhe rent ly use l ess energy dur-

ing Erase and Program than alternative flash technologies.

The total energy consumed is a function of the applied volt-

age, current, and time of application. Since for any given

voltage range, the SuperFlash technology uses less cur-

rent to program and has a shorter erase time, the total

energy consumed durin g any Erase or Program operatio n

is less than alternative flash technologies. The SST39LF/

VF100 also improve flexibility while lowering the cost for

program, data, and configuration storage applications.

The S upe r Flas h te ch no logy pr ovid es fi xed Erase an d P r o-

gram times, in depen dent o f the num ber of Erase/ Pro gram

cycles that have occurred. Therefore the system software

or hardware does not hav e to be modified or de-rated as is

nec essary with al ternati ve flash tec hnologi es, whos e Erase

and Pr ogram tim es inc rease with accumul ated Erase/Pr o-

gr am cycles .

To meet surface mount requirements, the SST39LF/VF100

are offered in 40-lead TSOP and 48-ball TFBGA packages.

See Figure 1 for pin assignments.

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asse rtin g WE# low while keepi ng CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever oc curs l ast. T he data bus is latc hed o n

the rising edge of WE# or CE#, whichev er occurs first.

SST39LF/VF1003.0 & 2.7V 1Mb (x16) MPF memories

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

Read

The Read operation of the SST39LF/VF100 is controlled

by CE# and OE#, both have to be low for the system to

obtain data from the outputs. CE# is used for de vice selec-

tion. When CE# is high, the chip is deselected and only

standby po wer is consumed. OE# is the output control and

is used to gate data from the output pins. The data bus is in

high impedance state when either CE# or OE# is high.

Refer to the Read cycle timing diagram for further details

(Figure 2).

Word-Program Operation

The SST39LF/VF100 are programmed on a word-b y-word

basis. Before programming, the sector where the word

exists must be fully erased. The Program operation is

accomplished in three steps. The first step is the three-byte

load sequence for Software Data Protection. The second

step is to load word address and word data. During the

W ord-Program operation, the addresses are latched on the

falling edge o f either CE# or WE#, whicheve r occurs last.

The data is latched on the rising edge of either CE# or

WE#, wh ichever occurs first. The third step is the inter nal

Program operation which is initiated after the rising edge of

the fourth WE# or CE#, whichever occurs first. The Pro-

gram operation, once initiated, will be completed within 20

µs. See Figures 3 and 4 for WE# and CE# controlled Pro-

gram operation timing diagrams and Figure 13 for flow-

charts. Dur ing th e Program op eration, th e on ly valid rea ds

are Data# Polling and Toggle Bit. During the internal Pro-

gr am ope rat ion , the host is fr ee to p erform additi onal task s .

Any comman ds is s ued during the i nte rnal Program ope ra-

tion are ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the

device on a sector-by-sector ba sis. The sector architecture

is based on uniform sector size of 2 KWord. The Sector-

Erase operation is initiated by executing a six-byte com-

mand sequence with Sector-Erase command (30H) and

secto r address (SA ) in the last bus cycle . The addr ess lines

A11-A15 are used to determine the sector address. The

sector address is latched on the falling edge of the sixth

WE# pulse, while the command (30H) is latched on the ris-

ing edge of the sixth WE# pulse. The internal Erase opera-

tion begins after the sixth WE# pulse. The End-of-Erase

operatio n can be de ter m ined usin g eith er Data # Polling or

Toggle Bit methods. See Figure 8 for timing waveforms.

Any comma nds issued during the Sector-Erase operation

are ignored.

Chip-Erase Operation

The SST39LF/VF100 provide a Chip-Erase operation,

which al lows the user to erase the entire mem or y array to

the “1” state. This is useful when the entire device must be

quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command (10H)

at address 5555H in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

CE#, whichever occurs first. During the Erase operation,

the only v alid read is Toggle Bit or Data# P olling. See Table

4 for the command sequence, Figure 7 for timing diagram,

and Figure 16 for the flowchart. Any commands issued dur-

ing the Chip-Erase operation are ignored.

Write Opera ti on Status De te ct ion

The SST39LF/VF100 provide two software means to

detect the completion of a Write (Program or Erase) cycle,

in o rder t o optim ize the syste m wri te cycle ti me. The so ft-

ware detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE#, which ini-

tiates the internal program or erase operation.

The act ual co mple tion of the nonvolatile wr ite is as ynchr o-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

Data# Polling (DQ7)

When the SST39LF/VF100 are in the internal Program

operatio n, any attempt to r ead DQ7 will pro duce the co m-

plement of the true data. Once the Program operation is

completed, DQ7 will produce true data. Note that even

though DQ 7 may have valid da ta im me di ate ly following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycles after an interval of 1 µs. During internal Erase opera-

tion, any a ttempt to read DQ7 will pro duce a ‘ 0’. Once the

inter nal Erase operati on is completed, DQ 7 will produce a

‘1’. The Data# Polling is valid after the rising edge of fourth

WE# ( or CE # ) pu ls e for Program ope ration. For Secto r- or

Chip-E rase, the Data# Po lling is valid aft er the r ising edge

of sixth WE# (or CE#) pulse. See Figure 5 for Data# P olling

timing diagram and Figure 14 for a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will p roduce alter nating 1s

and 0s, i.e., toggling between 1 and 0. When the inter nal

Program or Erase op eration is compl eted, the DQ6 bit will

stop togglin g. T he device is the n re ady for the next ope ra-

tion. The Toggle Bit is valid after the rising edge of four th

WE# ( or CE # ) pu ls e for Program ope ration . For Sec to r - or

Chip-Erase, the Toggle Bit is valid after the rising edge of

sixth WE # ( or CE #) p ul s e. See Fig ur e 6 for Toggle B it ti m-

ing diag ram an d Figu re 14 f or a fl owc hart.

Data Protection

The SST39LF/VF100 provide both hardware and software

features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pu lse of less t han 5

ns will not ini tiate a Wri te cycle .

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will in hi bit t he Writ e ope ration . T hi s prevents inadvert-

ent Writes during power-up or power-down.

Software Data Protection (SDP)

The SST39LF/VF100 provide the JEDEC approved Soft-

ware Data P rotect ion s cheme for all data altera tion opera-

tions, i.e., Program and Erase. Any Program operation

requires the inclusion of the three-byte sequence. The

three-byte load sequence is used to initiate the Program

operation, providing optimal protection from inadvertent

Write operations, e.g., during the system power-up or

po w e r-d own. Any Er as e o pe r at i on req ui re s th e in cl usi o n of

six-byte sequence. The SST39LF/VF100 devices are

shipped with the Software Data Protection permanently

enabled. See Table 4 for the specific software command

codes. During SDP command sequence, invalid com-

mands will abort the device to Read mode within TRC. The

contents of DQ15-DQ8 can be VIL or VIH, but no other value,

during any SDP command sequence.

Product Identifica tion

The Product Identification mode identifies the devices as

SST39LF/VF100 and manufacturer as SST. This mode

may be acces sed by software operati ons. Users m ay u se

the Software Pr o duc t Id ent ifi cati on opera ti on to id en tif y th e

par t (i.e., using the device ID) when using multiple manu-

facturers in the same socket. For details, see Table 4 for

software operation, Figure 9 for the Software ID Entry and

Read timing diagram, and Figure 15 for the Software ID

Entry comman d sequen ce flo wchart.

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software

Produc t Ident ificati on mode must be exited. Exit is acco m-

plished by issuing the Software ID Exit command

sequence, which returns the device to Read mode. Please

note that the Software ID Exit command is ignored during

an internal Program or Erase operation. See Table 4 for

software c ommand co des, Figure 10 for timi ng waveform,

and Figure 15 for a flowchart.

TABLE 1: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H 00BFH

Device ID

SST39LF/VF100 0001H 2788H

T1.3 363

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

FIGURE 1: PIN ASSIGNMENTS FOR 40-LEAD TSOP AND 48-BALL TFBGA

Y-Decoder

I/O Buffers and Data Latches

363 ILL B1.2

Address Buffer & Latches

X-Decoder

DQ15 - DQ0

A0-A15

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

A13

WE#

A12

A14

A10

A15

A11

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

363 ILL F02b.1

TOP VIEW (balls facing down)

A B C D E F G H

A10

A11

A12

A13

A14

A15

WE#

VDD

CE#

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

VSS

OE#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VSS

363 ILL F01.3

Standard Pinout

To p V i ew

Die Up

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

A15-A0Address Inputs To provide memory addresses.

During Sector-Eras e A15-A11 address lines will select the sector.

DQ15-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF100

2.7-3.6V for SST39VF100

VSS Ground

NC No Connection Unconnected pins.

T2.2 363

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector or Block address,

XXH for Chip-Erase

Standby VIH XXHigh Z X

Write Inhibit X VIL XHigh Z/ D

OUT X

XXV

IH High Z/ DOUT X

Product Identification

Softw are Mode VIL VIL VIH See Table 4

T3.2 363

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence 1st Bus

Write Cycle 2nd Bus

Write Cycle 3rd Bus

Write Cycle 4th Bus

Write Cycle 5th Bus

Write Cycle 6th Bus

Write Cycle

Addr1

1. Address format A14-A0 (Hex), Addresse s A15 can be VIL or VIH, b ut no other value, for the Command sequence

Data2

2. DQ15 - DQ8 can be VIL or VIH, but no other va lue, for the Command sequence

Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3

3. WA = Program word address

Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX4

4. SAX for Sector-Erase; uses A15-A11 address lines

30H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Softw are ID Entry5,6

5. The device does not remain in Software Product ID mode if powered down.

6. With A15-A1 = 0;SST Manuf acturer’s ID = 00BFH, is read with A0 = 0,

SST39LF/VF100 Device ID = 2788H, is read with A0 = 1

5555H AAH 2AAAH 55H 5555H 90H

Softw are ID Exit7

7. Both Software ID Exit operations are equivalent

XXH F0H

Softw are ID Exit75555H AAH 2AAAH 55H 5555H F0H

T4.5 363

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may caus e per manent d amage to the device. This is a stres s rating only and funct ional operatio n

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Pac kage Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Curr ent1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shor ted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE: SST 39LF 100

Range Ambient Temp VDD

Commercial 0°C to +70°C 3.0-3.6V

OPERATING RANGE: SST 39VF1 00

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for SST39LF100

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF fo r SST39VF100

See Figu res 11 and 12

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

TABLE 5: DC OPERATING CHARACTERISTICS

VDD = 3.0-3.6V FOR SS T39L F10 0 AND 2 .7-3.6V FOR S ST39V F1001

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT, at f=1/TRC Min,

VDD=VDD Max

Read 30 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

Program and Erase 30 mA CE#=WE#=VIL, OE# =VIH

ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltag e 0.8 VDD=VDD Min

VIH Input High Voltage 0.7VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=3 mA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T5.7 363

1. Typical conditions for the Activ e Current shown on the front data sheet page are average values at 25°C

(room temperature), and VDD = 3V for VF devices. Not 100% tested.

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T6.0 363

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T7.0 363

TABLE 8: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a

higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD m A JED EC Standard 78

T8.2 363

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

AC CHARACTERISTICS

TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 3.0-3.6V FOR SST39LF100 AND 2.7-3.6V FOR SS T39VF 100

Symbol Parameter

SST39LF100-45 SST39VF100-70

UnitsMinMaxMinMax

TRC Read Cyc le Tim e 45 70 ns

TCE Chip Enable Access Time 45 70 ns

TAA Address Access Time 45 70 ns

TOE Output Enable Access Time 20 35 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 0 ns

TOLZ1OE# Low to Active Output 0 0 ns

TCHZ1CE# High to High-Z Output 15 20 ns

TOHZ1OE# High to High-Z Output 15 20 ns

TOH1Output Hold from Address Change 0 0 ns

T9.4 363

TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TBP Word-Program Time 20 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# Hi gh Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 100 ms

T10.1 363

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

FIGURE 2: READ CYCLE TIMING DIAGRAM

FIGURE 3: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

363 ILL F03.1

ADDRESS A15-0

DQ15-0

WE#

OE#

CE# TCE

TRC TAA

TOE

TOLZVIH

HIGH-Z TCLZ TOH TCHZ HIGH-Z

D ATA VALIDD ATA VALID

TOHZ

363 ILL F04.2

ADDRESS A15-0

DQ15-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

WE#

TBP

Note: X can be VIL or VIH, but no other value

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

FIGURE 4: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

FIGURE 5: DATA# POLLING TIMING DIAGRAM

363 ILL F05.2

ADDRESS A15-0

DQ15-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

CE#

TBP

Note: X can be VIL or VIH, but no other value

363 ILL F06.1

ADDRESS A15-0

DQ7DATA DATA# DATA# DATA

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

FIGURE 6: TOGGLE BIT TIMING DIAGRAM

FIGURE 7: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

363 ILL F07.1

ADDRESS A15-0

DQ6

WE#

OE#

CE#

TOETOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

363 ILL F08.5

ADDRESS A15-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX10XX55XXAA XX80 XXAA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and

CE# signals are interchageable as long as minimum timings are met. (See Table 10)

X can be VIL or VIH, but no other value.

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

FIGURE 8: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

FIGURE 9: SOFTWARE ID ENTRY AND READ

363 ILL F18.4

ADDRESS A15-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX30XX55XXAA XX80 XXAA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 10)

SAX = Sector Address

X can be VIL or VIH, but no other value.

363 ILL F09.4

ADDRESS A14-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

5555 2AAA 5555 0000 0001

OE#

CE#

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

TWP

TWPH TAA

00BFH Device IDXX55XXAA XX90

Device ID = 2788H for SST39LF/VF100

X can be VIL or VIH, but no other value.

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

FIGURE 10: SOFTWARE ID EXIT

363 ILL F10.1

ADDRESS A14-0

X can be VIL or VIH, but no other value.

TIDA

TWP

T WHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

XXAA XX55 XXF0

DQ15-0

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

FIGURE 11: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 12: A TEST LOAD EXAMPLE

363 ILL F11.1

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

A C test inputs are driven at VIHT (0.9 VDD) f or a logic “1” and VILT (0.1 VDD) f or a lo gic “0”. Mea surement re f erence poin ts

f or inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and f all times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

363 ILL F12.2

T O TESTER

TO DUT

1.3 V

1N914

3.3 KΩ

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

FIGURE 13: WORD-PROGRAM ALGORITHM

363 ILL F13.3

Start

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXA0H

Address: 5555H

Load W ord

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

X can be VIL or VIH but no other value.

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

FIGURE 14: WAIT OPTIONS

363 ILL F14.0

W ait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Yes

Program/Erase

Completed

Does DQ6

match?

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

FIGURE 15: SOFTWARE PRODUCT ID COMMAND FLOWCHARTS

363 ILL F15.2

Load data: XXAAH

Address: 5555H

Software ID Entry

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX90H

Address: 5555H

W ait TIDA

Read Software ID

Load data: XXAAH

Address: 5555H

Software ID Exit

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XXF0H

Address: 5555H

Load data: XXF0H

Address: XXH

Return to normal

operation

W ait TIDA

Return to normal

operation

X can be VIL or VIH, but no other value.

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

FIGURE 16: ERASE COMMAND SEQUENCE

363 ILL F16.3

Load data: XXAA

Address: 5555

Chip-Erase

Command Sequence

Load data: XX55

Address: 2AAA

Load data: XX80

Address: 5555

Load data: XX55

Address: 2AAA

Load data: XX10

Address: 5555

Load data: XXAA

Address: 5555

W ait TSCE

Chip erased

to FFFFH

Load data: XXAA

Address: 5555

Sector-Erase

Command Sequence

Load data: XX55

Address: 2AAA

Load data: XX80

Address: 5555

Load data: XX55

Address: 2AAA

Load data: XX30

Address: SAX

Load data: XXAA

Address: 5555

W ait TSE

Sector erased

to FFFFH

X can be VIL or VIH, but no other value.

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

PRODUCT ORDERING INFORMATION

Valid combinations for SST39LF100

SST39LF100-45-4C-WI SST39LF100-45-4C-B3K

SST39LF100-45-4C-WIE SST39LF100-45-4C-B3KE

Valid combinations for SST39VF100

SST39VF100-70-4C-WI SST39VF100-70-4C-B3K

SST39VF100-70-4C-WIE SST39VF100-70-4C-B3KE

SST39VF100-70-4I-WI SST39VF100-70-4I-B3K

SST39VF100-70-4I-WIE SST39VF100-70-4I-B3KE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales rep-

resentative to confirm availability of valid combinations and to determine availability of new combinations.

Environmental Attribut e

E = non-Pb

Package M od i f ier

I = 40 leads

K = 48 balls

Package Type

B3 = TFBGA (0.8mm pitch, 6mm x 8mm)

W = TSOP (type 1, die up, 10mm x 14mm)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

45 = 45 ns

70 = 70 ns

Device Density

100 = 1 Mbit

Voltage

L = 3.0-3.6V

V = 2.7-3.6 V

Product Series

39 = Multi-Purpose Flash

SST 39 VF 100 - 70 - 4C - B3K E

XX XX XXXX - XXX -XX-XXX X

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

PACKAGING DIAGRAMS

40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 10MM X 14MM

SST PACKAGE CODE: WI

12.50

12.30

14.20

13.80

0.70

0.50

10.10

9.90

0.27

0.17

1.05

0.95

0.15

0.05

0.70

0.50

40-tsop-WI-7

Note: 1. Complies with JEDEC publication 95 MO-142 CA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

Pin # 1 Identifier 0.50

BSC

1.20

max.

1mm

0˚- 5˚

DETAIL

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Data Sheet

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM

SST PACKAGE CODE: B3K

TABLE 11: REVISION HISTORY

Number Description Date

02 •2002 Data Book May 2002

03 •Changes to Table 5 on page 7

– Added footnote for Typical conditions

– Clarified the Test Conditions for Power Supply Current and Read parameters

•Added footnote for non-Pb packages

Mar 2003

04 •2004 Data Book

•Added non-Pb MPNs and removed footnote. (See page 19)

•Updated mechanical diagram for B3K package.

Nov 2003

A1 CORNER

H G F E D C B A

A B C D E F G H

BOTTOM VIEWTOP VIEW

SIDE VIEW

SEATING PLANE

0.35 ± 0.05

1.10 ± 0.10

0.12

6.00 ± 0.20

0.45 ± 0.05

(48X)

A1 CORNER

8.00 ± 0.20

0.80

4.00

0.80

5.60

48-tfbga-B3K-6x8-450mic-4

Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1mm

Silicon Stor age Technol ogy, Inc. • 1171 Sonor a C ourt • Sunnyvale , CA 940 86 • Telephone 408-73 5-91 10 • Fax 408-735 -90 36

www.SuperFlash.com or www.sst.com

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