M41ST84Y M41ST84W 512 bit (64 x 8) Serial RTC with Supervisory Functions PRELIMINARY DATA FEATURES SUMMARY 3V or 5V OPERATING VOLTAGE SUPPORTS I2C Figure 1. Packages SERIAL INTERFACE (400 KHz) 2.5V to 5.5V CLOCK OPERATING VOLTAGE AUTOMATIC SWITCH-OVER and DESELECT CIRCUITRY BUS 16 1 SO16 (MQ) CHOICE of POWER-FAIL DESELECT VOLTAGES: - M41ST84Y: VCC = 4.5 to 5.5V; VPFD = 4.40 0.10V - M41ST84W: VCC = 2.8 to 3.6V; VPFD = 2.75 0.05V 1.25V REFERENCE (for PFI/PFO) COUNTERS for TENTHS/HUNDREDTHS of SECONDS, SECONDS, MINUTES, HOURS, DAY, DATE, MONTH, YEAR and CENTURY 44 BYTES of GENERAL PURPOSE RAM PROGRAMMABLE ALARM and INTERRUPT FUNCTION (VALID EVEN DURING BATTERY BACK-UP MODE) WATCHDOG TIMER MICROPROCESSOR POWER-ON RESET BATTERY LOW FLAG LOW OPERATING CURRENT of 400A ULTRA-LOW BATTERY SUPPLY CURRENT of 500 nA (max) OPTIONAL PACKAGING INCLUDES a 28LEAD SOIC and SNAPHAT TOP (to be ordered separately) SNAPHAT PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP, WHICH CONTAINS THE BATTERY and CRYSTAL SNAPHAT (SH) Battery & Crystal 28 1 SOH28 (MH) January 2001 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/32 M41ST84Y, M41ST84W TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Logic Diagram (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 16-pin SOIC Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 28-pin SOIC Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Hardware Hookup (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Bus Data Transfer Sequence (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Acknowledgement Sequence (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus Timing Requirements Sequence (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 AC Characteristics (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Battery Low Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Slave Address Location (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Mode Sequences (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Alternate Read Mode Sequences (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write Mode Sequence (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TIMEKEEPER Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TIMEKEEPER Register Map (Table 3.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Back-Up Mode Alarm Waveform (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Alarm Interrupt Reset Waveforms (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Alarm Repeat Modes (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Square Wave Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Square Wave Output Frequency (Table 5.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power-on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reset Input (RSTIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 RSTIN Timing Waveform (Figure 16.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power-fail INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Calibrating the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Initial Power-on Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Crystal Accuracy Across Temperature (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock Calibration (Figure 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/32 M41ST84Y, M41ST84W MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Absolute Maximum Ratings (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC and AC Measurement Conditions (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC Testing Load Circuit (Figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC Testing Input/Output Waveforms (Figure 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Capacitance (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC Characteristics (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Crystal Electrical Characteristics (Externally Supplied) (Table 11.). . . . . . . . . . . . . . . . . . . . . . . . . 24 Power Down/Up Mode AC Waveforms (Figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power Down/Up AC Characteristics (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3/32 M41ST84Y, M41ST84W SUMMARY DESCRIPTION The M41ST84Y/W Serial supervisory TIMEKEEPER SRAM is a low power 512 bit static CMOS SRAM organized as 64 words by 8 bits. A built-in 32.768 kHz oscillator (external crystal controlled) and 8 bytes of the SRAM (see Figure 3, page 15) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 12 bytes of RAM provide status/control of Alarm, Watchdog and Square Wave functions. Addresses and data are transferred serially via a two line, bi-directional I2C interface. The built-in address register is incremented automatically after each write or read data byte. The M41ST84Y/W has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the SRAM and clock operations can be supplied by a small lithium button-cell supply when a power failure occurs. Functions available to the user include a non-volatile, time-of-day clock/calendar, Alarm interrupts, Watchdog Timer and programmable Square Wave output. Other features include a Power-On Reset as well as an additional input (RSTIN) which can also generate an output Reset (RST). The eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year 4/32 - valid until year 2100), 30 and 31 day months are made automatically. The ninth clock address location controls user access to the clock information and also stores the clock software calibration setting. The M41ST84Y/W is supplied in a 28 lead SOIC SNAPHAT package (which integrates both crystal and battery in a single SNAPHAT top) or a 16 pin SOIC. The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery/crystal package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is also keyed to prevent reverse insertion. The 28-pin SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28 lead SOIC, the battery/crystal package (i.e. SNAPHAT) part number is "M4TXX-BR12SH" (see Table 18, page 30). Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery. M41ST84Y, M41ST84W Figure 2. Logic Diagram Table 1. Signal Names VCC VBAT XI XO XI (1) Oscillator Input XO (1) Oscillator Output IRQ/FT /OUT Interrupt/Frequency Test/ Out Output (Open Drain) PFI Power Fail Input RST PFO Power Fail Output IRQ/FT/OUT RST Reset Output (Open Drain) SQW RSTIN Reset Input PFO SCL Serial Clock Input SDA Serial Data Input/Output SQW Square Wave Output WDI Watchdog Input VCC Supply Voltage VBAT (1) Battery Supply Voltage VSS Ground (1) (1) (1) SCL SDA M41ST84Y M41ST84W RSTIN WDI PFI VSS AI03677 Note: 1. For SO16 package only. Note: 1. For SO16 package only. Figure 3. 16-pin SOIC Connections Figure 4. 28-pin SOIC Connections XI XO RST WDI RSTIN PFO VBAT VSS 1 16 2 15 3 14 4 M41ST84Y 13 5 M41ST84W 12 6 11 7 10 8 9 AI03678 VCC NC IRQ/FT/OUT NC PFI SQW SCL SDA SQW NC NC NC NC NC NC WDI RSTIN NC NC NC PFO VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 M41ST84Y 22 8 M41ST84W 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC NC IRQ/FT/OUT NC NC NC PFI NC SCL NC RST NC SDA NC AI03679 5/32 M41ST84Y, M41ST84W Figure 5. Block Diagram REAL TIME CLOCK CALENDAR SDA 44 BYTES USER RAM I2C INTERFACE RTC w/ALARM & CALIBRATION SCL WATCHDOG 32KHz OSCILLATOR Crystal SQUARE WAVE WDI VCC AF WDF IRQ/FT/OUT(1) SQW POWER VBAT VBL= 2.5V COMPARE VSO= 2.5V COMPARE VPFD= 4.4V COMPARE (2.75V for ST84W) RSTIN BL POR RST(1) PFI 1.25V Note: 1. Open drain output 6/32 COMPARE PFO AI03931 M41ST84Y, M41ST84W Figure 6. Hardware Hookup Regulator Unregulated Voltage VCC From MCU VIN VCC IRQ/FT/OUT SCL SDA WDI RST RSTIN SQW To INT RST To LED Display R1 PFI R2 VSS PFO To NMI AI03680 7/32 M41ST84Y, M41ST84W OPERATING MODES The M41ST84Y/W clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 64 bytes contained in the device can then be accessed sequentially in the following order: 1. Tenths/Hundredths of a Second Register 2. Seconds Register 3. Minutes Register 4. Century/Hours Register 5. Day Register 6. Date Register 7. Month Register 8. Year Register 9. Control Register 10. Watchdog Register 11 - 16. Alarm Registers 17 - 19. Reserved 20. Square Wave Register 21 - 64. User RAM The M41ST84Y/W clock continually monitors VCC for an out-of tolerance condition. Should VCC fall below VPFD, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. When VCC falls below VSO, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD plus tREC. For more information on Battery Storage Life refer to Application Note AN1012. 2-Wire Bus Characteristics The bus is intended for communication between different IC's. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is High. 8/32 - Changes in the data line, while the clock line is High, will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy. Both data and clock lines remain High. Start data transfer. A change in the state of the data line, from High to Low, while the clock is High, defines the START condition. Stop data transfer. A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition. Data Valid. The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter", the receiving device that gets the message is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves". Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition. M41ST84Y, M41ST84W Figure 7. Serial Bus Data Transfer Sequence DATA LINE STABLE DATA VALID CLOCK DATA START CONDITION CHANGE OF DATA ALLOWED STOP CONDITION AI00587 Figure 8. Acknowledgement Sequence CLOCK PULSE FOR ACKNOWLEDGEMENT START SCL FROM MASTER DATA OUTPUT BY TRANSMITTER 1 MSB 2 8 9 LSB DATA OUTPUT BY RECEIVER AI00601 9/32 M41ST84Y, M41ST84W Figure 9. Bus Timing Requirements Sequence SDA tBUF tHD:STA tHD:STA tR tF SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR tSU:STO P AI00589 Table 2. AC Characteristics Symbol Parameter fSCL SCL Clock Frequency tBUF Time the bus must be free before a new transmission can start tF Min Max Unit 0 400 kHz s 1.3 SDA and SCL Fall Time 300 ns 0 s START Condition Hold Time (after this period the first clock pulse is generated) 600 ns tHIGH Clock High Period 600 ns tLOW Clock Low Period 1.3 s tHD:DAT Data Hold Time tHD:STA tR tSU:DAT (1) SDA and SCL Rise Time 300 ns Data Setup Time 100 ns tSU:STA START Condition Setup Time (only relevant for a repeated start condition) 600 ns tSU:STO STOP Condition Setup Time 600 ns Note: 1. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL. 10/32 M41ST84Y, M41ST84W Read Mode In this mode the master reads the M41ST84Y/W slave after setting the slave address (see Figure 10, page 12). Following the write mode control bit (R/W=0) and the acknowledge bit, the word address `An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ mode control bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge bit. The M41ST84Y/W slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter (see Figure 11, page 12). The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer increments to a RAM address. An alternate READ mode may also be implemented whereby the master reads the M41ST84Y/W slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 12, page 12). Write Mode In this mode the master transmitter transmits to the M41ST84Y/W slave receiver. Bus protocol is shown in Figure Figure 13, page 13. Following the START condition and slave address, a logic `0' (R/ W=0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge clock. The M41ST84Y/W slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address (see Figure 10, page 12) and again after it has received the word address and each data byte. Data Retention Mode With valid VCC applied, the M41ST84Y/W can be accessed as described above with read or write cycles. Should the supply voltage decay, the M41ST84Y/W will automatically deselect, write protecting itself when VCC falls between VPFD (max) and VPFD (min). This is accomplished by internally inhibiting access to the clock registers. At this time, the Reset pin (RST) is driven active and will remain active until VCC returns to nominal levels. When VCC falls below the Battery Back-up Switchover Voltage (VSO), power input is switched from the VCC pin to the SNAPHAT (or external) battery and the clock registers and SRAM are maintained from the attached battery supply. All outputs become high impedance. On power up, when VCC returns to a nominal value, write protection continues for tREC. The RST signal also remains active during this time (see Figure 21, page 25). For a further more detailed review of lifetime calculations, please see Application Note AN1012. Battery Low Warning The M41ST84Y/W automatically performs battery voltage monitoring upon power-up and at factoryprogrammed time intervals of approximately 24 hours. The Battery Low (BL) bit, Bit D4 of Flags Register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. The SNAPHAT top may be replaced while VCC is applied to the device. Note: This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is disconnected. The M41ST84Y/W only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. 11/32 M41ST84Y, M41ST84W Figure 10. Slave Address Location R/W SLAVE ADDRESS 1 A LSB MSB START 1 0 1 0 0 0 AI00602 ACK DATA n+1 ACK DATA n S ACK BUS ACTIVITY: R/W START R/W WORD ADDRESS (n) S ACK SDA LINE ACK BUS ACTIVITY: MASTER START Figure 11. Read Mode Sequences SLAVE ADDRESS STOP SLAVE ADDRESS P NO ACK DATA n+X AI00899 ACK DATA n+X P NO ACK SLAVE ADDRESS DATA n+1 ACK DATA n BUS ACTIVITY: 12/32 STOP R/W S ACK SDA LINE ACK BUS ACTIVITY: MASTER START Figure 12. Alternate Read Mode Sequences AI00895 M41ST84Y, M41ST84W STOP R/W SLAVE ADDRESS DATA n+X P ACK DATA n+1 ACK BUS ACTIVITY: DATA n ACK WORD ADDRESS (n) S ACK SDA LINE ACK BUS ACTIVITY: MASTER START Figure 13. Write Mode Sequence AI00591 13/32 M41ST84Y, M41ST84W CLOCK OPERATION The eight byte clock register (see Figure 3, page 15) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained within the first four registers. Bits D6 and D7 of clock register 3 (Century/Hours Register) contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a `1' will cause CB to toggle, either from `0' to `1' or from `1' to `0' at the turn of the century (depending upon its initial state). If CEB is set to a `0', CB will not toggle. Bits D0 through D2 of register 4 contain the Day (day of week). Registers 5, 6 and 7 contain the Date (day of month), Month and Years. The ninth clock register is the Control Register (this is described in the Clock Calibration section). Bit D7 of register 1 contains the STOP Bit (ST). Setting this bit to a `1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a `0' the oscillator restarts within one second. The eight Clock Registers may be read one byte at a time, or in a sequential block. The Control Register (Address location 08h) may be accessed independently. Provision has been made to assure 14/32 that a clock update does not occur while any of the seven clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the read. Note: Upon power-up following a power failure, the HT bit will automatically be set to a `1'. This will prevent the clock from updating the TIMEKEEPER registers, and will allow the user to read the exact time of the power-down event. Resetting the HT bit to a `0' will allow the clock to update the TIMEKEEPER registers with the current time. TIMEKEEPER Registers The M41ST84Y/W offers 12 additional internal registers which contain the Alarm, Watchdog, Flag, Square Wave and Control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. TIMEKEEPER and Alarm Registers store data in BCD. Control, Watchdog and Square Wave Registers store data in Binary Format. M41ST84Y, M41ST84W Table 3. TIMEKEEPER Register Map Data Address D7 00h D6 D5 D4 D3 D2 0.1 Seconds D1 D0 Function/Rang e BCD Format 0.01 Seconds Seconds 00-99 01h ST 10 Seconds Seconds Seconds 00-59 02h 0 10 Minutes Minutes Minutes 00-59 03h CEB CB Hours (24 Hour Format) Century/Hour 0-1/00-23 04h 0 0 Day 01-7 05h 0 0 Date: Day of Month Date 01-31 06h 0 0 Month Month 01-12 Year Year 00-99 07h 10 Hours 0 0 0 10 Date 0 Day of Week 10M 10 Years 08h OUT FT S Calibration 09h WDS BMB4 BMB3 BMB2 0Ah AFE SQWE ABE Al 10M 0Bh RPT4 RPT5 0Ch RPT3 HT 0Dh RPT2 0Eh RPT1 0Fh WDF AF 0 BL 0 0 0 0 Flags 10h 0 0 0 0 0 0 0 0 Reserved 11h 0 0 0 0 0 0 0 0 Reserved 12h 0 0 0 0 0 0 0 0 Reserved 13h RS3 RS2 RS1 RS0 0 0 0 0 SQW BMB1 BMB0 Control RB1 RB0 Watchdog Alarm Month Al Month 01-12 AI 10 Date Alarm Date Al Date 01-31 AI 10 Hour Alarm Hour Al Hour 00-23 Alarm 10 Minutes Alarm Minutes Al Min 00-59 Alarm 10 Seconds Alarm Seconds Al Sec 00-59 Keys: S = Sign Bit FT = Frequency Test Bit ST = Stop Bit 0 = Must be set to zero BL = Battery Low Flag BMB0-BMB4 = Watchdog Multiplier Bits CEB = Century Enable Bit CB = Century Bit OUT = Output level AFE = Alarm Flag Enable Flag RB0-RB1 = Watchdog Resolution Bits WDS = Watchdog Steering Bit ABE = Alarm in Battery Back-Up Mode Enable Bit RPT1-RPT5 = Alarm Repeat Mode Bits WDF = Watchdog flag AF = Alarm flag SQWE = Square Wave Enable RS0-RS3 = SQW Frequency HT = Halt Update Bit 15/32 M41ST84Y, M41ST84W Setting Alarm Clock Registers Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every year, month, day, hour, minute, or second. It can also be programmed to go off while the M41ST84Y/W is in the battery back-up to serve as a system wake-up call. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 4, page 17 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT/OUT pin. The IRQ/FT/ OUT output is cleared by a read to the Flags register. This read of the Flags register will also reset the Alarm Flag (D6; Register 0Fh). The IRQ/FT/OUT pin can also be activated in the battery back-up mode. The IRQ/FT/OUT will go low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the Flag Register at system boot-up to determine if an alarm was generated while the M41ST84Y/W was in the deselect mode during power-up. Figure 14 illustrates the back-up mode alarm timing. Figure 14. Back-Up Mode Alarm Waveform VCC VPFD VSO tREC AFE bit in Interrupt Register AF bit in Flags Register IRQ/FT/OUT HIGH-Z HIGH-Z AI03920 16/32 M41ST84Y, M41ST84W Figure 15. Alarm Interrupt Reset Waveforms 0Eh 0Fh 10h ACTIVE FLAG HIGH-Z IRQ/FT/OUT AI03664 Table 4. Alarm Repeat Modes RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting 1 1 1 1 1 Once per Second 1 1 1 1 0 Once per Minute 1 1 1 0 0 Once per Hour 1 1 0 0 0 Once per Day 1 0 0 0 0 Once per Month 0 0 0 0 0 Once per Year Watchdog Timer The watchdog timer can be used to detect an outof-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the Watchdog Register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The amount of timeout is then determined to be the multiplication of the five bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3*1 or 3 seconds). If the processor does not reset the timer within the specified period, the M41ST84Y/W sets the WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. Note: If the Square Wave function is enabled, the accuracy of the Watchdog Timer will be a function of the selected resolution. The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS). When set to a `0', the watchdog will activate the IRQ/FT/OUT pin when timed-out. When WDS is set to a `1', the watchdog will output a negative pulse on the RST pin for tREC. The Watchdog register, FT, AFE, ABE and SQWE Bits will reset to a `0' at the end of a Watchdog time-out when the WDS bit is set to a `1'. The watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high) can be applied to the Watchdog Input pin (WDI) or 2) the microprocessor can perform a write of the Watchdog Register. The time-out period then starts over. Note: The WDI pin should be tied to VSS if not used. In order to perform a software reset of the watchdog timer, the original time-out period can be written into the Watchdog Register, effectively restarting the count-down cycle. Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt, a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ/FT/OUT pin. This will also disable the watchdog function until it is again programmed correctly. A read of the Flags Register will reset the Watchdog Flag (Bit D7; Register 0Fh). The watchdog function is automatically disabled upon power-up and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ/FT/OUT pin and the frequency test function is activated, the watchdog function prevails and the frequency test function is denied. The OUT function has the lowest priority and will only be enabled when the Watchdog Register (09h), AFE Bit and FT Bit are `0'. 17/32 M41ST84Y, M41ST84W Square Wave Output The M41ST84Y/W offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These fre- quencies are listed in Table 5. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the Square Wave Enable Bit (SQWE) located in Register 0Ah. Table 5. Square Wave Output Frequency Square Wave Bits 18/32 Square Wave RS3 RS2 RS1 RS0 Frequency Units 0 0 0 0 None - 0 0 0 1 32.768 kHz 0 0 1 0 8.192 kHz 0 0 1 1 4.096 kHz 0 1 0 0 2.048 kHz 0 1 0 1 1.024 kHz 0 1 1 0 512 Hz 0 1 1 1 256 Hz 1 0 0 0 128 Hz 1 0 0 1 64 Hz 1 0 1 0 32 Hz 1 0 1 1 16 Hz 1 1 0 0 8 Hz 1 1 0 1 4 Hz 1 1 1 0 2 Hz 1 1 1 1 1 Hz M41ST84Y, M41ST84W Power-on Reset The M41ST84Y/W continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC passes VPFD. The RST pin is an open drain output and an appropriate pull-up resistor should be chosen to control rise time. Reset Input (RSTIN) The M41ST84Y/W provides an independent input which can generate an output reset. The duration and function of this reset is identical to a reset generated by a power cycle. Table 6, page 19 and Figure 16, page 19 illustrate the AC reset characteristics of this function. Pulses shorter than tRLRH will not generate a reset condition. RSTIN is internally pulled up to VCC through a 100k resistor. Figure 16. RSTIN Timing Waveform RSTIN tRLRH RST (1) tRHRSH Note: 1. With pull-up resistor AI03682 Table 6. Reset AC Characteristics Symbol tRLRH (1) tRHRSH (2) Parameter Min RSTIN Low to RSTIN High 200 RSTIN High to RST High 40 Max Unit ns 200 ms Note: VCC = 2.7 to 5.5V 1. Pulse width less than 50ns will result in no RESET (for noise immunity). 2. CL = 5pF (see Figure 19, page 23). 19/32 M41ST84Y, M41ST84W Power-fail INPUT/OUTPUT The Power-Fail Input (PFI) is compared to an internal reference voltage (independent from the VPFD comparator). If PFI is less than the power-fail threshold (VPFI), the Power-Fail Output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure 6, page 7) to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the M41ST84Y/W or the microprocessor drops below the minimum operating voltage. During battery back-up, the power-fail comparator turns off and PFO goes (or remains) low. This occurs after VCC drops below VPFD(min). When power returns, PFO is forced high, irrespective of VPFI for the write protect time (tREC), which is the time from VPFD(max) until the inputs are recognized. At the end of this time, the power-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. Calibrating the Clock The M41ST84Y/W is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed +/-35 PPM (parts per million) oscillator frequency error at 25 oC, which equates to about +/-1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than +1/-2 PPM at 25C. The oscillation rate of crystals changes with temperature (see Figure 17, page 21). Therefore, the M41ST84Y/W design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 18, page 21. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bits occupy the five lower order bits (D4-D0) in the Control Register (8h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; `1' indicates positive calibration, `0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once 20/32 per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary `1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 PPM of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41ST84Y/W may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Application Note AN934: TIMEKEEPER CALIBRATION. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT/OUT pin. The pin will toggle at 512Hz, when the Stop bit (ST, D7 of 1h) is `0',the Frequency Test bit (FT, D6 of 8h) is `1', the Alarm Flag Enable bit (AFE, D7 of Ah) is `0', and the Watchdog Steering bit (WDS, D7 of 9h) is `1' or the Watchdog Register (9h=0) is reset. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 PPM oscillator frequency error, requiring a -10 (XX001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. The IRQ/FT/OUT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500 to 10k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down. M41ST84Y, M41ST84W Output Driver Pin When the FT bit, AFE bit and watchdog register are not set, the IRQ/FT/OUT pin becomes an output driver that reflects the contents of D7 of the Control Register. In other words, when D6 of location 08h is a `0', D7 of location 08h and 0Ah and the watchdog register are a `0' then the IRQ/FT/ OUT pin will be driven low. Note: The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor. Initial Power-on Defaults Upon initial application of power to the device, the following register bits are set to a `0' state: Watchdog Register; FT; AFE; ABE and SQWE. The following bits are set to a `1' state: ST; OUT; and HT. Century Bit Bits D7 and D6 of Clock Register 03h contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a "1" will cause CB to toggle, either from a "0" to "1" or from "1" to "0" at the turn of the century (depending upon its initial state). If CEB is set to a "0", CB will not toggle. Figure 17. Crystal Accuracy Across Temperature Frequency (ppm) 20 0 -20 -40 -60 -80 -100 F = -0.038 ppm (T - T )2 10% 0 F C2 -120 T 0 = 25 C -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature C AI00999 Figure 18. Clock Calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B 21/32 M41ST84Y, M41ST84W MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7. Absolute Maximum Ratings Symbol TSTG TSLD (1) Parameter Storage Temperature (VCC Off, Oscillator Off) Value Unit SNAPHAT -40 to 85 C SOIC -55 to 125 C 260 C -0.3 to VCC + 0.3 V M41ST84Y -0.3 to 7.0 V M41ST84W -0.3 to 4.6 V Lead Solder Temperature for 10 seconds V IO Input or Output Voltages VCC Supply Voltage IO Output Current 20 mA PD Power Dissipation 1 W Note: 1. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPH AT sockets. 22/32 M41ST84Y, M41ST84W DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 8. DC and AC Measurement Conditions Parameter M41ST84Y M41ST84W VCC Supply Voltage 4.5 to 5.5V 2.8 to 3.6V Ambient Operating Temperature -40 to 85C -40 to 85C Load Capacitance (CL) 100pF 50pF Input Rise and Fall Times 50ns 50ns Input Pulse Voltages 0.2 to 0.8VCC 0.2 to 0.8VCC Input and Output Timing Ref. Voltages 0.3 to 0.7VCC 0.3 to 0.7VCC Figure 19. AC Testing Load Circuit Figure 20. AC Testing Input/Output Waveforms 645 DEVICE UNDER TEST 0.8VCC CL=100pF(1) or 50pF 1.75V 0.7VCC 0.3VCC 0.2VCC AI02568 CL includes JIG capacitance AI03916 Note: 1. CL = 100pF for the M41ST84Y, 50pF for the M41ST84W Table 9. Capacitance Symbol C IN CIO (1) tLP Parameter Min Max Unit Input Capacitance 7 pF Input / Output Capacitance 10 pF Low-pass filter input time constant (SDA and SCL) 50 ns Note: Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. 1. Outputs deselected. 23/32 M41ST84Y, M41ST84W Table 10. DC Characteristics Symbol Parameter Test Condition Battery Current OSC ON Min TA = 25C, VCC = 0V, VBAT = 3V IBAT Battery Current OSC OFF Typ Max Unit 400 500 nA 50 nA M41ST84Y ICC1 Supply Current ICC2 Supply Current (Standby) M41ST84W ILI (1,2) ILO (1) 1.4 mA 750 A 1 mA 500 A 1 A 25 nA 1 A f = 400kHz M41ST84Y M41ST84W SCL, SDA = VCC - 0.3V Input Leakage Current 0V VIN V CC Input Leakage Current (PFI) 0V VIN V CC -25 2 0V VOUT VCC Output Leakage Current VIH Input High Voltage 0.7V CC VCC + 0.3 V VIL Input Low Voltage -0.3 0.3VCC V VBAT Battery Voltage VOH Output High Voltage IOH = -1.0mA Output Low Voltage IOL = 3.0mA 0.4 V Output Low Voltage (Open Drain)(3) IOL = 10mA 0.4 V VOL 3.0 V 2.4 V M41ST84Y 4.30 4.40 4.50 V M41ST84W 2.70 2.75 2.80 V 1.225 1.250 1.275 V VPFD Power Fail Deselect VPFI PFI Input Threshold VSO Battery Back-up Switchover 2.5 V Note: 1. Outputs deselected. 2. RSTIN internally pulled-up to VCC through 100K resistor. WDI internally pulled-down to VSS through 100K resistor. 3. For IRQ/FT/OU T, RST pins (Open Drain). Table 11. Crystal Electrical Characteristics (Externally Supplied) Symbol Parameter f0 Resonant Frequency RS Series Resistance CL Load Capacitance Typ Min Max 32.768 Unit kHz 60 12.5 k pF Note: 1. Load capacitors are integrated within the M41ST84Y/W. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. STMicroelectronics recommends the KDS DT-38 Tuning Fork Type (thru-hole) or DMX-26 (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 24/32 M41ST84Y, M41ST84W Figure 21. Power Down/Up Mode AC Waveforms VCC VPFD (max) VPFD (min) VSO tF tR tFB tRB tDR tREC PFO INPUTS RECOGNIZED RECOGNIZED DON'T CARE RST HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) AI03681 Table 12. Power Down/Up AC Characteristics Symbol Parameter Min Typ Max Unit tF (1) V PFD (max) to VPFD (min) VCC Fall Time 300 s tFB (2) V PFD (min) to VSS VCC Fall Time 10 s tPFD PFI to PFO Propagation Delay 15 25 s tR V PFD (min) to VPFD (max) VCC Rise Time 10 s tRB V SS to VPFD (min) VCC Rise Time 1 s tREC Power up Deselect Time 40 tDR Expected Data Retention Time 10 (3) 200 ms YEARS Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. 3. At 25C (when using SOH28 + M4T28-BR12SH SNAPH AT top). 25/32 M41ST84Y, M41ST84W PACKAGE MECHANICAL Figure 22. SO16 - 16 lead Plastic Small Outline, Package Outline A2 A C B CP e D N E H 1 A1 L SO-b Note: Drawing is not to scale. Table 13. SO16 - 16 lead Plastic Small Outline, Package Mechanical Data mm inches Symbol Typ. Min. A Typ. Min. 1.75 A1 0.10 A2 Max. 0.069 0.25 0.004 1.60 0.010 0.063 B 0.35 0.46 0.014 0.018 C 0.19 0.25 0.007 0.010 D 9.80 10.00 0.386 0.394 E 3.80 4.00 0.150 0.158 - - - - H 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 a 0 8 0 8 N 16 e CP 26/32 Max. 1.27 0.050 16 0.10 0.004 M41ST84Y, M41ST84W Figure 23. SOH28 - 28 lead Plastic Small Outline, Battery SNAPHAT, Package Outline A2 A C B eB e CP D N E H A1 L 1 SOH-A Note: Drawing is not to scale. Table 14. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 3.05 Max 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 - - - - eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 0 8 0 8 N 28 e CP 1.27 0.050 28 0.10 0.004 27/32 M41ST84Y, M41ST84W Figure 24. SH - SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline A1 A2 A eA A3 B L eB D E SHTK-A Note: Drawing is not to scale. Table 15. SH - SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data millimeters inches Symbol Typ Min A Typ Min 9.78 Max 0.3850 A1 6.73 7.24 0.2650 0.2850 A2 6.48 6.99 0.2551 0.2752 A3 28/32 Max 0.38 0.0150 B 0.46 0.56 0.0181 0.0220 D 21.21 21.84 0.8350 0.8598 E 14.22 14.99 0.5598 0.5902 eA 15.55 15.95 0.6122 0.6280 eB 3.20 3.61 0.1260 0.1421 L 2.03 2.29 0.0799 0.0902 M41ST84Y, M41ST84W Figure 25. SH - SNAPHAT Housing for 120 mAh Battery & Crystal, Package Outline A1 A2 A eA A3 B L eB D E SHTK-A Note: Drawing is not to scale. Table 16. SH - SNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 10.54 Max 0.4150 A1 6.73 7.24 0.2650 0.2850 A2 6.48 6.99 0.2551 0.2752 A3 0.38 0.0150 B 0.46 0.56 0.0181 0.0220 D 21.21 21.84 0.8350 0.8598 E 14.22 14.99 0.5598 0.5902 eA 15.55 15.95 0.6122 0.6280 eB 3.20 3.61 0.1260 0.1421 L 2.03 2.29 0.0799 0.0902 29/32 M41ST84Y, M41ST84W PART NUMBERING Table 17. Ordering Information Scheme Example: M41ST 84Y -70 MH 6 TR Device Type M41ST Supply Voltage and Write Protect Voltage 84Y = V CC = 4.5 to 5.5V; VPFD = 4.3 to 4.5V 84W = VCC = 2.8 to 3.6V; VPFD = 2.7 to 2.8V Speed 70 = 70ns 85 = 85ns Package MQ = SO16 MH (1) = SOH28 Temperature Range 6 = -40 to 85 C Shipping Method for SOIC blank = Tubes TR = Tape & Reel Note: 1. The 28-pin SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part number "M4TXX-BR12SHX" in plastic tube or "M4TXX-BR12SHXTR" in Tape & Reel form. Caution: Do not place the SNAPHAT battery package "M4TXX-BR12SH" in conductive foam since will drain the lithium button-cell battery. For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 18. SNAPHAT Battery Table Part Number Description Package M4T28-BR12SH Lithium Battery (48mAh) and Crystal SNAPHAT SH M4T32-BR12SH Lithium Battery (120mAh) and Crystal SNAPHAT SH 30/32 M41ST84Y, M41ST84W REVISION HISTORY Table 19. Document Revision History Date Revision Details August 2000 First Issue 08/24/00 Block Diagram added (Figure 5) 09/08/00 SO16 package measures change 12/18/00 Reformatted, TOC added, and PFI Input Leakage Current added (Table 10) 31/32 M41ST84Y, M41ST84W Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . www.st.com 32/32