ADC104S021/ADC104S021Q 4 Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter General Description Features The ADC104S021/ADC104S021Q is a low-power, four-channel CMOS 10-bit analog-to-digital converter with a highspeed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC104S021/ADC104S021Q is fully specified over a sample rate range of 50 ksps to 200 ksps. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to four input signals at inputs IN1 through IN4. The output serial data is straight binary, and is compatible with several standards, such as SPITM, QSPITM, MICROWIRE, and many common DSP serial interfaces. The ADC104S021/ADC104S021Q operates with a single supply, that can range from +2.7V to +5.25V. Normal power consumption using a +3V or +5V supply is 1.94 mW and 6.9 mW, respectively. The power-down feature reduces the power consumption to just 0.12 W using a +3V supply, or 0.47 W using a +5V supply. The ADC104S021/ADC104S021Q is packaged in a 10-lead MSOP package. Operation over the industrial temperature range of -40C to +85C is guaranteed. Specified over a range of sample rates. Four input channels Variable power management Single power supply with 2.7V - 5.25V range ADC104S021Q is AEC-Q100 Grade 3 qualified and is manufactured on an Automotive Grade flow Meets AEC-Q100-011 C2 CDM classification Key Specifications DNL INL SNR Power Consumption -- 3V Supply -- 5V Supply 0.13 LSB (typ) 0.13 LSB (typ) 61.8 dB (typ) 1.94 mW (typ) 6.9 mW (typ) Applications Portable Systems Remote Data Acquisition Instrumentation and Control Systems Automotive Pin-Compatible Alternatives by Resolution and Speed All devices are fully pin and function compatible. Resolution Specified for Sample Rate Range of: 50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps 12-bit ADC124S021 ADC124S051 ADC124S101 10-bit ADC104S021/ ADC104S021Q ADC104S051 ADC104S101 8-bit ADC084S021 ADC084S051 ADC084S101 Connection Diagram 20124405 TRI-STATE(R) is a trademark of National Semiconductor Corporation QSPITM and SPITM are trademarks of Motorola, Inc. (c) 2012 Texas Instruments Incorporated 201244 SNAS278G www.ti.com ADC104S021/ADC104S021Q 4 Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter April 19, 2012 ADC104S021/ADC104S021Q Ordering Information Temperature Range Description Top Mark ADC104S021CIMM Order Code -40C to +85C 10-Lead MSOP Package X20C ADC104S021CIMMX -40C to +85C 10-Lead MSOP Package, Tape & Reel X20C ADC104S021QIMM -40C to +85C 10-Lead MSOP Package, AEC-Q100 (Note 11) Q20C ADC104S021QIMMX -40C to +85C 10-Lead MSOP Package, Tape & Reel AEC-Q100 (Note 11) Q20C ADC104S021EVAL Evaluation Board Block Diagram 20124407 Pin Descriptions and Equivalent Circuits Pin No. Symbol Description ANALOG I/O 4-7 IN1 to IN4 Analog inputs. These signals can range from 0V to VA. DIGITAL I/O 10 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 9 DOUT Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. 8 DIN Digital data input. The ADC104S021/ADC104S021Q's Control Register is loaded through this pin on rising edges of the SCLK pin. 1 CS Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low. 2 VA Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with a 1 F capacitor and a 0.1 F monolithic capacitor located within 1 cm of the power pin. 3 GND POWER SUPPLY www.ti.com The ground return for supply and signals. 2 Operating Temperature Range 2) Junction Temperature Storage Temperature -40C TA +85C VA Supply Voltage If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Supply Voltage VA Voltage on Any Pin to GND Input Current at Any Pin (Note 3) Package Input Current(Note 3) Power Consumption at TA = 25C ESD Susceptibility (Note 5) Human Body Model Machine Model Charged Device Model (Note 1, Note 2) +2.7V to +5.25V -0.3V to VA 50 kHz to 16 MHz 0V to VA Digital Input Pins Voltage Range Clock Frequency Analog Input Voltage -0.3V to 6.5V -0.3V to VA +0.3V 10 mA 20 mA See (Note 4) Package Thermal Resistance Package JA 10-lead MSOP 190C / W Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) 2500V 250V 500V +150C -65C to +150C ADC104S021/ADC104S021Q Converter Electrical Characteristics (Note 9) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25C. Symbol Parameter Conditions Typical Limits (Note 7) Units 10 Bits +0.3 LSB (max) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL Integral Non-Linearity 0.13 DNL Differential Non-Linearity VOFF OEM -0.4 LSB (min) 0.13 0.4 LSB (max) Offset Error +0.1 0.4 LSB (max) Channel to Channel Offset Error Match 0.02 0.5 LSB (max) FSE Full-Scale Error -0.1 0.7 LSB (max) FSEM Channel to Channel Full-Scale Error Match +0.02 0.5 LSB (max) DYNAMIC CONVERTER CHARACTERISTICS SINAD Signal-to-Noise Plus Distortion Ratio VA = +2.7 to 5.25V fIN = 39.9 kHz, -0.02 dBFS 61.8 61 dB (min) SNR Signal-to-Noise Ratio VA = +2.7 to 5.25V fIN = 39.9 kHz, -0.02 dBFS 61.8 61.3 dB (min) THD Total Harmonic Distortion VA = +2.7 to 5.25V fIN = 39.9 kHz, -0.02 dBFS -86 -72 dB (max) SFDR Spurious-Free Dynamic Range VA = +2.7 to 5.25V fIN = 39.9 kHz, -0.02 dBFS 82 75 dB (min) ENOB Effective Number of Bits VA = +2.7 to 5.25V fIN = 39.9 kHz, -0.02 dBFS 9.9 9.8 Bits (min) Channel-to-Channel Crosstalk VA = +5.25V fIN = 39.9 kHz -87 dB Intermodulation Distortion, Second Order Terms VA = +5.25V fa = 40.161 kHz, fb = 41.015 kHz -82 dB Intermodulation Distortion, Third Order VA = +5.25V Terms fa = 40.161 kHz, fb = 41.015 kHz -81 dB VA = +5V 11 MHz VA = +3V 8 MHz IMD FPBW -3 dB Full Power Bandwidth 3 www.ti.com ADC104S021/ADC104S021Q Operating Ratings Absolute Maximum Ratings (Note 1, Note ADC104S021/ADC104S021Q Symbol Parameter Conditions Typical Limits (Note 7) Units 1 A (max) ANALOG INPUT CHARACTERISTICS VIN Input Range IDCL DC Leakage Current CINA Input Capacitance 0 to VA V Track Mode 33 pF Hold Mode 3 pF DIGITAL INPUT CHARACTERISTICS VIH Input High Voltage VIL Input Low Voltage IIN Input Current CIND Digital Input Capacitance VA = +5.25V 2.4 V (min) VA = +3.6V 2.1 V (min) 0.8 V (max) 0.1 10 A (max) 2 4 pF (max) ISOURCE = 200 A VA - 0.03 VA - 0.5 V (min) ISOURCE = 1 mA VA - 0.1 ISINK = 200 A 0.03 ISINK = 1 mA 0.1 VIN = 0V or VA DIGITAL OUTPUT CHARACTERISTICS VOH Output High Voltage VOL Output Low Voltage IOZH, IOZL TRI-STATE(R) Leakage Current COUT TRI-STATE(R) Output Capacitance V 0.4 V (max) V 0.01 1 A (max) 2 4 pF (max) Output Coding Straight (Natural) Binary POWER SUPPLY CHARACTERISTICS (CL = 10 pF) VA Supply Voltage Supply Current, Normal Mode (Operational, CS low) IA V (min) V (max) VA = +5.25V, fSAMPLE = 200 ksps, fIN = 40 kHz 1.3 1.8 mA (max) VA = +3.6V, fSAMPLE = 200 ksps, fIN = 40 kHz 0.55 0.7 mA (max) VA = +5.25V, fSAMPLE = 0 ksps 90 nA VA = +3.6V, fSAMPLE = 0 ksps 32 nA Power Consumption, Normal Mode (Operational, CS low) VA = +5.25V 6.9 9.5 mW (max) VA = +3.6V 1.94 2.5 mW (max) Power Consumption, Shutdown (CS high) VA = +5.25V 0.47 W VA = +3.6V 0.12 W Supply Current, Shutdown (CS high) PD 2.7 5.25 AC ELECTRICAL CHARACTERISTICS fSCLK Clock Frequency (Note 8) fS Sample Rate (Note 8) tCONV Conversion Time DC SCLK Duty Cycle fSCLK = 3.2 MHz tACQ Track/Hold Acquisition Time Throughput Time www.ti.com 0.8 MHz (min) 3.2 MHz (max) 50 ksps (min) 200 ksps (max) 13 SCLK cycles 30 % (min) 70 % (max) Full-Scale Step Input 3 SCLK cycles Acquisition Time + Conversion Time 16 SCLK cycles 4 50 The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25C. Symbol Parameter Conditions tCSU Setup Time SCLK High to CS Falling Edge (Note 10) tCLH Hold time SCLK Low to CS Falling Edge (Note 10) tEN Delay from CS Until DOUT active tACC Data Access Time after SCLK Falling Edge tSU Data Setup Time Prior to SCLK Rising Edge tH Data Valid SCLK Hold Time tCH SCLK High Pulse Width tCL SCLK Low Pulse Width Units 10 ns (min) 10 ns (min) 30 ns (max) 30 ns (max) +3 10 ns (min) +3 10 ns (min) VA = +3.0V -3.5 VA = +5.0V -0.5 VA = +3.0V +4.5 VA = +5.0V +1.5 VA = +3.0V +4 VA = +5.0V +2 VA = +3.0V +16.5 VA = +5.0V +15 0.5 x tSCLK 0.3 x tSCLK ns (min) 0.5 x tSCLK 0.3 x tSCLK ns (min) Output Falling tDIS Limits (Note 7) Typical CS Rising Edge to DOUT High-Impedance Output Rising VA = +3.0V 1.7 VA = +5.0V 1.2 VA = +3.0V 1.0 VA = +5.0V 1.0 20 ns (max) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (JA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax - TA) / JA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k resistor. Machine model is 220 pF discharged through zero ohms. Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under Operating Ratings. Note 9: Min/max specification limits are guaranteed by design, test, or statistical analysis. Note 10: Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed. Note 11: PPAP (Production part Approval Process) documentation of the device technology, process and qualification is available from Texas Instruments upon request. 5 www.ti.com ADC104S021/ADC104S021Q ADC104S021/ADC104S021Q Timing Specifications ADC104S021/ADC104S021Q Timing Diagrams 20124408 Timing Test Circuit 20124451 ADC104S021/ADC104S021Q Operational Timing Diagram 20124406 ADC104S021/ADC104S021Q Serial Timing Diagram 20124450 SCLK and CS Timing Parameters www.ti.com 6 ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion. CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy from one analog input that appears at the measured analog input. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 11/2 LSB below VREF+ and is defined as: VFSE = Vmax + 1.5 LSB - VREF+ where Vmax is the voltage at which the transition to the maximum code occurs. FSE can be expressed in Volts, LSB or percent of full scale range. GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5 LSB), after adjusting for offset error. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (1/2 LSB below the first code transition) through positive full scale (1/2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies. THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the acquisition time plus the conversion and read out times. In the case of the ADC104S021/ADC104S021Q, this is 16 SCLK periods. 7 www.ti.com ADC104S021/ADC104S021Q INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third order intermodulation products to the power in one of the original frequencies. IMD is usually expressed in dB. MISSING CODES are those output codes that will never appear at the ADC outputs. These codes cannot be reached with any input value. The ADC104S021/ADC104S021Q is guaranteed not to have any missing codes. OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB). SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal where a spurious signal is any signal present in the output spectrum that is not present at the input, excluding d.c. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as Specification Definitions ADC104S021/ADC104S021Q Typical Performance Characteristics TA = +25C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. DNL - VA = 3.0V INL - VA = 3.0V 20124420 20124421 DNL - VA = 5.0V INL - VA = 5.0V 20124462 20124463 DNL vs. Supply INL vs. Supply 20124422 www.ti.com 20124423 8 ADC104S021/ADC104S021Q DNL vs. Clock Frequency INL vs. Clock Frequency 20124424 20124425 DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle 20124426 20124427 DNL vs. Temperature INL vs. Temperature 20124428 20124429 9 www.ti.com ADC104S021/ADC104S021Q SNR vs. Supply THD vs. Supply 20124430 20124435 SNR vs. Clock Frequency THD vs. Clock Frequency 20124431 20124436 SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle 20124432 www.ti.com 20124437 10 ADC104S021/ADC104S021Q SNR vs. Input Frequency THD vs. Input Frequency 20124433 20124438 SNR vs. Temperature THD vs. Temperature 20124434 20124439 SFDR vs. Supply SINAD vs. Supply 20124440 20124445 11 www.ti.com ADC104S021/ADC104S021Q SFDR vs. Clock Frequency SINAD vs. Clock Frequency 20124441 20124446 SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle 20124442 20124447 SFDR vs. Input Frequency SINAD vs. Input Frequency 20124443 www.ti.com 20124448 12 ADC104S021/ADC104S021Q SFDR vs. Temperature SINAD vs. Temperature 20124444 20124449 ENOB vs. Supply ENOB vs. Clock Frequency 20124452 20124453 ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency 20124454 20124455 13 www.ti.com ADC104S021/ADC104S021Q ENOB vs. Temperature Spectral Response - 3V, 200 ksps 20124456 20124459 Spectral Response - 5V, 200 ksps Power Consumption vs. Throughput 20124460 www.ti.com 20124461 14 1.0 ADC104S021/ADC104S021Q OPERATION For the rest of this document, the ADC104S021/ADC104S021Q will be referred to as ADC104S021. The ADC104S021/ADC104S021Q is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. Simplified schematics of the ADC104S021/ADC104S021Q in both track and hold modes are shown in Figures 1, 2, respectively. In Figure 1, the ADC104S021/ADC104S021Q is in track mode: switch SW1 connects the sampling capacitor to one of four analog input channels through the multiplexer, and SW2 balances the comparator inputs. The ADC104S021/ADC104S021Q is in this state for the first three SCLK cycles after CS is brought low. 20124409 FIGURE 1. ADC104S021/ADC104S021Q in Track Mode 20124410 FIGURE 2. ADC104S021/ADC104S021Q in Hold Mode active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a power down state when CS is high, and also between continuous conversion cycles. During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting on the 5th clock. If there is more than one conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising edge of SCLK, and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK, where "N" is an integer. When CS is brought high, SCLK is internally gated off. If SCLK is stopped in the low state while CS is high, the subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped 2.0 USING THE ADC104S021/ADC104S021Q An ADC104S021/ADC104S021Q timing diagram and a serial interface timing diagram for the ADC104S021/ADC104S021Q are shown in the Timing Diagrams section. CS is chip select, which initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC104S021/ADC104S021Q's Control Register is placed on DIN, the serial data input pin. New data is written to the ADC at DIN with each conversion. A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when CS is high and is 15 www.ti.com ADC104S021/ADC104S021Q Figure 2 shows the ADC104S021/ADC104S021Q in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The ADC104S021/ADC104S021Q is in this state for the fourth through sixteenth SCLK cycles after CS is brought low. The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of 16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is clocked into the DIN pin to indicate the multiplexer address for the next conversion. Applications Information ADC104S021/ADC104S021Q with SCLK high, the ADC enters the track mode on the first falling edge of SCLK after the falling edge of CS. During each conversion, data is clocked into the DIN pin on the first 8 rising edges of SCLK after the fall of CS. For each conversion, it is necessary to clock in the data indicating the input that is selected for the conversion after the current one. See Tables 1, 2 and Table 3. If CS and SCLK go low within the times defined by tCSU and tCLH, the rising edge of SCLK that begins clocking data in at DIN may be one clock cycle later than expected. It is, therefore, best to strictly observe the minimum tCSU and tCLH times given in the Timing Specifications. There are no power-up delays or dummy conversions required with the ADC104S021/ADC104S021Q. The ADC is able to sample and convert an input to full conversion immediately following power up. The first conversion result after power-up will be that of IN1. TABLE 1. Control Register Bits Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC TABLE 2. Control Register Bit Descriptions Bit #: Symbol: 7 - 6, 2 - 0 DONTC 5 ADD2 4 ADD1 3 ADD0 Description Don't care. The value of these bits do not affect device operation. These three bits determine which input channel will be sampled and converted in the next track/hold cycle. The mapping between codes and channels is shown in Table 3. TABLE 3. Input Channel Selection ADD2 ADD1 ADD0 Input Channel x 0 0 IN1 (Default) x 0 1 IN2 x 1 0 IN3 x 1 1 IN4 3.0 ADC104S021/ADC104S021Q TRANSFER FUNCTION The output format of the ADC104S021/ADC104S021Q is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC104S021/ADC104S021Q is VA/1024. The ideal transfer characteristic is shown in Figure 3. The transition from an output code of 00 0000 0000 to a code of 00 0000 0001 is at 1/2 LSB, or a voltage of VA/2048. Other code transitions occur at steps of one LSB. 20124411 FIGURE 3. Ideal Transfer Characteristic www.ti.com 16 20124413 FIGURE 4. Typical Application Circuit 5.0 ANALOG INPUTS An equivalent circuit for one of the ADC104S021/ ADC104S021Q's input channels is shown in Figure 5. Diodes D1 and D2 provide ESD protection for the analog inputs. At no time should any input go beyond (VA + 300 mV) or (GND - 300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. For this reason, these ESD diodes should NOT be used to clamp the input signal. The capacitor C1 in Figure 5 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor R1 is the on resistance of the multiplexer and track / hold switch, and is typically 500 ohms. Capacitor C2 is the ADC104S021/ADC104S021Q sampling capacitor, and is typically 30 pF. The ADC104S021/ADC104S021Q will deliver best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. This is especially important when using the ADC104S021/ADC104S021Q to sample AC signals. Also important when sampling dynamic signals is a band-pass or low-pass filter to reduce harmonics and noise, improving dynamic performance. 6.0 DIGITAL INPUTS AND OUTPUTS The ADC104S021/ADC104S021Q's digital output DOUT is limited by, and cannot exceed, the supply voltage, VA. The digital input pins are not prone to latch-up and, and although not recommended, SCLK, CS and DIN may be asserted before VA without any latch-up risk. 7.0 POWER SUPPLY CONSIDERATIONS The ADC104S021/ADC104S021Q is fully powered-up whenever CS is low, and fully powered-down whenever CS is high, with one exception: the ADC104S021/ADC104S021Q automatically enters power-down mode between the 16th falling edge of a conversion and the 1st falling edge of the subsequent conversion (see Timing Diagrams). The ADC104S021/ADC104S021Q can perform multiple conversions back to back; each conversion requires 16 SCLK cycles. The ADC104S021/ADC104S021Q will perform conversions continuously as long as CS is held low. The user may trade off throughput for power consumption by simply performing fewer conversions per unit time. The Power Consumption vs. Sample Rate curve in the Typical Performance Curves section shows the typical power consumption of the ADC104S021/ADC104S021Q versus throughput. To calculate the power consumption, simply multiply the fraction of time spent in the normal mode by the normal mode power consumption, and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power dissipation. 7.1 Power Management When the ADC104S021/ADC104S021Q is operated continuously in normal mode, the maximum throughput is fSCLK/16. Throughput may be traded for power consumption by running fSCLK at its maximum 3.2 MHz and performing fewer conversions per unit time, putting the ADC104S021/ADC104S021Q into shutdown mode between conversions. A plot of typical power consumption versus throughput is shown in the Typical Performance Curves section. To calculate the power con- 20124414 FIGURE 5. Equivalent Input Circuit 17 www.ti.com ADC104S021/ADC104S021Q device noise performance. To keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other circuitry to keep noise off the ADC104S021/ADC104S021Q supply pin. Because of the ADC104S021/ADC104S021Q's low power requirements, it is also possible to use a precision reference as a power supply to maximize performance. The four-wire interface is also shown connected to a microprocessor or DSP. 4.0 TYPICAL APPLICATION CIRCUIT A typical application of the ADC104S021/ADC104S021Q is shown in Figure 4. Power is provided in this example by the National Semiconductor LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power supply pin is bypassed with a capacitor network located close to the ADC104S021/ADC104S021Q. Because the reference for the ADC104S021/ADC104S021Q is the supply voltage, any noise on the supply will degrade ADC104S021/ADC104S021Q sumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption. Generally, the user will put the part into normal mode and then put the part back into shutdown mode. Note that the curve of power consumption vs. throughput is nearly linear. This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the substrate that will degrade noise performance if that current is large enough. The larger is the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into the analog channel, degrading noise performance. To keep noise out of the power supply, keep the output load capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100 series resistor at the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge current of the output capacitance and improve noise performance. 7.2 Power Supply Noise Considerations The charging of any output load capacitance requires current from the power supply, VA. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. www.ti.com 18 ADC104S021/ADC104S021Q Physical Dimensions inches (millimeters) unless otherwise noted 10-Lead MSOP Order Number ADC104S021CIMM, ADC104S021CIMMX, ADC104S021QIMM, ADC104S021QIMMX NS Package Number P0MUB10A 19 www.ti.com ADC104S021/ADC104S021Q 4 Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter Notes www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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