VersaClock(R) 6E Programmable Clock Generator 5P49V6965 Datasheet Description Features The 5P49V6965 is a programmable clock generator intended for high-performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I2C interface. This is Renesas' sixth generation of programmable clock technology (VersaClock 6E). Flexible 1.8V, 2.5V, 3.3V power-rails High-performance, low phase noise PLL, < 0.5ps RMS typical phase jitter on outputs Four banks of internal OTP memory * In-system or factory programmable * 2 select pins accessible with processor GPIOs or The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless manual switchover function allows one of the redundant clocks to be selected during normal operation. bootstrapping I2C * serial programming interface 0xD0 or 0xD4 I2C address options allows multiple devices configured in a same system Two select pins allow up to four different configurations to be programmed and accessible using processor GPIOs or bootstrapping. The different selections may be used for different operating modes (full function, partial function, partial power-down), regional standards (US, Japan, Europe) or system production margin testing. The device may be configured to use one of two I2C addresses to allow multiple devices to be used in a system. Reference LVCMOS output clock Four universal output pairs individually configurable: Typical Applications Output frequency ranges: * Differential (LVPECL, LVDS or HCSL) * 2 single-ended (2 LVCMOS in-phase or 180 degrees out of phase) * I/O VDDs can be mixed and matched, supporting 1.8V (LVDS and LVCMOS), 2.5V, or 3.3V * LVCMOS clock outputs: 1kHz to 200MHz * LVDS, LVPECL, HCSL differential clock outputs: 1kHz to Ethernet switch/router PCI Express 1.0 / 2.0 / 3.0 / 4.0 Spread Spectrum on PCI Express 1.0 / 2.0 / 3.0 / 4.0 / 5.0 Spread Spectrum off Broadcast video/audio timing Multi-function printer Processor and FPGA clocking Any-frequency clock conversion MSAN/DSLAM/PON Fiber Channel, SAN Telecom line cards Laser distance sensing 350MHz Redundant clock inputs with manual switchover Programmable output enable or power-down mode Available in 4 x 4 mm 24-VFQFPN package -40 to +85C industrial temperature operation Block Diagram VDDO 0 XIN/REF OUT0_SEL_I2CB VDDO1 XOUT OUT1 CLKIN FOD1 OUT1B CLKINB VDDO2 CLKSEL OUT2 SD/OE SEL1/SDA SEL0/SCL OTP and Control Logic FOD2 OUT2B PLL VDDO3 OUT3 VDDA FOD3 OUT3B VDDD V DDO4 OUT4 FOD4 OUT4B (c)2020 Renesas Electronics Corporation 1 August 20, 2020 5P49V6965 Datasheet Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 I2C Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Jitter Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PCI Express Jitter Performance and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Features and Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device Startup and Power-On-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reference Clock and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Manual Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Internal Crystal Oscillator (XIN/REF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Programmable Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Fractional Output Dividers (FOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SD/OE Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Input - Driving the XIN/REF or CLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Output - Single-ended or Differential Clock Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 (c)2020 Renesas Electronics Corporation 2 August 20, 2020 5P49V6965 Datasheet Pin Assignments VDDA 5 CLKSEL 6 VDDO1 VDDD OUT1B 4 EPAD 7 VDDO2 17 OUT2 16 OUT2B 15 VDDO3 14 OUT3 13 OUT3B 8 9 10 11 12 OUT4B XIN/REF OUT1 3 18 OUT4 XOUT 19 VDDO4 2 21 20 SEL0/SCL CLKINB 24 23 22 SEL1/SDA 1 SD/OE CLKIN VDDO0 OUT0_SEL_I2CB Figure 1. Pin Assignments for 4 x 4 mm 24-VFQFPN Package - Top View 4 x 4 mm 24-VFQFPN Pin Descriptions Table 1. Pin Descriptions Number Name Type Description 1 CLKIN Input Internal Pull-down Differential clock input. Weak 100k internal pull-down. 2 CLKINB Input Internal Pull-down Complementary differential clock input. Weak 100k internal pull-down. 3 XOUT Output 4 XIN/REF Input Crystal oscillator interface input, or single-ended LVCMOS clock input. Input voltage needs to be below 1.2V. Refer to the section Driving XIN/REF with a CMOS Driver. 5 VDDA Power Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD should have the same voltage applied. Crystal oscillator interface output. Input clock select. Selects the active input reference source in manual switchover mode. 0 = XIN/REF, XOUT (default). 1 = CLKIN, CLKINB. See Table 20. Input Clock Select for more details. 6 CLKSEL Input Internal Pull-down 7 SD/OE Input Internal Pull-down Enables/disables the outputs (OE) or powers down the chip (SD). 8 SEL1/SDA Input Internal Pull-down Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB. Weak internal pull-down resistor. 9 SEL0/SCL Input Internal Pull-down Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB. Weak internal pull-down resistor. (c)2020 Renesas Electronics Corporation 3 August 20, 2020 5P49V6965 Datasheet Table 1. Pin Descriptions (Cont.) Number Name Type Description 10 VDDO4 Power Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT4/OUT4B. 11 OUT4 Output Output clock 4. Refer to the Output Drivers section for more details. 12 OUT4B Output Complementary output clock 4. Refer to the Output Drivers section for more details. 13 OUT3B Output Complementary output clock 3. Refer to the Output Drivers section for more details. 14 OUT3 Output Output clock 3. Refer to the Output Drivers section for more details. 15 VDDO3 Power Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT3/OUT3B. 16 OUT2B Output Complementary output clock 2. Refer to the Output Drivers section for more details. 17 OUT2 Output Output clock 2. Refer to the Output Drivers section for more details. 18 VDDO2 Power Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT2/OUT2B. 19 OUT1B Output Complementary output clock 1. Refer to the Output Drivers section for more details. 20 OUT1 Output Output clock 1. Refer to the Output Drivers section for more details. 21 VDDO1 Power Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT1/OUT1B. 22 VDDD Power Digital functions power supply pin. Connect to 1.8 to 3.3V. VDDA and VDDD should have the same voltage applied. 23 VDDO0 Power Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT0. 24 OUT0_SEL _I2CB 25 GND Input/ Output Internal Pull-down GND (c)2020 Renesas Electronics Corporation Latched input/LVCMOS output. At power-up, the voltage at the pin OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8 and 9. If a weak pull-up (10k) is placed on OUT0_SEL_I2CB, pins 8 and 9 will be configured as hardware select pins, SEL1 and SEL0. If a weak pull-down (10k) is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will act as the SDA and SCL pins of an I2C interface. After power-up, the pin acts as an LVCMOS reference output. Connect to ground pad. 4 August 20, 2020 5P49V6965 Datasheet Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the device at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 2. Absolute Maximum Ratings Item Rating Supply Voltage, V DDA, VDDD, VDDO 3.6V. XIN/REF Input 1.2V. CLKIN, CLKINB Input VDDO0, 1.2V voltage swing. 2 I C Loading Current 10mA. Storage Temperature, T STG -65C to 150C. Junction Temperature 125C ESD Human Body Model 2000V. Thermal Characteristics Table 3. Thermal Characteristics Symbol Parameter Value Units 42 C/W JA Theta JA. Junction to air thermal impedance (0mps). JB Theta JB. Junction to board thermal impedance (0mps). 2.35 C/W JC Theta JC. Junction to case thermal impedance (0mps). 41.8 C/W Recommended Operating Conditions Table 4. Recommended Operating Conditions Symbol Minimum Typical Maximum Units Power supply voltage for supporting 1.8V outputs. 1.71 1.8 1.89 V Power supply voltage for supporting 2.5V outputs. 2.375 2.5 2.625 V Power supply voltage for supporting 3.3V outputs. 3.135 3.3 3.465 V VDDD Power supply voltage for core logic functions. 1.71 3.465 V VDDA Analog power supply voltage. Use filtered analog power supply. 1.71 3.465 V TPU Power ramp time for all VDDs to reach 90% of VDD. 0.05 50 ms TA Operating temperature, ambient. -40 85 C CL Maximum load capacitance (3.3V LVCMOS only). 15 pF VDDOX Parameter (c)2020 Renesas Electronics Corporation 5 August 20, 2020 5P49V6965 Datasheet Electrical Characteristics Table 5. Current Consumption VDDA, VDDD, VDDO0 = 3.3V 5%, 2.5V 5%, 1.8V 5%, TA = -40C to +85C. Symbol IDDCORE 1 Parameter Core Supply Current Conditions Minimum Typical Maximum Units 33 42 mA 45 58 mA LVPECL, 350MHz, 2.5V VDDOx.2. 36 47 mA LVDS, 350MHz, 3.3V VDDOx . 26 32 mA . 25 30 mA 22 27 mA 39 48 mA 100MHz on all outputs, 25MHz REFCLK. LVPECL, 350MHz, 3.3V VDDOx. LVDS, 350MHz, 2.5V VDDOx 2 2 2 . LVDS, 350MHz, 1.8V VDDOx2. IDDOx Output Buffer Supply Current HCSL, 250MHz, 3.3V VDDOx 2 . HCSL, 250MHz, 2.5V VDDOx 2. 37 46 mA 2,3. 22 27 mA 2,3. 20 24 mA LVCMOS, 50MHz, 1.8V, VDDOx 2,3. 17 21 mA LVCMOS, 200MHz, 3.3V VDDOx 2,3. 43 56 mA 2,3. 33 43 mA LVCMOS, 200MHz, 1.8V VDDOx 2,3. 24 31 mA SD asserted, 10 12 mA LVCMOS, 50MHz, 3.3V, VDDOx LVCMOS, 50MHz, 2.5V, VDDOx LVCMOS, 200MHz, 2.5V VDDOx IDDPD 1 2 3 Power Down Current I2C programming. IDDCORE = IDDA + IDDD. Measured into a 5" 50 trace. See Test Loads section for more details. Single CMOS driver active. (c)2020 Renesas Electronics Corporation 6 August 20, 2020 5P49V6965 Datasheet Table 6. AC Timing Characteristics VDDA, VDDD, VDDO0 = 3.3V 5%, 2.5V 5%, 1.8V 5%, TA = -40C to +85C unless stated otherwise. Symbol FIN 1 FOUT 2 fVCO TDC 3 Parameter Input Frequency Output Frequency Output Duty Cycle Output Skew TSTARTUP 4,5 Startup Time 2 3 4 5 6 Minimum Typical Maximum Units Input frequency limit (crystal). 8 40 MHz Input frequency limit (CLKIN,CLKINB). 1 350 MHz Input frequency limit (single-ended over XIN). 1 200 MHz Single-ended clock output limit (LVCMOS), individual FOD mode. 1 200 Differential clock output limit (LVPECL/LVDS/HCSL), individual FOD mode. 1 350 Single-ended clock output limit (LVCMOS), cascaded FOD mode, output 2-4. 0.001 200 Differential clock output limit (LVPECL/LVDS/HCSL), cascaded FOD mode, output 2-4. 0.001 350 2500 2900 MHz VCO Operating Frequency Range TSKEW 1 Conditions MHz Measured at VDD/2, all outputs except reference output, VDDOX = 2.5V or 3.3V. 45 50 55 % Measured at VDD/2, all outputs except reference output, VDDOX = 1.8V 40 50 60 % Measured at VDD/2, reference output OUT0 (5MHz-150.1MHz) with 50% duty cycle input. 40 50 60 % Measured at VDD/2, reference output OUT0 (150.1MHz-200MHz) with 50% duty cycle input. 30 50 70 % Skew between the same frequencies, with outputs using the same driver format and phase delay set to 0ns. 75 Measured after all VDDs have risen above 90% of their target value 6. PLL lock time from shutdown mode. 3 ps 30 ms 4 ms Practical lower frequency is determined by loop filter settings. A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher. Duty cycle is only guaranteed at maximum slew rate settings. Actual PLL lock time depends on the loop configuration. Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/write time. Power-up with temperature calibration enabled; contact Renesas if shorter lock-time is required in system. (c)2020 Renesas Electronics Corporation 7 August 20, 2020 5P49V6965 Datasheet Table 7. General Input Characteristics VDDA, VDDD, VDDO0 = 3.3V 5%, 2.5V 5%, 1.8V 5%, TA = -40C to +85C unless stated otherwise. Symbol Parameter Conditions Minimum Typical Maximum Units 3 7 pF 100 300 k CIN Input Capacitance CLKIN,CLKINB,CLKSEL,SD/OE,SEL1/SD A, SEL0/SCL. RPD Pull-down Resistor CLKSEL, SD/OE, SEL1/SDA, SEL0/SCL, CLKIN, CLKINB, OUT0_SEL_I2CB. VIH Input High Voltage CLKSEL, SD/OE. 0.7 x VDDD VDDD + 0.3 V VIL Input Low Voltage CLKSEL, SD/OE. GND - 0.3 0.3 x VDDD V VIH Input High Voltage OUT0_SEL_I2CB. 1.7 VDDO0 + 0.3 V VIL Input Low Voltage OUT0_SEL_I2CB. GND - 0.3 0.4 V VIH Input High Voltage XIN/REF. 0.8 1.2 V VIL Input Low Voltage XIN/REF. GND - 0.3 0.4 V Input Rise/Fall Time CLKSEL, SD/OE, SEL1/SDA, SEL0/SCL. 300 ns Maximum Units TR/TF Table 8. CLKIN Electrical Characteristics VDDA, VDDD, VDDO0 = 3.3V 5%, 2.5V 5%, 1.8V 5%, TA = -40C to +85C unless stated otherwise. Symbol Parameter Conditions Minimum Typical VSWING Input Amplitude - CLKIN, CLKINB Peak to peak value, single-ended. 200 1200 mV dv/dt Input Slew Rate - CLKIN, CLKINB Measured differentially. 0.4 8 V/ns IIL Input Leakage Low Current VIN = GND. -5 5 A IIH Input Leakage High Current VIN = 1.7V. 20 A Input Duty Cycle Measurement from differential waveform. 55 % DCIN (c)2020 Renesas Electronics Corporation 8 45 August 20, 2020 5P49V6965 Datasheet Table 9. Electrical Characteristics - CMOS Outputs VDDA, VDDD, VDDO0 = 3.3V 5%, 2.5V 5%, 1.8V 5%, TA = -40C to +85C unless stated otherwise. Symbol Parameter Conditions 0.7 x VDDO VDDO V IOH = -8mA (1.8V). 0.5 x VDDO VDDO V 0.45 V Output High Voltage VOL Output Low Voltage IOL = 15mA (3.3V), 12mA (2.5V), 8mA (1.8V). ROUT Output Driver Impedance CMOS output driver. 17 Slew Rate, SLEW[1:0] = 00 Slew Rate, SLEW[1:0] = 10 Slew Rate, SLEW[1:0] = 11 Single-ended 3.3V LVCMOS output clock rise and fall time, 20% to 80% of VDDO (output load = 5pF) VDDOX = 3.3V. Slew Rate, SLEW[1:0] = 00 TSR Slew Rate, SLEW[1:0] = 01 Slew Rate, SLEW[1:0] = 10 Slew Rate, SLEW[1:0] = 11 Single-ended 2.5V LVCMOS output clock rise and fall time, 20% to 80% of VDDO (output load = 5pF) VDDOX = 2.5V. Slew Rate, SLEW[1:0] = 00 Slew Rate, SLEW[1:0] = 01 Slew Rate, SLEW[1:0] = 10 Slew Rate, SLEW[1:0] = 11 IOZDD Typical Maximum Units IOH = -15mA (3.3V), -12mA (2.5V). VOH Slew Rate, SLEW[1:0] = 01 Minimum Single-ended 1.8V LVCMOS output clock rise and fall time, 20% to 80% of VDDO (output load = 5pF) VDD = 1.8V. 1.0 2.2 1.2 2.3 1.3 2.4 1.7 2.7 0.6 1.3 0.7 1.4 0.6 1.4 1.0 1.7 0.3 0.7 0.4 0.8 0.4 0.9 0.7 1.2 V/ns Output Leakage Current (OUT1-4) Tri-state outputs. 5 A Output Leakage Current (OUT0) Tri-state outputs. 30 A Maximum Units Table 10. Electrical Characteristics - LVDS Outputs VDDA, VDDD, VDDO0 = 3.3V 5%, 2.5V 5%, 1.8V 5%, TA = -40C to +85C unless stated otherwise. Symbol Parameter Minimum Typical VOT (+) Differential Output Voltage for the TRUE Binary State 247 454 mV VOT (-) Differential Output Voltage for the FALSE Binary State -454 -247 mV VOT Change in VOT between Complimentary Output States 50 mV VOS VOS Output Common Mode Voltage (Offset Voltage) at 3.3 V 5%, 2.5V 5% Output Common Mode Voltage (Offset Voltage) at 1.8V 5% 1.125 1.25 1.375 V 0.8 0.875 0.96 V 50 mV Change in VOS between Complimentary Output States IOS Outputs Short Circuit Current, V OUT+ or VOUT - = 0V or VDDO 9 24 mA IOSD Differential Outputs Short Circuit Current, VOUT+ = VOUT - 6 12 mA TR LVDS rise time 20%-80% 300 ps TF LVDS fall time 80%-20% 300 ps (c)2020 Renesas Electronics Corporation 9 August 20, 2020 5P49V6965 Datasheet Table 11. Electrical Characteristics - LVPECL Outputs VDDA, VDDD, VDDO0 = 3.3V 5%, 2.5V 5%, TA = -40C to +85C unless stated otherwise. Symbol Parameter Minimum Typical Maximum Units VOH Output Voltage High, Terminated through 50 tied to VDD - 2V VDDO - 1.19 VDDO - 0.69 V VOL Output Voltage Low, Terminated through 50 tied to VDD - 2V VDDO - 1.94 VDDO - 1.4 V 1.1 2 V VSWING Peak-to-Peak Differential Output Voltage Swing TR LVPECL rise time 20%-80% 400 ps TF LVPECL fall time 80%-20% 400 ps Table 12. Electrical Characteristics - HCSL Outputs 1 VDDA, VDDD, VDDO0 = 3.3V 5%, 2.5V 5%, TA = -40C to +85C unless stated otherwise. Symbol dV/dt Parameter Conditions Scope averaging on 2,3. Slew Rate Minimum Scope averaging on VMAX Maximum Voltage VMIN Minimum Voltage Measurement on single-ended signal using absolute value (scope averaging off). 2,6 4 V/ns 20 % 1150 mV -300 mV mV VSWING Voltage Swing Scope averaging off . 300 VCROSS Crossing Voltage Value Scope averaging off 4,6 . 250 VCROSS Crossing Voltage Variation 2 Units 1 Slew Rate Matching 1 Maximum 2,3. dV/dt Scope averaging off Typical 5. 550 mV 140 mV Guaranteed by design and characterization. Not 100% tested in production. Measured from differential waveform. 3 Slew rate is measured through the VSWING voltage range centered around differential 0V. This results in a 150mV window around differential 0V. 4V CROSS is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 5 The total variation of all V 6 CROSS measurements in any particular system. Note that this is a subset of VCROSS min/max (V CROSS absolute) allowed. The intent is to limit VCROSS induced modulation by setting VCROSS to be smaller than VCROSS absolute. Measured from single-ended waveform. Table 13. Spread Spectrum Generation Specifications Symbol fSSOUT fMOD fSPREAD Parameter Conditions Spread Frequency Output frequency range for spread spectrum. Mod Frequency Modulation frequency. Spread Value Minimum Typical Maximum Units 300 MHz 5 30 to 63 Amount of spread value (programmable)-center spread. 0.1% to 2.5% Amount of spread value (programmable)-down spread. -0.2% to -5% (c)2020 Renesas Electronics Corporation 10 kHz %fOUT August 20, 2020 5P49V6965 Datasheet I2C Bus Characteristics Table 14. I2C Bus (SCL/SDA) DC Characteristics Symbol Parameter Conditions VIH Input High Level For SEL1/SDA pin and SEL0/SCL pin. VIL Input Low Level For SEL1/SDA pin and SEL0/SCL pin. VHYS Hysteresis of Inputs IIN Input Leakage Current VOL Output Low Voltage Minimum Typical Maximum 0.7 x VDDD Units V 0.3 x VDDD 0.05 x VDDD V V -1 IOL = 3mA. 36 A 0.45 V Maximum Units 400 kHz Table 15. I2C Bus (SCL/SDA) AC Characteristics Symbol Conditions Minimum Serial Clock Frequency (SCL) -- 10 Bus Free Time between Stop and Start -- 1.3 s tSU:START Setup Time, Start -- 0.6 s tHD:START Hold Time, Start -- 0.6 s tSU:DATA Setup Time, Data Input (SDA) -- 0.1 s tHD:DATA Hold Time, Data Input (SDA) 1 -- 0 s tOVD Output Data Valid from Clock -- 0.9 s CB Capacitive Load for Each Bus Line -- 400 pF tR Rise Time, Data and Clock (SDA, SCL) -- 20 + 0.1 x CB 300 ns tF Fall Time, Data and Clock (SDA, SCL) -- 20 + 0.1 x CB 300 ns tHIGH High Time, Clock (SCL) -- 0.6 s tLOW Low Time, Clock (SCL) -- 1.3 s Setup Time, Stop -- 0.6 s FSCLK tBUF tSU:STOP Parameter Typical 1 A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. 2 I2 C inputs are 3.3V tolerant. (c)2020 Renesas Electronics Corporation 11 August 20, 2020 5P49V6965 Datasheet Test Loads Figure 2. LVCMOS Test Load Test Point 33 Ohm Zo = 50 Ohm 5pF Device Figure 3. HCSL Test Load 50 Ohm 33 Ohm 2pF Differential Zo = 100 Ohm 33 Ohm Test Points 50 Ohm 2pF Device Figure 4. LVDS Test Load 2pF Differential Zo = 100 Ohm 100 Ohm Test Points 2pF Device Figure 5. LVPECL Test Load Differential Zo = 100 Ohm Test Points 2pF Device (c)2020 Renesas Electronics Corporation 50Ohm R 12 50 Ohm 2pF R = 50 Ohm for 3.3V LVPECL R = 18 Ohm for 2.5V LVPECL August 20, 2020 5P49V6965 Datasheet Jitter Performance Characteristics Figure 6. Typical Phase Jitter Plot at 156.25MHz Note: Measured with OUT2 = 156.25MHz on, 39.625MHz input. Table 16. Jitter Performance Symbol 1,2 Parameter JCY-CY Cycle to Cycle Jitter JPK-PK Period Jitter JRMS RMS Phase Jitter (12kHz-20MHz) 1 2 Conditions Minimum Typical Maximum Units LVCMOS 3.3V 5%, -40C-90C. 5 30 ps All differential outputs 3.3V 5%, -40C-90C. 25 35 ps LVCMOS 3.3V 5%, -40C-90C. 28 40 ps All differential outputs 3.3V 5%, -40C-90C. 4 30 ps LVCMOS 3.3V 5%, -40C-90C. 0.3 ps All differential outputs 3.3V 5%, -40C-90C. 0.5 ps Measured with 25MHz crystal input. Configured with OUT0 = 25MHz-LVCMOS; OUT1 = 100MHz-HCSL; OUT2 = 125MHz-LVDS; OUT3 = 156.25MHz-LVPECL. (c)2020 Renesas Electronics Corporation 13 August 20, 2020 5P49V6965 Datasheet PCI Express Jitter Performance and Specification Table 17. PCI Express Jitter Performance (Spread Spectrum = Off) Parameter Symbol Conditions tjphPCIeG1-CC PCIe Gen1 (2.5 GT/s) SSC = OFF Limit Units Notes 4 86 ps (p-p) 1,2 PCIe Gen2 Lo Band (5.0 GT/s) SSC = OFF 0.05 3 ps (RMS) 1,2 PCIe Gen2 Hi Band (5.0 GT/s) SSC = OFF 0.22 3.1 ps (RMS) 1,2 tjphPCIeG3-CC PCIe Gen3 (8.0 GT/s) SSC = OFF 0.12 1 ps (RMS) 1,2 tjphPCIeG4-CC PCIe Gen4 (16.0 GT/s) SSC = OFF 0.12 0.5 ps (RMS) 1,2,3,4 tjphPCIeG5-CC PCIe Gen5 (32.0 GT/s) SSC = OFF 0.05 0.15 ps (RMS) 1,2,3,5 tjphPCIeG1-SRNS PCIe Gen1 (2.5 GT/s) SSC = OFF 0.3 ps (p-p) 1,2,6 tjphPCIeG2-SRNS PCIe Gen2 (5.0 GT/s) SSC = OFF 0.26 ps (RMS) 1,2,6 PCIe Phase Jitter t (SRNS Architectures) jphPCIeG3-SRNS PCIe Gen3 (8.0 GT/s) SSC = OFF 0.07 ps (RMS) 1,2,6 tjphPCIeG4-SRNS PCIe Gen4 (16.0 GT/s) SSC = OFF 0.07 ps (RMS) 1,2,6 tjphPCIeG5-SRNS PCIe Gen5 (32.0 GT/s) SSC = OFF 0.07 ps (RMS) 1,2,6 tjphPCIeG2-CC PCIe Phase Jitter (Common Clocked Architectures) Minimum Typical Maximum N/A 1 The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section 2 3 4 5 6 of the data sheet for the exact measurement setup. The worst case results for each data rate are summarized in this table. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of 20GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for RTO measurements. Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5GT/s data rate, the RMS jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA measurements have both been done and produce different results, the RTO result must be used. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC content. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system. While the PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, it does not provide specification limits, hence the n/a in the Limit column. SRIS values are informative only. In general, a clock operating in an SRIS system must be twice as good as a clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by O2. (c)2020 Renesas Electronics Corporation 14 August 20, 2020 5P49V6965 Datasheet Table 18. PCI Express Jitter Performance (Spread Spectrum = On) Parameter Symbol Conditions tjphPCIeG1-CC PCIe Gen 1 (2.5 GT/s) SSC -0.5% Limit Units Notes 16 86 ps (p-p) 1,2 PCIe Gen 2 Lo Band (5.0 GT/s) SSC -0.5% 0.02 3 ps (RMS) 1,2 PCIe Gen 2 Hi Band (5.0 GT/s) SSC -0.5% 0.92 3.1 ps (RMS) 1,2 tjphPCIeG3-CC PCIe Gen 3 (8.0 GT/s) SSC -0.5% 0.37 1 ps (RMS) 1,2 tjphPCIeG4-CC PCIe Gen 4 (16.0 GT/s) SSC -0.5% 0.37 0.5 ps (RMS) 1,2,3,4 tjphPCIeG5-CC PCIe Gen 5 (32.0 GT/s) SSC -0.5% N/A 0.15 ps (RMS) 1,2,3,5 tjphPCIeG1-SRIS PCIe Gen 1 (2.5 GT/s) SSC -0.3% 14 ps (p-p) 1,2,6 tjphPCIeG2-SRIS PCIe Gen 2 (5.0 GT/s) SSC -0.3% 1.4 ps (RMS) 1,2,6 tjphPCIeG3-SRIS PCIe Gen 3 (8.0 GT/s) SSC -0.3% 0.42 ps (RMS) 1,2,6 tjphPCIeG4-SRIS PCIe Gen 4 (16.0 GT/s) SSC -0.3% 0.36 ps (RMS) 1,2,6 tjphPCIeG5-SRIS PCIe Gen 5 (32.0 GT/s) SSC -0.3% N/A ps (RMS) 1,2,6 tjphPCIeG2-CC PCIe Phase Jitter (Common Clocked Architectures) PCIe Phase Jitter (SRIS Architectures) 1 2 3 4 5 6 Minimum Typical Maximum N/A The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section of the data sheet for the exact measurement setup. The worst case results for each data rate are summarized in this table. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of 20GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for RTO measurements. Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5GT/s data rate, the RMS jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA measurements have both been done and produce different results, the RTO result must be used. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC content. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system. While the PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, it does not provide specification limits, hence the n/a in the Limit column. SRIS values are informative only. In general, a clock operating in an SRIS system must be twice as good as a clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by O2. (c)2020 Renesas Electronics Corporation 15 August 20, 2020 5P49V6965 Datasheet Features and Functional Blocks Device Startup and Power-On-Reset Reference Clock and Selection The device has an internal power-up reset (POR) circuit. All V DDs must be connected to desired supply voltage to trigger POR. The device supports up to two clock inputs. Crystal input, can be driven by a single-ended clock. Clock input (CLKIN, CLKINB), a fully differential input that only accepts a reference clock. A single-ended clock can also drive it on CLKIN. User can define specific default configurations through internal One-Time-Programmable (OTP) memory. Either customer or factory can program the default configuration. Please refer to VersaClock 6E Family Register Descriptions and Programming Guide for details or contact Renesas if a specific factory-programmed default configuration is required. Figure 7. Clock Input Diagram, Internal Logic XIN/REF Device will identity which of the 2 modes to operate in by the state of OUT0_SEL_I2CB pin at POR. Both of the 2 modes default configurations can be programmed as stated above. XOUT 1. Software Mode (I2C): OUT0_SEL_I2CB is low at POR. CLKIN I2C interface will be open to users for in-system programming, overriding device default configurations at any time. CLKINB 2. Hardware Select Mode: OUT0_SEL_I2CB is high at POR. Device has been programmed to load OTP at power-up (REG0[7]=1). The device will load internal registers according to Table 19. Power-up Behavior. Internal OTP memory can support up to 4 configurations, selectable by SEL0/SEL1 pins. At POR, logic levels at SEL0 and SEL1 pins must be settled, resulting the selected configuration to be loaded at power up. After the first 10ms of operation, the levels of the SELx pins can be changed, either to low or to the same level as VDDD/VDDA. The SELx pins must be driven with a digital signal of < 300ns rise/fall time and only a single pin can be changed at a time. After a pin level change, the device must not be interrupted for at least 1ms so that the new values have time to load and take effect. CLKSEL OUT0_SEL_I2CB at POR SEL1 SEL0 Access REG0:7 Config 1 0 0 No 0 0 1 0 1 No 0 1 1 1 0 No 0 2 1 1 1 No 0 3 0 X X Yes 1 I2C defaults 0 X X Yes 0 0 (c)2020 Renesas Electronics Corporation OTP and Control Logic Manual Switchover The CLKSEL pin selects the input clock between either XTAL/REF or (CLKIN, CLKINB). CLKSEL polarity can be changed by I2C programming (Byte 0x13[1]) as shown in the table below. 0 = XIN/REF, XOUT (default); 1 = CLKIN, CLKINB. Table 20. Input Clock Select Table 19. Power-up Behavior I2C PRIMSRC Reg 0x13[1] PRIMSRC CLKSEL Source 0 0 XIN/REF 0 1 CLKIN, CLKINB 1 0 CLKIN, CLKINB 1 1 XIN/REF When SM[1:0] is "0x", the redundant inputs are in manual switchover mode. In this mode, CLKSEL pin is used to switch between the primary and secondary clock sources. The PRIMSRC bit determines the primary and secondary clock source setting. During the switchover, no glitches will occur at the output of the device, although there may be frequency and phase drift, depending on the exact phase and frequency relationship between the primary and secondary clocks. 16 August 20, 2020 5P49V6965 Datasheet Internal Crystal Oscillator (XIN/REF) Ci1 and Ci2 are commonly programmed to be the same value. Adjustment of the crystal tuning capacitors allows maximum flexibility to accommodate crystals from various manufacturers. The range of tuning capacitor values available are in accordance with the following table. Choosing Crystals A crystal manufacturer will calibrate its crystals to the nominal frequency with a certain load capacitance value. When the oscillator load capacitance matches the crystal load capacitance, the oscillation frequency will be accurate. When the oscillator load capacitance is lower than the crystal load capacitance, the oscillation frequency will be higher than nominal and vice versa so for an accurate oscillation frequency you need to make sure to match the oscillator load capacitance with the crystal load capacitance. Ci1/Ci2 starts at 9pF with setting 000000b and can be increased up to 25pF with setting 111111b. The step per bit is 0.5pF. Table 21. XTAL[5:0] Tuning Capacitor Tuning the Crystal Load Capacitor Parameter Bits Step (pF) Minimum (pF) Maximum (pF) XTAL 6 0.5 9 25 You can write the following equation for this capacitance: Ci = 9pF + 0.5pF x XTAL[5:0] CXIN = Ci1 + Cs1 + Ce1 CXOUT = Ci2 + Cs2 + Ce2 The final load capacitance of the crystal: CL = CXIN x CXOUT / (CXIN + CXOUT) It is recommended to set the same value for capacitors the same at each crystal pin, meaning: CXIN = CXOUT Example 1: The crystal load capacitance is specified as 8pF and the stray capacitance at each crystal pin is Cs = 1.5pF. Assuming equal capacitance value at XIN and XOUT, the equation is as follows: Cs1 and Cs2 are stray capacitances at each crystal pin and typical values are between 1pF and 3pF. 8pF = (9pF + 0.5pF x XTAL[5:0] + 1.5pF) / 2 So, XTAL[5:0] = 11 (decimal). Ce1 and Ce2 are additional external capacitors, increasing the load capacitance reduces the oscillator gain so please consult the factory when adding Ce1 and/or Ce2 to avoid crystal startup issues. Ci1 and Ci2 are integrated programmable load capacitors, one at XIN and one at XOUT. Ci1 and Ci2. Example 2: The crystal load capacitance is specified as 12pF and the stray capacitance Cs is unknown. Footprints for external capacitors Ce are added and a worst case Cs of 5pF is used. For now we use Cs + Ce = 5pF and the right value for Ce can be determined later to make 5pF together with Cs. The value of each capacitor is composed of a fixed capacitance amount plus a variable capacitance amount set with the XTAL[5:0] register. 12pF = (9pF + 0.5pF x XTAL[5:0] + 5pF) / 2 So, XTAL[5:0] = 20 (decimal). Table 22. Recommended Crystal Characteristics Parameter Minimum Mode of Oscillation Typical Maximum Units 25 40 MHz 10 100 7 pF 12 pF 8 pF 100 W Fundamental Frequency 8 Equivalent Series Resistance (ESR) Shunt Capacitance Load Capacitance (CL) at < = 25MHz 6 Load Capacitance (CL) > 25MHz to 40MHz 6 Maximum Crystal Drive Level (c)2020 Renesas Electronics Corporation 17 8 August 20, 2020 5P49V6965 Datasheet Programmable Loop Filter When device is at hardware select mode outputs will be automatically aligned at POR. The same synchronization reset is also triggered when switching between configurations with the SEL0/1 pins. This ensures that the outputs remain aligned in every configuration. The device PLL loop bandwidth range depends on the input reference frequency (Fref). Table 23. Loop Filter Settings Input Reference Frequency (MHz) Loop Bandwidth Minimum (kHz) Loop Bandwidth Maximum (kHz) 1 40 126 350 300 1000 When using software mode I2C to reprogram an output divider during operation, alignment can be lost. Alignment can be restored by manually triggering the reset through I2C. The outputs are aligned on the falling edges of each output by default. Rising edge alignment can also be achieved by utilizing the programmable skew feature to delay the faster clock by 180 degrees. The programmable skew feature also allows for fine tuning of the alignment. Fractional Output Dividers (FOD) The device has 4 fractional output dividers (FOD). Each of the FODs are comprised of a 12-bit integer counter, and a 24-bit fractional counter. The output divider can operate in integer divide only mode for improved performance, or utilize the fractional counters to generate a clock frequency accurate to 50ppb. Programmable Skew The device has the ability to skew outputs by quadrature values. The skew on each output can be adjusted from 0 to 360 degrees. Skew is adjusted in units equal to 1/32 of the VCO period. So, for 100MHz output and a 2800MHz VCO, you can select how many 11.161ps units you want added to your skew (resulting in units of 0.402 degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and so on. The granularity of the skew adjustment is always dependent on the VCO period and the output period. FOD has the following features: Individual Spread Spectrum Modulation The output clock frequencies can be modulated to spread energy across a broader range of frequencies, lowering system EMI. Each divider has individual spread ability. Spread modulation independent of output frequency, a triangle wave modulation between 30 and 63kHz. Output Drivers Spread spectrum can be applied to any output clock, any clock frequency, and any spread amount from 0.25% to 2.5% center-spread and -0.5% to -5% down-spread. 2.5V or 3.3V voltage level for HCSL/LVPECL operation 1.8V, 2.5V or 3.3V voltage levels for CMOS/LVDS operation CMOS supports 4 operating modes: The device output drivers support the following features individually: * * * * Bypass Mode Bypass mode (divide by 1) to allow the output to behave as a buffered copy from the input or another FOD. Cascaded Mode When a given output is configured to at CMOSD or CMOSX2, then all previously described configuration and control apply equally to both pins. As shown in the block diagram, FODs can be cascaded for lower output frequency. For example, user currently has OUT1 running at 12.288MHz and needs another 48kHz output. The user can cascade FOD2 by taking input from OUT1, with a divide ratio of 256. In this way, OUT 2 is running at 48kHz while in alignment with 12.288MHz on OUT1. Independent output enable/disabled by register bits. When disabled, an output can be either in a logic 1 state or Hi-Z. The following options are used to disable outputs: 1. Output turned off by I 2C. 2. Output turned off by SD/OE pin. Dividers Alignment 3. Output unused, which means is turned off regardless of OE pin status. Each output divider block has a synchronizing pulse to provide startup alignment between outputs dividers. This allows alignment of outputs for low skew performance. (c)2020 Renesas Electronics Corporation CMOSD: OUTx and OUTxB 180 degrees out of phase CMOSX2: OUTx and OUTxB phase-aligned CMOS1: only OUTx pin is on CMOS2: only OUTxB pin is on 18 August 20, 2020 5P49V6965 Datasheet SD/OE Pin Function I2C Operation SD/OE pin can be programmed as following functions: The device acts as a slave device on the I2C bus using one of the two I2C addresses (0xD0 or 0xD4) to allow multiple devices to be used in the system. The interface accepts byte-oriented block write and block read operations. 1. OE output enable (low active). 2. OE output enable (high active). 3. Global shutdown (low active). 4. Global shutdown (high active). Address bytes(2 bytes) specify the register address of the byte position of the first register to write or read. Output behavior when disabled is also programmable. User will have the option to choose output driver behavior when it's off: Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first). 1. OUTx pin high, OUTxB pin low. (Controlled by SD/OE pin). Read and write block transfers can be stopped after any complete byte transfer. During a write operation, data will not be moved into the registers until the STOP bit is received, at which point, all data received in the block write will be written simultaneously. 2. OUTx/OUTxB Hi-Z (Controlled by SD/OE pin). 3. OUTx pin high, OUTxB pin low. (Configured through I2C). 4. OUTx/OUTxB Hi-Z (Configured by I2C). For full electrical I2C compliance, use external pull-up resistors for SDATA and SCLK. The user has the option to disable the output with either I2C or SD/OE pin. Refer to VersaClock 6E Family Register Descriptions and Programming Guide for details. Figure 8. I2C R/W Sequence (c)2020 Renesas Electronics Corporation 19 August 20, 2020 A B C 1 R7 10K C7 2 3 FB1 2 C1 10uF 7 SD/OE SD/OE SEL1/SDA SEL0/SCL CLKSEL CLKIN CLKINB XOUT XIN/REF 2 CLKIN .1uF 1 2 CLKINB C12 .1uF 8 9 1 C13 6 SDA SCL 1 2 CLKSEL CLKIN CLKINB 3 4 6 U5 5P49V6965A C5 .1uF V1P8VC C4 .1uF C8 .1uF C11 .1uF C14 .1uF VDDD VDDA 5 C15 .1uF 1 R2 2.2 V1P8VC V1P8VC OUTR0 V1P8VC OUTR1 OUTRB1 V1P8VC OUTR2 OUTRB2 V1P8VC OUTR3 OUTRB3 V1P8VC OUTR4 OUTRB4 23 24 21 20 19 18 17 16 15 14 13 10 11 12 R6 1 OUT_0_SEL-I2C R9 10K PULL-UP FOR V1P8VC HARDWARE CONFIGURATION CONTROL REMOVE FOR I2C V1P8VCA 5 22 4 2 C2 1uF V1P8VCA C3 .1uF pin# 5 following pins have weak internal pull down resistors: 6, 7, 8, 9 and 24 VDDO4 OUT4 OUT4B VDDO3 OUT3 OUT3B VDDO2 OUT2 OUT2B VDDO1 OUT1 OUT1B VDDO0 OUT0_SEL_I2CB FOR LVDS, LVPECL USE TERMINATION ON RIGHT BEFORE AC COUPLING NP FG_X1 FG_X2 7 OUT_0_SEL-I2C 1 R10 1 R11 1 R12 R3 1 2 2 50 2 50 2 50 R5 49.9 1% 2 33 2 33 R4 49.9 1% 2 1 2 1 2 1 LVCMOS TERMINATION R15 1 2 33 2.5V and 3.3V HCSL TERMINATION 1 R13 1 R14 2 100 3.3V LVPECL TERMINATION LVDS TERMINATION 2 33 3 RECEIVER U4 RECEIVER U2 RECEIVER U3 1 8 for 7 6 pins#: 22,23,21,18,15,10 5 4 Date: 3 Wednesday, November 30, 2016 2 Sheet 1 of 1 1 Layout notes: 1. Separate Xout and Xin Traces by 3 x the trace width 2. Do not share crystal load capacitor ground via with other components. 3. Route power from bead through bulk capacitor pad then through 0.1uF capacitor pad then to clock chip NOTE:FERRITE BEAD FB1 = Vdd pad. Manufacture Part Number Z@100MHz PkgSz DC res. Current(Ma) 4. Do not share ground vias. One ground pin one ground Fair-Rite 2504021217Y0 120 0402 0.5 200 via. muRata BLM15AG221SN1 220 0402 0.35 300 muRata BLM15BB121SN1 120 0402 0.35 300 Integrated Device Technology TDK MMZ1005S241A 240 0402 0.18 200 San Jose, CA TECSTAR TB4532153121 120 0402 0.3 300 Size Document Number Rev Revision history A 5P49V6965_SCH 0.1 0.1 11/30/16 first publication SIGNAL_BEAD 1 VCC1P8 PLACE NEAR I2C CONTROLLER IF USED SDA SCL R8 10K V3P3 C6 NP GND 25.000 MHz CL = 8pF GND 2 1 D 4 Y1 2 1 2 1 1 2 2 1 1 2 1 2 1 2 1 2 1 2 1 2 2 EPAD EPAD EPAD EPAD EPAD EPAD EPAD EPAD EPAD 25 26 27 28 29 30 31 32 33 1 2 1 2 1 20 2 2 1 (c)2020 Renesas Electronics Corporation 1 8 A B C D 5P49V6965 Datasheet Typical Application Circuits Figure 9. Application Circuit Example August 20, 2020 5P49V6965 Datasheet Input - Driving the XIN/REF or CLKIN Driving XIN/REF with a CMOS Driver In some cases, it is encouraged to have XIN/REF driven by a clock input for reasons like better SNR, multiple input select with device CLKIN, etc. The XIN/REF pin is able to take an input when its amplitude is between 500mV and 1.2V and the slew rate more than 0.2V/ns. The XIN/REF input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XOUT pin can be left floating. Figure 10. Overdriving XIN with a CMOS Driver XOUT VDD Ro Rs Zo = 50 Ohm C3 R1 V_XIN XIN / REF Ro + Rs = 50 ohm 1 nF LVCMOS R2 Table 24. Nominal Voltage Divider Values for Overdriving XIN with Single-ended Driver LVCMOS Diver VDD Ro + Rs R1 R2 V_XIN (peak) Ro+Rs+R1+R2 3.3 50.0 130 75 0.97 255 2.5 50.0 100 100 1.00 250 1.8 50.0 62 130 0.97 242 Driving XIN with an LVPECL Driver Figure 11 shows an example of the interface diagram for a +3.3V LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XIN/REF input. It is recommended that all components in the schematics be placed in the layout; though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. If the driver is 2.5V LVPECL, the only change necessary is to use the appropriate value of R3. Figure 11. Overdriving XIN with an LVPECL Driver XOUT Zo = 50 Ohm C1 Zo = 50 Ohm 1 nF XIN / REF +3.3V LVPECL Driv er R1 50 R2 50 R3 50 (c)2020 Renesas Electronics Corporation 21 August 20, 2020 5P49V6965 Datasheet Wiring the CLKIN Pin to Accept Single-ended Inputs CLKIN cannot take a signal larger than 1.2V pk-pk due to the 1.2V regulated input inside. However, it is internally AC coupled so it is able to accept both LVDS and LVPECL input signals. Occasionally, it is desired to have CLKIN to take CMOS levels. Below is an example showing how this can be achieved. This configuration has three properties: 1. Total output impedance of Ro and Rs matches the 50 transmission line impedance. 2. Vrx voltage is generated at the CLKIN which maintains the LVCMOS driver voltage level across the transmission line for best S/N. 3. R1-R2 voltage divider values ensure that Vrx p-p at CLKIN is less than the maximum value of 1.2V. Figure 12. Recommended Schematic for Driving CLKIN with LVCMOS Driver VDD Ro Rs Zo = 50 Ohm R1 Vrx CLKI N Ro + Rs = 5 0 LVCMOS CLKI NB R2 VersaCloc k6 5Receiver Rec eiver VersaClock Table 25 shows resistor values that ensure the maximum drive level for the CLKIN port is not exceeded for all combinations of 5% tolerance on the driver VDD, VDDO0 and 5% resistor tolerances. The values of the resistors can be adjusted to reduce the loading for slower and weaker LVCMOS driver by increasing the impedance of the R1-R2 divider. To better assist this assessment, the total load (Ro + Rs + R1 + R2) on the driver is included in the table. Table 25. Nominal Voltage Divider Values for Overdriving CLKIN with Single-ended Driver LVCMOS Diver VDD Ro + Rs R1 R2 Vrx (peak) Ro+Rs+R1+R2 3.3 50.0 130 75 0.97 255 2.5 50.0 100 100 1.00 250 1.8 50.0 62 130 0.97 242 Driving CLKIN with Differential Clock CLKIN/CLKINB will accept DC coupled HCSL/LVPECL/LVDS signals. Figure 13. CLKIN, CLKINB Input Driven by an HCSL Driver Q nQ Zo=50ohm CLKIN Zo=50ohm CLKINB VersaClock 6 Receiver (c)2020 Renesas Electronics Corporation 22 August 20, 2020 5P49V6965 Datasheet Output - Single-ended or Differential Clock Terminations LVDS Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Zo) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100. differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. The standard termination schematic as shown in figure Standard Termination or the termination of figure Optional Termination can be used, which uses a center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. In addition, since these outputs are LVDS compatible, the input receiver's amplitude and common-mode input range should be verified for compatibility with the Renesas LVDS output. If using a non-standard termination, it is recommended to contact Renesas and confirm that the termination will function as intended. For example, the LVDS outputs can be AC coupled by placing capacitors between the LVDS outputs and the 100 shunt load. This is a common practice with receiver with internal self-bias circuitry. If using a non-standard termination, it is recommended to contact Renesas and confirm that the termination will function as intended. Figure 14. Standard and Optional Terminations Standard Termination LVDS Driver Z O ZT ZT LVDS Receiver Optional Termination LVDS Driver ZT 2 Z O ZT (c)2020 Renesas Electronics Corporation C 23 ZT 2 LVDS Receiver August 20, 2020 5P49V6965 Datasheet LVPECL Termination The clock layout topology shown below is a typical termination for LVPECL outputs. The differential outputs generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. For VDDO = 2.5V, the VDDO - 2V is very close to ground level. The R3 in 2.5V LVPECL output termination can be eliminated and the termination is shown in Figure 17, 2.5V LVPECL Output Termination. Figure 15. 3.3V LVPECL Output Termination (1) Figure 17. 2.5V LVPECL Output Termination 2.5V 3.3V 3.3V VDDO = 2.5V Zo = 50 Ohm + R1 250 Ohm Zo = 50 Ohm + Zo = 50 Ohm LVPECL R1 50 Ohm Zo = 50 Ohm Input R2 50 Ohm 2.5V LVPECL Driver RTT 50 Ohm Figure 16. 3.3V LVPECL Output Termination (2) R3 125 Ohm - R2 62.5 Ohm R4 62.5 Ohm Figure 18. 2.5V LVPECL Driver Termination (1) 3.3V 3.3V VDDO = 2.5V 2.5V 3.3V R4 125 Ohm Zo = 50 Ohm + Zo = 50 Ohm + Zo = 50 Ohm LVPECL Zo = 50 Ohm - 2.5V LVPECL Driver Input R1 84 Ohm 2.5V R3 250 Ohm R2 84 Ohm - R1 50 Ohm R2 50 Ohm Figure 19. 2.5V LVPECL Driver Termination (2) VDDO = 2.5V 2.5V Zo = 50 Ohm + Zo = 50 Ohm 2.5V LVPECL Driver - R1 50 Ohm R2 50 Ohm R3 18 Ohm (c)2020 Renesas Electronics Corporation 24 August 20, 2020 5P49V6965 Datasheet HCSL Termination HCSL termination scheme applies to both 3.3V and 2.5V V DDO. Figure 20. HCSL Receiver Terminated 33 Ohm VersaClock 6E Output Driver 33 Ohm Zo = 50 Ohm + Receiver Zo = 50 Ohm - HCSL 50 Ohm 50 Ohm Figure 21. HCSL Source Terminated Zo = 50 Ohm 33 Ohm VersaClock 6E Output Driver + Receiver Zo = 50 Ohm 33 Ohm - HCSL 50 Ohm 50 Ohm LVCMOS Termination Each output pair can be configured as a standalone CMOS or dual-CMOS output driver. CMOSD driver termination example is shown below. CMOS1 - Single CMOS active on OUTx pin. CMOS2 - Single CMOS active on OUTxB pin. CMOSD - Dual CMOS outputs active on both OUTx and OUTxB pins, 180 degrees out of phase. CMOSX2 - Dual CMOS outputs active on both OUTx and OUTxB pins, in-phase. Figure 22. LVCMOS Termination 33 Ohm VersaClock 6E Output Driver Zo = 50 Ohm + Receiver 33 Ohm Zo = 50 Ohm - CMOSD (c)2020 Renesas Electronics Corporation 25 August 20, 2020 5P49V6965 Datasheet Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/us/en/document/psc/24-vfqfpn-package-outline-drawing-40-x-40-x-09-mm-body-05mm-pitch-epad-280-x-280-mm-nlg24p2 Marking Diagram 6965A ddd YWW**$ Line 1: truncated part number. Line 2: "ddd" denotes dash code. Line 3: * "YWW" is the last digit of the year and week that the part was assembled. * "**" denotes sequential lot number. * "$" denotes mark code. Ordering Information 1 2 Orderable Part Number Package Carrier Type Temperature 5P49V6965AdddNLGI 4 x 4 mm, 0.5mm pitch 24-VFQFPN Tray -40 to +85C 5P49V6965AdddNLGI8 4 x 4 mm, 0.5mm pitch 24-VFQFPN Tape and Reel -40 to +85C 5P49V6965A000NLGI 4 x 4 mm, 0.5mm pitch 24-VFQFPN Tray -40 to +85C 5P49V6965A000NLGI8 4 x 4 mm, 0.5mm pitch 24-VFQFPN Tape and Reel -40 to +85C "ddd" denotes factory programmed configurations based on required settings. Contact factory for factory programming. "000" denotes un-programmed parts for user customization. (c)2020 Renesas Electronics Corporation 26 August 20, 2020 5P49V6965 Datasheet Revision History Revision Date Description of Change August 20, 2020 Updated the slew rate terminology in section Driving XIN/REF with a CMOS Driver. September 18, 2019 Updated Absolute Maximum Ratings table. Updated PCI Express Jitter Performance tables (Table 17 and Table 18). Updated Electrical Characteristics tables (Table 9, Table 11, and Table 14). June 19, 2019 August 31, 2018 Updated schematics for Driving XIN/REF with a CMOS Driver and Driving XIN with an LVPECL Driver. March 15, 2018 Updated absolute maximum ratings for supply voltage to 3.6V. Updated typical and maximum values in Current Consumption table. Minor updates to AC Timing Characteristics, Electrical Characteristics - CMOS Outputs, and Electrical PCIe specification updated. Added recommended power ramp time. Expanded spread spectrum value range. I2C tolerant voltage footnote changed to 3.3V. LVDS Termination section allows AC-coupling for LVDS signals. Characteristics - LVDS Outputs tables. November 6, 2017 Initial release. (c)2020 Renesas Electronics Corporation 27 August 20, 2020 24-VFQFPN, Package Outline Drawing 4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.80 x 2.80 mm NLG24P2, PSC-4192-02, Rev 02, Page 1 (c) Integrated Device Technology, Inc. 24-VFQFPN, Package Outline Drawing 4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.80 x 2.80 mm NLG24P2, PSC-4192-02, Rev 02, Page 2 Package Revision History (c) Integrated Device Technology, Inc. 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