LM5107
LM5107 100V / 1.4A Peak Half Bridge Gate Driver
Literature Number: SNVS333C
LM5107
100V / 1.4A Peak Half Bridge Gate Driver
General Description
The LM5107 is a low cost high voltage gate driver, designed
to drive both the high side and the low side N-Channel
MOSFETs in a synchronous buck or a half bridge configura-
tion. The floating high-side driver is capable of working with
rail voltages up to 100V. The outputs are independently
controlled with TTL compatible input thresholds. An inte-
grated on chip high voltage diode is provided to charge the
high side gate drive bootstrap capacitor. A robust level shifter
technology operates at high speed while consuming low
power and providing clean level transitions from the control
input logic to the high side gate driver. Under-voltage lockout
is provided on both the low side and the high side power
rails. The device is available in the SOIC-8 and the thermally
enhanced LLP-8 packages.
Features
nDrives both a high side and low side N-Channel
MOSFET
nHigh peak output current (1.4A sink / 1.3A source)
nIndependent TTL compatible inputs
nIntegrated bootstrap diode
nBootstrap supply voltage to 118V DC
nFast propagation times (27 ns typical)
nDrives 1000 pF load with 15ns rise and fall times
nExcellent propagation delay matching (2 ns typical)
nSupply rail under-voltage lockout
nLow power consumption
nPin compatible with ISL6700
Typical Applications
nCurrent Fed push-pull converters
nHalf and Full Bridge power converters
nSolid state motor drives
nTwo switch forward power converters
Package
nSOIC-8
nLLP-8 (4 mmx4mm)
Simplified Block Diagram
20130001
FIGURE 1.
March 2005
LM5107 100V / 1.4A Peak Half Bridge Gate Driver
© 2005 National Semiconductor Corporation DS201300 www.national.com
Connection Diagrams
Ordering Information
Ordering Number Package Type NSC Package Drawing Supplied As
LM5107MA SOIC-8 M08A Shipped in anti static rails
LM5107MAX SOIC-8 M08A 2500 shipped as Tape & Reel
LM5107SD LLP-8 SDC08A 1000 shipped as Tape & Reel
LM5107SDX LLP-8 SDC08A 4500 shipped as Tape & Reel
Pin Description
Pin # Name Description Application Information
SO-8 LLP-8
11V
DD
Positive gate drive supply Locally decouple to V
SS
using low ESR/ESL capacitor located
as close to IC as possible.
2 2 HI High side control input The LM5107 HI input is compatible with TTL input thresholds.
Unused HI input should be tied to ground and not left open
3 3 LI Low side control input The LM5107 LI input is compatible with TTL input thresholds.
Unused LI input should be tied to ground and not left open.
44V
SS
Ground reference All signals are referenced to this ground.
5 5 LO Low side gate driver output Connect to the gate of the low side N-MOS device.
6 6 HS High side source connection Connect to the negative terminal of the bootstrap capacitor
and to the source of the high side N-MOS device.
7 7 HO High side gate driver output Connect to the gate of the low side N-MOS device.
8 8 HB High side gate driver positive
supply rail
Connect the positive terminal of the bootstrap capacitor to HB
and the negative terminal of the bootstrap capacitor to HS.
The bootstrap capacitor should be placed as close to IC as
possible.
Note: For LLP-8 package it is recommended that the exposed pad on the bottom of the LM5107 be soldered to ground plane on the PCB board and the
ground plane should extend out from underneath the package to improve heat dissipation.
20130002 20130003
FIGURE 2.
LM5107
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
DD
to V
SS
-0.3V to 18V
HB to HS −0.3V to 18V
LI or HI to V
SS
−0.3V to V
DD
+0.3V
LO to V
SS
−0.3V to V
DD
+0.3V
HO to V
SS
V
HS
−0.3V to V
HB
+0.3V
HS to V
SS
(Note 6) −5V to 100V
HB to V
SS
118V
Junction Temperature -40˚C to +150˚C
Storage Temperature Range −55˚C to +150˚C
ESD Rating HBM (Note 2) 2 kV
Recommended Operating
Conditions
V
DD
8V to 14V
HS (Note 6) −1V to 100V
HB V
HS
+8V to V
HS
+14V
HS Slew Rate <50 V/ns
Junction Temperature −40˚C to +125˚C
Electrical Characteristics
Specifications in standard typeface are for T
J
= +25˚C, and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified, V
DD
=V
HB
= 12V, V
SS
=V
HS
= 0V, No Load on LO or HO .
Symbol Parameter Conditions Min Typ Max Units
SUPPLY CURRENTS
I
DD
V
DD
Quiescent Current LI = HI = 0V 0.3 0.6 mA
I
DDO
V
DD
Operating Current f = 500 kHz 2.1 3.4 mA
I
HB
Total HB Quiescent Current LI = HI = 0V 0.06 0.2 mA
I
HBO
Total HB Operating Current f = 500 kHz 1.6 3.0 mA
I
HBS
HB to V
SS
Current, Quiescent V
HS
=V
HB
= 100V 0.1 10 µA
I
HBSO
HB to V
SS
Current, Operating f = 500 kHz 0.5 mA
INPUT PINS LI and HI
V
IL
Low Level Input Voltage Threshold 0.8 1.8 V
V
IH
High Level Input Voltage Threshold 1.8 2.2 V
R
I
Input Pulldown Resistance 100 180 500 kΩ
UNDER VOLTAGE PROTECTION
V
DDR
V
DD
Rising Threshold V
DDR
=V
DD
-V
SS
6.0 6.9 7.4 V
V
DDH
V
DD
Threshold Hysteresis 0.5 V
V
HBR
HB Rising Threshold V
HBR
=V
HB
-V
HS
5.7 6.6 7.1 V
V
HBH
HB Threshold Hysteresis 0.4 V
BOOT STRAP DIODE
V
DL
Low-Current Forward Voltage I
VDD-HB
= 100 µA
V
DL
=V
DD
-V
HB
0.58 0.9 V
V
DH
High-Current Forward Voltage I
VDD-HB
= 100 mA
V
DH
=V
DD
-V
HB
0.82 1.1 V
R
D
Dynamic Resistance I
VDD-HB
= 100 mA 0.8 1.5 Ω
LO GATE DRIVER
V
OLL
Low-Level Output Voltage I
LO
= 100 mA
V
OHL
=V
LO
–V
SS
0.28 0.45 V
V
OHL
High-Level Output Voltage I
LO
= −100 mA,
V
OHL
=V
DD
–V
LO
0.45 0.75 V
I
OHL
Peak Pullup Current V
LO
= 0V 1.3 A
I
OLL
Peak Pulldown Current V
LO
= 12V 1.4 A
HO GATE DRIVER
V
OLH
Low-Level Output Voltage I
HO
= 100 mA
V
OLH
=V
HO
–V
HS
0.28 0.45 V
V
OHH
High-Level Output Voltage I
HO
= −100 mA
V
OHH
=V
HB
–V
HO
0.45 0.75 V
I
OHH
Peak Pullup Current V
HO
= 0V 1.3 A
I
OLH
Peak Pulldown Current V
HO
= 12V 1.4 A
LM5107
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Electrical Characteristics (Continued)
Specifications in standard typeface are for T
J
= +25˚C, and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified, V
DD
=V
HB
= 12V, V
SS
=V
HS
= 0V, No Load on LO or HO .
Symbol Parameter Conditions Min Typ Max Units
HO GATE DRIVER
THERMAL RESISTANCE
θ
JA
Junction to Ambient SOIC-8 160 ˚C/W
LLP-8 (Note 3) 40
Switching Characteristics
Specifications in standard typeface are for T
J
= +25˚C, and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified, V
DD
=V
HB
= 12V, V
SS
=V
HS
= 0V, No Load on LO or HO.
Symbol Parameter Conditions Min Typ Max Units
LM5100A
t
LPHL
Lower Turn-Off Propagation Delay (LI
Falling to LO Falling) 27 56 ns
t
HPHL
Upper Turn-Off Propagation Delay (HI
Falling to HO Falling) 27 56 ns
t
LPLH
Lower Turn-On Propagation Delay (LI
Rising to LO Rising) 29 56 ns
t
HPLH
Upper Turn-On Propagation Delay (HI
Rising to HO Rising) 29 56 ns
t
MON
Delay Matching: Lower Turn-On and
Upper Turn-Off 215 ns
t
MOFF
Delay Matching: Lower Turn-Off and
Upper Turn-On 215 ns
t
RC
,t
FC
Either Output Rise/Fall Time C
L
= 1000 pF 15 - ns
t
PW
Minimum Input Pulse Width that
Changes the Output 50 ns
t
BS
Bootstrap Diode Turn-Off Time I
F
= 100 mA,
I
R
= 100 mA 105 ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩresistor into each pin. Pin 6 , Pin 7 and Pin 8 are rated at 500V.
Note 3: 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power
planes embedded in PCB. See Application Note AN-1187.
Note 4: Min and Max limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 5: The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions.
Note 6: In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V.
However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently.
If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD = 10V, the negative transients at HS must not
exceed -5V.
LM5107
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Typical performance Characteristics
V
DD
Operating Current vs Frequency HB Operating Current vs Frequency
20130004 20130005
Operating Current vs Temperature Quiescent Current vs Temperature
20130006 20130007
Quiescent Current vs Voltage Propagation Delay vs Temperature
20130008 20130009
LM5107
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Typical performance Characteristics (Continued)
LO and HO High Level Output Voltage vs Temperature LO and HO Low Level Output Voltage vs Temperature
20130010 20130011
HO and LO Peak Output Current vs Output Voltage Doide Forward Voltage
20130012 20130013
Undervoltage Rising Thresholds vs Temperature Undervoltage Hysteresis vs Temperature
20130014 20130015
LM5107
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Typical performance Characteristics (Continued)
Input Thresholds vs Temperature Input Thresholds vs Supply Voltage
20130016 20130017
LM5107
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Timing Diagram
Layout Considerations
The optimum performance of high and low side gate drivers
cannot be achieved without taking due considerations during
circuit board layout. Following points are emphasized.
1. A low ESR / ESL capacitor must be connected close to
the IC, and between V
DD
and V
SS
pins and between HB
and HS pins to support high peak currents being drawn
from VDD during turn-on of the external MOSFET.
2. To prevent large voltage transients at the drain of the top
MOSFET, a low ESR electrolytic capacitor must be con-
nected between MOSFET drain and ground (V
SS
).
3. In order to avoid large negative transients on the switch
node (HS) pin, the parasitic inductances in the source of
top MOSFET and in the drain of the bottom MOSFET
(synchronous rectifier) must be minimized.
4. Grounding Considerations:
a) The first priority in designing grounding connections
is to confine the high peak currents from charging and
discharging the MOSFET gate in a minimal physical
area. This will decrease the loop inductance and mini-
mize noise issues on the gate terminal of the MOSFET.
The MOSFETs should be placed as close as possible to
the gate driver.
b) The second high current path includes the boot-
strap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low side MOSFET
body diode. The bootstrap capacitor is recharged on the
cycle-by-cycle basis through the bootstrap diode from
the ground referenced V
DD
bypass capacitor. The re-
charging occurs in a short time interval and involves high
peak current. Minimizing this loop length and area on the
circuit board is important to ensure reliable operation.
HS Transient Voltages Below
Ground
The HS node will always be clamped by the body diode of
the lower external FET. In some situations, board resis-
tances and inductances can cause the HS node to tran-
siently swing several volts below ground. The HS node can
swing below ground provided:
1. HS must always be at a lower potential than HO. Pulling
HO more than -0.3V below HS can activate parasitic
transistors resulting in excessive current to flow from the
HB supply possibly resulting in damage to the IC. The
same relationship is true with LO and VSS. If necessary,
a Schottky diode can be placed externally between HO
and HS or LO and GND to protect the IC from this type
of transient. The diode must be placed as close to the IC
pins as possible in order to be effective.
2. HB to HS operating voltage should be 15V or less .
Hence, if the HS pin transient voltage is -5V, VDD should
be ideally limited to 10V to keep HB to HS below 15V.
3. A low ESR bypass capacitor between HB to HS as well
as VDD to VSS is essential for proper operation. The
capacitor should be located at the leads of the IC to
minimize series inductance. The peak currents from LO
and HO can be quite large. Any series inductances with
the bypass capacitor will cause voltage ringing at the
leads of the IC which must be avoided for reliable
operation.
20130018
FIGURE 3.
LM5107
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Physical Dimensions inches (millimeters) unless otherwise noted
Controlling dimension is inch. Values in [ ] are millimeters.
Notes: Unless otherwise specified.
1. Standard lead finish to be 200 microinches/5.08 micrometers minimum lead/tin (solder) on copper.
2. Dimension does not include mold flash.
3. Reference JEDEC registration MS-012, Variation AA, dated May 1990.
SOIC-8 Outline Drawing
NS Package Number M08A
LM5107
www.national.com9
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Notes: Unless otherwise specified.
1. For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor web
page (www.national.com).
2. Maximum allowable metal burr on lead tips at the package edges is 76 microns.
3. No JEDEC registration as of May 2003.
LLP-8 Outline Drawing
NS Package Number SDC08A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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LM5107 100V / 1.4A Peak Half Bridge Gate Driver
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