204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS Description Pin Identification DDR3 SO-DIMM is high-speed, low power memory Symbol module that use 512Mx8bits DDR3 SDRAM in FBGA A0~A15, BA0~BA2 Address/Bank input DQ0~DQ63 Data Input / Output. DQS0~DQS7 Data strobes /DQS0~/DQS7 Differential Data strobes CK0, /CK0,CK1, /CK1 Clock Input. (Differential pair) use of system clock. Data I/O transactions are possible CKE0, CKE1 Clock Enable Input. on both edges of DQS. Range of operation frequencies, ODT0, ODT1 On-die termination control line programmable latencies allow the same device to be /CS0, /CS1 DIMM Rank Select Lines. useful for a variety of high bandwidth, high performance /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable DM0~DM7 Data masks/high data strobes VDD Voltage power supply VREFDQ/ VREFCA Power Supply for Reference VDDSPD SPD EEPROM Power Supply package and a 2048 bits serial EEPROM on a 204-pin printed circuit board. DDR3 SO-DIMM is a Dual In-Line Memory Module and is intended for mounting into 204-pin Function edge connector sockets. Synchronous design allows precise cycle control with the memory system applications. Features RoHS compliant products. JEDEC standard 1.5V 0.075V Power supply VDDQ=1.5V 0.075V Clock Freq: 667MHZ for 1333Mb/s/Pin. Clock Freq: 800MHZ for 1600Mb/s/Pin. I2C serial bus address select for SA0~SA2 Clock Freq: 933MHZ for 1866Mb/s/Pin. EEPROM Programmable CAS Latency: 5, 6, 7, 8, 9 ,10 ,11, 13 SCL I2C serial bus clock for EEPROM SDA I2C serial bus data for EEPROM VSS Ground /RESET Set DRAMs Known State 8 bit pre-fetch VTT SDRAM I/O termination supply Burst Length: 4, 8 NC No Connection Programmable Additive Latency (Posted /CAS): 0,CL-2 or CL-1 clock Programmable /CAS Write Latency (CWL) = 7(DDR3-1333), 8(DDR3-1600), 9(DDR3-1866) Bi-directional Differential Data-Strobe Internal calibration through ZQ pin On Die Termination with ODT pin Serial presence detect with EEPROM Asynchronous reset Dimensions (Unit: millimeter) Transcend Information Inc. 1 204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS Note: 1. Tolerances on all dimensions +/-0.15mm unless otherwise specified. Transcend Information Inc. 2 204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS Pin Assignments Pin No 01 03 05 07 09 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 Pin Name VREFDQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS /DQS1 DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS /DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 Pin No 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 Pin Name DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 VDD A8 A5 VDD A3 A1 VDD CK0 /CK0 VDD A10/AP BA0 VDD /WE /CAS VDD A13 /CS1,NC VDD TEST VSS DQ32 DQ33 VSS /DQS4 Pin No 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 Pin Name DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS /DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 Vtt Pin No 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 Pin Name VSS DQ4 DQ5 VSS /DQS0 DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 /RESET VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS /DQS3 DQS3 VSS DQ30 Pin No 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 Pin Name DQ31 VSS CKE1,NC VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1,NC /CK1,NC VDD BA1 /RAS VDD /CS0 ODT0 VDD ODT1,NC NC VDD VREFCA VSS DQ36 DQ37 VSS DM4 Pin No 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 /CS1,ODT1,CKE1Used for dual-rank SO-DIMMs; NC on single-rank SO-DIMMs. CK1 and /CK1Used for dual-rank SO-DIMMs; not used on single-rank SO-DIMMs but terminated. Transcend Information Inc. 3 Pin Name VSS DQ38 DQ39 VSS DQ44 DQ45 VSS /DQS5 DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS /DQS7 DQS7 VSS DQ62 DQ63 VSS NC SDA SCL Vtt 204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS Block Diagram 4GB, 512Mx64 Module(1 Rank x8) /S0 /D QS4 D QS4 DM4 /D QS 0 D QS0 D M0 DM DQ DQ DQ DQ DQ DQ DQ DQ 0 1 2 3 4 5 6 7 I /O I /O I /O I /O I /O I /O I /O I /O /C S D QS /D QS 0 1 2 3 4 5 6 7 DM DQ DQ DQ DQ DQ DQ DQ DQ D0 /D QS1 D QS1 D M1 8 9 10 11 12 13 14 15 I /O I /O I /O I /O I /O I /O I /O I /O /C S D QS /D QS 0 1 2 3 4 5 6 7 D1 I /O I /O I /O I /O I /O I /O I /O I /O B A 0~B A 2 A 0~A 15 CK E 0 /R A S /C A S /W E OD T 0 CK 0 /C K 0 /C S D QS /D QS 0 1 2 3 4 5 6 7 D5 DM DQ DQ DQ DQ DQ DQ DQ DQ D2 48 49 50 51 52 53 54 55 I /O I /O I /O I /O I /O I /O I /O I /O /C S D QS /D QS 0 1 2 3 4 5 6 7 D6 /D QS7 D QS7 DM7 DM 24 25 26 27 28 29 30 31 I /O I /O I /O I /O I /O I /O I /O I /O 40 41 42 43 44 45 46 47 /C S D QS /D QS 0 1 2 3 4 5 6 7 /D QS3 D QS3 D M3 DQ DQ DQ DQ DQ DQ DQ DQ D4 /D QS6 D QS6 DM6 DM 16 17 18 19 20 21 22 23 /C S D QS /D QS 0 1 2 3 4 5 6 7 DM DQ DQ DQ DQ DQ DQ DQ DQ /D QS2 D QS2 D M2 DQ DQ DQ DQ DQ DQ DQ DQ I/O I/O I/O I/O I/O I/O I/O I/O /D QS5 D QS5 DM5 DM DQ DQ DQ DQ DQ DQ DQ DQ 32 33 34 35 36 37 38 39 I /O I /O I /O I /O I /O I /O I /O I /O /C S D QS /D QS 0 1 2 3 4 5 6 7 DM DQ DQ DQ DQ DQ DQ DQ DQ D3 B A 0- B A 2: SD R A Ms D 0- D 7 A 0-A 15: SD R A Ms D 0- D 7 C K E : SD R A Ms D 0- D 7 /R A S : SD R A Ms D 0- D 7 /C A S : SD R A Ms D 0- D 7 /W E : SD R A Ms D 0- D 7 OD T : SD R A Ms D 0- D 7 C K : SD R A Ms D 0- D 7 /C K : SD R A Ms D 0- D 7 I /O I /O I /O I /O I /O I /O I /O I /O 56 57 58 59 60 61 62 63 E E PR OM SC L WP A0 A1 A2 SA 0 SA 1SA 2 /C S D QS /D QS 0 1 2 3 4 5 6 7 D7 V D D SPD V D D /V D D Q SD A V R E FDQ V SS V RE FCA E E PR OM D 0~D 7 D 0~D 7 D 0~D 7 D 0~D 7 NOTE: 1. D Q -to-I/O w iring is show n as recom m ended but m ay be changed. 2. D Q ,D Q S ,/D Q S ,O D T ,D M ,C K E ,/S relationships m ust be m aintained as show n. 3. D Q ,D M ,D Q S ,/D Q S resistors: R efer to associated topology diagram . This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice. 8GB, 1Gx64 Module(2 Rank x8) Transcend Information Inc. 4 204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS /S0 /S1 /D Q S4 D Q S4 DM 4 /D Q S0 D Q S0 DM 0 DM DQ DQ DQ DQ DQ DQ DQ DQ 0 1 2 3 4 5 6 7 I/O I/O I/O I/O I/O I/O I/O I/O /C S D Q S /D Q S 0 1 2 3 4 5 6 7 D0 ZQ DM I/O I/O I/O I/O I/O I/O I/O I/O /C S D Q S /D Q S 0 1 2 3 4 5 6 7 DM DQ DQ DQ DQ DQ DQ DQ DQ D8 ZQ /D Q S1 D Q S1 DM 1 I/O I/O I/O I/O I/O I/O I/O I/O 8 9 10 11 12 13 14 15 /C S D Q S /D Q S 0 1 2 3 4 5 6 7 D1 ZQ DM I/O I/O I/O I/O I/O I/O I/O I/O /C S D Q S /D Q S 0 1 2 3 4 5 6 7 D4 ZQ DM I/O I/O I/O I/O I/O I/O I/O I/O /C S D Q S /D Q S 0 1 2 3 4 5 6 7 D 12 ZQ D9 ZQ I/O I/O I/O I/O I/O I/O I/O I/O 40 41 42 43 44 45 46 47 /C S D Q S /D Q S 0 1 2 3 4 5 6 7 D5 ZQ DM I/O I/O I/O I/O I/O I/O I/O I/O /C S D Q S /D Q S 0 1 2 3 4 5 6 7 D 13 ZQ /D Q S6 D Q S6 DM 6 DM 16 17 18 19 20 21 22 23 I/O I/O I/O I/O I/O I/O I/O I/O /C S D Q S /D Q S 0 1 2 3 4 5 6 7 D2 ZQ DM I/O I/O I/O I/O I/O I/O I/O I/O /C S D Q S /D Q S 0 1 2 3 4 5 6 7 DM DQ DQ DQ DQ DQ DQ DQ DQ D 10 ZQ /D Q S3 D Q S3 DM 3 48 49 50 51 52 53 54 55 I/O I/O I/O I/O I/O I/O I/O I/O /C S D Q S /D Q S 0 1 2 3 4 5 6 7 D6 ZQ DM I/O I/O I/O I/O I/O I/O I/O I/O /C S D Q S /D Q S 0 1 2 3 4 5 6 7 D 14 ZQ /D Q S7 D Q S7 DM 7 DM DQ DQ DQ DQ DQ DQ DQ DQ /C S D Q S /D Q S 0 1 2 3 4 5 6 7 DM DQ DQ DQ DQ DQ DQ DQ DQ /D Q S2 D Q S2 DM 2 DQ DQ DQ DQ DQ DQ DQ DQ I/O I/O I/O I/O I/O I/O I/O I/O /D Q S5 D Q S5 DM 5 DM DQ DQ DQ DQ DQ DQ DQ DQ 32 33 34 35 36 37 38 39 I/O I/O I/O I/O I/O I/O I/O I/O 24 25 26 27 28 29 30 31 /C S D Q S /D Q S 0 1 2 3 4 5 6 7 D3 ZQ ZQ of D 0- D 15 DM I/O I/O I/O I/O I/O I/O I/O I/O /C S D Q S /D Q S 0 1 2 3 4 5 6 7 DM DQ DQ DQ DQ DQ DQ DQ DQ D 11 ZQ 240 O hm *16 I/O I/O I/O I/O I/O I/O I/O I/O 56 57 58 59 60 61 62 63 EEPR O M SC L B A 0~B A 2 A 0~A 15 C K E1 C K E0 /R A S /C A S /W E O D T0 O D T1 CK 0 /C K 0 CK 1 /C K 1 B A 0- B A 2:SD R A M s D 0- D 15 A 0-A 15:SD R A M s D 0- D 15 C K E:SD R A M s D 8- D 15 C K E:SD R A M s D 0- D 7 /R A S:SD R A M s D 0- D 15 /C A S:SD R A M s D 0- D 15 /W E:SD R A M s D 0- D 15 O D T:SD R A M s D 0- D 7 O D T:SD R A M s D 8- D 15 C K :SD R A M s D 0- D 7 /C K :SD R A M s D 0- D 7 C K :SD R A M s D 8- D 15 /C K :SD R A M s D 8- D 15 WP A0 A1 A2 SA 0 SA 1SA 2 /C S D Q S /D Q S 0 1 2 3 4 5 6 7 D7 ZQ DM I/O I/O I/O I/O I/O I/O I/O I/O /C S D Q S /D Q S 0 1 2 3 4 5 6 7 D 15 ZQ EEPR O M D 0~D 15 D 0~D 15 D 0~D 15 D 0~D 15 V D D SPD V D D /V D D Q SD A V R EFD Q V SS V R EFC A NOTE: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ,DQS,/DQS,ODT,DM,CKE,/S relationships must be maintained as shown. 3. DQ,DM,DQS,/DQS resistors: Refer to associated topology diagram. 4. For each DRAM,a unique ZQ resistor is connected to ground. The ZQ resistor is 240 Ohm +/-1% This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice. Operating Temperature Condition Parameter Operating Temperature Transcend Information Inc. 5 Symbol Rating Unit Note TOPER 0 to 85 1,2 204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS Note: 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 2. At 0 - 85C, operation temperature range are the temperature which all DRAM specification will be supported. Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD -0.4 ~ 1.975 V 1 Voltage on VDDQ pin relative to Vss VDDQ -0.4 ~ 1.975 V 1 Voltage on any pin relative to Vss VIN, VOUT -0.4 ~ 1.975 V 1 Storage temperature TSTG -55~+100 1,2 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the Note: device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. AC & DC Operating Conditions Recommended DC operating conditions (SSTL -1.5) Rating Parameter Symbol Unit Note Min Typ. Max Supply voltage VDD 1.425 1.5 1.575 V Supply voltage for Output VDDQ 1.425 1.5 1.575 V I/O Reference Voltage (DQ) VREFDQ(DC) 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ V I/O Reference Voltage (CMD/ADD) VREFCA(DC) 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ V AC Input Logic High VIH(AC) VREF+0.175 V AC Input Logic Low VIL(AC) VREF-0.175 V DC Input Logic High VIH(DC) VREF+0.1 VDD V DC Input Logic Low VIL(DC) VSS VREF-0.1 V Note: There is no specific device VDD supply voltage requirement for SSTL-1.5 compliance. 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together. 3. Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD. 1, 2 1, 2 3 3 AC Input Level for Differential Signals Parameter Differential Input Logical High Differential Input Logical Low Transcend Information Inc. Symbol VIHdiff VILdiff 6 Value +200 -200 Unit mV Note 204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS IDD Specification parameters Definition( IDD values are for full operating range of Voltage and Temperature) 4GB, 512Mx64 Module(1 Rank x8) Parameter Symbol DDR3 1333 CL9 DDR3 1600 Unit CL11 IDD0 320 360 mA IDD1 400 440 mA IDD2P 120 120 mA IDD2Q 160 160 mA IDD2N 160 160 mA IDD3P 160 160 mA IDD3N 240 240 mA IDD4R 680 800 mA IDD4W 720 880 mA IDD5 1160 1160 mA IDD6 120 120 mA IDD7 1360 1400 mA Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and /CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Note: 1.Module IDD was calculated on the specific brand DRAM(3Xnm) component IDD and can be differently measured according to DQ loading capacitor. 8GB, 1Gx64 Module(2 Rank x8) Transcend Information Inc. 7 204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS Parameter Symbol DDR3 1333 CL9 DDR3 1600 CL11 DDR3 1866 CL13 Unit IDD0 480 520 520 mA IDD1 560 600 600 mA IDD2P 240 240 240 mA IDD2Q 320 320 320 mA IDD2N 320 320 320 mA IDD3P 320 320 320 mA IDD3N 400 400 400 mA IDD4R 840 960 1000 mA IDD4W 880 1040 1080 mA IDD5 1320 1320 1320 mA IDD6 240 240 240 mA IDD7 1520 1560 1560 mA Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and /CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Note: 1.Module IDD was calculated on the specific brand DRAM(3Xnm) component IDD and can be differently measured according to DQ loading capacitor. Timing Parameters & Specifications Speed Transcend Information Inc. DDR3 1333 8 DDR3 1600 DDR3 1866 Unit 204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS Parameter Symbol Min Max Min Max <1.5 Min 1.07 Max <1.25 Average Clock Period tCK 1.5 <1.875 1.25 ns CK high-level width tCH 0.47 0.53 0.47 0.53 0.47 0.53 tCK CK low-level width tCL 0.47 0.53 0.47 0.53 0.47 0.53 tCK tDQSQ - 125 - 100 - 85 ps tQH 0.38 - 0.38 - 0.38 - tCK tLZ(DQ) -500 250 -450 225 -390 195 tHZ(DQ) - 250 - 225 - 195 tDS 30 - 10 - - - ps tDH 65 - 45 - 20 - ps tDIPW 400 - 360 - 320 - ps tRPRE 0.9 - 0.9 - 0.9 - tCK tRPST 0.3 - 0.3 - 0.3 - tCK tWPRE 0.9 - 0.9 - 0.9 - tCK DQS, /DQS Write postamble DQS, /DQS low-impedance time tWPST tLZ(DQS) 0.3 -500 250 0.3 -450 225 0.3 -390 195 tCK ps DQS, /DQS high-impedance time tHZ(DQS) - 250 - 225 - 195 ps tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 tCK tDQSS -0.25 +0.25 -0.27 +0.27 -0.27 +0.27 tCK tDSS 0.2 - 0.9 - 0.18 - tCK tDSH 0.2 - 0.3 - 0.18 - tCK DQS, /DQS to DQ skew, per group, per access DQ output hold time from DQS, /DQS DQ low-impedance time from CK, /CK DQ high-impedance time from CK, /CK Data setup time to DQS, /DQS reference to Vih(ac)Vil(ac) levels Data hold time to DQS, /DQS reference to Vih(ac)Vil(ac) levels DQ and DM input pulse width for each input DQS, /DQS Read preamble DQS, /DQS differential Read postamble DQS, /DQS Write preamble DQS, /DQS differential input low pulse width DQS, /DQS differential input high pulse width DQS, /DQS rising edge to CK, /CK rising edge DQS, /DQS falling edge setup time to CK, /CK rising edge DQS, /DQS falling edge hold time to CK, /CK rising edge Delay from start of Internal write transaction to Internal read command Write recovery time Mode register set command cycle time /CAS to /CAS command delay Auto precharge write recovery + precharge time Speed Parameter Active to active command period for Transcend Information Inc. tWR Max (4tck, 7.5ns) 15 - Max (4tck, 7.5ns) 15 tMRD 4 - tCCD 4 - tDAL tWR+tRP/tck Symbol tRRD DDR3 1333 Min Max Max - tWTR - 9 - Max (4tck, 7.5ns) 15 4 - 4 - - ps ps - ns 4 - tCK 4 - nCK tWR+tRP/tck tWR+tRP/tck nCK DDR3 1600 Min Max Max - DDR3 1866 Min Max Max - Unit ns 204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS 1KB page size Active to active command period for 2KB page size Four Activate Window for 1KB page size Four Activate Window for 2KB page size products Power-up and RESET calibration time Normal operation Full calibration time Normal operation short calibration time Exit self refresh to commands not requiring a locked DLL Exit self refresh to commands requiring a locked DLL Internal read to precharge command delay tRRD - - 30 - 27 - ns tFAW 45 - 40 - 35 - ns tZQinitl 512 - 512 - 512 - tCK tZQoper 256 - 256 - 256 - tCK tZQcs 64 - 64 - 64 - tCK tXS Max (5tCK, tRFC+10n s) - Max (5tCK, tRFC+10 ns) - Max (5tCK, tRFC+10 ns) - tXSDLL tDLL(min) - tDLL(min) - tDLL(min) - tRTP Exit power down with DLL to any valid command: Exit Precharge Power Down with DLL tXP CKE minimum pulse width (high and low pulse width) tCKE Transcend Information Inc. - (4tck, 5ns) Max (4tck, 6ns) 30 tCKESR ODT turn-off - (4tck, 6ns) Max (4tck, 7.5ns) tFAW Minimum CKE low width for Self refresh entry to exit timing Asynchronous RTT turn-on delay (Power-Down mode) Asynchronous RTT turn-off delay (Power-Down mode) ODT turn-on (4tck, 6ns) Max (4tck, 7.5ns) Max (4tCK, 7.5ns) tCK(min)+ 1tCK Max (3tCK, 6ns) Max (3tCK,5.6 25ns) - - Max (4tck, 7.5ns) tCK(min)+ 1tCK Max (3tCK, 6ns) Max (3tCK, 5ns) - - Max (4tck, 7.5ns) tCK(min)+ 1tCK Max (3tCK, 6ns) Max (3tCK, 5ns) tCK - - tAONPD 2 8.5 2 8.5 2 8.5 ns tAOFPD 2 8.5 2 8.5 2 8.5 ns tAON -250 250 -225 225 -195 195 ps tAOF 0.3 0.7 0.3 0.7 0.3 0.7 tCK 10 204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS Serial Presence Detect Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32-59 60 Function Described Standard Specification CRC:0-116Byte Number of SPD Bytes written / SPD device size / CRC SPD Byte use: 176Byte coverage during module production SPD Byte total: 256Byte SPD Revision Version 1.0 Key Byte / DRAM Device Type DDR3 SDRAM Key Byte / Module Type SODIMM SDRAM Density and Banks 4Gb 8banks SDRAM Addressing ROW:16, Column:10 Reserved Module Organization 2Rank / x8 Module Memory Bus Width Non ECC, 64bit Fine Timebase Dividend and Divisor 2.5ps Medium Timebase Dividend 0.125ns Medium Timebase Divisor 0.125ns SDRAM Minimum Cycle Time (tCKmin) 1.5ns Reserved CAS Latencies Supported, Least Significant Byte 5, 6, 7, 8, 9 CAS Latencies Supported, Most Significant Byte Minimum CAS Latency Time (tAAmin) 13.125ns Minimum Write Recovery Time (tWRmin) 15ns Minimum /RAS to /CAS Delay Time (tRCDmin) 13.125ns Minimum Row Active to Row Active Delay Time 6ns (tRRDmin) Minimum Row Precharge Time (tRPmin) 13.125ns Upper Nibble for tRAS and tRC Minimum Active to Precharge Time (tRASmin) 36ns Minimum Active to Active/Refresh Time (tRCmin) 49.125ns Minimum Refresh Recovery Time (tRFCmin), Least 260ns Significant Byte Minimum Refresh Recovery Time (tRFCmin), Most 260ns Significant Byte Minimum Internal Write to Read Command Delay Time 7.5ns (tWTmin) Minimum Internal Read to Precharge Command Delay 7.5ns Time (tRTPmin) Upper Nibble for tFAW 30ns Minimum Four Active Window Delay Time (tFAWmin) 30ns DLL off Mode, SDRAM Optional Features RZQ/6, RZQ/7 SDRAM Thermal and Refresh Options No ODTs, No ASR Reserved Module Nominal Height 30mm Transcend Information Inc. 11 Vendor Part 92 10 0B 03 04 21 00 09 03 52 01 08 0C 00 3E 00 69 78 69 30 69 11 20 89 20 08 3C 3C 00 F0 83 01 00 0F 204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS 61 62 63 64-116 117 118 119 120-121 122-125 126-127 Module Max Thickness Reference Raw Card Used Address Mapping from Edge Connector to DRAM Reserved Module Manufacturer ID Code, Least Significant Byte Module Manufacturer ID Code, Most Significant Byte Module Manufacturing Location Module Manufacturing Date Module Serial Number Cyclical Redundancy Code Planar Double Sides R/C F Standard Transcend Transcend Taipei - 11 25 00 00 01 4F 54 00 00 DA, DE 54 53 31 47 53 4B 128-145 Module Part Number 36 34 56 33 48 20 20 20 20 20 20 20 146-147 148-149 150-175 176-255 Revision Code DRAM Manufacturer ID Code Manufacturer Specific Data Open for customer use Transcend Information Inc. By Manufacturer By Manufacturer Undefined 12 00 Variable Variable 00 204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS Serial Presence Detect Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32-59 60 61 62 Function Described Standard Specification CRC:0-116Byte Number of SPD Bytes written / SPD device size / CRC SPD Byte use: 176Byte coverage during module production SPD Byte total: 256Byte SPD Revision Version 1.0 Key Byte / DRAM Device Type DDR3 SDRAM Key Byte / Module Type SODIMM SDRAM Density and Banks 4Gb 8banks SDRAM Addressing ROW:16, Column:10 Reserved Module Organization 2Rank / x8 Module Memory Bus Width Non ECC, 64bit Fine Timebase Dividend and Divisor 1ps Medium Timebase Dividend 0.125ns Medium Timebase Divisor 0.125ns SDRAM Minimum Cycle Time (tCKmin) 1.25ns Reserved CAS Latencies Supported, Least Significant Byte 5, 6, 7, 8, 9,10,11 CAS Latencies Supported, Most Significant Byte Minimum CAS Latency Time (tAAmin) 13.125ns Minimum Write Recovery Time (tWRmin) 15ns Minimum /RAS to /CAS Delay Time (tRCDmin) 13.125ns Minimum Row Active to Row Active Delay Time 6ns (tRRDmin) Minimum Row Precharge Time (tRPmin) 13.125ns Upper Nibble for tRAS and tRC Minimum Active to Precharge Time (tRASmin) 35ns Minimum Active to Active/Refresh Time (tRCmin) 48.125ns Minimum Refresh Recovery Time (tRFCmin), Least 260ns Significant Byte Minimum Refresh Recovery Time (tRFCmin), Most 260ns Significant Byte Minimum Internal Write to Read Command Delay Time 7.5ns (tWTmin) Minimum Internal Read to Precharge Command Delay 7.5ns Time (tRTPmin) Upper Nibble for tFAW 30ns Minimum Four Active Window Delay Time (tFAWmin) 30ns DLL off Mode, SDRAM Optional Features RZQ/6, RZQ/7 SDRAM Thermal and Refresh Options No ODTs, No ASR Reserved Module Nominal Height 30mm Module Max Thickness Planar Double Sides Reference Raw Card Used R/C F Transcend Information Inc. 13 Vendor Part 92 10 0B 03 04 21 00 09 03 11 01 08 0A 00 FE 00 69 78 69 30 69 11 18 81 20 08 3C 3C 00 F0 83 01 00 0F 11 25 204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS 63 64-116 117 118 119 120-121 122-125 126-127 Address Mapping from Edge Connector to DRAM Reserved Module Manufacturer ID Code, Least Significant Byte Module Manufacturer ID Code, Most Significant Byte Module Manufacturing Location Module Manufacturing Date Module Serial Number Cyclical Redundancy Code Standard Transcend Transcend Taipei - 00 00 01 4F 54 00 00 19, 92 54 53 31 47 53 4B 128-145 Module Part Number 36 34 56 36 48 20 20 20 20 20 20 20 146-147 148-149 150-175 176-255 Revision Code DRAM Manufacturer ID Code Manufacturer Specific Data Open for customer use Transcend Information Inc. By Manufacturer By Manufacturer Undefined 14 00 Variable Variable 00 204Pin DDR3 1600 SO-DIMM 8GB Based on 512Mx8 TS8D30AR00SNS Transcend Information Inc. 15