R10DS0152EJ0100 Rev.1.00 Page 1 of
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R1LV0108E Series
1Mb Advanced LPSRAM (128k word x 8bit)
Description
The R1LV0108E Series is a family of low vo ltage 1-Mbit static RAMs organized as 131,072-word by 8-bit, fabricated
by Renesas’s high-performance 0.15um CMOS and TFT technologies. The R1LV0108E Series has realized higher
density, higher performance an d low power consumption. The R1LV0108E Series is suitable for memory applications
where a simple interfacing, battery operating and battery backup are the important design objectives. It has been
packaged in 32-pin SOP,32-pin TSOP and 32-pin sTSOP.
Features
Single 2.7~ 3. 6 V power suppl y
Small stand-by current: 0.6µA (3.0V, typical)
No clocks, No refresh
All inputs and outputs are TTL compatible.
Easy memory expansion by CS1# and CS2
Common Data I/O
Three-state outputs: OR-tie Capability
OE# prevents data contention on the I/O bus
R10DS0152EJ0100
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R1LV0108E Series
R10DS0152EJ0100 Rev.1.00 Page 2 of
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Ordering Information
Orderable Part Name Access
time
Temperature
Range Package Shipping
Container Quantity
R1LV0108ESN-5SR#B*
55 ns
0 ~ +70°C
525-mil 32-pin
plastic SOP
PRSP0032DF-A
(32P2S-A)
Tube
Max. 25pcs/Tube
Max. 225pcs/Inner Bag
Max. 900pcs/Inner Box
R1LV0108ESN-5SI#B* -40 ~ +85°C
R1LV0108ESN-7SR#B*
70 ns
0 ~ +70°C
R1LV0108ESN-7SI#B* -40 ~ +85°C
R1LV0108ESN-5SR#S*
55 ns
0 ~ +70°C
Embossed
tape 1000pcs/Reel
R1LV0108ESN-5SI#S* -40 ~ +85°C
R1LV0108ESN-7SR#S*
70 ns
0 ~ +70°C
R1LV0108ESN-7SI#S* -40 ~ +85°C
R1LV0108ESA-5SR#B*
55 ns
0 ~ +70°C
8mm×13.4mm 32-pin
plastic sTSOP
(normal-bend type)
PTSA0032KB-A
(32P3K-B)
Tray Max. 234pcs/Tray
Max. 1872pcs/Inner Box
R1LV0108ESA-5SI#B* -40 ~ +85°C
R1LV0108ESA-7SR#B*
70 ns
0 ~ +70°C
R1LV0108ESA-7SI#B* -40 ~ +85°C
R1LV0108ESA-5SR#S*
55 ns
0 ~ +70°C
Embossed
tape 1000pcs/Reel
R1LV0108ESA-5SI#S* -40 ~ +85°C
R1LV0108ESA-7SR#S*
70 ns
0 ~ +70°C
R1LV0108ESA-7SI#S* -40 ~ +85°C
R1LV0108ESF-5SR#B*
55 ns
0 ~ +70°C
8mm×20mm 32-pin
plastic TSOP
(normal-bend type)
PTSA0032KA-A
(32P3H-E)
Tray Max. 156pcs/Tray
Max. 1248pcs/Inner Box
R1LV0108ESF-5SI#B* -40 ~ +85°C
R1LV0108ESF-7SR#B*
70 ns
0 ~ +70°C
R1LV0108ESF-7SI#B* -40 ~ +85°C
R1LV0108ESF-5SR#S*
55 ns
0 ~ +70°C
Embossed
tape 1000pcs/Reel
R1LV0108ESF-5SI#S* -40 ~ +85°C
R1LV0108ESF-7SR#S*
70 ns
0 ~ +70°C
R1LV0108ESF-7SI#S* -40 ~ +85°C
R1LV0108E Series
R10DS0152EJ0100 Rev.1.00 Page 3 of
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Pin Arrangement
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
V
cc
A15
CS2
WE#
A13
A8
A9
A11
OE#
A10
CS1#
DQ7
DQ6
DQ5
DQ4
DQ3
32-pin SOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
WE#
CS2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
OE#
A10
CS1#
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-pin sTSOP
A11
A9
A8
A13
WE#
CS2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
OE#
A10
CS1#
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-pin TSOP
(normal-bend)
R1LV0108E Series
R10DS0152EJ0100 Rev.1.00 Page 4 of
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Pin Description
Pin name Function
Vcc Power supply
Vss Ground
A0 to A16 Address input
DQ0 to DQ7 Data input/output
CS1# Chip select 1
CS2 Chip select 2
WE# Write enable
OE# Output enable
NC Non connection
Block Diagram
A
0
CS1#
A
1
WE#
OE#
A16
DQ0
DQ1
DQ7
Vcc
Vss
COLUMN DECODER
DQ
BUFFER
ADDRESS
BUFFER
ROW
DECODER
SENSE / WRITE AMPLIFIER
CLOCK
GENERATOR
MEMORY ARRAY
128k-word x8-bit
CS2
R1LV0108E Series
R10DS0152EJ0100 Rev.1.00 Page 5 of
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Operation Table
CS1# CS2 WE# OE# DQ0~7 Operation
X L X X High-Z Stand-by
H X X X High-Z Stand-by
L H L X Din Write
L H H L Dout Read
L H H H High-Z Output disable
Note 1. H: VIH L:V
IL X: V
IH or VIL
Absolute Maximum
Parameter Symbol Value unit
Power supply voltage relative to Vss Vcc -0.3 to +4.6 V
Terminal voltage on any pin relative to Vss VT -0.3*1 to Vcc+0.3*2 V
Power dissipation PT 0.7 W
Operation temperature Topr*3 R Ver. 0 to +70 °C
I Ver. -40 to +85
Storage temperature range Tstg -65 to 150 °C
Storage temperature range under bias Tbias*3 R Ver. 0 to +70 °C
I Ver. -40 to +85
Note 1. –3.0V for pulse ≤ 30ns (full width at half maximum)
2. Maximum voltage is +4.6V.
3. Ambient temperature range depends on R/I-version. Please see table on page 1.
R1LV0108E Series
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DC Operating Conditions
Parameter Symbol Min. Typ. Max. Unit Note
Supply voltage Vcc 2.7 3.0 3.6 V
Vss 0 0 0 V
Input high voltage VIH 2.0 - Vcc+0.3 V
Input low voltage VIL -0.3 - 0.6 V 1
Ambient temperature range R Ver. Ta 0 - +70 °C 2
I Ver. -40 - +85 °C 2
Note 1. –3.0V for pulse ≤ 30ns (full width at half maximum)
2. Ambient temperature range depends on R/I-version. Please see table on page 1.
DC Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions
Input leakage current | ILI | - - 1 A Vin = Vss to Vcc
Output leakage current
| ILO | - - 1 A
CS1# =VIH or CS2 =VIL or
OE# =VIH,
VI/O =Vss to Vcc
Average operating current ICC1 - 15 25 mA Min. cycle, duty =100%, II/O = 0mA
CS1# =VIL, CS2 =VIH, Others = VIH/VIL
ICC2 - 2 5 mA
Cycle =1s, duty =100%, II/O = 0mA
CS1# ≤ 0.2V, CS2 ≥ Vcc-0.2V,
VIH ≥ Vcc-0.2V, VIL ≤ 0.2V
Standby current
ISB - - 0.33 mA
“CS2 =VIL“ or
“CS2 = VIH and CS1# =VIH”,
Others = Vss to Vcc
Standby current
ISB1
- 0.6*1 2 A ~+25°C Vin = Vss to Vcc
(1) CS2 ≤ 0.2V or
(2) CS1# ≥ Vcc-0.2V,
CS2 ≥ Vcc-0.2V
- - 3 A ~+40°C
- - 8 A ~+70°C
- - 10 A ~+85°C
Output high voltage VOH 2.4 - - V IOH = -0.5mA
VOH2
Vcc
- 0.5 - - V IOH = -0.05mA
Output low voltage VOL - - 0.4 V IOL = 2mA
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
Capacitance
(Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = 0 ~ +70°C / -40 ~ +85°C*2)
Parameter Symbol Min. Typ. Max. Unit Test conditions Note
Input capacitance C in - - 8 pF Vin =0V 1
Input / output capacitance C I/O - - 10 pF VI/O =0V 1
Note 1. This parameter is sampled and not 100% tested.
2. Ambient temperature range depends on R/I-version. Please see table on page 1.
R1LV0108E Series
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AC Characteristics
Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = 0 ~ +70°C / -40 ~ +85°C*1)
Input pulse levels: VIL = 0.4V, VIH = 2.2V
Input rise and fall time: 5n s
Input and output timing reference level: 1.5V
Output load: See figures (Including scope and jig)
Note 1. Ambient temperature range depends on R/I-version. Please see table on page 1.
DQ
1.5V
RL = 500 ohm
CL = 30 pF
R1LV0108E Series
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Read Cycle
Parameter Symbol R1LV0108E**-5** R1LV0108E**-7** Unit Note
Min. Max. Min. Max.
Read cycle time tRC 55 - 70 - ns
Address access time tAA - 55 - 70 ns
Chip select access time tACS1 - 55 - 70 ns
tACS2 - 55 - 70 ns
Output enable to output valid tOE - 30 - 35 ns
Output hold from address change tOH 5 - 10 - ns
Chip select to output in low-Z tCLZ1 5 - 10 - ns 2,3
tCLZ2 5 - 10 - ns 2,3
Output enable to output in low-Z tOLZ 5 - 5 - ns 2,3
Chip deselect to output in high-Z tCHZ1 0 20 0 25 ns 1,2,3
tCHZ2 0 20 0 25 ns 1,2,3
Output disable to output in high-Z tOHZ 0 20 0 25 ns 1,2,3
Write Cycle
Parameter Symbol R1LV0108E**-5** R1LV0108E**-7** Unit Note
Min. Max. Min. Max.
Write cycle time tWC 55 - 70 - ns
Address valid to end of write tAW 50 - 55 - ns
Chip select to end of write tCW 50 - 55 - ns 5
Write pulse width tWP 45 - 50 - ns 4
Address setup time tAS 0 - 0 - ns 6
Write recovery time tWR 0 - 0 - ns 7
Data to write time overlap tDW 25 - 30 - ns
Data hold from write time tDH 0 - 0 - ns
Output enable from end of write tOW 5 - 5 - ns 2
Output disable to output in high-Z tOHZ 0 20 0 25 ns 1,2
Write to output in high-Z tWHZ 0 20 0 25 ns 1,2
Note 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from
device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE#.
A write begins at the latest transition among CS1# going low, CS2 going high and WE# going low.
A write ends at the earliest transition among CS1# going high, CS2 going low and WE# going high.
tWP is measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS1# going low or CS2 going high to end of write.
6. tAS is measured the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
8. Don’t apply inverted phase signal externally when DQ pin is output mode.
R1LV0108E Series
R10DS0152EJ0100 Rev.1.00 Page 9 of
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Timing Waveforms
Read Cycle
tAA
CS1#
A0~16
tOH
tCLZ1
tACS1
tOE
tOLZ
tCHZ1
OE#
WE#
DQ0~7
VIH
tOHZ
High impedance
WE# = “H” level
tRC
Valid Data
CS2
tCLZ2
tACS2
tCHZ2
R1LV0108E Series
R10DS0152EJ0100 Rev.1.00 Page 10 of
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Write Cycle (1) (WE# CLOCK)
CS1#
tCW
tOW
tWC
DQ0~7
tDW t
DH
Valid Data
tOHZ
OE#
WE#
tAW
tAS t
WP t
WR
tWHZ tOLZ
A0~16
CS2
tCW
R1LV0108E Series
R10DS0152EJ0100 Rev.1.00 Page 11 of
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Write Cycle (2) (CS1#, CS2 CLOCK)
CS1#
A0~16
tCW
tWC
tAW
tAS t
WR
OE#
WE#
DQ0~7
VIH
OE# = “H” level
tDW t
DH
tWP
Valid Data
CS2
tCW t
WR tAS
R1LV0108E Series
R10DS0152EJ0100 Rev.1.00 Page 12 of
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Low Vcc Data Retention Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions*2
VCC for data retention VDR 2.0 - 3.6 V
Vin ≥ 0V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ Vcc-0.2V,
CS2 ≥ Vcc-0.2V
Data retention current ICCDR
- 0.6*1 2 A ~+25°C
Vcc=3.0V, Vin ≥ 0V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ Vcc-0.2V,
CS2 ≥ Vcc-0.2V
- - 3 A ~+40°C
- - 8 A ~+70°C
- - 10 A ~+85°C
Chip deselect to data retention time tCDR 0 - - ns
See retention waveform.
Operation recovery time tR 5 - - ms
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer and Din buffer. If CS2 controls data
retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state.
If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input
levels (address, WE# ,OE#, DQ) can be in the high impedance state.
Low Vcc Data Retention Timing Waveforms
CS1#
Vcc
(1) CS1# Controlled
tCDR t
R
2.7V 2.7V
2.2V 2.2V
V
DR
CS1# ≥
V
cc - 0.2V
CS2
Vcc
(2) CS2 Controlled
tCDR t
R
2.7V 2.7V
0.2V 0.2V
V
DR
0V ≤CS2 ≤0.2V
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Revision History R1LV0108E Series Data Sheet
Rev. Date
Description
Page Summary
1.00 2013.6.21 - First Edition issued
Notice
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