NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 1
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Based on DDR3-1066/1333 256Mx8 SDRAM B-Die
Features
•Performance:
Speed Sort
PC3-8500
PC3-10600
Unit
-BE
-CG
DIMM CAS Latency
7
9
fck – Clock Frequency
533
667
MHz
tck – Clock Cycle
1.875
1.5
ns
fDQ – DQ Burst Frequency
1066
1333
Mbps
• 240-Pin Dual In-Line Memory Module (UDIMM)
• 256Mx72 and 512Mx72 DDR3 Unbuffered DIMM with ECC based
on 256Mx8 DDR3 SDRAM B-Die devices.
• Intended for 533MHz/667MHz applications
•VDD = VDDQ = 1.5V ± 0.075V (for DDR3)
•VDD = VDDQ = 1.35V -0.0675/+0.1V (for DDR3L)
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Nominal and Dynamic On-Die Termination support
• Programmable Operation:
- DIMM  Latency: 6,7,8,9, 11
- Burst Type: Sequential or Interleave
- Burst Length: BC4, BL8
- Operation: Burst Read and Write
• Two different termination values (Rtt_Nom & Rtt_WR)
• 15/10/1 (row/column/rank) Addressing for 2GB
• 15/10/2 (row/column/rank) Addressing for 4GB
• Extended operating temperature rage
• Auto Self-Refresh option
• Serial Presence Detect
• Gold contacts
• SDRAMs are in 78-ball BGA Package
• RoHS compliance and Halogen free
Description
NT2GC72B89B0NF / NT4GC72B8PB0NF / NT2GC72C89B0NF / NT4GC72C8PB0NF / NT2GC72C89B2NF and NT4GC72C8PB2NF are
240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Unbuffered Dual In-Line Memory Module with ECC (UDIMM w/ ECC), organized
as one rank of 256Mx72 (2GB) and two ranks of 512Mx72 (4GB) high-speed memory array. Modules use nine 256Mx8 (2GB) 78-ball BGA
packaged devices and eighteen 256Mx8 (4GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw cards
developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between
suppliers. All NANYA DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating of 533MHz/667MHz clock speeds and achieves high-speed data transfer rates of
1066Mbps/1333Mbps. Prior to any access operation, the device  latency and burst/length/operation type must be programmed into the
DIMM by address inputs A0-A14 and I/O inputs BA0~BA2 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 2
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Ordering Information
Part Number
Speed
Power
Leads
Note
NT2GC72B89B0NF-BE
DDR3-1066
PC3-8500
533MHz (1.875ns @ CL = 7)
1.5V
Gold
NT2GC72B89B0NF-CG
DDR3-1333
PC3-10600
667MHz (1.5ns @ CL = 9)
NT4GC72B8PB0NF-BE
DDR3-1066
PC3-8500
533MHz (1.875ns @ CL = 7)
NT4GC72B8PB0NF-CG
DDR3-1333
PC3-10600
667MHz (1.5ns @ CL = 9)
NT2GC72C89B0NF-BE
DDR3-1066
PC3-8500
533MHz (1.875ns @ CL = 7)
1.35V
Gold
NT2GC72C89B0NF-CG
DDR3-1333
PC3-10600
667MHz (1.5ns @ CL = 9)
NT2GC72C89B2NF-CG
DDR3-1333
PC3-10600
667MHz (1.5ns @ CL = 9)
NT4GC72C8PB0NF-BE
DDR3-1066
PC3-8500
533MHz (1.875ns @ CL = 7)
NT4GC72C8PB0NF-CG
DDR3-1333
PC3-10600
667MHz (1.5ns @ CL = 9)
NT4GC72C8PB2NF-CG
DDR3-1333
PC3-10600
667MHz (1.5ns @ CL = 9)
Pin Description
Pin Name
Description
Pin Name
Description
CK0, CK1
Clock Inputs, positive line
DQ0-DQ63
Data input/output
, 
Clock Inputs, negative line
DQS0-DQS8
Data strobes
CKE0, CKE1
Clock Enable
-
Data strobes complement

Row Address Strobe
DM0-DM8
Data Masks

Column Address Strobe
CB0-CB7
ECC Check Bits

Write Enable

Temperature event pin
, 
Chip Selects

Reset pin
A0-A9, A11, A14
Address Inputs
VREFDQ , VREFCA
Input/Output Reference
A10/AP
Address Input/Auto-Precharge
VDDSPD
SPD and Temp sensor power
A12/
Address Input/Burst Chop
SA0, SA1
Serial Presence Detect Address Inputs
BA0-BA2
SDRAM Bank Address Inputs
Vtt
Termination voltage
ODT0, ODT1
Active termination control lines
VSS
Ground
SCL
Serial Presence Detect Clock Input
VDD
Core and I/O power
SDA
Serial Presence Detect Data input/output
NC
No Connect
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 3
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
DDR3 SDRAM Pin Assignment
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
VREFDQ
121
VSS
31
DQ25
151
VSS
61
A2
181
A1
91
DQ41
211
VSS
2
VSS
122
DQ4
32
VSS
152
DM3
62
VDD
182
VDD
92
VSS
212
DM5
3
DQ0
123
DQ5
33

153
NC
63
CK1/NC
183
VDD
93

213
NC
4
DQ1
124
VSS
34
DQS3
154
VSS
64
/NC
184
CK0
94
DQS5
214
VSS
5
VSS
125
DM0
35
VSS
155
DQ30
65
VDD
185

95
VSS
215
DQ46
6

126
NC
36
DQ26
156
DQ31
66
VDD
186
VDD
96
DQ42
216
DQ47
7
DQS0
127
VSS
37
DQ27
157
VSS
67
VREFCA
187

97
DQ43
217
VSS
8
VSS
128
DQ6
38
VSS
158
CB4
68
NC
188
A0
98
VSS
218
DQ52
9
DQ2
129
DQ7
39
CB0
159
CB5
69
VDD
189
VDD
99
DQ48
219
DQ53
10
DQ3
130
VSS
40
CB1
160
VSS
70
A10/AP
190
BA1
100
DQ49
220
VSS
11
VSS
131
DQ12
41
VSS
161
DM8
71
BA0
191
VDD
101
VSS
221
DM6
12
DQ8
132
DQ13
42

162
NC
72
VDD
192

102

222
NC
13
DQ9
133
VSS
43
DQS8
163
VSS
73

193

103
DQS6
223
VSS
14
VSS
134
DM1
44
VSS
164
CB6
74

194
VDD
104
VSS
224
DQ54
15

135
NC
45
CB2
165
CB7
75
VDD
195
ODT0
105
DQ50
225
DQ55
16
DQS1
136
VSS
46
CB3
166
VSS
76

196
A13
106
DQ51
226
VSS
17
VSS
137
DQ14
47
VSS
167
NC
77
ODT1/NC
197
VDD
107
VSS
227
DQ60
18
DQ10
138
DQ15
48
NC
168

78
VDD
198
NC
108
DQ56
228
DQ61
19
DQ11
139
VSS
49
NC
169
CKE1/NC
79
NC
199
VSS
109
DQ57
229
VSS
20
VSS
140
DQ20
50
CKE0
170
VDD
80
VSS
200
DQ36
110
VSS
230
DM7
21
DQ16
141
DQ21
51
VDD
171
NC
81
DQ32
201
DQ37
111

231
NC
22
DQ17
142
VSS
52
BA2
172
NC
82
DQ33
202
VSS
112
DQS7
232
VSS
23
VSS
143
DM2
53
NC
173
VDD
83
VSS
203
DM4
113
VSS
233
DQ62
24

144
NC
54
VDD
174
A12/
84

204
NC
114
DQ58
234
DQ63
25
DQS2
145
VSS
55
A11
175
A9
85
DQS4
205
VSS
115
DQ59
235
VSS
26
VSS
146
DQ22
56
A7
176
VDD
86
VSS
206
DQ38
116
VSS
236
VDDSPD
27
DQ18
147
DQ23
57
VDD
177
A8
87
DQ34
207
DQ39
117
SA0
237
SA1
28
DQ19
148
VSS
58
A5
178
A6
88
DQ35
208
VSS
118
SCL
238
SDA
29
VSS
149
DQ28
59
A4
179
VDD
89
VSS
209
DQ44
119
SA2
239
VSS
30
DQ24
150
DQ29
60
VDD
180
A3
90
DQ40
210
DQ45
120
VTT
240
VTT
Note: CK1, , CKE1,  and ODT1 are for 2GB modules only.
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 4
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Input/Output Functional Description
Symbol
Type
Polarity
Function
CK0, CK1
, 
Input
Cross
point
The system clock inputs. All address and command lines are sampled on the cross point of the
rising edge of CK and falling edge of . A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock.
CKE0, CKE1
Input
Active
High
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
, 
Input
Active
Low
Enables the associated DDR3 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue, Rank 0 is selected by ; Rank 1 is selected by 
, , 
Input
Active
Low
When sampled at the positive rising edge of CK and falling edge of , signals , , 
define the operation to be executed by the SDRAM.
ODT0, ODT1
Input
Active
High
Asserts on-die termination for DQ, DM, DQS, and  signals if enabled via the DDR3 SDRAM
mode register.
DM0 – DM8
Input
Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high. In Read
mode, DM lines have no effect.
DQS0 – DQS8
 – 
I/O
Cross
point
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the
data strobe is sourced by the controller and is centered in the data window. In Read mode, the
data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window.
 signals are complements, and timing is relative to the cross point of respective DQS and
. If the module is to be operated in single ended strobe mode, all  signals must be tied on
the system board to VSS and DDR3 SDRAM mode registers programmed appropriately.
BA0, BA1, BA2
Input
-
Selects which DDR3 SDRAM internal bank of four or eight is activated.
A0 – A9
A10/AP
A11
A12/
A13
Input
-
During a Bank Activate command cycle, defines the row address when sampled at the cross point
of the rising edge of CK and falling edge of . During a Read or Write command cycle, defines
the column address when sampled at the cross point of the rising edge of CK and falling edge of
. In addition to the column address, AP is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the
bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then
BA0-BAn are used to define which bank to precharge.
DQ0 – DQ63
Input
-
Data Input/Output pins.
CB0 – CB7
I/O
Check bits are used for ECC
VDD, VDDSPD, VSS
Supply
-
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
VREFDQ, VREFCA
Supply
-
Reference voltage for SSTL15 inputs
SDA
I/O
-
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor.
A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull
up.
SCL
Input
-
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
SA0 – SA2
Input
-
Address pins used to select the Serial Presence Detect and Temp sensor base address.

Output
-
The  pin is reserved for use to flag critical module temperature.

Input
-
This signal resets the DDR3 SDRAM
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 5
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram
[2GB – 1 Rank, 256Mx8 DDR3 SDRAMs]
DQ0
DQ1
DQ2
DQ7
DQ4
DQ6
DQ5
DQ3
I/O 0
D0
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown.
3. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ
resistor is 240Ω ±1%.
ZQ
VDDSPD
VSS
VREFDQ
VREFCA
VDD/VDDQ
SPD
D0-D8
D0-D8
D0-D8
BA0-BA2 D0-D8
BA0-BA2: SDRAMs D0-D8
A0-A13


CKE0

ODT0
A0-A13: SDRAMs D0-D8
: SDRAMs D0-D8
: SDRAMs D0-D8
ODT: SDRAMs D0-D8
: SDRAMs D0-D8
CKE: SDRAMs D0-D8
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM  DQS 
DQ32
DQ33
DQ34
DQ39
DQ36
DQ38
DQ37
DQ35
I/O 0
D4
ZQ
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM  DQS 
DM0
DQS0

DM4
DQS4


DQ8
DQ9
DQ10
DQ15
DQ12
DQ14
DQ13
DQ11
I/O 0
D1
ZQ
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM  DQS 
DM1
DQS1

DQ40
DQ41
DQ42
DQ47
DQ44
DQ46
DQ45
DQ43
I/O 0
D5
ZQ
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM  DQS 
DM5
DQS5

DQ16
DQ17
DQ18
DQ23
DQ20
DQ22
DQ21
DQ19
I/O 0
D2
ZQ
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM  DQS 
DM2
DQS2

DQ48
DQ49
DQ50
DQ55
DQ52
DQ54
DQ53
DQ51
I/O 0
D6
ZQ
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM  DQS 
DM6
DQS6

DQ24
DQ25
DQ26
DQ31
DQ28
DQ30
DQ29
DQ27
I/O 0
D3
ZQ
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM  DQS 
DM3
DQS3

DQ56
DQ57
DQ58
DQ63
DQ60
DQ62
DQ61
DQ59
I/O 0
D7
ZQ
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM  DQS 
DM7
DQS7

CB0
CB1
CB2
CB7
CB4
CB6
CB5
CB3
I/O 0
D8
ZQ
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM  DQS 
DM8
DQS8

CK0 CK: SDRAMs D0-D8
 : SDRAMs D0-D8
 : SDRAMs D0-D8
Temp Sensor
SCL

SCL
SDA

SA0
SA1 A0
A1
A2
DDR3
SDRAM
VTT
CKE0, A[13:0],
, , ,
ODT0, BA[2:0], 
DDR3
SDRAM
VDD
CK

NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 6
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Functional Block Diagram
[4GB – 2 Ranks, 256Mx8 DDR3 SDRAMs]

DM1
DQS1
DQ8
DQ9
DQ10
DQ15
DQ12
DQ14
DQ13
DQ11
DQS2
DQ16
DQ17
DQ18
DQ23
DQ20
DQ22
DQ21
DQ19
DM2
DQS3
DQ24
DQ25
DQ26
DQ31
DQ28
DQ30
DQ29
DQ27
DM3
DM0
DQS0
DQ0
DQ1
DQ2
DQ7
DQ4
DQ6
DQ5
DQ3
DM5
DQS5
DQS5
DQ40
DQ41
DQ42
DQ47
DQ44
DQ46
DQ45
DQ43 D5
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
DM6
DQS6
DQS6
DQ48
DQ49
DQ50
DQ55
DQ52
DQ54
DQ53
DQ51 D6
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
DM7
DQS7
DQ56
DQ57
DQ58
DQ63
DQ60
DQ62
DQ61
DQ59 D7
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
DQS4
DQ32
DQ33
DQ34
DQ39
DQ36
DQ38
DQ37
DQ35 D4
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
DQS4
DM4
D1
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D2
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D3
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
CS
D0
DQSDQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D10
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D11
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D12
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D9
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D14
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D15
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D16
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM
D13
DQS
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM

DQS8
DQS8
CB0
CB1
CB2
CB6
CB3
CB5
CB4
CB2
DM8
D8 D17
DM
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DQS I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
DM DQS
DQS0
DQS1
DQS2
DQS3
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
CS DQS
DQS7
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown.
3. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ
resistor is 240Ω ±1%.
VDDSPD
VSS
VREFDQ
VREFCA
VDD/VDDQ
SPD
D0-D17
D0-D17
D0-D17
BA0-BA2 D0-D17
BA0-BA2: SDRAMs D0-D17
A0-A13


CKE0

ODT0
A0-A13: SDRAMs D0-D17
: SDRAMs D0-D8
: SDRAMs D0-D8
ODT: SDRAMs D0-D8
: SDRAMs D0-D8
CKE: SDRAMs D0-D8
CK0 CK: SDRAMs D0-D8
 : SDRAMs D0-D8
 : SDRAMs D0-D17
CKE1 CKE: SDRAMs D9-D17
ODT1 ODT: SDRAMs D9-D17
CK1 CK: SDRAMs D9-D17
 : SDRAMs D9-D17
Temp Sensor
SCL

SCL
SDA

SA0
SA1 A0
A1
A2
ZQ ZQ ZQ ZQ
ZQ ZQ ZQ ZQ
ZQ ZQ ZQ ZQ
ZQZQ
ZQ
ZQ
ZQ
ZQ
DDR3
SDRAM
VTT
CKE[1:0], A[13:0],
, , ,
ODT[1:0], BA[2:0],
[1:0]
DDR3
SDRAM
VDD
CK

NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 7
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Environmental Requirements
Symbol
Parameter
Rating
Units
Note
HOPR
Operating Humidity (relative)
10 to 90
%
1
TSTG
Storage Temperature (Plastic)
-55 to 100
°C
1
HSTG
Storage Humidity (without condensation)
5 to 95
%
1
PBAR
Barometric Pressure (operating & storage)
105 to 69
K Pascal
1, 2
Note:
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and device functional
operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. Up to 9850 ft.
Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
Note
VDD
Voltage on VDD pins relative to Vss
-0.4 V ~ 1.975 V
V
1, 3
VDDQ
Voltage on VDDQ pins relative to Vss
-0.4 V ~ 1.975 V
V
1, 3
VIN, VOUT
Voltage on I/O pins relative to Vss
-0.4 V ~ 1.975 V
V
1
TSTG
Storage Temperature
-55 to +100
°C
1, 2
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREF must be not greater
Operating temperature Conditions
Symbol
Parameter
Rating
Units
Note
TOPER
Normal Operating Temperature Range
0 to 85
°C
1, 2
Extended Temperature Range
85 to 95
°C
1, 3
Note:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions,
please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the
DRAM case temperature must be maintained between 0 to 85 °C under all operating conditions
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 °C and 95 °C case temperature. Full
specifications are supported in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 μs. It is also possible to specify
a component with 1X refresh (tREFI to 7.8μs) in the Extended Temperature Range. Please refer to supplier data sheet and/or the
DIMM SPD for option availability.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh
mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode
(MR2 A6 = 1b and MR2 A7 = 0b). Please refer to the supplier data sheet and/or the DIMM SPD for Auto Self-Refresh option
availability, Extended Temperature Range support and tREFI requirements in the Extended Temperature Range.
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 8
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
DC Electrical Characteristics and Operating Conditions
Symbol
Parameter
Min
Type
Max
Units
Notes
VDD
Supply Voltage
1.425
1.5
1.575
V
1,2
VDDQ
Output Supply Voltage
1.425
1.5
1.575
V
1,2
VDD
Supply Voltage
1.28
1.35
1.45
V
DDR3L
VDDQ
Output Supply Voltage
1.28
1.35
1.45
V
DDR3L
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
Single-Ended AC and DC Input Levels for Command and Address
Symbol
Parameter
DDR3-1066 (-BE)
DDR3-1333 (-CG)
Units
Note
Min.
Max.
Min.
Max.
VIH.CA(DC)
DC Input Logic High
Vref + 0.100
VDD
Vref + 0.100
VDD
V
1
VIL.CA(DC)
DC Input Logic Low
VSS
Vref - 0.100
VSS
Vref - 0.100
V
1
VIH.CA(AC)
AC Input Logic High
Vref + 0.175
Note 2
Vref + 0.175
Note 2
V
1, 2
VIL.CA(AC)
AC Input Logic Low
Note 2
Vref - 0.175
Note 2
Vref - 0.175
V
1, 2
VIH.CA(AC150)
AC Input Logic High
-
-
Vref + 0.15
Note 2
V
1, 2
VIL.CA(AC150)
AC Input Logic Low
-
-
Note 2
Vref - 0.15
V
1, 2
VRefCA(DC)
Reference Voltage for
ADD, CMD Inputs
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
Note:
1. For input only pins except RESET#. Vref = VrefCA(DC).
2. See “Overshoot and Undershoot Specifications” in the device datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
Single-Ended AC and DC Input Levels for DQ and DM
Symbol
Parameter
DDR3-1066 (-BE)
DDR3-1333 (-CG)
Units
Note
Min.
Max.
Min.
Max.
VIH.DQ(DC)
DC Input Logic High
Vref + 0.100
VDD
Vref + 0.100
VDD
V
1
VIL.DQ(DC)
DC Input Logic Low
VSS
Vref - 0.100
VSS
Vref - 0.100
V
1
VIH.DQ(AC)
AC Input Logic High
Vref + 0.175
Note 2
Vref + 0.15
Note 2
V
1, 2, 5
VIL.DQ(AC)
AC Input Logic Low
Note 2
Vref - 0.175
Note 2
Vref - 0.15
V
1, 2, 5
VRefDQ(DC)
Reference Voltage for
DQ, DM Inputs
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
Note:
1. For input only pins except RESET#. Vref = VrefDQ(DC).
2. See “Overshoot and Undershoot Specifications” in the device datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. Single-ended swing requirement for DQS, DQS# is 350 mV (peak to peak). Differential swing requirement for DQS - DQS# is 700 mV
(peak to peak).
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 9
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Operating, Standby, and Refresh Currents
TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.5V ± 0.075V [2GB – 1 Rank, 256Mx8 DDR3 SDRAMs]
Symbol
Parameter/Condition
PC3-8500
(-BE)
PC3-10600
(-CG)
Unit
IDD0
Operating One Bank Active-Precharge Current
649
697
mA
IDD1
Operating One Bank Active-Read-Precharge Current
816
879
mA
IDD2P0
Precharge Power-Down Current Slow Exit
37
40
mA
IDD2P1
Precharge Power-Down Current Fast Exit
117
135
mA
IDD2Q
Precharge Quiet Standby Current
187
214
mA
IDD2N
Precharge Standby Current
205
238
mA
IDD3P
Active Power-Down Current
128
145
mA
IDD3N
Active Standby Current
265
265
mA
IDD4R
Operating Burst Read Current
1137
1370
mA
IDD4W
Operating Burst Write Current
1156
1378
mA
IDD5B
Burst Refresh Current
1723
1733
mA
IDD6
Self Refresh Current: Normal Temperature Range
94
94
mA
IDD7
Operating Bank Interleave Read Current
2914
3552
mA
TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.35V -0.0675/+0.1V [2GB – 1 Rank, 256Mx8 DDR3 SDRAMs]
Symbol
Parameter/Condition
PC3-8500
(-BE)
PC3-10600
(-CG)
Unit
IDD0
Operating One Bank Active-Precharge Current
634
673
mA
IDD1
Operating One Bank Active-Read-Precharge Current
780
836
mA
IDD2P0
Precharge Power-Down Current Slow Exit
33
36
mA
IDD2P1
Precharge Power-Down Current Fast Exit
103
117
mA
IDD2Q
Precharge Quiet Standby Current
157
177
mA
IDD2N
Precharge Standby Current
172
193
mA
IDD3P
Active Power-Down Current
111
125
mA
IDD3N
Active Standby Current
228
228
mA
IDD4R
Operating Burst Read Current
1119
1346
mA
IDD4W
Operating Burst Write Current
1139
1356
mA
IDD5B
Burst Refresh Current
1663
1673
mA
IDD6
Self Refresh Current: Normal Temperature Range
74
74
mA
IDD7
Operating Bank Interleave Read Current
2822
3406
mA
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 10
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.5V ± 0.075V [4GB – 2 Ranks, 256Mx8 DDR3 SDRAMs]
Symbol
Parameter/Condition
PC3-8500
(-BE)
PC3-10600
(-CG)
Unit
IDD0
Operating One Bank Active-Precharge Current
915
962
mA
IDD1
Operating One Bank Active-Read-Precharge Current
1081
1144
mA
IDD2P0
Precharge Power-Down Current Slow Exit
74
79
mA
IDD2P1
Precharge Power-Down Current Fast Exit
235
269
mA
IDD2Q
Precharge Quiet Standby Current
375
428
mA
IDD2N
Precharge Standby Current
409
475
mA
IDD3P
Active Power-Down Current
256
290
mA
IDD3N
Active Standby Current
531
531
mA
IDD4R
Operating Burst Read Current
1402
1635
mA
IDD4W
Operating Burst Write Current
1422
1643
mA
IDD5B
Burst Refresh Current
1988
1998
mA
IDD6
Self Refresh Current: Normal Temperature Range
187
187
mA
IDD7
Operating Bank Interleave Read Current
3179
3817
mA
TCASE = 0 °C ~ 85 °C; VDDQ = VDD =1.35V -0.0675/+0.1V [4GB – 2 Ranks, 256Mx8 DDR3 SDRAMs]
Symbol
Parameter/Condition
PC3-8500
(-BE)
Unit
IDD0
Operating One Bank Active-Precharge Current
863
mA
IDD1
Operating One Bank Active-Read-Precharge Current
1010
mA
IDD2P0
Precharge Power-Down Current Slow Exit
66
mA
IDD2P1
Precharge Power-Down Current Fast Exit
206
mA
IDD2Q
Precharge Quiet Standby Current
314
mA
IDD2N
Precharge Standby Current
343
mA
IDD3P
Active Power-Down Current
222
mA
IDD3N
Active Standby Current
457
mA
IDD4R
Operating Burst Read Current
1348
mA
IDD4W
Operating Burst Write Current
1368
mA
IDD5B
Burst Refresh Current
1893
mA
IDD6
Self Refresh Current: Normal Temperature Range
148
mA
IDD7
Operating Bank Interleave Read Current
3051
mA
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 11
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Standard Speed Bins
DDR3-1066MHz
Speed Bin
DDR3-1066
Unit
CL-nRCD-nRP
7-7-7 (-BE)
Parameter
Symbol
Min
Max
Internal read command to first data
tAA
13.125
20.000
ns
ACT to internal read or write delay time
tRCD
13.125
-
ns
PRE command period
tRP
13.125
-
ns
ACT to ACT or REF command period
tRC
50.625
-
ns
ACT to PRE command period
tRAS
37.500
9*tREFI
ns
CL=5
CWL=5
tCK(AVG)
3.000
3.300
ns
CWL=6
tCK(AVG)
Reserved
ns
CL=6
CWL=5
tCK(AVG)
2.500
3.300
ns
CWL=6
tCK(AVG)
Reserved
ns
CL=7
CWL=5
tCK(AVG)
Reserved
ns
CWL=6
tCK(AVG)
1.875
<2.5
ns
CL=8
CWL=5
tCK(AVG)
Reserved
ns
CWL=6
tCK(AVG)
1.875
<2.5
ns
Supported CL Settings
6,7,8
nCK
Supported CWL Settings
5,6
nCK
DDR3-1333MHz
Speed Bin
DDR3-1333
Unit
CL-nRCD-nRP
9-9-9 (-CG)
Parameter
Symbol
Min
Max
Internal read command to first data
tAA
13.125
20.000
ns
ACT to internal read or write delay time
tRCD
13.125
-
ns
PRE command period
tRP
13.125
-
ns
ACT to ACT or REF command period
tRC
49.125
-
ns
ACT to PRE command period
tRAS
36.000
9*tREFI
ns
CL=5
CWL=5
tCK(AVG)
Reserved
Reserved
ns
CWL=6
tCK(AVG)
Reserved
Reserved
ns
CWL=7
tCK(AVG)
Reserved
Reserved
ns
CL=6
CWL=5
tCK(AVG)
2.500
3.300
ns
CWL=6
tCK(AVG)
Reserved
Reserved
ns
CWL=7
tCK(AVG)
Reserved
Reserved
ns
CL=7
CWL=5
tCK(AVG)
Reserved
Reserved
ns
CWL=6
tCK(AVG)
1.875*
<2.5*
ns
CWL=7
tCK(AVG)
Reserved
Reserved
ns
CL=8
CWL=5
tCK(AVG)
Reserved
Reserved
ns
CWL=6
tCK(AVG)
1.875
<2.5
ns
CWL=7
tCK(AVG)
Reserved
Reserved
ns
CL=9
CWL=5
tCK(AVG)
Reserved
Reserved
ns
CWL=6
tCK(AVG)
Reserved
Reserved
ns
CWL=7
tCK(AVG)
1.500
<1.875
ns
CL=10
CWL=5
tCK(AVG)
Reserved
Reserved
ns
CWL=6
tCK(AVG)
Reserved
Reserved
ns
CWL=7
tCK(AVG)
1.500*
<1.875*
ns
Supported CL Settings
6,7,8,9
nCK
Supported CWL Settings
5,6,7
nCK
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 12
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
AC Timing Specifications for DDR3 SDRAM Devices Used on Module (1066MHz)
Parameter
Symbol
DDR3-1066
Units
Notes
Min.
Max.
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
tCK (DLL_OFF)
8
-
ns
Average Clock Period
tCK(avg)
Refer to "Standard Speed Bins)
ps
Average high pulse width
tCH(avg)
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
tCK(avg)
Absolute Clock Period
tCK(abs)
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT(per)max
ps
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
tCK(avg)
Absolute clock LOW pulse width
tCL(abs)
0.43
-
tCK(avg)
Clock Period Jitter
JIT(per)
-90
90
ps
Clock Period Jitter during DLL locking period
JIT(per, lck)
-80
80
ps
Cycle to Cycle Period Jitter
tJIT(cc)
180
180
ps
Cycle to Cycle Period Jitter during DLL locking period
JIT(cc, lck)
160
160
ps
Duty Cycle Jitter
tJIT(duty)
-
-
ps
Cumulative error across 2 cycles
tERR(2per)
-132
132
ps
Cumulative error across 3 cycles
tERR(3per)
-157
157
ps
Cumulative error across 4 cycles
tERR(4per)
-175
175
ps
Cumulative error across 5 cycles
tERR(5per)
-188
188
ps
Cumulative error across 6 cycles
tERR(6per)
-200
200
ps
Cumulative error across 7 cycles
tERR(7per)
-209
209
ps
Cumulative error across 8 cycles
tERR(8per)
-217
217
ps
Cumulative error across 9 cycles
tERR(9per)
-224
224
ps
Cumulative error across 10 cycles
tERR(10per)
-231
231
ps
Cumulative error across 11 cycles
tERR(11per)
-237
237
ps
Cumulative error across 12 cycles
tERR(12per)
-242
242
ps
Cumulative error across n = 13, 14 . . . 49, 50 cycles
tERR(nper)
tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min
tERR(nper)max = (1 + 0.68ln(n)) * tJIT(per)max
ps
Data Timing
DQS, DQS# to DQ skew, per group, per access
tDQSQ
-
150
ps
DQ output hold time from DQS, DQS#
tQH
0.38
-
tCK(avg)
DQ low-impedance time from CK, CK#
tLZ(DQ)
-600
300
ps
DQ high impedance time from CK, CK#
tHZ(DQ)
-
300
ps
Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels
tDS(base)
AC175
25
ps
Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels
tDS(base)
AC150
75
ps
Data hold time from DQS, DQS# referenced to Vih(dc) / Vil(dc) levels
tDH(base)
DC100
100
ps
DQ and DM Input pulse width for each input
tDIPW
490
ps
Data Strobe Timing
DQS,DQS# differential READ Preamble
tRPRE
0.9
Note 19
tCK(avg)
DQS, DQS# differential READ Postamble
tRPST
0.3
Note 11
tCK(avg)
DQS, DQS# differential output high time
tQSH
0.38
-
tCK(avg)
DQS, DQS# differential output low time
tQSL
0.38
-
tCK(avg)
DQS, DQS# differential WRITE Preamble
tWPRE
0.9
-
tCK(avg)
DQS, DQS# differential WRITE Postamble
tWPST
0.3
-
tCK(avg)
DQS, DQS# rising edge output access time from rising CK, CK#
tDQSCK
-300
300
tCK(avg)
DQS and DQS# low-impedance time
(Referenced from RL - 1)
tLZ(DQS)
-600
300
tCK(avg)
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
tHZ(DQS)
-
300
tCK(avg)
DQS, DQS# differential input low pulse width
tDQSL
0.45
0.55
tCK(avg)
DQS, DQS# differential input high pulse width
tDQSH
0.45
0.55
tCK(avg)
DQS, DQS# rising edge to CK, CK# rising edge
tDQSS
-0.25
0.25
tCK(avg)
DQS, DQS# falling edge setup time to CK, CK# rising edge
tDSS
0.2
-
tCK(avg)
DQS, DQS# falling edge hold time from CK, CK# rising edge
tDSH
0.2
-
tCK(avg)
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 13
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Command and Address Timing
DLL locking time
tDLLK
512
-
nCK
Internal READ Command to PRECHARGE Command delay
tRTP
tRTPmin.: max(4nCK, 7.5ns)
tRTPmax.: -
Delay from start of internal write
transaction to internal read command
tWTR
tWTRmin.: max(4nCK, 7.5ns)
tWTRmax.:
WRITE recovery time
tWR
15
-
ns
Mode Register Set command cycle time
tMRD
4
-
nCK
Mode Register Set command update delay
tMOD
tMODmin.: max(12nCK, 15ns)
tMODmax.:
ACT to internal read or write delay time
tRCD
PRE command period
tRP
ACT to ACT or REF command period
tRC
CAS# to CAS# command delay
tCCD
4
-
nCK
Auto precharge write recovery + precharge time
tDAL(min)
WR + roundup(tRP / tCK(avg))
nCK
Multi-Purpose Register Recovery Time
tMPRR
1
-
nCK
ACTIVE to PRECHARGE command period
tRAS
Standard Speed Bins
ACTIVE to ACTIVE command period for 1KB page size
tRRD
max(4nCK, 7.5ns)
-
ACTIVE to ACTIVE command period for 2KB page size
tRRD
tRRDmin.: max(4nCK, 10ns)
tRRDmax.:
Four activate window for 1KB page size
tFAW
37.5
-
ns
Four activate window for 2KB page size
tFAW
50
-
ns
Command and Address setup time to CK, CK#
referenced to Vih(ac) / Vil(ac) levels
tIS(base)
125
-
ps
Command and Address hold time from CK, CK#
referenced to Vih(dc) / Vil(dc) levels
tIH(base)
200
-
ps
Command and Address setup time to CK, CK#
referenced to Vih(ac) / Vil(ac) levels
tIS(base) AC150
125+150
-
ps
Control and Address Input pulse width for each input
tIPW
780
-
ps
Calibration Timing
Power-up and RESET calibration time
tZQinit
512
-
nCK
Normal operation Full calibration time
tZQoper
256
-
nCK
Normal operation Short calibration time
tZQCS
64
-
nCK
Reset Timing
Exit Reset from CKE HIGH to a valid command
tXPR
tXPRmin.: max(5nCK, tRFC(min) + 10ns)
tXPRmax.: -
Self Refresh Timings
Exit Self Refresh to commands not requiring a locked DLL
tXS
tXSmin.: max(5nCK, tRFC(min) + 10ns)
tXSmax.: -
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
tXSDLLmin.: tDLLK(min)
tXSDLLmax.: -
nCK
Minimum CKE low width for Self Refresh entry to exit timing
tCKESR
tCKESRmin.: tCKE(min) + 1 nCK
tCKESRmax.: -
Valid Clock Requirement after Self Refresh Entry (SRE)
or Power-Down Entry (PDE)
tCKSRE
tCKSREmin.: max(5 nCK, 10 ns)
tCKSREmax.: -
Valid Clock Requirement before Self Refresh Exit (SRX)
or Power-Down Exit (PDX) or Reset Exit
tCKSRX
tCKSRXmin.: max(5 nCK, 10 ns)
tCKSRXmax.: -
Power Down Timings
Exit Power Down with DLL on to any valid command;
Exit Precharge Power Down with DLL frozen to commands
not requiring a locked DLL
tXP
tXPmin.: max(3nCK, 7.5ns)
tXPmax.: -
Exit Precharge Power Down with DLL frozen to commands
requiring a locked DLL
tXPDLL
tXPDLLmin.: max(10nCK, 24ns)
tXPDLLmax.: -
CKE minimum pulse width
tCKE
tCKEmin.: max(3nCK 5.625ns)
tCKEmax.: -
Command pass disable delay
tCPDED
tCPDEDmin.: 1
tCPDEDmin.: -
nCK
Power Down Entry to Exit Timing
tPD
tPDmin.: tCKE(min)
tPDmax.: 9*tREFI
Timing of ACT command to Power Down entry
tACTPDEN
tACTPDENmin.: 1
nCK
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 14
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
tACTPDENmax.: -
Timing of PRE or PREA command to Power Down entry
tPRPDEN
tPRPDENmin.: 1
tPRPDENmax.: -
nCK
Timing of RD/RDA command to Power Down entry
tRDPDEN
tRDPDENmin.: RL+4+1
tRDPDENmax.: -
nCK
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRPDENmin.: WL + 4 + (tWR / tCK(avg))
tWRPDENmax.: -
nCK
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRAPDEN
tWRAPDENmin.: WL+4+WR+1
tWRAPDENmax.: -
nCK
Timing of WR command to Power Down entry (BC4MRS)
tWRPDEN
tWRPDENmin.: WL + 2 + (tWR / tCK(avg))tWRPDENmax.: -
nCK
Timing of WRA command to Power Down entry
(BC4MRS)
tWRAPDEN
tWRAPDENmin.: WL + 2 +WR + 1
tWRAPDENmax.: -
nCK
Timing of REF command to Power Down entry
tREFPDEN
tREFPDENmin.: 1
tREFPDENmax.: -
nCK
Timing of MRS command to Power Down entry
tMRSPDEN
tMRSPDENmin.: tMOD(min)
tMRSPDENmax.: -
ODT Timings
ODT high time without write command or
with write command and BC4
ODTH4
ODTH4min.: 4
ODTH4max.: -
nCK
ODT high time with Write command and BL8
ODTH8
ODTH8min.: 6
ODTH8max.: -
nCK
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
tAONPD
2
8.5
ns
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
tAOFPD
2
8.5
ns
RTT turn-on
tAON
-300
300
ps
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
tAOF
0.3
0.7
tCK(avg)
RTT dynamic change skew
tADC
0.3
0.7
tCK(avg)
Write Leveling Timings
First DQS/DQS# rising edge after
write leveling mode is programmed
tWLMRD
40
-
nCK
DQS/DQS# delay after write leveling mode is programmed
tWLDQSEN
25
-
nCK
Write leveling setup time from rising CK, CK#
crossing to rising DQS, DQS# crossing
tWLS
245
-
ps
Write leveling hold time from rising DQS, DQS#
crossing to rising CK, CK# crossing
tWLH
245
-
ps
Write leveling output delay
tWLO
0
9
ns
Write leveling output error
tWLOE
0
2
ns
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 15
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
AC Timing Specifications for DDR3 SDRAM Devices Used on Module (1333MHz)
Parameter
Symbol
DDR3-1333
Units
Notes
Min.
Max.
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
tCK (DLL_OFF)
8
-
ns
Average Clock Period
tCK(avg)
Refer to "Standard Speed Bins)
ps
Average high pulse width
tCH(avg)
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
tCK(avg)
Absolute Clock Period
tCK(abs)
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT(per)max
ps
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
tCK(avg)
Absolute clock LOW pulse width
tCL(abs)
0.43
-
tCK(avg)
Clock Period Jitter
JIT(per)
-80
80
ps
Clock Period Jitter during DLL locking period
JIT(per, lck)
-70
70
ps
Cycle to Cycle Period Jitter
tJIT(cc)
160
160
ps
Cycle to Cycle Period Jitter during DLL locking period
JIT(cc, lck)
140
140
ps
Duty Cycle Jitter
tJIT(duty)
-
-
ps
Cumulative error across 2 cycles
tERR(2per)
-118
118
ps
Cumulative error across 3 cycles
tERR(3per)
-140
140
ps
Cumulative error across 4 cycles
tERR(4per)
-155
155
ps
Cumulative error across 5 cycles
tERR(5per)
-168
168
ps
Cumulative error across 6 cycles
tERR(6per)
-177
177
ps
Cumulative error across 7 cycles
tERR(7per)
-186
186
ps
Cumulative error across 8 cycles
tERR(8per)
-193
193
ps
Cumulative error across 9 cycles
tERR(9per)
-200
200
ps
Cumulative error across 10 cycles
tERR(10per)
-205
205
ps
Cumulative error across 11 cycles
tERR(11per)
-210
210
ps
Cumulative error across 12 cycles
tERR(12per)
-215
215
ps
Cumulative error across n = 13, 14 . . . 49, 50 cycles
tERR(nper)
tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min
tERR(nper)max = (1 + 0.68ln(n)) * tJIT(per)max
ps
Data Timing
DQS, DQS# to DQ skew, per group, per access
tDQSQ
-
125
ps
DQ output hold time from DQS, DQS#
tQH
0.38
-
tCK(avg)
DQ low-impedance time from CK, CK#
tLZ(DQ)
-500
250
ps
DQ high impedance time from CK, CK#
tHZ(DQ)
-
250
ps
Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels
tDS(base)
AC175
-
ps
Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels
tDS(base)
AC150
30
ps
Data hold time from DQS, DQS# referenced to Vih(dc) / Vil(dc) levels
tDH(base)
DC100
65
ps
DQ and DM Input pulse width for each input
tDIPW
400
-
ps
Data Strobe Timing
DQS,DQS# differential READ Preamble
tRPRE
0.9
Note 19
tCK(avg)
DQS, DQS# differential READ Postamble
tRPST
0.3
Note 11
tCK(avg)
DQS, DQS# differential output high time
tQSH
0.4
-
tCK(avg)
DQS, DQS# differential output low time
tQSL
0.4
-
tCK(avg)
DQS, DQS# differential WRITE Preamble
tWPRE
0.9
-
tCK(avg)
DQS, DQS# differential WRITE Postamble
tWPST
0.3
-
tCK(avg)
DQS, DQS# rising edge output access time from rising CK, CK#
tDQSCK
-255
255
tCK(avg)
DQS and DQS# low-impedance time
(Referenced from RL - 1)
tLZ(DQS)
-500
250
tCK(avg)
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
tHZ(DQS)
-
250
tCK(avg)
DQS, DQS# differential input low pulse width
tDQSL
0.45
0.55
tCK(avg)
DQS, DQS# differential input high pulse width
tDQSH
0.45
0.55
tCK(avg)
DQS, DQS# rising edge to CK, CK# rising edge
tDQSS
-0.25
0.25
tCK(avg)
DQS, DQS# falling edge setup time to CK, CK# rising edge
tDSS
0.2
-
tCK(avg)
DQS, DQS# falling edge hold time from CK, CK# rising edge
tDSH
0.2
-
tCK(avg)
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 16
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Command and Address Timing
DLL locking time
tDLLK
512
-
nCK
Internal READ Command to PRECHARGE Command delay
tRTP
tRTPmin.: max(4nCK, 7.5ns)
tRTPmax.: -
Delay from start of internal write
transaction to internal read command
tWTR
tWTRmin.: max(4nCK, 7.5ns)
tWTRmax.:
WRITE recovery time
tWR
15
-
ns
Mode Register Set command cycle time
tMRD
4
-
nCK
Mode Register Set command update delay
tMOD
tMODmin.: max(12nCK, 15ns)
tMODmax.:
ACT to internal read or write delay time
tRCD
PRE command period
tRP
ACT to ACT or REF command period
tRC
CAS# to CAS# command delay
tCCD
4
nCK
Auto precharge write recovery + precharge time
tDAL(min)
WR + roundup(tRP / tCK(avg))
nCK
Multi-Purpose Register Recovery Time
tMPRR
1
-
nCK
ACTIVE to PRECHARGE command period
tRAS
Standard Speed Bins
ACTIVE to ACTIVE command period for 1KB page size
tRRD
tRRDmin.: max(4nCK, 6ns)
tRRDmax.:
ACTIVE to ACTIVE command period for 2KB page size
tRRD
tRRDmin.: max(4nCK, 7.5ns)
tRRDmax.:
Four activate window for 1KB page size
tFAW
30
0
ns
Four activate window for 2KB page size
tFAW
45
0
ns
Command and Address setup time to CK, CK#
referenced to Vih(ac) / Vil(ac) levels
tIS(base)
65
-
ps
Command and Address hold time from CK, CK#
referenced to Vih(dc) / Vil(dc) levels
tIH(base)
140
-
ps
Command and Address setup time to CK, CK#
referenced to Vih(ac) / Vil(ac) levels
tIS(base) AC150
65+125
-
ps
Control and Address Input pulse width for each input
tIPW
620
-
ps
Calibration Timing
Power-up and RESET calibration time
tZQinit
512
-
nCK
Normal operation Full calibration time
tZQoper
256
-
nCK
Normal operation Short calibration time
tZQCS
64
-
nCK
Reset Timing
Exit Reset from CKE HIGH to a valid command
tXPR
tXPRmin.: max(5nCK, tRFC(min) + 10ns)
tXPRmax.: -
Self Refresh Timings
Exit Self Refresh to commands not requiring a locked DLL
tXS
tXSmin.: max(5nCK, tRFC(min) + 10ns)
tXSmax.: -
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
tXSDLLmin.: tDLLK(min)
tXSDLLmax.: -
nCK
Minimum CKE low width for Self Refresh entry to exit timing
tCKESR
tCKESRmin.: tCKE(min) + 1 nCK
tCKESRmax.: -
Valid Clock Requirement after Self Refresh Entry (SRE)
or Power-Down Entry (PDE)
tCKSRE
tCKSREmin.: max(5 nCK, 10 ns)
tCKSREmax.: -
Valid Clock Requirement before Self Refresh Exit (SRX)
or Power-Down Exit (PDX) or Reset Exit
tCKSRX
tCKSRXmin.: max(5 nCK, 10 ns)
tCKSRXmax.: -
Power Down Timings
Exit Power Down with DLL on to any valid command;
Exit Precharge Power Down with DLL frozen to commands
not requiring a locked DLL
tXP
tXPmin.: max(3nCK, 6ns)
tXPmax.: -
Exit Precharge Power Down with DLL frozen to commands
requiring a locked DLL
tXPDLL
tXPDLLmin.: max(10nCK, 24ns)
tXPDLLmax.: -
CKE minimum pulse width
tCKE
tCKEmin.: max(3nCK ,5.625ns)
tCKEmax.: -
Command pass disable delay
tCPDED
tCPDEDmin.: 1
tCPDEDmin.: -
nCK
Power Down Entry to Exit Timing
tPD
tPDmin.: tCKE(min)
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 17
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
tPDmax.: 9*tREFI
Timing of ACT command to Power Down entry
tACTPDEN
tACTPDENmin.: 1
tACTPDENmax.: -
nCK
Timing of PRE or PREA command to Power Down entry
tPRPDEN
tPRPDENmin.: 1
tPRPDENmax.: -
nCK
Timing of RD/RDA command to Power Down entry
tRDPDEN
tRDPDENmin.: RL+4+1
tRDPDENmax.: -
nCK
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRPDENmin.: WL + 4 + (tWR / tCK(avg))
tWRPDENmax.: -
nCK
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRAPDEN
tWRAPDENmin.: WL+4+WR+1
tWRAPDENmax.: -
nCK
Timing of WR command to Power Down entry (BC4MRS)
tWRPDEN
tWRPDENmin.: WL + 2 + (tWR / tCK(avg))tWRPDENmax.: -
nCK
Timing of WRA command to Power Down entry
(BC4MRS)
tWRAPDEN
tWRAPDENmin.: WL + 2 +WR + 1
tWRAPDENmax.: -
nCK
Timing of REF command to Power Down entry
tREFPDEN
tREFPDENmin.: 1
tREFPDENmax.: -
nCK
Timing of MRS command to Power Down entry
tMRSPDEN
tMRSPDENmin.: tMOD(min)
tMRSPDENmax.: -
ODT Timings
ODT high time without write command or
with write command and BC4
ODTH4
ODTH4min.: 4
ODTH4max.: -
nCK
ODT high time with Write command and BL8
ODTH8
ODTH8min.: 6
ODTH8max.: -
nCK
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
tAONPD
2
8.5
ns
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
tAOFPD
2
8.5
ns
RTT turn-on
tAON
-250
250
ps
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
tAOF
0.3
0.7
tCK(avg)
RTT dynamic change skew
tADC
0.3
0.7
tCK(avg)
Write Leveling Timings
First DQS/DQS# rising edge after
write leveling mode is programmed
tWLMRD
40
-
nCK
DQS/DQS# delay after write leveling mode is programmed
tWLDQSEN
25
-
nCK
Write leveling setup time from rising CK, CK#
crossing to rising DQS, DQS# crossing
tWLS
195
-
ps
Write leveling hold time from rising DQS, DQS#
crossing to rising CK, CK# crossing
tWLH
195
-
ps
Write leveling output delay
tWLO
0
9
ns
Write leveling output error
tWLOE
0
2
ns
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 18
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Package Dimensions
[2GB – 1 Rank, 256Mx8 DDR3 SDRAMs]
FRONT
1.50 +/- 0.10
Detail A Detail B
0.80 +/- 0.05
BACK
3.80
4.00
1.00 Pitch
Detail A
9.50
133.35 +/- 0.15
Units: Millimeters
30.00 +0.5/-0.15
SIDE
2.7 Max.
1.27 +0.07/-0.10
17.30
5.175 47.00
Detail B
71.00
5.00
2.50
3.0 (x4)
Note: Device position and scale are only for reference.
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 19
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Package Dimensions
[4GB – 2 Ranks, 256Mx8 DDR3 SDRAMs]
FRONT
1.50 +/- 0.10
Detail A Detail B
0.80 +/- 0.05
BACK
3.80
4.00
1.00 Pitch
Detail A
9.50
133.35 +/- 0.15
Units: Millimeters
30.00 +0.5/-0.15
SIDE
4.00 Max.
1.27 +0.07/-0.10
17.30
5.175 47.00
Detail B
71.00
5.00
2.50
3.0 (x4)
Note: Device position and scale are only for reference.
NT2GC72B89B0NF / NT4GC72B8PB0NF
NT2GC72C89B0NF / NT4GC72C8PB0NF
NT2GC72C89B2NF / NT4GC72C8PB2NF
2GB: 256M x 72 / 4GB: 512M x 72
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM with ECC
REV 1.1 20
10/2010
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Revision Log
Rev
Date
Modification
0.1
02/2010
Preliminary Release
0.5
05/2010
Preliminary 2nd Release
1.0
05/2010
Official Release
Nanya Technology Corporation
Hwa Ya Technology Park 669
Fu Hsing 3rd Rd., Kueishan,
Taoyuan, 333, Taiwan, R.O.C.
Tel: +886-3-328-1688
Please visit our home page for more information: www.nanya.com
Printed in Taiwan
© 2010