Quad, 12-/14-/16-Bit nanoDACs with
5 ppm/°C On-Chip Reference
Data Sheet AD5624R/AD5644R/AD5664R
Rev. C Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Low power, smallest pin-compatible, quad nanoDACs
AD5664R: 16 bits
AD5644R: 14 bits
AD5624R: 12 bits
User-selectable external or internal reference
External reference default
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
10-lead MSOP; 10-lead, 3 mm × 3 mm LFCSP_WD; and
12-ball, 1.665 mm × 2.245 mm WLCSP
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale
Per channel power-down
Serial interface, up to 50 MHz
APPLICATIONS
Process controls
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
Table 1. Related Devices
Part No. Description
AD5624/AD5664 2.7 V to 5.5 V quad, 12-/16-bit DACs, external
reference
AD5666 2.7 V to 5.5 V quad, 16-bit DAC, internal
reference, LDAC, CLR pins
GENERAL DESCRIPTION
The AD5624R/AD5644R/AD5664R, members of the nanoDAC®
family, are low power, quad, 12-/14-/16-bit buffered voltage-out
DACs. All devices operate from a single 2.7 V to 5.5 V supply
and are guaranteed monotonic by design.
The AD5624R/AD5644R/AD5664R have an on-chip reference.
The AD56x4R-3 has a 1.25 V, 5 ppm/°C reference, giving a full-
scale output range of 2.5 V; the AD56x4R-5 has a 2.5 V, 5 ppm/°C
reference giving a full-scale output range of 5 V. The on-chip
reference is off at power-up, allowing the use of an external
reference; all devices can be operated from a single 2.7 V to
5.5 V supply. The internal reference is enabled via a software
write.
The part incorporates a power-on reset circuit that ensures the
DAC output powers up to 0 V and remains there until a valid
write takes place. The part contains a per-channel power-down
feature that reduces the current consumption of the device to
480 nA at 5 V and provides software-selectable output loads
while in power-down mode. The low power consumption of
this part in normal operation makes it ideally suited to portable
battery-operated equipment.
The AD5624R/AD5644R/AD5664R use a versatile 3-wire serial
interface that operates at clock rates up to 50 MHz, and is com-
patible with standard SPI, QSPI™, MICROWIRE™, and DSP
interface standards. The on-chip precision output amplifier
enables rail-to-rail output swing.
PRODUCT HIGHLIGHTS
1. Quad 12-/14-/16-bit DACs.
2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
3. Available in 10-lead MSOP; 10-lead, 3 mm × 3 mm
LFCSP_WD; and 12-ball, 1.665 mm × 2.245 mm WLCSP.
4. Low power, typically consumes 1.32 mW at 3 V and
2.25 mW at 5 V.
0
5856-001
BUFFER
BUFFER
AD5624R/AD5644R/AD5664R 1.25V/2.5V REF
V
DD
V
REFIN
/
V
REFOUT
GND
POWER-
DOWN
LOGIC
POWER-ON
LOGIC
SCLK
S
YNC
DIN
STRING
DAC A
STRING
DAC B
STRING
DAC C
STRING
DAC D
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INTERFACE
LOGIC
BUFFER
BUFFER
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
AD5624R/AD5644R/AD5664R Data Sheet
Rev. C | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AD5624R-5/AD5644R-5/AD5664R-5 ...................................... 3
AD5624R-3/AD5644R-3/AD5664R-3 ...................................... 4
AC Characteristics ........................................................................ 6
Timing Characteristics ................................................................ 7
Timing Diagram ........................................................................... 7
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 20
Digital-to-Analog Section ......................................................... 20
Resistor String ............................................................................. 20
Output Amplifier ........................................................................ 20
Internal Reference ...................................................................... 20
External Reference ..................................................................... 20
Serial Interface ............................................................................ 20
Input Shift Register .................................................................... 21
SYNC Interrupt ........................................................................... 21
Power-On Reset .......................................................................... 22
Software Reset ............................................................................. 22
Power-Down Modes .................................................................. 22
LDAC Function ........................................................................... 23
Internal Reference Setup ........................................................... 23
Microprocessor Interfacing ....................................................... 24
Applications Information .............................................................. 25
Using a Reference as a Power Supply for the
AD5624R/AD5644R/AD5664R ............................................... 25
Bipolar Operation Using the AD5624R/AD5644R/AD5664R
....................................................................................................... 25
Using AD5624R/AD5644R/AD5664R with a Galvanically
Isolated Interface ........................................................................ 25
Power Supply Bypassing and Grounding ................................ 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 28
REVISION HISTORY
4/13—Rev. B to Rev. C
Added 12-Ball WLCSP ...................................................... Universal
Changes to Features and Product Highlights Sections ................ 1
Change to Reference TC Parameter, Table 2 ................................. 3
Added Thermal Impedance, WLCSP Package (4-Layer Board),
θJA Parameter, Table 6 ....................................................................... 8
Added Figure 4; Renumbered Sequentially .................................. 9
Changes to Figure 3 Caption and Table 7...................................... 9
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
4/08—Rev. A to Rev. B
Changes to Figure 50...................................................................... 20
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
11/06—Rev. 0 to Rev. A
Changes to Reference Output Parameter in Table 2 ..................... 3
Changes to Reference Output Parameter in Table 3 ..................... 5
Added Note to Figure 3 .................................................................... 9
4/06—Revision 0: Initial Version
Data Sheet AD5624R/AD5644R/AD5664R
Rev. C | Page 3 of 28
SPECIFICATIONS
AD5624R-5/AD5644R-5/AD5664R-5
VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
B Grade1
Parameter
Min
Typ
Max
Conditions/Comments
STATIC PERFORMANCE
2
AD5664R
Resolution 16 Bits
Relative Accuracy ±8 ±16 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
AD5644R
Resolution 14 Bits
Relative Accuracy ±2 ±4 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design
AD5624R
Resolution 12 Bits
Relative Accuracy ±0.5 ±1 LSB
Differential Nonlinearity
±0.25
Guaranteed monotonic by design
Zero-Code Error 2 10 mV All zeroes loaded to DAC register
Offset Error ±1 ±10 mV
Full-Scale Error −0.1 ±1 % of FSR All ones loaded to DAC register
Gain Error ±1.5 % of FSR
Zero-Code Error Drift ±2 µV/°C
Gain Temperature Coefficient ±2.5 ppm Of FSR/°C
DC Power Supply Rejection Ratio −100 dB DAC code = midscale; VDD = 5 V ± 10%
DC Crosstalk
External Reference 10 µV
Due to full-scale output change, RL = 2 kΩ to GND or VDD
10 µV/mA Due to load current change
5 µV Due to powering down (per channel)
Internal Reference 25 µV
Due to full-scale output change, RL = 2 kΩ to GND or VDD
20 µV/mA Due to load current change
10 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range 0 VDD V
Capacitive Load Stability 2 nF RL = ∞
10 nF RL = 2 kΩ
DC Output Impedance 0.5 Ω
Short-Circuit Current 30 mA VDD = 5 V
Power-Up Time 4 µs Coming out of power-down mode; VDD = 5 V
REFERENCE INPUTS
Reference Current
170
200
V
REF
= V
DD
= 5.5 V
Reference Input Range 0.75 VDD V
Reference Input Impedance 26 kΩ
REFERENCE OUTPUT
Output Voltage 2.495 2.505 V At ambient
Reference TC3 ±5 ±10 ppm/°C MSOP package models
±10 ppm/°C LFCSP package models
±15 ppm/°C WLCSP package models
Output Impedance 7.5 kΩ
AD5624R/AD5644R/AD5664R Data Sheet
Rev. C | Page 4 of 28
B Grade1
Parameter Min Typ Max Unit Conditions/Comments
LOGIC INPUTS3
Input Current ±2 µA All digital inputs
VINL, Input Low Voltage 0.8 V VDD = 5 V
VINH, Input High Voltage 2 V VDD = 5 V
Pin Capacitance 3 pF
POWER REQUIREMENTS
VDD 4.5 5.5 V
IDD VIH = VDD, VIL = GND, VDD = 4.5 V to 5.5 V
Normal Mode4 0.45 0.9 mA Internal reference off
0.95 1.2 mA Internal reference on
All Power-Down Modes5 0.48 1 µA
1 Temperature range: B grade: −40°C to +105°C.
2 Linearity calculated using a reduced code range: AD5664R (Code 512 to Code 65,024); AD5644R (Code 128 to Code 16,256); AD5624R (Code 32 to Code 4064). Output
unloaded.
3 Guaranteed by design and characterization, not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All DACs powered down.
AD5624R-3/AD5644R-3/AD5664R-3
VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
B Grade1
Parameter Min Typ Max Unit Conditions/Comments
STATIC PERFORMANCE2
AD5664R
Resolution
16
Relative Accuracy ±8 ±16 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
AD5644R
Resolution 14 Bits
Relative Accuracy ±2 ±4 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design
AD5624R
Resolution 12 Bits
Relative Accuracy ±0.5 ±1 LSB
Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design
Zero-Code Error 2 10 mV All zeroes loaded to DAC register
Offset Error ±1 ±10 mV
Full-Scale Error −0.1 ±1 % of FSR All ones loaded to DAC register
Gain Error ±1.5 % of FSR
Zero-Code Error Drift ±2 µV/°C
Gain Temperature Coefficient ±2.5 ppm Of FSR/°C
DC Power Supply Rejection Ratio
−100
DAC code = midscale; V
DD
= 3 V ± 10%
DC Crosstalk
External Reference 10 µV
Due to full-scale output change, RL = 2 kΩ to GND or VDD
10 µV/mA Due to load current change
5 µV Due to powering down (per channel)
Internal Reference
25
Due to full-scale output change, R
L
= 2 kΩ to GND or V
DD
20 µV/mA Due to load current change
10 µV Due to powering down (per channel)
Data Sheet AD5624R/AD5644R/AD5664R
Rev. C | Page 5 of 28
B Grade1
Parameter Min Typ Max Unit Conditions/Comments
OUTPUT CHARACTERISTICS3
Output Voltage Range 0 VDD V
Capacitive Load Stability 2 nF RL = ∞
10 nF RL = 2 kΩ
DC Output Impedance 0.5 Ω
Short-Circuit Current 30 mA VDD = 3 V
Power-Up Time 4 µs Coming out of power-down mode; VDD = 3 V
REFERENCE INPUTS
Reference Current 170 200 µA VREF = VDD = 3.6 V
Reference Input Range 0 VDD V
Reference Input Impedance 26 kΩ
REFERENCE OUTPUT
Output Voltage 1.247 1.253 V At ambient
Reference TC3 ±5 ±15 ppm/°C MSOP package models
±10 ppm/°C LFCSP package models
Output Impedance 7.5 kΩ
LOGIC INPUTS3
Input Current
±2
All digital inputs
VINL, Input Low Voltage 0.8 V VDD = 3 V
VINH, Input High Voltage 2 V VDD = 3 V
Pin Capacitance 3 pF
POWER REQUIREMENTS
VDD 2.7 3.6 V
IDD VIH = VDD, VIL = GND, VDD = 2.7 V to 3.6 V
Normal Mode4 0.44 0.85 mA Internal reference off
0.95 1.15 mA Internal reference on
All Power-Down Modes5 0.2 1 µA
1 Temperature range: B grade: −40°C to +105°C.
2 Linearity calculated using a reduced code range: AD5664R (Code 512 to Code 65,024); AD5644R (Code 128 to Code 16,256); AD5624R (Code 32 to Code 4064). Output
unloaded.
3 Guaranteed by design and characterization, not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All DACs powered down.
AD5624R/AD5644R/AD5664R Data Sheet
Rev. C | Page 6 of 28
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.1
Table 4.
Parameter2 Min Typ Max Unit Conditions/Comments3
Output Voltage Settling Time
AD5624R 3 4.5 µs ¼ to ¾ scale settling to ±0.5 LSB
AD5644R 3.5 5 µs ¼ to ¾ scale settling to ±0.5 LSB
AD5664R 4 7 µs ¼ to ¾ scale settling to ±2 LSB
Slew Rate
1.8
V/µs
Digital-to-Analog Glitch Impulse
10
nV-s
1 LSB change around major carry
Digital Feedthrough 0.1 nV-s
Reference Feedthrough −90 dB VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
Digital Crosstalk 0.1 nV-s
Analog Crosstalk 1 nV-s External reference
4 nV-s Internal reference
DAC-to-DAC Crosstalk 1 nV-s External reference
4 nV-s Internal reference
Multiplying Bandwidth 340 kHz VREF = 2 V ± 0.1 V p-p
Total Harmonic Distortion −80 dB VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz
100
nV/√Hz
DAC code = midscale, 10 kHz
Output Noise 15 µV p-p 0.1 Hz to 10 Hz
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C, typical at 25°C.
Data Sheet AD5624R/AD5644R/AD5664R
Rev. C | Page 7 of 28
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2).
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.1
Table 5.
Limit at TMIN, TMAX
Parameter VDD = 2.7 V to 5.5 V Unit Conditions/Comments
t12 20 ns min SCLK cycle time
t2 9 ns min SCLK high time
t3 9 ns min SCLK low time
t4 13 ns min SYNC to SCLK falling edge setup time
t5 5 ns min Data setup time
t6 5 ns min Data hold time
t7 0 ns min SCLK falling edge to SYNC rising edge
t8 15 ns min Minimum SYNC high time
t
9
13
ns min
SYNC
rising edge to SCLK fall ignore
t10 0 ns min SCLK falling edge to SYNC fall ignore
1 Guaranteed by design and characterization, not production tested.
2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
TIMING DIAGRAM
Figure 2. Serial Write Operation
DB0DB23
t10
SCLK
SYNC
DIN
t1t9
t7
t2
t3
t6
t5
t4
t8
05856-002
AD5624R/AD5644R/AD5664R Data Sheet
Rev. C | Page 8 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to GND −0.3 V to +7 V
VOUT to GND −0.3 V to VDD + 0.3 V
VREFIN/VREFOUT to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial −40°C to +105°C
Storage Temperature Range
−65°C to +150°C
Junction Temperature (TJ max) 150°C
Power Dissipation (TJ max − TA)/θJA
Thermal Impedance
LFCSP_WD Package (4-Layer Board)
θJA 61°C/W
MSOP Package (4-Layer Board)
θJA 142°C/W
θJC 43.7°C/W
WLCSP Package (4-Layer Board)
θJA 75°C/W
Reflow Soldering Peak Temperature
Pb-Free 260°C ± 5°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Data Sheet AD5624R/AD5644R/AD5664R
Rev. C | Page 9 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. 10-Lead LFCSP and 10-Lead MSOP Pin Configuration
Figure 4. 12-Ball WLCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
LFCSP MSOP WLCSP Mnemonic Description
1 1 A3 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
2
2
B3
V
OUT
B
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
3 3 A2, B2,
C2
GND Ground Reference Point for all Circuitry on the Part.
4 4 C3 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
5 5 D3 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
6 6 D2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data.
When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift
register. Data is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high
before the 24th falling edge, the rising edge of SYNC acts as an interrupt and the write
sequence is ignored by the device.
7 7 D1 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates up to 50 MHz.
8 8 C1 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
9 9 B1 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
10 10 A1 VREFIN/VREFOUT The AD5624R/AD5644R/AD5664R have a common pin for reference input and reference
output. When using the internal reference, this is the reference output pin. When using an
external reference, this is the reference input pin. The default for this pin is as a reference input.
N/A N/A EPAD Exposed Pad. The exposed pad must be tied to GND on the LFCSP package.
1
V
OUT
A
10
V
REFIN
/V
REFOUT
2
V
OUT
B
9
V
DD
3
GND
8
DIN
4
V
OUT
C
7
SCLK
5
V
OUT
D
6
SYNC
AD5624R/
AD5644R/
AD5664R
TOP VIEW
(Not t o Scale)
05856-003
EXPOSED PAD TIED TO
GND O N LF CSP PACKAGE
TOP VIEW
(BALL SIDE DOWN)
Not t o Scal e
GND VOUTA
VDD GND VOUTB
DIN GND VOUTC
SCLK SYNC VOUTD
1
A
B
C
D
2 3
BALLA1
INDICATOR
05856-104
V
REFIN
/
V
REFOUT
AD5624R/AD5644R/AD5664R Data Sheet
Rev. C | Page 10 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. AD5664R INL, External Reference
Figure 6. AD5644R INL, External Reference
Figure 7. AD5624R INL, External Reference
Figure 8. AD5664R DNL, External Reference
Figure 9. AD5644R DNL, External Reference
Figure 10. AD5624R DNL, External Reference
CODE
INL ERROR (L S B)
10
4
6
8
0
2
–6
–10
–8
–2
–4
05k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
05856-004
V
DD
= V
REF
= 5V
T
A
= 25° C
CODE
INL ERROR (L S B)
4
–4 02500 5000 7500 10000 12500 15000
05856-005
–3
–2
–1
0
1
2
3
VDD = VREF = 5V
TA = 25° C
CODE
INL ERROR (L S B)
1.0
–1.0 0500 1000 1500 2000 2500 3000 3500 4000
05856-006
–0.8
–0.6
–0.4
0
0.4
0.2
–0.2
0.6
0.8 VDD = VREF = 5V
TA = 25° C
CODE
DNL ERRO R ( LSB)
1.0
0.6
0.4
0.2
0.8
0
–0.4
–0.2
–0.6
–1.0
–0.8
010k 20k 30k 40k 50k 60k
05856-007
VDD = VREF = 5V
TA = 25° C
DNL ERRO R ( LSB)
0.5
0.3
0.2
0.1
0.4
0
–0.2
–0.1
–0.3
–0.5
–0.4
05856-008
VDD = VREF = 5V
TA = 25° C
CODE
02500 5000 7500 10000 12500 15000
DNL ERRO R ( LSB)
0.20
0.10
0.05
0.15
0
–0.05
–0.10
–0.20
–0.15
05856-009
CODE
0500 1000 1500 2000 2500 3000 3500 4000
VDD = VREF = 5V
TA = 25° C
Data Sheet AD5624R/AD5644R/AD5664R
Rev. C | Page 11 of 28
Figure 11. AD5664R-5 INL, Internal Reference
Figure 12. AD5644R-5 INL, Internal Reference
Figure 13. AD5624R-5 INL, Internal Reference
Figure 14. AD5664R-5 DNL, Internal Reference
Figure 15. AD5644R-5 DNL, Internal Reference
Figure 16. AD5624R-5 DNL, Internal Reference
CODE
INL ERROR (L S B)
10
8
0
–10
–6
–8
–4
6
–2
4
2
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
VDD = 5V
VREFOUT = 2. 5V
T
A
= 25°C
05856-010
CODE
INL ERROR (L S B)
4
3
–4
–3
–2
2
–1
1
0
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
VDD= 5V
VREFOUT= 2.5V
T
A
=25°C
05856-011
CODE
INL ERRO R ( LSB)
1.0
0.8
0
–1.0
–0.8
–0.6
0.6
–0.4
–0.2
0.4
0.2
01000500 20001500 350030002500 4000
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
05856-012
CODE
DNL ERRO R ( LSB)
1.0
0.
8
0
–1.0
–0.6
–0.8
–0.4
0.6
–0.2
0.4
0.2
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
05856-013
CODE
DNL ERRO R ( LSB)
0.5
0.4
0
–0.5
–0.3
–0.4
–0.2
0.3
–0.1
0.2
0.1
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
VDD = 5V
V
REFOUT
= 2.5V
T
A
= 25°C
05856-014
CODE
DN
L ERROR (LSB)
0.20
0.15
0
–0.20
–0.15
–0.10
0.10
–0.05
0.05
01000500 20001500 3500
30002500 4000
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
05856-015
AD5624R/AD5644R/AD5664R Data Sheet
Rev. C | Page 12 of 28
Figure 17. AD5664R-3 INL, Internal Reference
Figure 18. AD5644R-3 INL, Internal Reference
Figure 19. AD5624R-3 INL, Internal Reference
Figure 20. AD5664R-3 DNL, Internal Reference
Figure 21. AD5644R-3 DNL, Internal Reference
Figure 22. AD5624R-3 DNL, Internal Reference
CODE
INL ERROR (L S B)
10
8
4
6
2
0
–4
–2
–6
–8
–10
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
05856-016
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25° C
CODE
INL ERROR (L S B)
4
–4
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
05856-017
3
2
1
0
–1
–2
–3
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25° C
CODE
INL ERROR (L S B)
1.0
–1.0 0500 1000 1500 2000 2500 3000 3500 4000
0
0.8
0.6
0.4
0.2
–0.2
–0.4
–0.6
–0.8
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25° C
05856-018
CODE
DNL ERRO R ( LSB)
1.0
0.8
0.4
0.6
0.2
0
–0.4
–0.2
–0.6
–0.8
–1.0
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
VDD = 3V
VREFOUT = 1. 25V
TA = 25° C
05856-019
CODE
DNL ERRO R ( LSB)
0.5
–0.5
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
0
0.4
0.3
0.2
0.1
–0.1
–0.2
–0.3
–0.4
VDD = 3V
VREFOUT = 1. 25V
TA = 25° C
05856-020
CODE
DNL ERRO R ( LSB)
0.20
–0.20 0500 1000 1500 2000 2500 3000 3500 4000
0
0.15
0.10
0.05
–0.05
–0.10
–0.15
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25° C
05856-021
Data Sheet AD5624R/AD5644R/AD5664R
Rev. C | Page 13 of 28
Figure 23. INL Error and DNL Error vs. Temperature
Figure 24. INL Error and DNL Error vs. VREF
Figure 25. INL Error and DNL Error vs. Supply
Figure 26. Gain Error and Full-Scale Error vs. Temperature
Figure 27. Zero-Scale Error and Offset Error vs. Temperature
Figure 28. Gain Error and Full-Scale Error vs. Supply
TEMPERATURE (°C)
ERROR (LSB)
8
6
4
2
–6
–4
–2
0
–8
–40 –20 40200 1008060
05856-022
MIN DNL
MAX DNL
MAX INL
MIN INL
V
DD
= V
REF
= 5V
V
REF
(V)
ERROR (LSB)
10
4
6
8
2
0
–8
–6
–4
–2
–10
0.75 1.25 1.75 2.25 4.253.753.252.75 4.75
MIN DNL
MAX DNL
MAX INL
MIN INL
V
DD
= 5V
T
A
= 25°C
05856-023
V
DD
(V)
ERROR (LSB)
8
6
4
2
–6
–4
–2
0
–8
2.7 3.2 3.7 4.74.2 5.2
MIN DNL
MAX DNL
MAX INL
MIN INL
T
A
= 25°C
05856-024
TEMPERATURE (°C)
ERROR (% FSR)
0
–0.04
–0.02
–0.06
–0.08
–0.10
–0.18
–0.16
–0.14
–0.12
–0.20
–40 –20 402001008060
VDD = 5V
GAIN ERROR
FULL-SCALE ERROR
05856-025
TEMPERATURE (°C)
ERROR (mV)
1.5
1.0
0.5
0
–2.0
–1.5
–1.0
–0.5
–2.5
–40 –20 402008060 100
OFFSET ERROR
ZERO-SCALE ERROR
05856-026
V
DD
(V)
ERROR (% FSR)
1.0
–1.5
–1.0
–0.5
0
0.5
–2.0
2.7 3.2 3.7 4.74.2 5.2
GAIN ERROR
FULL-SCALE ERROR
05856-027
AD5624R/AD5644R/AD5664R Data Sheet
Rev. C | Page 14 of 28
Figure 29. Zero-Scale Error and Offset Error vs. Supply
Figure 30. IDD Histogram with External Reference, 5.5 V
Figure 31. IDD Histogram with Internal Reference, VREFOUT = 2.5 V
Figure 32. IDD Histogram with External Reference, 3.6 V
Figure 33. IDD Histogram with Internal Reference, VREFOUT = 1.25 V
Figure 34. Headroom at Rails vs. Source and Sink
V
DD
(V)
ERRO R ( mV )
1.0
0.5
0
–2.0
–1.5
–1.0
–0.5
–2.52.7 3.2 4.23.7 5.24.7
ZE RO-SCALE E RROR
OFFSET ERROR
T
A
= 25° C
05856-028
I
DD
(mA)
FREQUENCY
0
1
2
3
4
5
6
0.41 0.42 0.43 0.44 0.45
05856-029
V
DD
= 5.5V
T
A
= 25°C
I
DD
(mA)
FREQUENCY
0
1
2
3
4
5
6
0.92 0.94 0.96 0.98
05856-030
V
DD
= 5.5V
T
A
= 25°C
I
DD
(mA)
FREQUENCY
0
1
2
3
5
4
6
8
7
0.39 0.40 0.41 0.42 0.43
05856-060
V
DD
= 3.6V
T
A
= 25°C
I
DD
(mA)
FREQUENCY
0
1
2
3
5
4
6
8
7
0.90 0.92 0.94 0.96
05856-061
V
DD
= 3.6V
T
A
= 25°C
CURRENT ( mA)
ERRO R V OLTAGE (V)
0.5
0.4
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
–10 –8 –6 –4 –2 0 2 4 86 10
V
DD
= 3V
V
REFOUT
= 1.25V
V
DD
= 5V
V
REFOUT
= 2.5V
DAC LOADED W IT H
ZERO-SCALE
SI NKING CURRE NT
DAC LOADED W IT H
FULL-SCALE
SO URCING CURRE NT
05856-031
Data Sheet AD5624R/AD5644R/AD5664R
Rev. C | Page 15 of 28
Figure 35. AD56x4R-5 Source and Sink Capability
Figure 36. AD56x4R-3 Source and Sink Capability
Figure 37. Supply Current vs. Temperature
Figure 38. Full-Scale Settling Time, 5 V
Figure 39. Power-On Reset to 0 V
Figure 40. Exiting Power-Down to Midscale
CURRENT ( mA)
V
OUT
(V)
6
5
4
3
2
1
–1
0
–30 –20 –10 010 20 30
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25° C
ZE RO SCAL E
FULL SCALE
MIDSCALE
1/4 S CALE
3/4 S CALE
05856-046
CURRENT ( mA)
V
OUT
(V)
4
–1
0
1
2
3
–30 –20 –10 010 20 30
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25° C
ZE RO SCAL E
FULL SCALE
MIDSCALE
1/4 S CALE
3/4 S CALE
05856-047
TEMPERATURE (°C)
I
DD
(mA)
0.50
0.05
0.10
0.15
0.20
0.35
0.40
0.25
0.30
0.45
0
–40 –20 020 40 60 80 100
05856-063
T
A
= 25° C
V
DD
= V
REFIN
= 5V
V
DD
= V
REFIN
= 3V
TIME BASE = 4µs/DIV
VDD = VREF = 5V
TA = 25°C
FULL -SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LO ADE D WITH 2kΩ
AND 200pF TO GND
VOUT = 909mV /DI V
1
05856-048
CH1 2.0V CH2 500mV M100µ s 125M S /s
A CH1 1.28V 8.0ns/pt
V
DD
= V
REF
= 5V
T
A
= 25°C
V
OUT
V
DD
1
2
MAX(C2)
420.0mV
05856-049
05856-050
VDD = 5V
SYNC
SCLK
VOUT
1
3
CH1 5.0V
CH3 5.0V CH2 500mV M400ns A CH1 1.4V
2
AD5624R/AD5644R/AD5664R Data Sheet
Rev. C | Page 16 of 28
Figure 41. Digital-to-Analog Glitch Impulse (Negative)
Figure 42. Analog Crosstalk, External Reference
Figure 43. Analog Crosstalk, 2.5 V Internal Reference
Figure 44. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
Figure 46. 0.1 Hz to 10 Hz Output Noise Plot, 1.25 V Internal Reference
SAMPLE NUMBER
VOUT (V)
2.521
2.522
2.523
2.524
2.525
2.526
2.527
2.528
2.529
2.530
2.531
2.532
2.533
2.534
2.535
2.536
2.537
2.538
050 100 150 350 400200 250 300 450 512
05856-058
VDD = VREF = 5V
TA = 25°C
5ns/SAMP LE NUM BE R
GLITCH IMPULSE = 9.494nV
1LS B CHANGE AROUND
MI DS CALE (0x8000 TO 0x7FFF)
SAMPLE NUMBER
VOUT (V)
2.491
2.492
2.493
2.494
2.495
2.496
2.497
2.498
050 100 150 350 400200 250 300 450 512
05856-059
VDD = VREF = 5V
TA = 25°C
5ns/SAMP LE NUM BE R
ANALOG CROSS TAL K = 0.424nV
SAMPLE NUMBER
VOUT (V)
2.456
2.458
2.460
2.462
2.464
2.466
2.468
2.470
2.472
2.474
2.476
2.478
2.480
2.482
2.484
2.486
2.488
2.490
2.492
2.494
2.496
050 100 150 350 400200 250 300 450 512
05856-062
VDD = 5V
VREFOUT = 2. 5V
TA = 25°C
5ns/SAMP LE NUM BE R
ANALOG CROSS TAL K = 4.462nV
1
YAXIS = 2µV/DIV
XAXI S = 4s/DI V
VDD = VREF = 5V
TA = 25°C
DAC LOADED W IT H M IDSCAL E
05856-051
5s/DIV
10µV/DIV
1
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
DAC LOADED WIT H MIDSCALE
05856-052
4s/DIV
5µV/DIV
1
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
DAC LOADED WIT H MIDSCALE
05856-053
Data Sheet AD5624R/AD5644R/AD5664R
Rev. C | Page 17 of 28
Figure 47. Noise Spectral Density, Internal Reference
Figure 48. Total Harmonic Distortion
Figure 49. Settling Time vs. Capacitive Load
Figure 50. Multiplying Bandwidth
FREQUENCY (Hz)
OUTPUT NOISE (nV/√Hz)
800
0
100
200
300
400
500
600
700
100 10k
1k 100k 1M
V
DD
= 3V
V
REFOUT
= 1.25V
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25° C
MI DS CALE L OADED
05856-054
FREQUENCY (Hz)
AMPLITUDE ( dB)
–20
–50
–80
–30
–40
–60
–70
–90
–100 2k 4k 6k 8k 10k
V
DD
= 5V
T
A
= 25° C
DAC LOADED W IT H FULL SCALE
V
REF
= 2V ± 0.3V p-p
05856-055
CAPACITANCE (n F)
TIME (µs)
16
14
12
10
8
6
40 1 2 3 4 5 6 7 98 10
V
REF
= V
DD
T
A
= 25° C
V
DD =
5V
V
DD =
3V
05856-056
FRE QUENCY ( Hz )
AMPLITUDE ( dB)
5
–40
10k 100k 1M 10M
–35
–30
–25
–20
–15
–10
–5
0
V
DD
= 5V
T
A
= 25° C
05856-057
AD5624R/AD5644R/AD5664R Data Sheet
Rev. C | Page 18 of 28
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 5.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 8.
Zero-Code Error
Zero-scale error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5664R because the output of the DAC cannot go below
0 V due to a combination of the offset errors in the DAC and
the output amplifier. Zero-code error is expressed in mV. A plot
of zero-code error vs. temperature can be seen in Figure 27.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed in
percent of full-scale range. A plot of full-scale error vs.
temperature can be seen in Figure 26.
Gain Error
This is a measure of the span error of the DAC. It is the deviation
in slope of the DAC transfer characteristic from the ideal
expressed as % of FSR.
Zero-Code Error Drift
This is a measurement of the change in zero-code error with a
change in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
This is a measurement of the change in gain error with changes
in temperature. It is expressed in ppm of FSR/°C.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5664R
with code 512 loaded in the DAC register. It can be negative or
positive.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V, and VDD is varied by ±10%.
Output Voltage Settling Time
This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change
and is measured from the 24th falling edge of SCLK.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000) (see
Figure 41).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.
Noise Spectral Density
This is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale and
measuring noise at the output. It is measured in nV/√Hz. A plot
of noise spectral density can be seen in Figure 47.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC kept
at midscale. It is expressed in μV.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in μV/mA.
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.
Data Sheet AD5624R/AD5644R/AD5664R
Rev. C | Page 19 of 28
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa). Then execute a software LDAC
and monitor the output of the DAC whose digital code was not
changed. The area of the glitch is expressed in nV-s.
DAC-to-DAC Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent analog output
change of another DAC. It is measured by loading the attack
channel with a full-scale code change (all 0s to all 1s and vice
versa) using the command write to and update while monitor-
ing the output of the victim channel that is at midscale. The
energy of the glitch is expressed in nV-s.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
AD5624R/AD5644R/AD5664R Data Sheet
Rev. C | Page 20 of 28
THEORY OF OPERATION
DIGITAL-TO-ANALOG SECTION
The AD5624R/AD5644R/AD5664R DACs are fabricated on a
CMOS process. The architecture consists of a string DAC
followed by an output buffer amplifier. Figure 51 shows a block
diagram of the DAC architecture.
Figure 51. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
×= N
REFIN
OUT
D
VV 2
The ideal output voltage when using the internal reference is
given by
××=
N
REFOUTOUT
D
VV 2
2
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
0 to 4095 for AD5624R (12 bit).
0 to 16,383 for AD5644R (14 bit).
0 to 65,535 for AD5664R (16 bit).
N is the DAC resolution.
RESISTOR STRING
The resistor string is shown in Figure 52. It is simply a string of
resistors, each of value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off
to be fed into the output amplifier. The voltage is tapped off by
closing one of the switches connecting the string to the
amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. It can drive
a load of 2 kΩ in parallel with 1000 pF to GND. The source and
sink capabilities of the output amplifier can be seen in Figure 34
and Figure 35. The slew rate is 1.8 V/µs with a ¼ to ¾ full-scale
settling time of 7 µs.
Figure 52. Resistor String
INTERNAL REFERENCE
The AD5624R/AD5644R/AD5664R on-chip reference is off at
power-up and is enabled via a write to a control register. See the
Internal Reference Setup section for details.
The AD56x4R-3 has a 1.25 V, 5 ppm/°C reference giving a full-
scale output of 2.5 V. The AD56x4R-5 has a 2.5 V, 5 ppm/°C
reference giving a full-scale output of 5 V. The internal reference
associated with each part is available at the VREFOUT pin. A buffer
is required if the reference output is used to drive external loads.
When using the internal reference, it is recommended that a
100 nF capacitor is placed between reference output and GND
for reference stability.
EXTERNAL REFERENCE
The VREFIN pin on the AD56x4R-3 and AD56x4R-5 allows the
use of an external reference if the application requires it. The
default condition of the on-chip reference is off at power-up. All
devices (AD56x4R-3 and the AD56x4R-5) can be operated
from a single 2.7 V to 5.5 V supply.
SERIAL INTERFACE
The AD5624R/AD5644R/AD5664R have a 3-wire serial interface
(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as with most DSPs. See
Figure 2 for a timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5624R/AD5644R/AD5664R compat-
ible with high speed DSPs. On the 24th falling clock edge, the
last data bit is clocked in and the programmed function is
executed, that is, a change in DAC register contents and/or a
change in the mode of operation.
DAC
REGISTER
V
DD
GND
V
OUT
OUTPUT
AMPLIFIER
(GAIN = + 2)
05856-032
V
REFIN
RESISTOR
STRING
REF
R
R
R
R
RTO OUTPUT
AMPLIFIER
05856-033
Data Sheet AD5624R/AD5644R/AD5664R
Rev. C | Page 21 of 28
At this stage, the SYNC line can be kept low or be brought high. In
either case, it must be brought high for a minimum of 15 ns before
the next write sequence so that a falling edge of SYNC can initiate
the next write sequence.
Because the SYNC buffer draws more current when VIN = 2 V
than it does when VIN = 0.8 V, SYNC should be idled low
between write sequences for even lower power operation. As
mentioned previously, it must, however, be brought high again
just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 53). The first
two bits are don’t care bits. The next three are the command
bits, C2 to C0 (see Table 8), followed by the 3-bit DAC address,
A2 to A0 (see Table 9), and then the 16-, 14-, 12-bit data-word.
The data-word comprises the 16-, 14-, 12-bit input code
followed by 0, 2, or 4 don’t care bits, for the AD5664R,
AD5644R, and AD5624R, respectively (see Figure 53, Figure 54,
and Figure 55). These data bits are transferred to the DAC
register on the 24th falling edge of SCLK.
Table 8. Command Definition
C2 C1 C0 Command
0 0 0 Write to input register n
0 0 1 Update DAC register n
0 1 0 Write to input register n, update all
(software LDAC)
0 1 1 Write to and update DAC channel n
1 0 0 Power down DAC (power-up)
1
0
1
Reset
1 1 0 LDAC register setup
1 1 1 Internal reference setup (on/off)
Table 9. Address Command
A2
A1
A0
Address (n)
0 0 0 DAC A
0
0
1
DAC B
0 1 0 DAC C
0 1 1 DAC D
1 1 1 All DACs
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at least
24 falling edges of SCLK, and the DAC is updated on the 24th
falling edge. However, if SYNC is brought high before the 24th
falling edge, then this acts as an interrupt to the write sequence.
The input shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 56).
Figure 53. AD5664R Input Shift Register Contents
Figure 54. AD5644R Input Shift Register Contents
Figure 55. AD5624R Input Shift Register Contents
Figure 56. SYNC Interrupt Facility
XXC2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB23 (MSB) DB0 (LS B)
COMM AND BIT S ADDRES S BIT S
DATA BI TS
05856-034
X X C2 C1 C0 A2 A1 A0 X X
D11 D10D13 D12 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB23 (MSB) DB0 (LS B)
COMM AND BIT S ADDRES S BIT S
DATA BI TS
05856-035
X X C2 C1 C0 A2 A1 A0 XXXX
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB23 (MSB) DB0 (LS B)
COMM AND BIT S ADDRES S BIT S
DATA BI TS
05856-036
DIN
DB23 DB23 DB0DB0
VALID W RITE S E QUENCE, O UTPUT UP DATES
ON T HE 24
TH
FALLING EDGE
SYNC
SCLK
INVALI D WRITE SE QUENCE :
SYNC HI GH BEFORE 24
TH
FALLING EDGE
05856-037
AD5624R/AD5644R/AD5664R Data Sheet
Rev. C | Page 22 of 28
POWER-ON RESET
The AD5624R/AD5644R/AD5664R family contains a power-on
reset circuit that controls the output voltage during power-up.
The output of the AD5624R/AD5644R/AD5664R DACs powers
up to 0 V and the output remains there until a valid write
sequence is made to the DACs. This is useful in applications
where it is important to know the state of the output of the
DACs while they are in the process of powering up.
SOFTWARE RESET
The AD5624R/AD5644R/AD5664R contain a software reset
function. Command 101 is reserved for the software reset
function (see Table 8). The software reset command contains
two reset modes that are software programmable by setting bit
DB0 in the control register.
Table 10 shows how the state of the bit corresponds to the
software reset modes of operation of the devices.
Table 12 shows the contents of the input shift register during the
software reset mode of operation.
Table 10. Software Reset Modes for the
AD5624R/AD5644R/AD5664R
DB0
Registers Reset to 0
0 DAC register
Input shift register
1 (Power-On Reset) DAC register
Input shift register
LDAC register
Power-down register
Internal reference setup register
POWER-DOWN MODES
The AD5624R/AD5644R/AD5664R contain four separate modes
of operation. Command 100 is reserved for the power-down
function (see Table 8). These modes are software programmable
by setting two bits (DB5 and DB4) in the control register. Table 11
shows how the state of the bits corresponds to the mode of
operation of the device. All DACs (DAC D to DAC A) can be
powered down to the selected mode by setting the correspond-
ing four bits (DB3, DB2, DB1, and DB0) to 1.
By executing the same Command 100, any combination of DACs
can be powered up by setting the bits (DB5 and DB4) to normal
operation mode. To select which combination of DAC channels
to power-up, set the corresponding four bits (DB3, DB2, DB1,
and DB0) to 1. See Table 13 for contents of the input shift register
during power-down/power-up operation.
Table 11. Modes of Operation for the AD5624R/AD5644R/
AD5664R
DB5 DB4 Operating Mode
0 0 Normal operation
0 1 Power-down mode: 1 kΩ to GND
1 0 Power-down mode: 100 kΩ to GND
1
1
Power-down mode: three-state
When Bit DB5 and Bit DB4 are set to 0, the part works normally
with its normal power consumption of 450 µA at 5 V. However,
for the three power-down modes, the supply current falls to
480 nA at 5 V (200 nA at 3 V). Not only does the supply current
fall, but the output stage is also internally switched from the
output of the amplifier to a resistor network of known values.
This allows the output impedance of the part to be known while
the part is in power-down mode. The outputs can either be
connected internally to GND through a 1 kΩ resistor, or left
open-circuited (three-state) as shown in Figure 57.
Figure 57. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shutdown when power-down
mode is activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit power-down
is typically 4 µs for VDD = 5 V and for VDD = 3 V (see Figure 40).
Table 12. 24-Bit Input Shift Register Contents for Software Reset Command
DB23 to DB22 (MSB) DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0 (LSB)
x 1 0 1 x x x x 1/0
Don’t care Command bits (C2 to C0) Address bits (A2 to A0) Don’t care Determines software reset mode
Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation for the AD5624R/AD5644R/AD5664R
DB23 to
DB22
(MSB) DB21 DB20 DB19 DB18 DB17 DB16
DB15
to DB6 DB5 DB4 DB3 DB2 DB1
DB0
(LSB)
x 1 0 0 x x x x PD1 PD0 DAC D DAC C DAC B DAC A
Don’t
care
Command bits (C2 to C0) Address bits (A2 to A0)
Don’t care
Don’t
care
Power-down
mode
Power-down/power-up channel
selection, set bit to 1 to select channel
RESISTOR
NETWORK
V
OUT
RESISTOR
ST RING DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
05856-038
Data Sheet AD5624R/AD5644R/AD5664R
Rev. C | Page 23 of 28
LDAC FUNCTION
The AD5624R/AD5644R/AD5664R DACs have double-
buffered interfaces consisting of two banks of registers: input
registers and DAC registers. The input registers are connected
directly to the input shift register and the digital code is trans-
ferred to the relevant input register on completion of a valid
write sequence. The DAC registers contain the digital code used
by the resistor strings.
The double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to three of the input registers individually and then write to the
remaining input register, updating all DAC registers simulta-
neously. Command 010 is reserved for this software LDAC.
Access to the DAC registers is controlled by the LDAC function.
The LDAC register contains two modes of operation for each
DAC channel. The DAC channels are selected by setting the
bits of the 4-bit LDAC register (DB3, DB2, DB1, and DB0).
Command 110 is reserved for setting up the LDAC register.
When the LDAC bit register is set low, the corresponding DAC
registers are latched and the input registers can change state
without affecting the contents of the DAC registers. When the
LDAC bit register is set high, however, the DAC registers
become transparent and the contents of the input registers are
transferred to them on the falling edge of the 24th SCLK pulse.
This is equivalent to having an LDAC hardware pin tied perma-
nently low for the selected DAC channel, that is, synchronous
update mode. See Table 14 for the LDAC register mode of
operation. See Table 16 for contents of the input shift register
during the LDAC register setup command.
This flexibility is useful in applications where the user wants to
update select channels simultaneously, while the rest of the
channels update synchronously.
Table 14. LDAC Register Mode of Operation
LDAC Bits
(DB3 to DB0) LDAC Mode of Operation
0 Normal operation (default), DAC register
update is controlled by write command.
1 The DAC registers are updated after new
data is read in on the falling edge of the
24th SCLK pulse.
INTERNAL REFERENCE SETUP
The on-chip reference is off at power-up by default. This reference
can be turned on or off by setting a software programmable bit,
DB0, in the control register. Table 15 shows how the state of the
bit corresponds to the mode of operation. Command 111 is
reserved for setting up the internal reference (see Table 8).
Table 16 shows how the state of the bits in the input shift
register corresponds to the mode of operation of the device
during internal reference setup.
Table 15. Reference Setup Register
Internal Reference
Setup Register
(DB0) Action
0 Reference off (default)
1 Reference on
Table 16. 24-Bit Input Shift Register Contents for LDAC Setup Command for the AD5624R/AD5644R/AD5664R
DB23 to DB22
(MSB) DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB4 DB3 DB2 DB1 DB0 (LSB)
x 1 1 0 x x x x DAC D DAC C DAC B DAC A
Don’t care Command bits
(C2 to C0)
Address bits
(A2 to A0); don’t care
Don’t care Set bit to 0 or 1 for required mode of
operation on respective channel
Table 17. 24-Bit Input Shift Register Contents for Internal Reference Setup Command
DB23 to DB22
(MSB) DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0 (LSB)
x 1 1 1 x x x x 1/0
Don’t care Command bits (C2 to C0) Address bits (A2 to A0) Don’t care Reference setup register
AD5624R/AD5644R/AD5664R Data Sheet
Rev. C | Page 24 of 28
MICROPROCESSOR INTERFACING
AD5624R/AD5644R/AD5664R to Blackfin ADSP-BF53x
Interface
Figure 58 shows a serial interface between the AD5624R/
AD5644R/AD5664R and the Blackfin® ADSP-BF53x micro-
processor. The ADSP-BF53x processor family incorporates two
dual-channel synchronous serial ports, SPORT1 and SPORT0,
for serial and multiprocessor communications. Using SPORT0
to connect to the AD5624R/AD5644R/AD5664R, the setup for
the interface is that the DT0PRI drives the DIN pin of the
AD5624R/AD5644R/AD5664R, while TSCLK0 drives the
SCLK of the part. The SYNC is driven from TFS0.
Figure 58. Blackfin ADSP-BF53x Interface to AD5624R/AD5644R/AD5664R
AD5624R/AD5644R/AD5664R to 68HC11/68L11
Interface
Figure 59 shows a serial interface between the AD5624R/
AD5644R/AD5664R and the 68HC11/68L11 microcontroller.
SCK of the 68HC11/68L11 drives the SCLK of the AD5624R/
AD5644R/AD5664R, while the MOSI output drives the serial
data line of the DAC.
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are that the
68HC11/68L11 is configured with its CPOL bit as 0 and its
CPHA bit as 1. When data is transmitted to the DAC, the SYNC
line is taken low (PC7). When the 68HC11/68L11 is configured
as described previously, data appearing on the MOSI output is
valid on the falling edge of SCK. Serial data from the 68HC11/
68L11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. To load data to the AD5624R/AD5644R/AD5664R, PC7 is
left low after the first eight bits are transferred, and a second
serial write operation is performed to the DAC; PC7 is taken
high at the end of this procedure.
Figure 59. 68HC11/68L11 Interface to AD5624R/AD5644R/AD5664R
AD5624R/AD5644R/AD5664R to 80C51/80L51 Interface
Figure 60 shows a serial interface between the AD5624R/
AD5644R/AD5664R and the 80C51/80L51 microcontroller. The
setup for the interface is that the TxD of the 80C51/80L51 drives
SCLK of the AD5624R/AD5644R/AD5664R, while RxD drives the
serial data line of the part. The SYNC signal is derived from a bit-
programmable pin on the port. In this case, port line P3.3 is used.
When data is transmitted to the AD5624R/AD5644R/AD5664R,
P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes
only; thus, only eight falling clock edges occur in the transmit cycle.
To load data to the DAC, P3.3 is left low after the first eight bits are
transmitted, and a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion of
this cycle. The 80C51/80L51 outputs the serial data in LSB first
format. The AD5624R/AD5644R/AD5664R must receive data with
the MSB first. The 80C51/80L51 transmit routine should take this
into account.
Figure 60. 80C51/80L51 Interface to AD5624R/AD5644R/AD5664R
AD5624R/AD5644R/AD5664R to MICROWIRE Interface
Figure 61 shows an interface between the AD5624R/AD5644R/
AD5664R and any MICROWIRE-compatible device. Serial data
is shifted out on the falling edge of the serial clock and is
clocked into the AD5624R/AD5644R/AD5664R on the rising
edge of the SK.
Figure 61. MICROWIRE Interface to AD5624R/AD5644R/AD5664R
AD5624R/
AD5644R/
AD5664R
1
ADSP-BF53x
1
SYNC
TFS0
DIN
DTOPRI
SCLK
TSCLK0
1
ADDITIONAL PINS OMITTED FOR CLARITY.
05856-039
68HC11/68L11
1
SYNCPC7
SCLKSCK
DINMOSI
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD5624R/
AD5644R/
AD5664R
1
05856-040
80C51/80L51
1
SYNCP3.3
SCLKTxD
DINRxD
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD5624R/
AD5644R/
AD5664R
1
05856-041
MICROWIRE
1
SYNCCS
SCLKSK
DINSO
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD5624R/
AD5644R/
AD5664R
1
05856-042
Data Sheet AD5624R/AD5644R/AD5664R
Rev. C | Page 25 of 28
APPLICATIONS INFORMATION
USING A REFERENCE AS A POWER SUPPLY FOR
THE AD5624R/AD5644R/AD5664R
Because the supply current required by the AD5624R/AD5644R/
AD5664R is extremely low, an alternative option is to use a
voltage reference to supply the required voltage to the part (see
Figure 62). This is especially useful if the power supply is quite
noisy, or if the system supply voltages are at some value other
than 5 V or 3 V, for example, 15 V. The voltage reference outputs
a steady supply voltage for the AD5624R/AD5644R/AD5664R
(see Figure 60). If the low dropout REF195 is used, it must
supply 450 µA of current to the AD5624R/AD5644R/AD5664R
with no load on the output of the DAC. When the DAC output
is loaded, the REF195 also needs to supply the current to the
load. The total current required (with a 5 kΩ load on the DAC
output) is
450 µA + (5 V/5 kΩ) = 1.45 mA
The load regulation of the REF195 is typically 2 ppm/mA,
resulting in a 2.9 ppm (14.5 µV) error for the 1.45 mA current
drawn from it. This corresponds to a 0.191 LSB error.
Figure 62. REF195 as Power Supply to the AD5624R/AD5644R/AD5664R
BIPOLAR OPERATION USING THE
AD5624R/AD5644R/AD5664R
The AD5624R/AD5644R/AD5664R have been designed for
single-supply operation, but a bipolar output range is also
possible using the circuit in Figure 63. The circuit gives an
output voltage range of ±5 V. Rai l -to-rail operation at the
amplifier output is achievable using an AD820 or an OP295 as
the output amplifier.
The output voltage for any input code can be calculated as
follows:
×−
+
×
×= R1
R2
V
R1
R2R1D
VV DDDD
OUT 536,65
where D represents the input code in decimal (0 to 65,536).
With VDD = 5 V, R1 = R2 = 10 kΩ,
V5
536,65
10 −
×
=D
VOUT
This is an output voltage range of ±5 V, with 0x0000 corre-
sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
Figure 63. Bipolar Operation with the AD5624R/AD5644R/AD5664R
USING AD5624R/AD5644R/AD5664R WITH A
GALVANICALLY ISOLATED INTERFACE
In process control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from any hazardous common-
mode voltages that might occur in the area where the DAC is
functioning. Isocouplers provide isolation in excess of 3 kV. The
AD5624R/AD5644R/AD5664R use a 3-wire serial logic interface,
so the ADuM130x 3-channel digital isolator provides the
required isolation (see Figure 64). The power supply to the part
also needs to be isolated, which is done by using a transformer.
On the DAC side of the transformer, a 5 V regulator provides
the 5 V supply required for the AD5624R/AD5644R/AD5664R.
Figure 64. AD5624R/AD5644R/AD5664R with a Galvanically Isolated Interface
3-WIRE
SERIAL
INTERFACE
SYNC
SCLK
DIN
15V
5V
VOUT = 0V TO 5V
VDD
REF195
AD5624R/
AD5644R/
AD5664R
05856-043
3-WIRE
SERIAL
INTERFACE
R2 = 10kΩ
+5V
–5V
AD820/
OP295
+5V
AD5624R/
AD5644R/
AD5664R
V
DD
V
OUT
R1 = 10kΩ
±5V
0.1µF10µF
05856-044
0.1µF
5V
REGULATOR
GND
DIN
SYNC
SCLK
POWER 10µF
SDI
SCLK
DATA
AD5624R/
AD5644R/
AD5664R
V
OUT
V
OB
V
OA
V
OC
V
DD
V
IC
V
IB
V
IA
ADuM1300
05856-045
AD5624R/AD5644R/AD5664R Data Sheet
Rev. C | Page 26 of 28
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5624R/
AD5644R/AD5664R should have separate analog and digital
sections, each having its own area of the board. If the AD5624R/
AD5644R/AD5664R are in a system where other devices require
an AGND-to-DGND connection, the connection should be
made at one point only. This ground point should be as close as
possible to the AD5624R/AD5644R/AD5664R.
The power supply to the AD5624R/AD5644R/AD5664R should
be bypassed with 10 µF and 0.1 µF capacitors. The capacitors
should be located as close as possible to the device, with the
0.1 µF capacitor ideally right up against the device. The 10 µF
capacitor is the tantalum bead type. It is important that the
0.1 µF capacitor have low effective series resistance (ESR) and
effective series inductance (ESI), for example, common ceramic
types of capacitors. This 0.1 µF capacitor provides a low imped-
ance path to ground for high frequencies caused by transient
currents due to internal logic switching.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
Data Sheet AD5624R/AD5644R/AD5664R
Rev. C | Page 27 of 28
OUTLINE DIMENSIONS
Figure 65. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
Figure 66. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
0.50
0.40
0.30
10
1
6
5
0.30
0.25
0.20
PI N 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.74
1.64
1.49
0.20 RE F
0.05 M AX
0.02 NOM
0.50 BS C
EXPOSED
PAD
3.10
3.00 S Q
2.90
PI N 1
INDICATOR
(R 0. 15)
FOR PRO P E R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
02-05-2013-C
TOP VIEW BOTTOM VIEW
0.20 M IN
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
AD5624R/AD5644R/AD5664R Data Sheet
Rev. C | Page 28 of 28
Figure 67. 12-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-12-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Accuracy Internal Reference
Package
Description
Package
Option Branding
AD5624RBCPZ-3R2 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D7L
AD5624RBCPZ-3REEL7 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D7L
AD5624RBCPZ-5R2 −40°C to +105°C ±1 LSB INL 2.5 V 10-Lead LFCSP_WD CP-10-9 DBZ
AD5624RBCPZ-5REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 10-Lead LFCSP_WD CP-10-9 DBZ
AD5624RBRMZ-3
−40°C to +105°C
±1 LSB INL
1.25 V
10-Lead MSOP
RM-10
D7L
AD5624RBRMZ-3REEL7 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead MSOP RM-10 D7L
AD5624RBRMZ-5 −40°C to +105°C ±1 LSB INL 2.5 V 10-Lead MSOP RM-10 D7V
AD5624RBRMZ-5REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 10-Lead MSOP RM-10 D7V
AD5644RBRMZ-3 −40°C to +105°C ±4 LSB INL 1.25 V 10-Lead MSOP RM-10 D7E
AD5644RBRMZ-3REEL7 −40°C to +105°C ±4 LSB INL 1.25 V 10-Lead MSOP RM-10 D7E
AD5644RBRMZ-5 −40°C to +105°C ±4 LSB INL 2.5 V 10-Lead MSOP RM-10 D7D
AD5644RBRMZ-5REEL7 −40°C to +105°C ±4 LSB INL 2.5 V 10-Lead MSOP RM-10 D7D
AD5664RBCBZ-3RL7 −40°C to +105°C ±16 LSB INL 1.25 V 12 Ball WLCSP CB-12-9
AD5664RBCPZ-3R2 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D73
AD5664RBCPZ-3REEL7 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D73
AD5664RBRMZ-3
−40°C to +105°C
±16 LSB INL
1.25 V
10-Lead MSOP
RM-10
D73
AD5664RBRMZ-3REEL7 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead MSOP RM-10 D73
AD5664RBRMZ-5 −40°C to +105°C ±16 LSB INL 2.5 V 10-Lead MSOP RM-10 D75
AD5664RBRMZ-5REEL7 −40°C to +105°C ±16 LSB INL 2.5 V 10-Lead MSOP RM-10 D75
EVAL-AD5664REBZ Evaluation Board
1 Z = RoHS Compliant Part.
A
B
C
D
0.650
0.595
0.540
1.705
1.665
1.625
2.285
2.245
2.205
1
2
3
BOTTOM VI EW
(BALL SIDE UP)
TOP VIEW
(BALL SI DE DOW N)
END VIEW
0.340
0.320
0.300
1.50
REF
1.00
REF
0.50
BSC
BALLA1
IDENTIFIER
08-31-2012-A
SEATING
PLANE 0.270
0.240
0.210
0.380
0.355
0.330
COPLANARITY
0.05
©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05856-0-4/13(C)