128M DDR SDRAM
K4D263238D
-1- Rev. 1.3 (Jul. 2002)
128Mbit DDR SDRAM
Revision 1.3
July 2002
1M x 32Bit x 4 Banks
with Bi-directional Data Strobe and DLL
Double Data Rate Synchronous DRAM
128M DDR SDRAM
K4D263238D
-2- Rev. 1.3 (Jul. 2002)
Revision History
Revision 1.3 (July 18, 2002)
• Changed power dissipation from 2.0W to 1.8W
Revision 1.2 (June 17, 2002)
• Removed K4D263238D-QC55 from the spec.
• 183/166MHz were supported in K4D263238D-QC50.
Revision 1.1 (May 24, 2002)
• Removed K4D263238D-QC45/60 from the spec
Revision 1.0 (May 20, 2002)
• Define DC spec.
Revision 0.0 (April 23, 2002)- Target spec
• Define target spec.
128M DDR SDRAM
K4D263238D
-3- Rev. 1.3 (Jul. 2002)
The K4D263238D is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by
32 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 2.0GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
• 2.5V ± 5% power supply
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3,4 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Differential clock input
• No Write Interrupted by Read function
GENERAL DESCRIPTION
FEATURES
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 100pin TQFP package
• Maximum clock frequency up to 250MHz
• Maximum data rate up to 500Mbps/pin
FOR 1M x 32Bit x 4 Bank DDR SDRAM
1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
ORDERING INFORMATION
Part NO. Max Freq. MaxDataRate Interface Package
K4D263238D-QC40 250MHz 500Mbps/pin SSTL_2 100 TQFP
K4D263238D-QC50 200MHz 400Mbps/pin
128M DDR SDRAM
K4D263238D
-4- Rev. 1.3 (Jul. 2002)
PIN CONFIGURATION (Top View)
PIN DESCRIPTION
CK,CK Differential Clock Input BA0,BA1Bank Select Address
CKE Clock Enable A0~A11 Address Input
CS Chip Select DQ0~DQ31 Data Input/Output
RAS Row Address Strobe VDD Power
CAS Column Address Strobe VSS Ground
WE Write Enable VDDQ Power for DQ′s
DQS Data Strobe VSSQ Ground for DQ′s
DMi Data Mask MCL Must Connect Low
RFU Reserved for Future Use
DQ29
VSSQ
DQ30
DQ31
VSS
VDDQ
N.C
N.C
N.C
N.C
N.C
VSSQ
RFU
DQS
VDDQ
VDD
DQ0
DQ1
VSSQ
DQ2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DM0
DM2
WE
CAS
RAS
CS
BA0
BA1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A7
A6
A5
A4
VSS
A9
N.C
N.C
N.C
N.C
N.C
N.C
N.C
A11
A10
VDD
A3
A2
A1
A0
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
100 Pin TQFP
20 x 14 mm2
0.65mm pin Pitch
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
VREF
DM3
DM1
CK
CK
CKE
MCL
A8(AP)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
128M DDR SDRAM
K4D263238D
-5- Rev. 1.3 (Jul. 2002)
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
Symbol Type Function
CK, CK*1 Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ′sandDM′s that are sampled on both edges of the DQS.
CKE Input
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS Input
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS Input Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
CAS Input Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE Input Enables write operation and row precharge.
Latches data in starting from CAS,WEactive.
DQS Input/Output Data input and output are synchronized with both edge of DQS.
DM0~DM3Input
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM0for DQ0~DQ7, DM1for DQ8~DQ15, DM2for
DQ16 ~DQ23, DM3for DQ24 ~DQ31.
DQ0~DQ31 Input/Output Data inputs/Outputs are multiplexed on the same pins.
BA0,BA1Input Selects which bank is to be active.
A0~A11 Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0~RA11, Column addresses : CA0~CA7.
Column address CA8is used for auto precharge.
VDD/VSS Power Supply Power and ground for the input buffers and core logic.
VDDQ/VSSQ Power Supply Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VREF Power Supply Reference voltage for inputs, used for SSTL interface.
MCL Must Connect Low Must connect Low
128M DDR SDRAM
K4D263238D
-6- Rev. 1.3 (Jul. 2002)
BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank)
Bank Select
Timing Register
Address Register
Refresh Counter
Row Buffer
Row Decoder Col. Buffer
Data Input Register
Serial to parallel
1Mx32
1Mx32
1Mx32
1Mx32
Sense AMP
2-bit prefetch
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Strobe
Gen.
CK,CK
ADDR
LCKE
CK,CK CKE CS RAS CAS WE DMi
LDMi
CK,CK
LCAS
LRAS LCBR LWE
LWCBR
LRAS
LCBR
CK, CK
64
64 32
32
LWE
LDMi
x32
DQi
Data Strobe
Intput Buffer
DLL
128M DDR SDRAM
K4D263238D
-7- Rev. 1.3 (Jul. 2002)
•Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high.
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*1,2 7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
FUNCTIONAL DESCRIPTION
Power up & Initialization Sequence
Command
01 2 3 4 5 6 7 8 9 10111213141516171819
tRP 2Clockmin.
precharge
ALL Banks
2nd Auto
Refresh
Mode
Register Set
Any
Command
tRFC
1st Auto
Refresh
tRFC
EMRS MRS
2 Clock min.
DLL Reset
∼
∼∼
∼∼
∼
∼
∼∼
∼∼
∼
precharge
ALL Banks
tRP
CK
CK
Inputs must be
stable for 200us
∼
∼
200 Clock min.
∼
∼
2 Clock min.
128M DDR SDRAM
K4D263238D
-8- Rev. 1.3 (Jul. 2002)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS,RAS,CASand
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A0~A11 and BA0,BA1inthesamecycleasCS,RAS,CASand WE going low is written in the mode register.
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2,
addressing mode uses A3,CASlatency(read latency from column address) uses A4~A6.A7is used for test mode. A8is
used for DLL reset. A7,A8,BA0and BA1must be set to low for normal MRS operation. Refer to the table for specific codes
for various burst length, addressing modes and CAS latencies.
MODE REGISTER SET(MRS)
Address Bus
Mode
CAS Latency
A6A5A4Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 Reserved
011 3
100 4
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
Burst Length
A2A1A0
Burst Type
Sequential Interleave
0 0 0 Reserve Reserve
001 2 2
010 4 4
011 8 8
1 0 0 Reserve Reserve
1 0 1 Reserve Reserve
1 1 0 Reserve Reserve
111 Fullpage Reserve
Burst Type
A3Type
0 Sequential
1 Interleave
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
MRS Cycle
Command
*1: MRS can be issued only at all banks precharge state.
*2: Minimum tRP is required to issue MRS command.
CK, CK
Precharge NOP NOPMRS NOPNOP
201 534 867
Any
NOP All Banks Command
tRP tMRD=2 tCK
BA1BA0A11 A10 A9A8A7A6A5A4A3A2A1A0
RFU 0 RFU DLL TM CAS Latency BT Burst Length
BA0An~A0
0MRS
1EMRS
DLL
A8DLL Reset
0No
1Yes
Test Mode
A7mode
0Normal
1Test
Register
NOP
128M DDR SDRAM
K4D263238D
-9- Rev. 1.3 (Jul. 2002)
The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The
default value of the extended mode register is not defined, therefore the extend mode register must be written after power
up for enabling or disabling DLL. The extended mode register is written by asserting low on CS,RAS,CAS,WEand high
on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode
register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS,RAS,CASand WE going
low are written in the extended mode register. A1 and A6 are used for setting driver strength to weak or matched imped-
ance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register
contents can be changed using the same command and clock cycle requirements during operation as long as all banks
are in the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins
except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
A0DLL Enable
0 Enable
1Disable
BA0An~A0
0MRS
1EMRS
Figure 7. Extend Mode Register set
EXTENDED MODE REGISTER SET(EMRS)
Address Bus
Extended
BA1BA0A11 A10 A9A8A7A6A5A4A3A2A1A0
RFU 1 RFU D.I.C RFU D.I.C DLL Mode Register
* RFU(Reserved for future use)
should stay "0" during EMRS
cycle.
A6A1Output Driver Impedance Control
01 Weak
11 Matched
128M DDR SDRAM
K4D263238D
-10- Rev. 1.3 (Jul. 2002)
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN,VOUT -0.5 ~ 3.6 V
VoltageonV
DD supply relative to Vss VDD -1.0 ~ 3.6 V
VoltageonV
DD supply relative to Vss VDDQ -0.5 ~ 3.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD1.8 W
Short circuit current IOS 50 mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)
Parameter Symbol Min Typ Max Unit Note
Device Supply voltage VDD 2.3752.502.625 V 1
Output Supply voltage VDDQ 2.3752.502.625 V 1
Reference voltage VREF 0.49*VDDQ -0.51*VDDQ V2
Termination voltage Vtt VREF-0.04 VREF VREF+0.04 V 3
Input logic high voltage VIH VREF+0.15 - VDDQ+0.30 V 4
Input logic low voltage VIL -0.30 - VREF-0.15 V 5
Output logic high voltage VOH Vtt+0.76 - - V IOH=-15.2mA
Output logic low voltage VOL - - Vtt-0.76 V IOL=+15.2mA
Input leakage current IIL -5 - 5 uA 6
Output leakage current IOL -5 - 5 uA 6
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to
peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ,VREF is allowed + 25mV for DC error
and an additional + 25mV for AC noise.
3. Vtt of the transmitting device must track VREF of the receiving device.
4. VIH(max.)= VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate.
5. VIL(min.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V ≤ VIN ≤ VDD is acceptable. For all other pins that are not under test VIN=0V.
Note :
128M DDR SDRAM
K4D263238D
-11- Rev. 1.3 (Jul. 2002)
DC CHARACTERISTICS
Note: 1. Measured with outputs open.
2. Refresh period is 32ms.
Parameter Symbol Test Condition Version Unit Note
-40 -50
Operating Current
(One Bank Active) ICC1 Burst Lenth=2 tRC ≥ tRC(min)
IOL=0mA, tCC=tCC(min) 245 215 mA 1
Precharge Standby Current
in Power-down mode ICC2PCKE ≤VIL(max), tCC=tCC(min) 70 60 mA
Precharge Standby Current
in Non Power-down mode ICC2NCKE ≥ VIH(min), CS ≥ VIH(min),
tCC=tCC(min). 100 90 mA
Active Standby Current
power-down mode ICC3PCKE ≤ VIL(max), tCC=tCC(min) 100 80 mA
Active Standby Current in
in Non Power-down mode ICC3NCKE ≥ VIH(min), CS ≥ VIH(min),
tCC=tCC(min) . 175 150 mA
Operating Current
( Burst Mode) ICC4 IOL=0mA ,tCC=tCC(min), Page
Burst, All Banks activated. 630 530 mA
Refresh Current ICC5 tRC ≥ tRFC(min) 250 230 mA 2
Self Refresh Current ICC6 CKE ≤ 0.2V 3 mA
Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, VDD/VDDQ=2.5V+ 5%,TA=0 to 65°C)
Parameter Symbol Min Typ Max Unit Note
Input High (Logic 1) Voltage; DQ VIH VREF+0.35 - - V
Input Low (Logic 0) Voltage; DQ VIL --VREF-0.35 V
Clock Input Differential Voltage; CK and CK VID 0.7 - VDDQ+0.6 V 1
Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2 - 0.5*VDDQ+0.2 V 2
1. VID is the magnitude of the difference between the input level on CK and the input level on CK
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
Note :
128M DDR SDRAM
K4D263238D
-12- Rev. 1.3 (Jul. 2002)
AC OPERATING TEST CONDITIONS (VDD/VDDQ=2.5V+ 5% , TA=0to65°C)
Parameter Value Unit Note
Input reference voltage for CK(for single ended) 0.50*VDDQ V
CK and CK signal maximum peak swing 1.5 V
CK signal minimum slew rate 1.0 V/ns
Input Levels(VIH/VIL)VREF+0.35/VREF-0.35 V
Input timing measurement reference level VREF V
Output timing measurement reference level Vtt V
Output load condition See Fig.1
RT=50Ω
Output
CLOAD=30pF
(Fig. 1) Output Load Circuit
Z0=50ΩVREF
=0.5*VDDQ
Vtt=0.5*VDDQ
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter Symbol Value Unit
Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01 uF
Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 uF
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
Note :
CAPACITANCE (VDD=2.5V, TA=25°C, f=1MHz)
Parameter Symbol Min Max Unit
Input capacitance( CK, CK )CIN1 1.0 5.0 pF
Input capacitance(A0~A10,BA0~BA1)CIN2 1.0 4.0 pF
Input capacitance
( CKE, CS,RAS,CAS,WE)CIN3 1.0 4.0 pF
Data & DQS input/output capacitance(DQ0~DQ31)COUT 1.0 6.0 pF
Input capacitance(DM0 ~ DM3) CIN4 1.0 6.0 pF
128M DDR SDRAM
K4D263238D
-13- Rev. 1.3 (Jul. 2002)
13467
tCL
tCK
Hi-Z
Hi-Z
CK, CK
DQS
DQ
CS
DM
25
tIS
tIH
8
tDS tDH
01
tRPST
tRPRE
Db0 Db1
tDQSS tDQSH
tCH
Da1
Da2
tWPST
COMMAND
READA WRITEB
tDQSQ
tWPRES
tWPREH
tDQSCK
tAC
AC CHARACTERISTICS
Simplified Timing @ BL=2, CL=3
Parameter Symbol -40 -50 Unit Note
Min Max Min Max
CK cycle time CL=3 tCK -85.010
ns
CL=4 4.0 ns
CK high level width tCH 0.45 0.55 0.45 0.55 tCK
CK low level width tCL 0.45 0.55 0.45 0.55 tCK
DQS out access time from CK tDQSCK -0.6 0.6 -0.7 +0.7 ns
Output access time from CK tAC -0.6 0.6 -0.7 +0.7 ns
Data strobe edge to Dout edge tDQSQ - 0.4 - +0.45 ns 1
Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK
Read postamble tRPST 0.4 0.6 0.4 0.6 tCK
CK to valid DQS-in tDQSS 0.85 1.15 0.8 1.2 tCK
DQS-In setup time tWPRES 0-0-ns
DQS-in hold time tWPREH 0.35 - 0.25 - tCK
DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK
DQS-In high level width tDQSH 0.4 0.6 0.4 0.6 tCK
DQS-In low level width tDQSL 0.4 0.6 0.4 0.6 tCK
Address and Control input setup tIS 0.9 - 1.0 - ns
Address and Control input hold tIH 0.9 - 1.0 - ns
DQ and DM setup time to DQS tDS 0.4 - 0.45 - ns
DQ and DM hold time to DQS tDH 0.4 - 0.45 - ns
Clock half period tHP
tCLmin
or
tCHmin
-
tCLmin
or
tCHmin
-ns1
Data output hold time from DQS tQH tHP-0.4 - tHP-0.45 - ns 1
128M DDR SDRAM
K4D263238D
-14- Rev. 1.3 (Jul. 2002)
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
output valid window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle
variation and replaces tDV
-tQHmin=tHP-Xwhere
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL3, BL2)
134
tHP
CK, CK
DQS
DQ
CS
25
01
COMMAND
READA
tQH
Da0
tDQSQ(max)
tDQSQ(max)
Da1
128M DDR SDRAM
K4D263238D
-15- Rev. 1.3 (Jul. 2002)
AC CHARACTERISTICS (I)
Note :1 For normal write operation, even numbers of Din are to be written inside DRAM
Parameter Symbol -40 -50 Unit Note
Min Max Min Max
Row cycle time tRC 15 - 12 - tCK
Refresh row cycle time tRFC 17 - 14 - tCK
Row active time tRAS 10 100K 8 100K tCK
RAS to CAS delay for Read tRCDRD 5-4-
tCK
RAS to CAS delay for Write tRCDWR 32
tCK
Row precharge time tRP 5-4-
tCK
RowactivetoRowactive tRRD 3-2-
tCK
Last data in to Row precharge tWR 3-2-
tCK 1
Last data in to Read command tCDLR 2-2-
tCK 1
Col. address to Col. address tCCD 1-1-
tCK
Mode register set cycle time tMRD 2-2-
tCK
Auto precharge write recovery + Precharge tDAL 8-6-
tCK
Exit self refresh to read command tXSR 200 - 200 - tCK
Power down exit time tPDEX 1tCK+tIS -
1tCK+tIS
-ns
Refresh interval time tREF 7.8 - 7.8 -us
128M DDR SDRAM
K4D263238D
-16- Rev. 1.3 (Jul. 2002)
AC CHARACTERISTICS (II)
* 183/166MHz were supported in K4D263238D-QC50
K4D263238D-QC40
Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit
250MHz(4.0ns)4 15171053538tCK
200MHz(5.0ns)3 1214842426tCK
K4D623238F-QC50
Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit
200MHz(5.0ns)3 1214842426tCK
183MHz(5.5ns)3 1214842426tCK
166MHz(6.0ns)3 1012732325tCK
(Unit : Number of Clock)
128M DDR SDRAM
K4D263238D
-17- Rev. 1.3 (Jul. 2002)
012345 678
BAa
Ra
Ra
tRCD
ACTIVEA ACTIVEB WRITEA WRITEB
Db0 Db1 Db3
13 14 15 16 17 18 19 20 21
BAa BAb
Ca Cb
BAa
Ca
9101112
PRECH
BAa
22
Ra
Da0 Da1 Da2 Da3
Normal Write Burst
(@ BL=4)
Multi Bank Interleaving Write Burst
(@ BL=4)
BAa
Ra
Ra
BAb
Rb
Rb
Db2
tRAS
tRC
tRP
tRRD
COMMAND
DQS
DQ
WE
DM
CK, CK
A8/AP
ADDR
(A0~A7,
BA[1:0]
A9~,A11)
ACTIVEA WRITEA
Da0 Da1 Da2 Da3
Simplified Timing(2) @ BL=4, CL=3
128M DDR SDRAM
K4D263238D
-18- Rev. 1.3 (Jul. 2002)
0.825
0.575
0.65
0.13 MAX
PACKAGE DIMENSIONS (TQFP)
Dimensions in Millimeters
0.10 MAX
0~7°
17.20 ±0.20
14.00 ±0.10
23.20 ±0.20
1.00 ±0.10
1.20 MAX *
0.05 MIN
0.80 ±0.20
#1
0.09~0.20
#100
0.30 ±0.08
20.00 ±0.10
