SMSC USB3315 PRODUCT PREVIEW Revision 1.3 (11-02-07)
Data Brief
PRODUCT FEATURES
USB3315
Hi-Speed USB Transceiver
with 1.8V -3.3V ULPI Interface -
24MHz Reference Clock
USB-IF “Hi-Speed” compliant to the Universal Serial
Bus Specification Rev 2.0
Interface compliant with the ULPI Specification
revision 1.1 as a Single Data Rate (SDR) PHY
1.8V to 3.3V IO Voltage (+/- 10%)
SMSC flexPWRTM Technology
— Low current design ideal for battery powered
applications
— “Sleep” mode tri-states all ULPI pins and places the
part in a low current state
Supports FS pre-amble for F S hubs wi th a LS device
attached (UTMI+ Level 3)
Supports HS SOF and LS keep-alive pulse
Includes full support for the optional On-The-Go
(OTG) protocol detailed in the On-The-Go
Supplement Revision 1.0a specification
Supports the OTG Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP)
Allows host to turn VBUS off to conserve battery
power in OTG applications
Support OTG monitoring of VBUS levels with intern al
comparators
“Wrapper-less” design for optimal timing performance
and design ease
— Low Latency Hi-Speed Receiver (43 Hi-Speed clocks
Max) allows use of legacy UTMI Links with a ULPI
bridge
Internal 5V cable short-circuit protection of ID, DP
and DM lines to VBUS or ground
24MHz Reference Clock operation
— 0 to 3.6V input drive tolerant
— Able to accept “noisy” clock sources
Internal low jitter PLL for 480MHz Hi-Speed USB
operation
Internal detection of the value of resistance to ground
on the ID pin
Integrated battery to 3.3V LDO regulator
— 2.2uF bypass capacitor
— 100mV dropout voltage
Integrated ESD protection circuits
— Up to +-15kV without any external devices
Carkit UART mode for non-USB serial data transfers
Industrial Operating Temperature -40°C to +85°C
Packaging Options
— 24 pin QFN lead-free RoHS compliant package
(4 x 4 x 0.90 mm height)
Applications
The USB3315 is targeted for any applicatio n where a Hi-
Speed USB connection is desired and when board
space, power, and interface pins must be minimized.
The USB3315 is well suited for:
Cell Phones
PDAs
MP3 Players
GPS Personal Navigation
Scanners
External Hard Drives
Digital Still and Video Cameras
Portable Media Players
Entertainment Devices
Printers
Set Top Boxes
Video Record/Playback Systems
IP and Video Phones
Gaming Consoles
POS Terminals
Order Number(s):
USB3315-CP-TR FOR 24 PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (TAPE AND REEL)
REEL SIZE IS 4000 PIECES.
Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 24MHz Reference Clock
Revision 1.3 (11-02-07) 2 SMSC USB3315
PRODUCT PREVIEW
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2007 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other i nformation relating to SMSC products are in cluded as a means of illustrating typical applica tions. Consequently, complete informatio n sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assu med for inaccur acies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
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Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 24MHz Reference Clock
SMSC USB3315 3 Revision 1.3 (11-02-07)
PRODUCT PREVIEW
General Description
The USB3315 is a highly integrated Hi-Speed USB2.0 Transceiver (PHY) that supports systems
architectures based on a 24MHz reference clock. It is designed to be used in both commercial and
industrial temperature applications.
The USB3315 meets all of the electrical requirements to be used as a Hi-Speed USB Host, Device,
or an On-the-Go (OTG) device. In ad dition to the supportin g USB signaling the USB3315 al so provides
USB UART mode
USB3315 uses the industry standard U TMI+ Low Pin Interface (ULPI) to co nnect the USB PHY to the
Link. The industry standard ULPI interface uses a method of in-band signaling and status byte transfers
between the Link and PHY, to facilitate a USB session. By using in-band signaling and status byte
transfers the ULPI interface requires only 12 pins.
The USB3315 uses SMSC’s “wrapper-less” technology to implement th e ULPI interface. This “wrapper-
less” technology allows the PHY to achieve a low latency transmit and receive time. SMSC’s low
latency transceiver allows an existing UTMI Link to be reused by adding a UTMI to ULPI bridge. By
adding a bridge to the ASIC the existing and proven UTMI Link IP can be reused.
Figure 1 USB3315 Block Diagram
The USB3315 is designed to run with a 24MHz reference clock. By using a reference clock from the
Link the USB3315 is able to remove the cost of a crystal reference from the design.
The USB3315 includes a inte grated 3.3V LDO regulator to generate its own supply fro m power applied
at the VBAT pin. The voltage on the VBAT pin can range from 3.1 to 5.5V. The regulator dropout
voltage is less than 100mV which allows the PHY to continue USB signaling when the voltage on
VBAT drops to 3.1V. The USB transceiver will continue to operate at lower voltages, although some
parameters may be outside the limits of the USB specification s. If the user would like to provide a 3.3V
supply to the USB3315, the VBAT and VDD3.3 pins should be connected together.
The USB3315 also includes integrated pull-up resistors that can be used for detecting the attachment
of a USB Charger. By sensing the attachment to a USB Charger, a product using the USB3315 can
charge its battery at more than the 500mA allowed when charging from a USB Host.
OTG
Carkit
Hi-Speed
USB
Transceiver
U L P I In te rfa c e
ULPI
Registers
and State
Machine
BIAS
Lo w Jitte r
In te g ra ted
PLL
Inte gra te d
Power
Management
VBUS
ID
DP
DM
RBIAS
RESETB
VDD18
VDD33
REFCLK
ESD Protection
VBAT
VDDIO
DIR
NXT
STP
CLKOUT
DATA[7:0]
CPEN
Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 24MHz Reference Clock
Revision 1.3 (11-02-07) 4 SMSC USB3315
PRODUCT PREVIEW
USB3315 Pin Locations and Descriptions
Package Diagram with Pin Locations
The pinout below is viewed from the top of the package.
Figure 2 USB3315 QFN Pinout - Top View
Pin Definitions
The following table details the pin definitions for the figure above.
Table 1 USB3315 Pin Description
PIN NAME DIRECTION/
TYPE ACTIVE
LEVEL DESCRIPTION
1ID
Input,
Analog N/A ID pin of the USB cable. For non-OTG
applications this pin can be floated. For
an A-Device ID is grounded. For a B-
Device ID is floated.
2VBUS
I/O,
Analog N/A VBUS pin of the USB cable. This pin is
used for the Vbus comparator inputs and
for Vbus pulsing during session request
protocol.
CPEN
VBUS
ID
VDD3.3
DM
DP
NXT
DIR
STP
CLKOUT
DATA0
DATA2
DATA3
DATA1
VBAT
VDD1.8
DATA4
DATA6
DATA7
DATA5
1
2
3
4
5
6
7
8
9
10
11
12
18
17
16
15
14
13
24
23
22
21
20
19
24Pin QFN
4x4mm
RESETB
VDDIO
RBIAS
REFCLK
Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 24MHz Reference Clock
SMSC USB3315 5 Revision 1.3 (11-02-07)
PRODUCT PREVIEW
3VBAT Power N/A Regulator input. The regulator supply can
be from 5.5V to 3.1V.
4VDD3.3
Power N/A 3.3V Regulator Output. A 2.2uF (<1 o hm
ESR) bypass capacitor to ground is
required for regulator stability. The
bypass capacitor should be placed as
close as possible to the USB3315.
5DM I/O,
Analog N/A D- pin of the USB cable.
6DP I/O,
Analog N/A D+ pin of the USB cable.
7CPEN
Output,
CMOS High External 5 volt suppl y enable. This pin is
used to enable the external Vbus power
supply. The CPEN pin is low on POR.
This pad uses VDD3.3 logic level.
8DATA[7] I/O,
CMOS N/A ULPI bi-directional data bus. DATA[7] is
the MSB.
9DATA[6] I/O,
CMOS N/A ULPI bi-directional data bus.
10 DATA[5 I/O,
CMOS N/A ULPI bi-directional data bus.
11 DATA[4] I/O,
CMOS N/A ULPI bi-directional data bus.
12 CLKOUT
Output,
CMOS N/A 60MHz reference clock output. All ULPI
signals are driven synchronous to the
rising edge of this clock.
13 DATA[3] I/O,
CMOS N/A ULPI bi-directional data bus.
14 DATA[2] I/O,
CMOS N/A ULPI bi-directional data bus.
15 DATA[1] I/O,
CMOS N/A ULPI bi-directional data bus.
16 DATA[0] I/O,
CMOS N/A ULPI bi-directional data bus. DATA[0] is
the LSB.
17 VDDIO
Power N/A 1.8V to 3.3V ULPI interface supply
voltage. This voltage sets the value of
VOH for the ULPI interface.
18 NXT
Output,
CMOS High The PHY asserts NXT to throttle the data.
When the Link is sending data to the
PHY, NXT indicates when the current
byte has been accepted by the PHY. The
Link places the next byte on the data bus
in the following clock cycle.
Table 1 USB3315 Pin Description (continued)
Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 24MHz Reference Clock
Revision 1.3 (11-02-07) 6 SMSC USB3315
PRODUCT PREVIEW
19 DIR
Output,
CMOS N/A Controls the direction of the data bus.
When the PHY has data to transfer to the
Link, it drives DIR high to take ownership
of the bus. When the PHY has no data to
transfer it drives DIR low and monitors
the bus for commands from the Link.
20 STP
Input,
CMOS High The Link asserts STP for one clock cycle
to stop the data stream currently on the
bus. If the Link is sending data to the
PHY, STP indicates the last byte of data
was on the bus in the previous cycle.
21 VDD1.8
Power N/A External 1.8V Supply input pin. Th is pad
needs to be bypassed with a 0.1uF
capacitor to ground, placed as close as
possible to the USB3315.
22 RESETB
Input,
CMOS, N/A When low, the part is suspen ded with all
of the I/O tri-stated. When high the
USB3315 will operate as a normal ULPI
device.
23 REFCLK Input,
CMOS N/A 24MHz Reference Clock input.
24 RBIAS
Analog,
CMOS N/A Rbias pin. This pin requires an 8.06kΩ
(±1%) resistor to ground, placed as close
as possible to the USB3315.
FLAG GND
Ground N/A Ground.
QFN only: The flag should be connected
to the ground plane with a via array
under the exposed fla g. This is the main
ground for the IC.
Table 1 USB3315 Pin Description (continued)
Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 24MHz Reference Clock
SMSC USB3315 7 Revision 1.3 (11-02-07)
PRODUCT PREVIEW
Application Diagram
Figure 3 USB3315 QFN Application Diagram
USB
Connector
ULPI Interface
5 Volt
Supply
8.06KΩ
3.1-5.5V
Battery /
Supply
4.7uF
0.1u
F
12
CVBUS
Host/O TG On ly
CVBUS
Host
Device
OTG Device
Min
120uF
1uF
1uF
Max
10uF
6.5uF
VBUS
ID
VDD3.3
DM
DP
NXT
DIR
STP
CLKOUT
DATA0
DATA2
DATA3
DATA1
RBIAS
VDD1.8
REFCLK
DATA4
DATA6
(msb) DATA7
DATA5
RESETB
VDDIO
CPEN
1
2
3
4
5
6
7
8
9
10
11
12
18
17
16
15
14
13
24
23
22
21
20
19
24Pin
QFN
4 x 4 mm
VBAT
2.2u
F
1.8V
Supply
4.7uF
0.1u
F
Reference Clock
RESETB
QFN
Ground Flag
1.8-3.3V
IO Supply
0.1u
F
VDDIO
Note:
VDDIO can
be connected
to the 1.8V
supply for
1.8V IO
REFCLK and C LKO UT should be
isolated with a ground line on both
sides.
SMSC USB3315 8 Revision 1.3 (11-02-07)
PRODUCT PREVIEW
Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 24MHz Reference Clock
Package Outline
Figure 4 24-pin QFN, 4x4mm Body, 0.5mm Pitch
