HM5264165F-75/A60/B60 HM5264805F-75/A60/B60 HM5264405F-75/A60/B60 64M LVTTL interface SDRAM 133 MHz/100 MHz 1-Mword x 16-bit x 4-bank/2-Mword x 8-bit x 4-bank /4-Mword x 4-bit x 4-bank PC/133, PC/100 SDRAM ADE-203-940B (Z) Rev. 1.0 Nov. 10, 1999 Description The Hitachi HM5264165F is a 64-Mbit SDRAM organized as 1048576-word x 16-bit x 4 bank. The Hitachi HM5264805F is a 64-Mbit SDRAM organized as 2097152-word x 8-bit x 4 bank. The Hitachi HM5264405F is a 64-Mbit SDRAM organized as 4194304-word x 4-bit x 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II. Features * * * * * * * * 3.3 V power supply Clock frequency: 133 MHz/100 MHz (max) LVTTL interface Single pulsed RAS 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 1/2/4/8/full page 2 variations of burst sequence Sequential (BL = 1/2/4/8/full page) Interleave (BL = 1/2/4/8) HM5264165F/HM5264805F/HM5264405F-75/A60/B60 * Programmable CAS latency: 2/3 * Byte control by DQM: DQM (HM5264805F/HM5264405F) DQMU/DQML (HM5264165F) * Refresh cycles: 4096 refresh cycles/64 ms * 2 variations of refresh Auto refresh Self refresh * Full page burst length capability Sequential burst Burst stop capability Ordering Information Frequency CAS latency Package HM5264165FTT-75* HM5264165FTT-A60 HM5264165FTT-B60 *2 133 MHz 100 MHz 100 MHz 3 2/3 3 400-mil 54-pin plastic TSOP II (TTP-54D) HM5264165FLTT-75 *1 HM5264165FLTT-A60 HM5264165FLTT-B60 *2 133 MHz 100 MHz 100 MHz 3 2/3 3 HM5264805FTT-75 *1 HM5264805FTT-A60 HM5264805FTT-B60 *2 133 MHz 100 MHz 100 MHz 3 2/3 3 HM5264805FLTT-75 *1 HM5264805FLTT-A60 HM5264805FLTT-B60 *2 133 MHz 100 MHz 100 MHz 3 2/3 3 HM5264405FTT-75 *1 HM5264405FTT-A60 HM5264405FTT-B60 *2 133 MHz 100 MHz 100 MHz 3 2/3 3 HM5264405FLTT-75 *1 HM5264405FLTT-A60 HM5264405FLTT-B60 *2 133 MHz 100 MHz 100 MHz 3 2/3 3 Type No. 1 Note: 2 1. 100 MHz operation at CAS latency = 2. 2. 66 MHz operation at CAS latency = 2. HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Arrangement (HM5264165F) 54-pin TSOP VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC DQML WE CAS RAS CS A13 A12 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC DQMU CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS (Top view) Pin Description Pin name Function Pin name Function A0 to A13 Address input WE Write enable Row address A0 to A11 DQMU/DQML Input/output mask Column address A0 to A7 CLK Bank select address A12/A13 (BS) CKE Clock input Clock enable DQ0 to DQ15 Data-input/output VCC Power for internal circuit CS Chip select VSS Ground for internal circuit RAS Row address strobe command VCCQ Power for DQ circuit CAS Column address strobe command VSS Q Ground for DQ circuit NC No connection 3 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Arrangement (HM5264805F) 54-pin TSOP VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC WE CAS RAS CS A13 A12 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS (Top view) Pin Description Pin name Function Pin name Function A0 to A13 Address input WE Write enable Row address A0 to A11 DQM Input/output mask Column address A0 to A8 CLK Clock input Bank select address A12/A13 (BS) CKE Clock enable DQ0 to DQ7 Data-input/output VCC Power for internal circuit CS Chip select VSS Ground for internal circuit RAS Row address strobe command VCCQ Power for DQ circuit CAS Column address strobe command VSS Q Ground for DQ circuit NC No connection 4 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Arrangement (HM5264405F) 54-pin TSOP VCC NC VCCQ NC DQ0 VSSQ NC NC VCCQ NC DQ1 VSSQ NC VCC NC WE CAS RAS CS A13 A12 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS NC VSSQ NC DQ3 VCCQ NC NC VSSQ NC DQ2 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS (Top view) Pin Description Pin name Function Pin name Function A0 to A13 Address input WE Write enable Row address A0 to A11 DQM Input/output mask Column address A0 to A9 CLK Clock input Bank select address A12/A13 (BS) CKE Clock enable DQ0 to DQ3 Data-input/output VCC Power for internal circuit CS Chip select VSS Ground for internal circuit RAS Row address strobe command VCCQ Power for DQ circuit CAS Column address strobe command VSS Q Ground for DQ circuit NC No connection 5 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Block Diagram (HM5264165F) A0 to A13 A0 to A7 A0 to A13 Column address buffer Bank 1 4096 row X 256 column X 16 bit Input buffer Row decoder Memory array Bank 2 4096 row X 256 column X 16 bit Sense amplifier & I/O bus Memory array Column decoder 4096 row X 256 column X 16 bit Sense amplifier & I/O bus Bank 0 Column decoder Sense amplifier & I/O bus Column decoder Memory array Row decoder Sense amplifier & I/O bus Row decoder Row decoder Refresh counter Row address buffer Column decoder Column address counter Memory array Bank 3 4096 row X 256 column X 16 bit Control logic & timing generator Output buffer WE DQMU /DQML CAS CS RAS CLK 6 CKE DQ0 to DQ15 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Block Diagram (HM5264805F) A0 to A13 A0 to A8 A0 to A13 Column address buffer 4096 row X 512 column X 8 bit Bank 2 4096 row X 512 column X 8 bit Memory array Bank 3 4096 row X 512 column X 8 bit Control logic & timing generator Output buffer WE DQM CAS CS RAS DQ0 to DQ7 CLK Input buffer Memory array Sense amplifier & I/O bus Bank 1 Row decoder Column decoder Memory array Column decoder 4096 row X 512 column X 8 bit Sense amplifier & I/O bus Bank 0 Column decoder Sense amplifier & I/O bus Column decoder Memory array Row decoder Sense amplifier & I/O bus Row decoder Row decoder Refresh counter Row address buffer CKE Column address counter 7 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Block Diagram (HM5264405F) A0 to A13 A0 to A9 A0 to A13 Column address buffer Bank 1 4096 row X 1024 column X 4 bit Input buffer Row decoder Memory array Bank 2 4096 row X 1024 column X 4 bit Sense amplifier & I/O bus Memory array Column decoder 4096 row X 1024 column X 4 bit Sense amplifier & I/O bus Bank 0 Column decoder Sense amplifier & I/O bus Column decoder Memory array Row decoder Sense amplifier & I/O bus Row decoder Row decoder Refresh counter Row address buffer Column decoder Column address counter Memory array Bank 3 4096 row X 1024 column X 4 bit Control logic & timing generator Output buffer WE DQM CAS CS RAS CLK 8 CKE DQ0 to DQ3 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Functions CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A11 (input pins): Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. Column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) is determined by A0 to A7, A8 or A9 (A7; HM5264165F, A8; HM5264805F, A9; HM5264405F) level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by A12/A13 (BS) is precharged. For details refer to the command operation section. A12/A13 (input pins): A12/A13 are bank select signal (BS). The memory array of the HM5264165F, HM5264805F, the HM5264405F is divided into bank 0, bank 1, bank 2 and bank 3. HM5264165F contain 4096-row x 256-column x 16-bit. HM5264805F contain 4096-row x 512-column x 8-bit. HM5264405F contain 4096-row x 1024-column x 4-bit. If A12 is Low and A13 is Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected. CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down mode, clock suspend mode and self refresh mode. DQM, DQMU/DQML (input pins): DQM, DQMU/DQML controls input/output buffers. Read operation: If DQM, DQMU/DQML is High, the output buffer becomes High-Z. If the DQM, DQMU/DQML is Low, the output buffer becomes Low-Z. (The latency of DQM, DQMU/DQML during reading is 2 clocks.) Write operation: If DQM, DQMU/DQML is High, the previous data is held (the new data is not written). If DQM, DQMU/DQML is Low, the data is written. (The latency of DQM, DQMU/DQML during writing is 0 clock.) DQ0 to DQ15 (DQ pins): Data is input to and output from these pins (DQ0 to DQ15; HM5264165F, DQ0 to DQ7; HM5264805F, DQ0 to DQ3; HM5264405F). VCC and VCC Q (power supply pins): 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer.) 9 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 VSS and V SS Q (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the output buffer.) Command Operation Command Truth Table The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins. CKE CS A0 RAS CAS WE A12/A13 A10 to A11 x H x x x x x x H x L H H H x x x BST H x L H H L x x x Column address and read command READ H x L H L H V L V Read with auto-precharge READ A H x L H L H V H V Column address and write command WRIT H x L H L L V L V Write with auto-precharge WRIT A H x L H L L V H V Row address strobe and bank active ACTV H x L L H H V V V Precharge select bank PRE H x L L H L V L x Precharge all bank PALL H x L L H L x H x Refresh REF/SELF H V L L L H x x x Mode register set MRS x L L L L V V V Command Symbol n-1 n Ignore command DESL H No operation NOP Burst stop in full page H Note: H: VIH. L: V IL. x: VIH or VIL. V: Valid address input Ignore command [DESL]: When this command is set (CS is High), the SDRAM ignore command input at the clock. However, the internal status is held. No operation [NOP]: This command is not an execution command. However, the internal operations continue. Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page (256; HM5264165F, 512; HM5264805F, 1024; HM5264405F)), and is illegal otherwise. When data input/output is completed for a full page of data, it automatically returns to the start address, and input/output is performed repeatedly. 10 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (BS). After the read operation, the output buffer becomes High-Z. Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal. Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13). Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this command is illegal. Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A12/A13 (BS) and determines the row address (AX0 to AX11). When A12 and A13 are Low, bank 0 is activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank 2 is activated. When A12 and A13 are High, bank 3 is activated. Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A12/A13. If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mode register set [MRS]: The SDRAM has a mode register that defines how it operates. The mode register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the mode register configuration. After power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. 11 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DQM Truth Table (HM5264165F) CKE Command Symbol n-1 n DQMU DQML Upper byte write enable/output enable ENBU H x L x Lower byte write enable/output enable ENBL H x x L Upper byte write inhibit/output disable MASKU H x H x Lower byte write inhibit/output disable MASKL H x x H Note: H: VIH. L: V IL. x: VIH or VIL. Write: IDID is needed. Read: I DOD is needed. DQM Truth Table (HM5264805F/HM5264405F) CKE Command Symbol n-1 n DQM Write enable/output enable ENB H x L Write inhibit/output disable MASK H x H Note: H: VIH. L: V IL. x: VIH or VIL. Write: IDID is needed. Read: I DOD is needed. The SDRAM can mask input/output data by means of DQM, DQMU/DQML. DQMU masks the upper byte and DQML masks the lower byte. (HM5264165F) During reading, the output buffer is set to Low-Z by setting DQM, DQMU/DQML to Low, enabling data output. On the other hand, when DQM, DQMU/DQML is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQM, DQMU/DQML to Low. When DQM, DQMU/DQML is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQMU/DQML. For details, refer to the DQM, DQMU/DQML control section of the SDRAM operating instructions. 12 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 CKE Truth Table CKE Current state Command n-1 n CS RAS CAS WE Address Active Clock suspend mode entry H L x x x x x Any Clock suspend L L x x x x x Clock suspend Clock suspend mode exit L H x x x x x Idle Auto-refresh command (REF) H H L L L H x Idle Self-refresh entry (SELF) H L L L L H x Idle Power down entry H L L H H H x H L H x x x x L H L H H H x L H H x x x x L H L H H H x L H H x x x x Self refresh Power down Self refresh exit (SELFX) Power down exit Note: H: VIH. L: V IL. x: VIH or VIL. Clock suspend mode entry: The SDRAM enters clock suspend mode from active mode by setting CKE to Low. When command is input during CKE is low, the command is valid. The clock suspend mode changes depending on the current status (1 clock before) as shown below. ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. READ suspend and READ with Auto-precharge suspend: The data being output is held (and continues to be output). WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During clock suspend mode, keep the CKE to Low. Clock suspend mode exit: The SDRAM exits from clock suspend mode by setting CKE to High during the clock suspend state. IDLE: In this state, all banks are not selected, and completed precharge operation. Auto-refresh command [REF]: When this command is input from the IDLE state, the SDRAM starts autorefresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank select address are generated inside the SDRAM. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 4096 times are required to refresh the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge command is required after auto-refresh. 13 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Self-refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM starts selfrefresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since selfrefresh is performed internally and automatically, external refresh operations are unnecessary. Power down mode entry: When this command is executed during the IDLE state, the SDRAM enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit. Self-refresh exit: When this command is executed during self-refresh mode, the SDRAM can exit from selfrefresh mode. After exiting from self-refresh mode, the SDRAM enters the IDLE state. Power down exit: When this command is executed at the power down mode, the SDRAM can exit from power down mode. After exiting from power down mode, the SDRAM enters the IDLE state. Function Truth Table The following table shows the operations that are performed when each command is issued in each mode of the SDRAM. The following table assumes that CKE is high. Current state CS RAS CAS WE Address Command Operation Precharge H x x x x DESL Enter IDLE after t RP L H H H x NOP Enter IDLE after t RP L H H L x BST NOP L H L H BA, CA, A10 READ/READ A ILLEGAL*4 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*4 L L H H BA, RA ACTV ILLEGAL*4 L L H L BA, A10 PRE, PALL NOP*6 L L L H x REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H x x x x DESL NOP L H H H x NOP NOP L H H L x BST NOP L H L H BA, CA, A10 READ/READ A ILLEGAL*5 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*5 L L H H BA, RA ACTV Bank and row active L L H L BA, A10 PRE, PALL NOP L L L H x REF, SELF Refresh L L L L MODE MRS Mode register set Idle 14 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Current state CS RAS CAS WE Address Command Operation Row active H x x x x DESL NOP L H H H x NOP NOP L H H L x BST NOP L H L H BA, CA, A10 READ/READ A Begin read L H L L BA, CA, A10 WRIT/WRIT A Begin write L L H H BA, RA ACTV Other bank active ILLEGAL on same bank*3 L L H L BA, A10 PRE, PALL Precharge L L L H x REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H x x x x DESL Continue burst to end L H H H x NOP Continue burst to end L H H L x BST Burst stop to full page L H L H BA, CA, A10 READ/READ A Continue burst read to CAS latency and New read L H L L BA, CA, A10 WRIT/WRIT A Term burst read/start write L L H H BA, RA ACTV Other bank active ILLEGAL on same bank*3 L L H L BA, A10 PRE, PALL Term burst read and Precharge L L L H x REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H x x x x DESL Continue burst to end and precharge L H H H x NOP Continue burst to end and precharge L H H L x BST ILLEGAL L H L H BA, CA, A10 READ/READ A ILLEGAL*4 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*4 L L H H BA, RA ACTV Other bank active ILLEGAL on same bank*3 L L H L BA, A10 PRE, PALL ILLEGAL*4 L L L H x REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Read Read with autoprecharge 15 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Current state CS RAS CAS WE Address Command Operation Write H x x x x DESL Continue burst to end L H H H x NOP Continue burst to end L H H L x BST Burst stop on full page L H L H BA, CA, A10 READ/READ A Term burst and New read L H L L BA, CA, A10 WRIT/WRIT A Term burst and New write L L H H BA, RA ACTV Other bank active ILLEGAL on same bank*3 L L H L BA, A10 PRE, PALL Term burst write and Precharge*2 L L L H x REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H x x x x DESL Continue burst to end and precharge L H H H x NOP Continue burst to end and precharge L H H L x BST ILLEGAL L H L H BA, CA, A10 READ/READ A ILLEGAL*4 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*4 L L H H BA, RA ACTV Other bank active ILLEGAL on same bank*3 L L H L BA, A10 PRE, PALL ILLEGAL*4 L L L H x REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H x x x x DESL Enter IDLE after t RC L H H H x NOP Enter IDLE after t RC L H H L x BST Enter IDLE after t RC L H L H BA, CA, A10 READ/READ A ILLEGAL*5 L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*5 L L H H BA, RA ACTV ILLEGAL*5 L L H L BA, A10 PRE, PALL ILLEGAL*5 L L L H x REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL Write with autoprecharge Refresh (autorefresh) Notes: 1. 2. 3. 4. 5. 6. 16 H: VIH. L: V IL. x: VIH or VIL. The other combinations are inhibit. An interval of t DPL is required between the final valid data input and the precharge command. If tRRD is not satisfied, this operation is illegal. Illegal for same bank, except for another bank. Illegal for all banks. NOP for same bank, except for another bank. HM5264165F/HM5264805F/HM5264405F-75/A60/B60 From PRECHARGE state, command operation To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM enters the IDLE state after tRP has elapsed from the completion of precharge. From IDLE state, command operation To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The SDRAM enters refresh mode (auto-refresh or self-refresh). To [MRS]: The SDRAM enters the mode register set cycle. From ROW ACTIVE state, command operation To [DESL], [NOP] or [BST]: These commands result in no operation. To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands set the SDRAM to precharge mode. (However, an interval of tRAS is required.) From READ state, command operation To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle. To [ACTV]: This command makes other banks bank active. (However, an interval of t RRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the SDRAM enters precharge mode. 17 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 From READ with AUTO-PRECHARGE state, command operation To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the SDRAM then enters precharge mode. To [ACTV]: This command makes other banks bank active. (However, an interval of t RRD is required.) Attempting to make the currently active bank active results in an illegal command. From WRITE state, command operation To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the SDRAM then enters precharge mode. From WRITE with AUTO-PRECHARGE state, command operation To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the synchronous DRAM enters precharge mode. To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. From REFRESH state, command operation To [DESL], [NOP], [BST]: After an auto-refresh cycle (after t RC), the SDRAM automatically enters the IDLE state. 18 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Simplified State Diagram SELF REFRESH SR ENTRY SR EXIT MRS MODE REGISTER SET REFRESH IDLE *1 AUTO REFRESH CKE CKE_ IDLE POWER DOWN ACTIVE ACTIVE CLOCK SUSPEND CKE_ CKE ROW ACTIVE BST (on full page) BST (on full page) WRITE Write WRITE SUSPEND CKE_ WRITE READ WRITE WITH AP READ WRITE CKE READ WITH AP WRITE WITH AP WRITEA CKE_ READ CKE CKE POWER ON READ SUSPEND READ WITH AP CKE_ READA CKE PRECHARGE POWER APPLIED WRITE WITH AP Read PRECHARGE CKE_ WRITEA SUSPEND READ WITH AP READA SUSPEND PRECHARGE PRECHARGE PRECHARGE Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. 19 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Mode Register Configuration The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A13, A12, A11, A10, A9, A8: (OPCODE): The SDRAM has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. Burst read and burst write: Burst write is performed for the specified burst length starting from the column address specified in the write cycle. Burst read and single write: Data is only written to the column address specified during the write cycle, regardless of the burst length. A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set. A6, A5, A4: (LMODE): These pins specify the CAS latency. A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected. A2, A1, A0: (BL): These pins specify the burst length. A13 A12 A11 A10 A9 A8 OPCODE A7 A6 0 LMODE A6 A5 A4 CAS latency 0 A13 A12 A11 A10 0 20 0 0 0 0 A5 0 R A4 A3 A2 BT A1 A0 BL A3 Burst type 0 Sequential A2 A1 A0 Burst length BT=0 BT=1 0 0 1 R 0 0 0 1 0 1 0 2 0 0 1 2 2 0 1 1 3 0 1 0 4 4 1 X X R 0 1 1 8 8 1 0 0 R R Write mode 1 0 1 R R 1 1 0 R R 1 1 1 F.P. R A9 A8 0 0 X X X X 0 1 X X X X 1 0 X X X X 1 1 1 Burst read and burst write R Burst read and single write R Interleave F.P. = Full Page R is Reserved (inhibit) X: 0 or 1 1 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Burst Sequence Burst length = 2 Burst length = 4 Starting Ad. Addressing(decimal) A0 Sequential Interleave Starting Ad. Addressing(decimal) A1 A0 Sequential Interleave 0 0, 1, 0, 1, 0 0 0, 1, 2, 3, 0, 1, 2, 3, 1 1, 0, 1, 0, 0 1 1, 2, 3, 0, 1, 0, 3, 2, 1 0 2, 3, 0, 1, 2, 3, 0, 1, 1 1 3, 0, 1, 2, 3, 2, 1, 0, Burst length = 8 Addressing(decimal) Starting Ad. A2 A1 A0 Sequential Interleave 0 0 0 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0 0 1 1, 2, 3, 4, 5, 6, 7, 0, 1, 0, 3, 2, 5, 4, 7, 6, 0 1 0 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 6, 7, 4, 5, 0 1 1 3, 4, 5, 6, 7, 0, 1, 2, 3, 2, 1, 0, 7, 6, 5, 4, 1 0 0 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 1 0 1 5, 6, 7, 0, 1, 2, 3, 4, 5, 4, 7, 6, 1, 0, 3, 2, 1 1 0 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 4, 5, 2, 3, 0, 1, 1 1 1 7, 0, 1, 2, 3, 4, 5, 6, 7, 6, 5, 4, 3, 2, 1, 0, 21 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Operation of the SDRAM Read/Write Operations Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to the status of the A12/A13 pin, and the row address (AX0 to AX11) is activated by the A0 to A11 pins at the bank active command cycle. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CAS Latency - 1) cycle after read command set. HM5264165F, HM5264805F series, HM5264405F can perform a burst read operation. The burst length can be set to 1, 2, 4, 8 or full-page (256; HM5264165F, 512; HM5264805F, 1024; HM5264405F). The start address for a burst read is specified by the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13) at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the CAS Latency. The CAS Latency can be set to 2 or 3. When the burst length is 1, 2, 4, 8, the Dout buffer automatically becomes High-Z at the next clock after the successive burst-length data has been output. The CAS latency and burst length must be specified at the mode register. CAS Latency CLK t RCD Command Address Dout ACTV Row CL = 2 CL = 3 READ Column out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 CL = CAS latency Burst Length = 4 22 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Burst Length CLK t RCD Command ACTV READ Address Row Column out 0 BL = 1 out 0 out 1 BL = 2 Dout out 0 out 1 out 2 out 3 BL = 4 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 BL = 8 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8 out 0-1 BL = full page out 0 out 1 BL : Burst Length CAS Latency = 2 Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9, A8) of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13) at the write command set cycle. CLK t RCD Command ACTV WRIT Address Row Column BL = 1 in 0 in 0 in 1 in 0 in 1 in 2 in 3 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 BL = 2 Din BL = 4 BL = 8 BL = full page in 8 in 0-1 in 0 in 1 CAS Latency = 2, 3 23 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is only written to the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13) specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0 clock). CLK t RCD Command WRIT ACTV Row Address Column Din in 0 Auto Precharge Read with auto-precharge: In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by l APR is required before execution of the next command. CAS latency Precharge start cycle 3 2 cycle before the final data is output 2 1 cycle before the final data is output Burst Read (Burst Length = 4) CLK CL=2 Command ACTV READ A ACTV lRAS DQ (input) out0 out1 out2 out3 lAPR CL=3 Command ACTV READ A ACTV lRAS DQ (input) out0 out1 out2 out3 lAPR Note: Internal auto-precharge starts at the timing indicated by " ". And an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " 24 ". HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write with auto-precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval of lAPW is required between the final valid data input and input of next command. Burst Write (Burst Length = 4) CLK Command ACTV ACTV WRIT A IRAS DQ (input) in0 in1 in2 in3 lAPW Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ". Single Write CLK Command ACTV ACTV WRIT A IRAS DQ (input) in lAPW Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ". 25 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Full-page Burst Stop Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. The timing from command input to the last data changes depending on the CAS latency setting. In addition, the BST command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8. CAS latency BST to valid data BST to high impedance 2 1 2 3 2 3 CAS Latency = 2, Burst Length = full page CLK BST Command DQ (output) out out out out out out l BSH = 2 clocks l BSR = 1 clock CAS Latency = 3, Burst Length = full page CLK BST Command DQ (output) out out out out out out l BSR = 2 clocks 26 out l BSH = 3 clocks HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. No data is written in the same clock as the BST command, and in subsequent clocks. In addition, the BST command is only valid during full-page burst mode, and is illegal with burst lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge command. Burst Length = full page CLK BST Command DQ (input) in PRE/PALL in t DPL I BSW = 0 clock 27 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Command Intervals Read command to Read command interval: 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (same ROW address in same bank) CLK Command Address ACTV Row READ READ Column A Column B BS Dout out A0 out B0 out B1 out B2 out B3 Bank0 Active Column =A Column =B Column =A Column =B Dout Read Read Dout CAS Latency = 3 Burst Length = 4 Bank 0 2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. 3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (different bank) CLK Command ACTV ACTV READ READ Address Row 0 Row 1 Column A Column B BS Dout out A0 out B0 out B1 out B2 out B3 Bank0 Active 28 Bank3 Bank0 Bank3 Active Read Read Bank0 Bank3 Dout Dout CAS Latency = 3 Burst Length = 4 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write command to Write command interval: 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes, the second write command has priority. WRITE to WRITE Command Interval (same ROW address in same bank) CLK Command Address ACTV Row WRIT WRIT Column A Column B BS Din in A0 Bank0 Active in B0 in B1 in B2 in B3 Burst Write Mode Burst Length = 4 Bank 0 Column =A Column =B Write Write 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. 3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. In the case of burst write, the second write command has priority. WRITE to WRITE Command Interval (different bank) CLK Command ACTV Address Row 0 ACTV WRIT Row 1 WRIT Column A Column B BS Din in A0 Bank0 Active in B0 Bank3 Bank0 Bank3 Active Write Write in B1 in B2 in B3 Burst Write Mode Burst Length = 4 29 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read command to Write command interval: 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. READ to WRITE Command Interval (1) CLK Command READ WRIT DQM, CL=2 DQMU /DQML CL=3 in B0 Din in B1 in B2 in B3 Burst Length = 4 Burst write High-Z Dout READ to WRITE Command Interval (2) CLK Command DQM, DQMU/DQML CL=2 Dout CL=3 READ WRIT 2 clock High-Z High-Z Din 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command. 3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. 30 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write command to Read command interval: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed. WRITE to READ Command Interval (1) CLK Command WRIT READ DQM, DQMU/DQML Din in A0 Dout out B1 out B0 Column = A Write Column = B Read out B2 out B3 Burst Write Mode CAS Latency = 2 Burst Length = 4 Bank 0 CAS Latency Column = B Dout WRITE to READ Command Interval (2) CLK Command WRIT READ DQM, DQMU/DQML Din in A0 in A1 Dout out B0 Column = A Write out B1 CAS Latency Column = B Read Column = B Dout out B2 out B3 Burst Write Mode CAS Latency = 2 Burst Length = 4 Bank 0 2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command. 3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address). 31 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid. The internal auto-precharge of one bank starts at the next clock of the second command. Read with Auto Precharge to Read Command Interval (Different bank) CLK Command READ A READ BS Dout out A0 bank0 Read A out A1 out B0 bank3 Read out B1 CAS Latency = 3 Burst Length = 4 Note: Internal auto-precharge starts at the timing indicated by " ". 2. Same bank: The consecutive read command (the same bank) is illegal. Write with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank starts at the next clock of the second command . Write with Auto Precharge to Write Command Interval (Different bank) CLK Command WRIT A WRIT BS Din in A0 bank0 Write A in A1 in B0 in B1 in B2 bank3 Write Note: Internal auto-precharge starts at the timing indicated by " Burst Length = 4 ". 2. Same bank: The consecutive write command (the same bank) is illegal. 32 in B3 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. The internal auto-precharge of one bank starts at the next clock of the second command. Read with Auto Precharge to Write Command Interval (Different bank) CLK Command READ A WRIT BS DQM, DQMU/DQML CL = 2 CL = 3 Din in B0 Dout in B1 in B2 in B3 High-Z bank0 Read A Burst Length = 4 bank3 Write Note: Internal auto-precharge starts at the timing indicated by " ". 2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command. 33 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. However, in case of a burst write, data will continue to be written until one clock before the read command is executed. The internal auto-precharge of one bank starts at the next clock of the second command. Write with Auto Precharge to Read Command Interval (Different bank) CLK Command WRIT A READ BS DQM, DQMU/DQML Din in A0 Dout out B0 bank0 Write A out B1 out B3 CAS Latency = 3 Burst Length = 4 bank3 Read Note: Internal auto-precharge starts at the timing indicated by " out B2 ". Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. . It is necessary to separate the two commands with a bank active command. 34 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the clocks defined by lHZP , there is a case of interruption toburst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (same bank): To output all data CAS Latency = 2, Burst Length = 4 CLK Command READ PRE/PALL Dout out A0 out A1 CL=2 out A2 out A3 l EP = -1 cycle CAS Latency = 3, Burst Length = 4 CLK Command READ PRE/PALL Dout out A0 CL=3 out A1 out A2 out A3 l EP = -2 cycle 35 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 READ to PRECHARGE Command Interval (same bank): To stop output data CAS Latency = 2, Burst Length = 1, 2, 4, 8, full page burst CLK Command READ PRE/PALL High-Z Dout out A0 l HZP =2 CAS Latency = 3, Burst Length = 1, 2, 4, 8, full page burst CLK Command READ PRE/PALL High-Z Dout out A0 l HZP =3 36 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of DQM, DQMU/DQML for assurance of the clock defined by t DPL. WRITE to PRECHARGE Command Interval (same bank) Burst Length = 4 (To stop write operation) CLK Command WRIT PRE/PALL DQM, DQMU/DQML Din tDPL CLK Command PRE/PALL WRIT DQM, DQMU/DQML Din in A0 in A1 tDPL Burst Length = 4 (To write all data) CLK Command PRE/PALL WRIT DQM, DQMU/DQML Din in A0 in A1 in A2 in A3 tDPL 37 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Bank active command interval: 1. Same bank: The interval between the two bank-active commands must be no less than tRC. 2. In the case of different bank-active commands: The interval between the two bank-active commands must be no less than tRRD. Bank Active to Bank Active for Same Bank CLK Command ACTV ACTV Address ROW ROW BS t RC Bank 0 Active Bank 0 Active Bank Active to Bank Active for Different Bank CLK Command Address ACTV ACTV ROW:0 ROW:1 BS t RRD Bank 0 Active 38 Bank 3 Active HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than lRSA . CLK Command Address MRS ACTV CODE BS & ROW I RSA Mode Register Set Bank Active 39 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DQM Control The DQM mask the DQ data. The DQMU and DQML mask the upper and lower bytes of the DQ data, respectively. The timing of DQMU/DQML is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQM, DQMU/DQML. By setting DQM, DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM, DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQM, DQMU/DQML during reading is 2 clocks. Writing: Input data can be masked by DQM, DQMU/DQML. By setting DQM, DQMU/DQML to Low, data can be written. In addition, when DQM, DQMU/DQML is set to High, the corresponding data is not written, and the previous data is held. The latency of DQM, DQMU/DQML during writing is 0 clock. Reading CLK DQM, DQMU/DQML DQ (output) High-Z out 0 out 1 out 3 lDOD = 2 Latency Writing , CLK DQM, DQMU/DQML DQ (input) in 0 in 3 in 1 l DID = 0 Latency 40 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Refresh Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the autorefresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4096 cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer becomes HighZ after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A selfrefresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within 64 ms period on the condition (1) and (2) below. (1) Enter self-refresh mode within 15.6 s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. (2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 s after exiting from self-refresh mode. Others Power-down mode: The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not performed. Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the SDRAM enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details, refer to the "CKE Truth Table". Power-up sequence: The SDRAM should be gone on the following sequence with power up. The CLK, CKE, CS, DQM, DQMU/DQML and DQ pins keep low till power stabilizes. The CLK pin is stabilized within 100 s after power stabilizes before the following initialization sequence. The CKE and DQM, DQMU/DQML is driven to high between power stabilizes and the initialization sequence. This SDRAM has VCC clamp diodes for CLK, CKE, CS, DQM, DQMU/DQML and DQ pins. If these pins go high before power up, the large current flows from these pins to VCC through the diodes. Initialization sequence: When 200 s or more has past after the above power-up sequence, all banks must be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by keeping DQM, DQMU/DQML and CKE to High, the output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed with a number of device. 41 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Initialization sequence Power up sequence 100 s VCC, VCCQ 200 s 0V CKE, DQM, DQMU/DQML Low CLK Low CS, DQ Low Power stabilize Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to V SS VT -0.5 to VCC + 0.5 ( 4.6 (max)) V 1 Supply voltage relative to VSS VCC -0.5 to +4.6 V 1 Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +125 C Note: 1. Respect to V SS . DC Operating Conditions (Ta = 0 to +70C) Parameter Symbol Min Max Unit Notes Supply voltage VCC, VCCQ 3.0 3.6 V 1, 2 VSS , VSS Q 0 0 V 3 Input high voltage VIH 2.0 VCC + 0.3 V 1, 4 Input low voltage VIL -0.3 0.8 V 1, 5 Notes: 1. 2. 3. 4. 5. 42 All voltage referred to VSS . The supply voltage with all VCC and V CCQ pins must be on the same level. The supply voltage with all VSS and VSS Q pins must be on the same level. VIH (max) = VCC + 2.0 V for pulse width 3 ns at VCC. VIL (min) = VSS - 2.0 V for pulse width 3 ns at VSS . HM5264165F/HM5264805F/HM5264405F-75/A60/B60 VIL/VIH Clamp This SDRAM has VIL and V IH clamp for CLK, CKE, CS, DQM and D/Q pins. Minimum VIL Clamp Current VIL (V) I (mA) -2 -32 -1.8 -25 -1.6 -19 -1.4 -13 -1.2 -8 -1 -4 -0.9 -2 -0.8 -0.6 -0.6 0 -0.4 0 -0.2 0 0 0 0 -5 -2 -1.5 -1 -0.5 0 I (mA) -10 -15 -20 -25 -30 -35 VIL (V) 43 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Minimum VIH Clamp Current VIH (V) I (mA) VCC + 2 10 VCC + 1.8 8 VCC + 1.6 5.5 VCC + 1.4 3.5 VCC + 1.2 1.5 VCC + 1 0.3 VCC + 0.8 0 VCC + 0.6 0 VCC + 0.4 0 VCC + 0.2 0 VCC + 0 0 10 I (mA) 8 6 4 2 0 VCC + 0 VCC + 0.5 VCC + 1 VIH (V) 44 VCC + 1.5 VCC + 2 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 IOL/IOH Characteristics Output Low Current (IOL) I OL I OL Vout (V) Min (mA) Max (mA) 0 0 0 0.4 27 71 0.65 41 108 0.85 51 134 1 58 151 1.4 70 188 1.5 72 194 1.65 75 203 1.8 77 209 1.95 77 212 3 80 220 3.45 81 223 250 IOL (mA) 200 150 min max 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 Vout (V) 45 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Output High Current (I OH ) (Ta = 0 to +70C, VCC, VCCQ = 3.0 V to 3.45 V, VSS, VSSQ = 0 V) I OH I OH Vout (V) Min (mA) Max (mA) 3.45 -- -3 3.3 -- -28 3 0 -75 2.6 -21 -130 2.4 -34 -154 2 -59 -197 1.8 -67 -227 1.65 -73 -248 1.5 -78 -270 1.4 -81 -285 1 -89 -345 0 -93 -503 0 0 0.5 1 1.5 2 2.5 3 3.5 IOH (mA) -100 -200 min max -300 -400 -500 -600 Vout (V) 46 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DC Characteristics (Ta = 0 to +70C, VCC, VCC Q = 3.3 V 0.3 V, VS S, V SSQ = 0 V) (HM5264165F) HM5264165F -75 -A60 -B60 Parameter Symbol Min Max Min Max Min Max Unit Test conditions Operating current (CAS latency = 2) I CC1 -- 65 -- 65 -- 65 mA (CAS latency = 3) I CC1 -- 65 -- 65 -- 65 mA Standby current in power down I CC2P -- 1.5 -- 1.5 -- 1.5 Standby current in power down I CC2PS (input signal stable) -- 1 -- 1 -- Standby current in non power down I CC2N -- 10 -- 10 Standby current in non power down (input signal stable) I CC2NS -- 5 -- Active standby current in power I CC3P down -- 4 Active standby current in power I CC3PS down (input signal stable) -- Active standby current in non power down I CC3N Active standby current in non power down (input signal stable) Notes Burst length = 1 t RC = min 1, 2, 3 mA CKE = VIL, t CK = 12 ns 6 1 mA CKE = VIL, t CK = 7 -- 10 mA CKE, CS = VIH, t CK = 12 ns 4 5 -- 5 mA CKE = VIH, t CK = 9 -- 4 -- 4 mA CKE = VIL, t CK = 12 ns 1, 2, 6 3 -- 3 -- 3 mA CKE = VIL, t CK = 2, 7 -- 18 -- 18 -- 18 mA CKE, CS = VIH, t CK = 12 ns 1, 2, 4 I CC3NS -- 12 -- 12 -- 12 mA CKE = VIH, t CK = 2, 9 I CC4 -- 65 -- 65 -- 65 mA t CK = min, BL = 4 1, 2, 5 I CC4 -- 80 -- 65 -- 65 mA Refresh current I CC5 -- 110 -- 110 -- 110 mA t RC = min 3 Self refresh current I CC6 -- 1 -- 1 -- 1 mA VIH VCC - 0.2 V VIL 0.2 V 8 Self refresh current (L-version) I CC6 -- 0.4 -- 0.4 -- 0.4 mA Input leakage current I LI -1 1 -1 1 -1 1 A 0 Vin VCC Output leakage current I LO -1.5 1.5 -1.5 1.5 -1.5 1.5 A 0 Vout VCC DQ = disable Output high voltage VOH 2.4 -- 2.4 -- 2.4 -- V I OH = -4 mA Output low voltage VOL -- 0.4 -- 0.4 -- 0.4 V I OL = 4 mA Burst operating current (CAS latency = 2) (CAS latency = 3) 47 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DC Characteristics (Ta = 0 to +70C, VCC, VCC Q = 3.3 V 0.3 V, VS S, V SSQ = 0 V) (HM5264805F) HM5264805F -75 -A60 -B60 Parameter Symbol Min Max Min Max Min Max Unit Test conditions Operating current (CAS latency = 2) I CC1 -- 60 -- 60 -- 60 mA (CAS latency = 3) I CC1 -- 60 -- 60 -- 60 mA Standby current in power down I CC2P -- 1.5 -- 1.5 -- 1.5 Standby current in power down I CC2PS (input signal stable) -- 1 -- 1 -- Standby current in non power down I CC2N -- 10 -- 10 Standby current in non power down (input signal stable) I CC2NS -- 5 -- Active standby current in power I CC3P down -- 4 Active standby current in power I CC3PS down (input signal stable) -- Active standby current in non power down I CC3N Active standby current in non power down (input signal stable) Notes Burst length = 1 t RC = min 1, 2, 3 mA CKE = VIL, tCK = 12 ns 6 1 mA CKE = VIL, t CK = 7 -- 10 mA CKE, CS = VIH, t CK = 12 ns 4 5 -- 5 mA CKE = VIH, t CK = 9 -- 4 -- 4 mA CKE = VIL, tCK = 12 ns 1, 2, 6 3 -- 3 -- 3 mA CKE = VIL, t CK = 2, 7 -- 18 -- 18 -- 18 mA CKE, CS = VIH, t CK = 12 ns 1, 2, 4 I CC3NS -- 12 -- 12 -- 12 mA CKE = VIH, t CK = 2, 9 I CC4 -- 60 -- 60 -- 60 mA t CK = min, BL = 4 1, 2, 5 I CC4 -- 75 -- 60 -- 60 mA Refresh current I CC5 -- 110 -- 110 -- 110 mA t RC = min 3 Self refresh current I CC6 -- 1 -- 1 -- 1 mA VIH VCC - 0.2 V VIL 0.2 V 8 Self refresh current (L-version) I CC6 -- 0.4 -- 0.4 -- 0.4 mA Input leakage current I LI -1 1 -1 1 -1 1 A 0 Vin VCC Output leakage current I LO -1.5 1.5 -1.5 1.5 -1.5 1.5 A 0 Vout VCC DQ = disable Output high voltage VOH 2.4 -- 2.4 -- 2.4 -- V I OH = -4 mA Output low voltage VOL -- 0.4 -- 0.4 -- 0.4 V I OL = 4 mA Burst operating current (CAS latency = 2) (CAS latency = 3) 48 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DC Characteristics (Ta = 0 to +70C, VCC, VCC Q = 3.3 V 0.3 V, VS S, V SSQ = 0 V) (HM5264405F) HM5264405F -75 -A60 -B60 Parameter Symbol Min Max Min Max Min Max Unit Test conditions Operating current (CAS latency = 2) I CC1 -- 60 -- 60 -- 60 mA (CAS latency = 3) I CC1 -- 60 -- 60 -- 60 mA Standby current in power down I CC2P -- 1.5 -- 1.5 -- 1.5 Standby current in power down I CC2PS (input signal stable) -- 1 -- 1 -- Standby current in non power down I CC2N -- 10 -- 10 Standby current in non power down (input signal stable) I CC2NS -- 5 -- Active standby current in power I CC3P down -- 4 Active standby current in power I CC3PS down (input signal stable) -- Active standby current in non power down I CC3N Active standby current in non power down (input signal stable) Notes Burst length = 1 t RC = min 1, 2, 3 mA CKE = VIL, tCK = 12 ns 6 1 mA CKE = VIL, t CK = 7 -- 10 mA CKE, CS = VIH, t CK = 12 ns 4 5 -- 5 mA CKE = VIH, t CK = 9 -- 4 -- 4 mA CKE = VIL, tCK = 12 ns 1, 2, 6 3 -- 3 -- 3 mA CKE = VIL, t CK = 2, 7 -- 18 -- 18 -- 18 mA CKE, CS = VIH, t CK = 12 ns 1, 2, 4 I CC3NS -- 12 -- 12 -- 12 mA CKE = VIH, t CK = 2, 9 I CC4 -- 55 -- 55 -- 55 mA t CK = min, BL = 4 1, 2, 5 I CC4 -- 70 -- 55 -- 55 mA Refresh current I CC5 -- 110 -- 110 -- 110 mA t RC = min 3 Self refresh current I CC6 -- 1 -- 1 -- 1 mA VIH VCC - 0.2 V VIL 0.2 V 8 Self refresh current (L-version) I CC6 -- 0.4 -- 0.4 -- 0.4 mA Input leakage current I LI -1 1 -1 1 -1 1 A 0 Vin VCC Output leakage current I LO -1.5 1.5 -1.5 1.5 -1.5 1.5 A 0 Vout VCC DQ = disable Output high voltage VOH 2.4 -- 2.4 -- 2.4 -- V I OH = -4 mA Output low voltage VOL -- 0.4 -- 0.4 -- 0.4 V I OL = 4 mA Burst operating current (CAS latency = 2) (CAS latency = 3) 49 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CLK operating current. 7. After power down mode, no CLK operating current. 8. After self refresh mode set, self refresh current. 9. Input signals are V IH or VIL fixed. Capacitance (Ta = 25C, VCC, VCCQ = 3.3 V 0.3 V) Parameter Symbol Min Max Unit Notes Input capacitance (CLK) CI1 2.5 3.5 pF 1, 2, 4 Input capacitance (Input) CI2 2.5 3.8 pF 1, 2, 4 Output capacitance (DQ) CO 4 6.5 pF 1, 2, 3, 4 Notes: 1. 2. 3. 4. 50 Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQM, DQMU/DQML = VIH to disable Dout. This parameter is sampled and not 100% tested. HM5264165F/HM5264805F/HM5264405F-75/A60/B60 AC Characteristics (Ta = 0 to +70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) HM5264165F/HM5264805F/HM5264405F -75 -A60 -B60 Parameter HITACHI PC/100 Symbol Symbol Min Max Min Max Min Max Unit Notes System clock cycle time (CAS latency = 2) t CK Tclk 10 -- 10 -- 15 -- ns 1 (CAS latency = 3) t CK Tclk 7.5 -- 10 -- 10 -- ns CLK high pulse width t CKH Tch 2.5 -- 3 -- 3 -- ns 1 CLK low pulse width t CKL Tcl 2.5 -- 3 -- 3 -- ns 1 Access time from CLK (CAS latency = 2) t AC Tac -- 6 -- 6 -- 8 ns 1, 2 (CAS latency = 3) t AC Tac -- 5.4 -- 6 -- 6 ns t OH Toh 2.7 -- 3 -- 3 -- ns 1, 2 CLK to Data-out low impedance t LZ 2 -- 2 -- 2 -- ns 1, 2, 3 CLK to Data-out high impedance (CAS latency = 2, 3) t HZ -- 5.4 -- 6 -- 6 ns 1, 4 Input setup time t AS , t CS, t DS, t CES Tsi 1.5 -- 2 -- 2 -- ns 1, 5, 6 CKE setup time for power down t CESP exit Tpde 1.5 -- 2 -- 2 -- ns 1 Input hold time t AH, t CH, t DH, t CEH Thi 0.8 -- 1 -- 1 -- ns 1, 5 Ref/Active to Ref/Active command period t RC Trc 67.5 -- 70 -- 70 -- ns 1 Active to Precharge command period t RAS Tras 45 120000 50 120000 50 120000 ns 1 Active command to column command (same bank) t RCD Trcd 20 -- 20 -- 20 -- ns 1 Precharge to active command period t RP Trp 20 -- 20 -- 20 -- ns 1 Write recovery or data-in to precharge lead time t DPL Tdpl 10 -- 10 -- 10 -- ns 1 Active (a) to Active (b) command period t RRD Trrd 15 -- 20 -- 20 -- ns 1 Transition time (rise and fall) tT 1 5 1 5 1 5 ns Refresh period t REF -- 64 -- 64 -- 64 ms Data-out hold time 51 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Notes: 1. 2. 3. 4. 5. 6. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is CL = 50 pF. t LZ (min) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES define CKE setup time to CLK rising edge except power down exit command. t AS /tAH: Address, tCS/tCH: CS, RAS, CAS, WE, DQM, DQMU/DQML t DS/tDH: Data-in, tCES/tCEH: CKE Test Conditions * Input and output timing reference levels: 1.5 V * Input waveform and output load: See following figures 2.4 V input 0.4 V I/O 2.0 V 0.8 V CL t 52 T tT HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Relationship Between Frequency and Minimum Latency HM5264165F/ HM5264805F/ HM5264405F Parameter -75 -A60/B60 Frequency (MHz) 133 100 7.5 10 Notes tCK (ns) HITACHI Symbol PC/100 Symbol Active command to column command (same bank) lRCD 3 2 1 Active command to active command (same bank) lRC 9 7 = [lRAS+ lRP] 1 Active command to precharge command (same bank) lRAS 6 5 1 Precharge command to active command (same bank) lRP 3 2 1 Write recovery or data-in to precharge command (same bank) lDPL 2 1 1 Active command to active command (different bank) lRRD 2 2 1 Self refresh exit time lSREX Tsrx 1 1 2 Last data in to active command (Auto precharge, same bank) lAPW Tdal 5 3 = [lDPL + lRP] Self refresh exit to command input lSEC 9 7 = [lRC] 3 Precharge command to high impedance (CAS latency = 2) lHZP Troh 2 2 lHZP Troh 3 3 lAPR 1 1 lEP -1 -1 lEP -2 -2 (CAS latency = 3) Last data out to active command (Auto precharge, same bank) Last data out to precharge (early precharge) (CAS latency = 2) (CAS latency = 3) Tdpl Column command to column command lCCD Tccd 1 1 Write command to data in latency lWCD Tdwd 0 0 DQM to data in lDID Tdqm 0 0 DQM to data out lDOD Tdqz 2 2 CKE to CLK disable lCLE Tcke 1 1 Register set to active command lRSA Tmrd 1 1 53 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 HM5264165F/ HM5264805F/ HM5264405F Parameter -75 -A60/B60 Frequency (MHz) 133 100 7.5 10 tCK (ns) HITACHI Symbol CS to command disable lCDD 0 0 Power down exit to command input lPEC 1 1 Burst stop to output valid data hold (CAS latency = 2) lBSR 1 1 lBSR 2 2 lBSH 2 2 lBSH 3 3 lBSW 0 0 (CAS latency = 3) Burst stop to output high impedance (CAS latency = 2) (CAS latency = 3) Burst stop to write data ignore PC/100 Symbol Notes: 1. lRCD to l RRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP]. 54 Notes HM5264165F/HM5264805F/HM5264405F-75/A60/B60 # , #*2")&!(05$%+,3:;189<-4.67=>'/ 34:;/7?'6>=$,-CKL, Timing Waveforms Read Cycle t CK t CKH t CKL CLK t RC VIH CKE t RP , ,, , , ,,,, , t RAS t RCD t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH CS t CS t CH t CS t CH RAS t CS t CH t CS t CH CAS t CS t CH t CS t CH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t CS t CH t CS t CH WE t AS t AH BS t AS t AH t AS t AH A10 t AS t AH t AS t AH t AS t AH Address t CH t CS DQM, DQMU/DQML DQ (input) t AC DQ (output) t AC t AC t HZ t AC Bank 0 Active Bank 0 Read t LZ t OH t OH t OH Bank 0 Precharge t OH CAS latency = 2 Burst length = 4 Bank 0 access = VIH or VIL 55 " ! 4 , + $ # % ? : 2 > = 7 6 / 3 , $ < ; 5 4 . & % ' , 7?!'./,(!)0"*18 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write Cycle t CK t CKH t CKL CLK t RC VIH CKE t RAS t RCD t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH ,,, , t CS t CH t RP CS t CS t CH t CS t CH RAS t CS t CH t CS t CH CAS t CS t CH t CS t CH t CS t CH t AS t AH t AS t AH t AS t AH t AS t AH t CS t CH WE t AS t AH t AS t AH BS t AS t AH t AS t AH A10 t AS t AH t AS t AH t AS t AH Address t CS t CH DQM, DQMU/DQML t DS t DH tDS t DH t DS t DH t DS t DH DQ (input) t DPL DQ (output) Bank 0 Active 56 Bank 0 Write Bank 0 Precharge CAS latency = 2 Burst length = 4 Bank 0 access = VIH or VIL > G P O , , %&!IJH-6$%'()!1:@9B08/A74=>EF$DLMCNH@I%&/.76?'(098A- ,,,, ,,,,, ,,, ,, HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Mode Register Set Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 b+3 b' b'+1 b'+2 b'+3 18 CLK VIH CKE CS RAS CAS WE BS Address code R: b valid C: b' C: b DQM, DQMU/DQML DQ (output) b High-Z DQ (input) l RSA l RP Precharge If needed l RCD Mode Bank 3 register Active Set Output mask l RCD = 3 CAS latency = 3 Burst length = 4 = VIH or VIL Bank 3 Read Read Cycle/Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE VIH Read cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL CS RAS CAS WE BS Address DQM, DQMU/DQML R:a C:a R:b DQ (output) DQ (input) CKE C:b a C:b' a+1 a+2 a+3 b C:b" b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 High-Z Bank 0 Active Bank 0 Read Bank 3 Active Bank 3 Bank 0 Read Precharge Bank 3 Read Bank 3 Read Bank 3 Precharge VIH Write cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL CS RAS CAS WE BS Address DQM, DQMU/DQML DQ (output) R:a C:a R:b C:b C:b' C:b" High-Z DQ (input) a Bank 0 Active Bank 0 Write a+1 a+2 a+3 Bank 3 Active b Bank 3 Write b+1 b+2 b+3 b' Bank 0 Precharge Bank 3 Write b'+1 b" Bank 3 Write b"+1 b"+2 b"+3 Bank 3 Precharge 57 #+45=*3>,"GOPOEFMN,5>AIJH)&'./80(19B$@7?, :;CDKLEMNAJHI@'(/089BCK12:$ HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read/Single Write Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 , 0 CLK CKE VIH CS RAS CAS WE BS R:a Address DQM, DQMU/DQML DQ (input) C:a R:b a DQ (output) a Bank 0 Active CKE C:a' C:a Bank 0 Read Bank 3 Active C:a R:b a+1 a+2 a+3 a Bank 0 Bank 0 Write Read a+1 a+2 a+3 Bank 0 Precharge Bank 3 Precharge VIH CS RAS CAS WE BS Address DQM, DQMU/DQML DQ (input) R:a DQ (output) a Bank 0 Active Bank 0 Read Bank 3 Active a+1 C:a C:b C:c a b c a+3 Bank 0 Write Bank 0 Bank 0 Write Write Bank 0 Precharge Read/Single write RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL 58 G 5 > P " + 3 * ) ! F PGO>DMN-6?KL@HIMNC2:;D,&./7'0<E8%)?H,%67@.-$&/' HM5264165F/HM5264805F/HM5264405F-75/A60/B60 , , , Read/Burst Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE CS RAS CAS WE BS R:a Address DQM, DQMU/DQML DQ (input) C:a R:b a DQ (output) a Bank 0 Active CKE C:a' Bank 0 Read Bank 3 Active C:a R:b a+1 a+2 a+3 a+1 a+2 a+3 Clock suspend Bank 0 Write Bank 0 Precharge Bank 3 Precharge VIH CS RAS CAS WE BS Address DQM, DQMU/DQML DQ (input) R:a C:a a DQ (output) a Bank 0 Active Bank 0 Read Bank 3 Active a+1 a+1 a+2 a+3 a+3 Bank 0 Write Bank 0 Precharge Read/Burst write RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL 59 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 ;CLMVWE1:DNO'1:;DEMN()"+,5$6?@IRSH>4#-72<Q[GP\Z S]IJT^R\4=>GHQ Full Page Read/Write Cycle CLK CKE VIH Read cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = full page = VIH or VIL CS RAS CAS WE BS Address DQM, DQMU/DQML DQ (output) DQ (input) CKE R:a C:a R:b a a+1 a+2 a+3 High-Z Bank 0 Active Bank 0 Read Bank 3 Active Burst stop Bank 3 Precharge VIH Write cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = full page = VIH or VIL CS RAS CAS WE BS Address DQM, DQMU/DQML DQ (output) R:a R:b High-Z DQ (input) a Bank 0 Active 60 C:a Bank 0 Write a+1 a+2 Bank 3 Active a+3 a+4 a+5 a+6 Burst stop Bank 3 Precharge *23;:CD:BCKLL!"(16?@H.7IP$-F<=,45#4<=EF5DMN"+!)*2;:CL19'/078@I6?H%&$ , /78?@IH$6%&-.JKB9&'/ABJH?, HM5264165F/HM5264805F/HM5264405F-75/A60/B60 ,,, ,,, , , , , ,,,,,,, , Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a a+1 CLK CKE VIH CS RAS CAS WE BS Address DQM, DQMU/DQML C:a R:a A10=1 DQ (input) High-Z DQ (output) t RC t RP Auto Refresh Precharge If needed tRC Active Bank 0 Auto Refresh Read Bank 0 Refresh cycle and Read cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 = VIH or VIL Self Refresh Cycle CLK l SREX CKE Low CKE CS RAS CAS WE BS Address A10=1 DQM, DQMU/DQML DQ (input) High-Z DQ (output) tRP Precharge command If needed tRC tRC Self refresh entry command Self refresh exit ignore command or No operation Next clock enable Self refresh entry command Auto Next clock refresh enable Self refresh cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL 61 , # " PG()129:BK5=>LH?K<DEM;C2:B78@I%.6A'(/0&+34*"!,)=9N,& LM./78@ HM5264165F/HM5264805F/HM5264405F-75/A60/B60 ,,, , , , Clock Suspend Mode t CES 0 1 2 3 4 5 t CES t CEH 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE Read cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 = VIH or VIL CS RAS CAS WE BS Address DQM, DQMU/DQML DQ (output) R:a C:a R:b a C:b a+1 a+2 a+3 b b+1 b+2 b+3 High-Z DQ (input) Bank0 Active clock Active suspend start Active clock Bank0 suspend end Read Bank3 Active Read suspend start Read suspend end Bank3 Read Bank0 Precharge Earliest Bank3 Precharge CKE Write cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 = VIH or VIL CS RAS CAS WE BS Address DQM, DQMU/DQML DQ (output) C:a R:b R:a High-Z DQ (input) a Bank0 Active 62 C:b Active clock suspend start a+1 a+2 Active clock Bank0 Bank3 supend end Write Active Write suspend start a+3 b Write suspend end b+1 b+2 b+3 Bank3 Bank0 Write Precharge Earliest Bank3 Precharge HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Power Down Mode , , , , , ,,,,,, , , ,,, # ! + " P'(0)/78A9.?@HIBJ,45=>EFNOG/78?@HI9AJ'(0%&.6$6? CLK CKE Low CKE CS RAS CAS WE BS Address R: a A10=1 DQM, DQMU/DQML DQ (input) High-Z DQ (output) tRP Power down entry Precharge command If needed Power down mode exit Active Bank 0 Power down cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL , ,, ,,,, Initialization Sequence 0 1 2 3 4 5 6 7 8 9 10 48 49 50 51 52 53 54 55 CLK CKE VIH CS RAS CAS WE DQM, DQMU/DQML code valid Address Valid VIH High-Z DQ t RP All banks Precharge t RC Auto Refresh t RSA tRC Auto Refresh Mode register Set Bank active If needed 63 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Package Dimensions HM5264165FTT/FLTT HM5264805FTT/FLTT HM5264405FTT/FLTT Series (TTP-54D) Unit: mm 22.22 22.72 Max 28 10.16 54 1 0.80 *0.30 +0.10 -0.05 0.28 0.05 27 0.13 M 0.80 11.76 0.20 0.91 Max *Dimension including the plating thickness Base material dimension 64 0.50 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-54D -- -- 0.53 g 0.68 0.13 0.05 0.10 *0.145 0.05 0.125 0.04 1.20 Max 0 - 5 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Cautions 1. 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Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 65 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Revision Record Rev. Date Contents of Modification Drawn by 0.0 Jul. 17, 1998 Initial issue M. Takahashi J. Kitano 0.1 Dec. 28, 1998 Addition of HM5264165/HM5264805/ HM5264405FTT/FLTT-75 (133MHz) Unification with HM5264165/HM5264805/ HM5264405FTT/FLTT-B6 Change of part number to HM5264165/HM5264805/ HM5264405F-75/A60/B60 Change figure of mode register configuration DC Operating conditions Change of notes 4 to 5 DC Characteristics (Common) I CC2N max: --/20/-- mA to 16/16/16 mA I CC3P max: --/TBD/-- mA to 4/4/4 mA I CC3PS max: --/TBD/-- mA to 3/3/3 mA I CC3N max: --/30/-- mA to 20/20/20 mA I CC3NS max: --/20/-- mA to 15/15/15 mA I CC5 max: --/140/-- mA to 115/115/115 mA I CC6 max: --/TBD/-- mA to 0.4/0.4/0.4 mA DC Characteristics (HM5264165F) I CC1 max(CL = 2): --/100/-- mA to 85/75/70 mA I CC1 max(CL = 3): --/100/-- mA to 85/75/75 mA I CC4 max (CL = 2): --/120/-- mA to 90/90/70 mA I CC4 max (CL = 3): --/120/-- mA to 110/90/90 mA DC Characteristics (HM5264805F) I CC1 max(CL = 2): --/90/-- mA to 80/70/65 mA I CC1 max(CL = 3): --/90/-- mA to 80/70/70 mA I CC4 max (CL = 2): --/100/-- mA to 80/80/65 mA I CC4 max (CL = 3): --/100/-- mA to 100/80/80 mA DC Characteristics (HM5264405F) I CC1 max(CL = 2): --/90/-- mA to 80/70/65 mA I CC1 max(CL = 3): --/90/-- mA to 80/70/70 mA I CC4 max (CL = 2): --/90/-- mA to 70/70/60 mA I CC4 max (CL = 3): --/90/-- mA to 90/70/70 mA AC Characteristics t DPL min: --/15/-- ns to 10/10/10 ns Relationship between frequency and minimum latency lDPL : --/2 to 2/1 lHZP (CL = 2): --/-- to 2/2 lEP (CL = 2): --/-- to -1/-1 lBSR (CL = 2): --/-- to 1/1 lBSH (CL = 2): --/-- to 2/2 66 Approved by K. Nishimoto J. Kitano HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Revision Record (cont.) Rev. Date 1.0 Contents of Modification Drawn by Approved by Nov. 10, 1999 Ordering information Addition of notes 1 and 2 CKE Truth table Clock suspend mode entry CS: H to x Addition of description to clock suspend mode entry DC Characteristics (common) I CC2P max: 3/3/3 mA to 1.5/1.5/1.5 mA I CC2PS max: 2/2/2 mA to 1/1/1 mA I CC2N max: 16/16/16 mA to 10/10/10 mA I CC2NS max: 9/9/9 mA to 5/5/5 mA I CC3N max: 20/20/20 mA to 18/18/18 mA I CC3NS max: 15/15/15 mA to 12/12/12 mA I CC5 max:115/115/115 mA to 110/110/110 mA DC Characteristics (HM5264165F) I CC1 max (CL = 2): 85/75/70 mA to 65/65/65 mA I CC1 max (CL = 3): 85/75/75 mA to 65/65/65 mA I CC4 max (CL = 2): 90/90/70 mA to 65/65/65 mA I CC4 max (CL = 3): 110/90/90 mA to 80/65/65 mA DC Characteristics (HM5264805F) I CC1 max (CL = 2): 80/70/65 mA to 60/60/60 mA I CC1 max (CL = 3): 80/70/70 mA to 60/60/60 mA I CC4 max (CL = 2): 80/80/65 mA to 60/60/60 mA I CC4 max (CL = 3): 100/80/80 mA to 75/60/60 mA DC Characteristics (HM5264405F) I CC1 max (CL = 2): 80/70/65 mA to 60/60/60 mA I CC1 max (CL = 3): 80/70/70 mA to 60/60/60 mA I CC4 max (CL = 2): 70/70/60 mA to 55/55/55 mA I CC4 max (CL = 3): 90/70/70 mA to 70/55/55 mA Capacitance CI1 max: 4 pF to 3.5 pF CI2 max: 5 pF to 3.8 pF Relationship Between Frequency and Minimum Latency lAPW (-A60/B60): 4 to 3 67