HM5264165F-75/A60/B60
HM5264805F-75/A60/B60
HM5264405F-75/A60/B60
64M LVTTL interface SDRAM
133 MHz/100 MHz
1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank
/4-Mword × 4-bit × 4-bank
PC/133, PC/100 SDRAM
ADE-203-940B (Z)
Rev. 1.0
Nov. 10, 1999
Description
The Hitachi HM5264165F is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi
HM5264805F is a 64-Mbit SDRAM organized as 2097152-word × 8-bit × 4 bank. The Hitachi HM5264405F
is a 64-Mbit SDRAM organized as 4194304-word × 4-bit × 4 bank. All inputs and outputs are referred to the
rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
• 3.3 V power supply
• Clock frequency: 133 MHz/100 MHz (max)
• LVTTL interface
• Single pulsed RAS
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8/full page
• 2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
2
• Programmable CAS latency: 2/3
• Byte control by DQM:DQM (HM5264805F/HM5264405F)
DQMU/DQML (HM5264165F)
• Refresh cycles: 4096 refresh cycles/64 ms
• 2 variations of refresh
Auto refresh
Self refresh
• Full page burst length capability
Sequential burst
Burst stop capability
Ordering Information
Type No. Frequency CAS latency Package
HM5264165FTT-75*1
HM5264165FTT-A60
HM5264165FTT-B60*2
133 MHz
100 MHz
100 MHz
3
2/3
3
400-mil 54-pin plastic TSOP II (TTP-54D)
HM5264165FLTT-75*1
HM5264165FLTT-A60
HM5264165FLTT-B60*2
133 MHz
100 MHz
100 MHz
3
2/3
3
HM5264805FTT-75*1
HM5264805FTT-A60
HM5264805FTT-B60*2
133 MHz
100 MHz
100 MHz
3
2/3
3
HM5264805FLTT-75*1
HM5264805FLTT-A60
HM5264805FLTT-B60*2
133 MHz
100 MHz
100 MHz
3
2/3
3
HM5264405FTT-75*1
HM5264405FTT-A60
HM5264405FTT-B60*2
133 MHz
100 MHz
100 MHz
3
2/3
3
HM5264405FLTT-75*1
HM5264405FLTT-A60
HM5264405FLTT-B60*2
133 MHz
100 MHz
100 MHz
3
2/3
3
Note: 1. 100 MHz operation at CAS latency = 2.
2. 66 MHz operation at CAS latency = 2.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
3
Pin Arrangement (HM5264165F)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
VSS
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
DQML
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
VCC
54-pin TSOP
(Top view)
Pin Description
Pin name Function Pin name Function
A0 to A13 Address input WE Write enable
Row address A0 to A11 DQMU/DQML Input/output mask
Column address A0 to A7 CLK Clock input
Bank select address A12/A13 (BS) CKE Clock enable
DQ0 to DQ15 Data-input/output VCC Power for internal circuit
CS Chip select VSS Ground for internal circuit
RAS Row address strobe command VCCQ Power for DQ circuit
CAS Column address strobe command VSSQ Ground for DQ circuit
NC No connection
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
4
Pin Arrangement (HM5264805F)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ7
VSSQ
NC
DQ6
VCCQ
NC
DQ5
VSSQ
NC
DQ4
VCCQ
NC
VSS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VCC
DQ0
VCCQ
NC
DQ1
VSSQ
NC
DQ2
VCCQ
NC
DQ3
VSSQ
NC
VCC
NC
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
VCC
54-pin TSOP
(Top view)
Pin Description
Pin name Function Pin name Function
A0 to A13 Address input WE Write enable
Row address A0 to A11 DQM Input/output mask
Column address A0 to A8 CLK Clock input
Bank select address A12/A13 (BS) CKE Clock enable
DQ0 to DQ7 Data-input/output VCC Power for internal circuit
CS Chip select VSS Ground for internal circuit
RAS Row address strobe command VCCQ Power for DQ circuit
CAS Column address strobe command VSSQ Ground for DQ circuit
NC No connection
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
5
Pin Arrangement (HM5264405F)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
NC
VSSQ
NC
DQ3
VCCQ
NC
NC
VSSQ
NC
DQ2
VCCQ
NC
VSS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VCC
NC
VCCQ
NC
DQ0
VSSQ
NC
NC
VCCQ
NC
DQ1
VSSQ
NC
VCC
NC
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
VCC
54-pin TSOP
(Top view)
Pin Description
Pin name Function Pin name Function
A0 to A13 Address input WE Write enable
Row address A0 to A11 DQM Input/output mask
Column address A0 to A9 CLK Clock input
Bank select address A12/A13 (BS) CKE Clock enable
DQ0 to DQ3 Data-input/output VCC Power for internal circuit
CS Chip select VSS Ground for internal circuit
RAS Row address strobe command VCCQ Power for DQ circuit
CAS Column address strobe command VSSQ Ground for DQ circuit
NC No connection
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
6
Block Diagram (HM5264165F)
Column address
counter Column address
buffer Row address
buffer Refresh
counter
A0 to A13
A0 to A13
DQ0 to DQ15
Input
buffer Output
buffer Control logic &
timing generator
Row decoder
Sense amplifier & I/O bus
Column decoder
Memory array
CLK
CKE
CS
RAS
CAS
WE
DQMU
/DQML
A0 to A7
Bank 0
4096 row
X 256 column
X 16 bit
Row decoder
Sense amplifier & I/O bus
Column decoder
Memory array
Bank 1
4096 row
X 256 column
X 16 bit
Row decoder
Sense amplifier & I/O bus
Column decoder
Memory array
Bank 2
4096 row
X 256 column
X 16 bit
Row decoder
Sense amplifier & I/O bus
Column decoder
Memory array
Bank 3
4096 row
X 256 column
X 16 bit
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
7
Block Diagram (HM5264805F)
Column address
counter Column address
buffer Row address
buffer Refresh
counter
A0 to A13
A0 to A13
Input
buffer Output
buffer Control logic &
timing generator
Row decoder
Sense amplifier & I/O bus
Column decoder
Memory array
CLK
CKE
CS
RAS
CAS
WE
DQM
A0 to A8
Bank 0
4096 row
X 512 column
X 8 bit
Row decoder
Sense amplifier & I/O bus
Column decoder
Memory array
4096 row
X 512 column
X 8 bit
Row decoder
Sense amplifier & I/O bus
Column decoder
Memory array
4096 row
X 512 column
X 8 bit
Row decoder
Sense amplifier & I/O bus
Column decoder
Memory array
4096 row
X 512 column
X 8 bit
Bank 1 Bank 2 Bank 3
DQ0 to DQ7
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
8
Block Diagram (HM5264405F)
Column address
counter Column address
buffer Row address
buffer Refresh
counter
A0 to A13
A0 to A13
DQ0 to DQ3
Input
buffer Output
buffer Control logic &
timing generator
Row decoder
Sense amplifier & I/O bus
Column decoder
Memory array
CLK
CKE
CS
RAS
CAS
WE
DQM
A0 to A9
Bank 0
4096 row
X 1024 column
X 4 bit
Row decoder
Sense amplifier & I/O bus
Column decoder
Memory array
Bank 1
4096 row
X 1024 column
X 4 bit
Row decoder
Sense amplifier & I/O bus
Column decoder
Memory array
Bank 2
4096 row
X 1024 column
X 4 bit
Row decoder
Sense amplifier & I/O bus
Column decoder
Memory array
Bank 3
4096 row
X 1024 column
X 4 bit
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
9
Pin Functions
CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK
rising edge.
CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAMs,
they function in a different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels. For details, refer to the command operation section.
A0 to A11 (input pins): Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active
command cycle CLK rising edge. Column address (AY0 to AY7; HM5264165F, AY0 to AY8;
HM5264805F, AY0 to AY9; HM5264405F) is determined by A0 to A7, A8 or A9 (A7; HM5264165F, A8;
HM5264805F, A9; HM5264405F) level at the read or write command cycle CLK rising edge. And this
column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at
the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command
cycle, only the bank that is selected by A12/A13 (BS) is precharged. For details refer to the command
operation section.
A12/A13 (input pins): A12/A13 are bank select signal (BS). The memory array of the HM5264165F,
HM5264805F, the HM5264405F is divided into bank 0, bank 1, bank 2 and bank 3. HM5264165F contain
4096-row × 256-column × 16-bit. HM5264805F contain 4096-row × 512-column × 8-bit. HM5264405F
contain 4096-row × 1024-column × 4-bit. If A12 is Low and A13 is Low, bank 0 is selected. If A12 is High
and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and
A13 is High, bank 3 is selected.
CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK
rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down
mode, clock suspend mode and self refresh mode.
DQM, DQMU/DQML (input pins): DQM, DQMU/DQML controls input/output buffers.
Read operation: If DQM, DQMU/DQML is High, the output buffer becomes High-Z. If the DQM,
DQMU/DQML is Low, the output buffer becomes Low-Z. (The latency of DQM, DQMU/DQML during
reading is 2 clocks.)
Write operation: If DQM, DQMU/DQML is High, the previous data is held (the new data is not written). If
DQM, DQMU/DQML is Low, the data is written. (The latency of DQM, DQMU/DQML during writing is 0
clock.)
DQ0 to DQ15 (DQ pins): Data is input to and output from these pins (DQ0 to DQ15; HM5264165F, DQ0
to DQ7; HM5264805F, DQ0 to DQ3; HM5264405F).
VCC and VCCQ (power supply pins): 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the
output buffer.)
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
10
VSS and V SSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the
output buffer.)
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins.
CKE
Command Symbol n - 1 n CS RAS CAS WE A12/A13 A10 A0
to A11
Ignore command DESL H ×H×××× ××
No operation NOP H ×LHHH×××
Burst stop in full page BST H ×LHHL×××
Column address and read command READ H ×LHLHV LV
Read with auto-precharge READ A H ×LHLHV HV
Column address and write command WRIT H ×LHLLV LV
Write with auto-precharge WRIT A H ×LHLLV HV
Row address strobe and bank active ACTV H ×LLHHV VV
Precharge select bank PRE H ×LLHLV L×
Precharge all bank PALL H ×LLHL×H×
Refresh REF/SELF H V L L L H ×××
Mode register set MRS H ×LLLLV VV
Note: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input
Ignore command [DESL]: When this command is set (CS is High), the SDRAM ignore command input at
the clock. However, the internal status is held.
No operation [NOP]: This command is not an execution command. However, the internal operations
continue.
Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page
(256; HM5264165F, 512; HM5264805F, 1024; HM5264405F)), and is illegal otherwise. When data
input/output is completed for a full page of data, it automatically returns to the start address, and input/output
is performed repeatedly.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
11
Column address strobe and read command [READ]: This command starts a read operation. In addition,
the start address of burst read is determined by the column address (AY0 to AY7; HM5264165F, AY0 to
AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (BS). After the read operation,
the output buffer becomes High-Z.
Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a
burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal.
Column address strobe and write command [WRIT]: This command starts a write operation. When the
burst write mode is selected, the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F,
AY0 to AY9; HM5264405F) and the bank select address (A12/A13) become the burst write start address.
When the single write mode is selected, data is only written to the location specified by the column address
(AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select
address (A12/A13).
Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a
burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page,
this command is illegal.
Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by
A12/A13 (BS) and determines the row address (AX0 to AX11). When A12 and A13 are Low, bank 0 is
activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank
2 is activated. When A12 and A13 are High, bank 3 is activated.
Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by
A12/A13. If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If
A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected.
Precharge all banks [PALL]: This command starts a precharge operation for all banks.
Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation,
the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]: The SDRAM has a mode register that defines how it operates. The mode register
is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the mode
register configuration. After power on, the contents of the mode register are undefined, execute the mode
register set command to set up the mode register.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
12
DQM Truth Table (HM5264165F)
CKE
Command Symbol n - 1 n DQMU DQML
Upper byte write enable/output enable ENBU H ×L×
Lower byte write enable/output enable ENBL H ××L
Upper byte write inhibit/output disable MASKU H ×H×
Lower byte write inhibit/output disable MASKL H ××H
Note: H: VIH. L: VIL. ×: VIH or VIL.
Write: IDID is needed.
Read: IDOD is needed.
DQM Truth Table (HM5264805F/HM5264405F)
CKE
Command Symbol n - 1 n DQM
Write enable/output enable ENB H ×L
Write inhibit/output disable MASK H ×H
Note: H: VIH. L: VIL. ×: VIH or VIL.
Write: IDID is needed.
Read: IDOD is needed.
The SDRAM can mask input/output data by means of DQM, DQMU/DQML.
DQMU masks the upper byte and DQML masks the lower byte. (HM5264165F)
During reading, the output buffer is set to Low-Z by setting DQM, DQMU/DQML to Low, enabling data
output. On the other hand, when DQM, DQMU/DQML is set to High, the output buffer becomes High-Z,
disabling data output.
During writing, data is written by setting DQM, DQMU/DQML to Low. When DQM, DQMU/DQML is set
to High, the previous data is held (the new data is not written). Desired data can be masked during burst read
or burst write by setting DQMU/DQML. For details, refer to the DQM, DQMU/DQML control section of the
SDRAM operating instructions.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
13
CKE Truth Table
CKE
Current state Command n - 1 n CS RAS CAS WE Address
Active Clock suspend mode entry H L ×××××
Any Clock suspend L L ×××××
Clock suspend Clock suspend mode exit L H ×××××
Idle Auto-refresh command (REF) H H LLLH×
Idle Self-refresh entry (SELF) H LLLLH×
Idle Power down entry H L L H H H ×
HLH××××
Self refresh Self refresh exit (SELFX) L H L H H H ×
LHH××××
Power down Power down exit L H L H H H ×
LHH××××
Note: H: VIH. L: VIL. ×: VIH or VIL.
Clock suspend mode entry: The SDRAM enters clock suspend mode from active mode by setting CKE to
Low. When command is input during CKE is low, the command is valid. The clock suspend mode changes
depending on the current status (1 clock before) as shown below.
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining
the bank active status.
READ suspend and READ with Auto-precharge suspend: The data being output is held (and continues to
be output).
WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not
accepted. However, the internal state is held.
Clock suspend: During clock suspend mode, keep the CKE to Low.
Clock suspend mode exit: The SDRAM exits from clock suspend mode by setting CKE to High during the
clock suspend state.
IDLE: In this state, all banks are not selected, and completed precharge operation.
Auto-refresh command [REF]: When this command is input from the IDLE state, the SDRAM starts auto-
refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the
auto-refresh operation, refresh address and bank select address are generated inside the SDRAM. For every
auto-refresh cycle, the internal address counter is updated. Accordingly, 4096 times are required to refresh
the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state. In
addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge
command is required after auto-refresh.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
14
Self-refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM starts self-
refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-
refresh is performed internally and automatically, external refresh operations are unnecessary.
Power down mode entry: When this command is executed during the IDLE state, the SDRAM enters power
down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit.
Self-refresh exit: When this command is executed during self-refresh mode, the SDRAM can exit from self-
refresh mode. After exiting from self-refresh mode, the SDRAM enters the IDLE state.
Power down exit: When this command is executed at the power down mode, the SDRAM can exit from
power down mode. After exiting from power down mode, the SDRAM enters the IDLE state.
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of
the SDRAM.
The following table assumes that CKE is high.
Current state CS RAS CAS WE Address Command Operation
Precharge H ×××× DESL Enter IDLE after tRP
LHHH×NOP Enter IDLE after tRP
LHHL×BST NOP
L H L H BA, CA, A10 READ/READ A ILLEGAL*4
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*4
L L H H BA, RA ACTV ILLEGAL*4
L L H L BA, A10 PRE, PALL NOP*6
LLLH×REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Idle H ×××× DESL NOP
LHHH×NOP NOP
LHHL×BST NOP
L H L H BA, CA, A10 READ/READ A ILLEGAL*5
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*5
L L H H BA, RA ACTV Bank and row active
L L H L BA, A10 PRE, PALL NOP
LLLH×REF, SELF Refresh
L L L L MODE MRS Mode register set
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
15
Current state CS RAS CAS WE Address Command Operation
Row active H ×××× DESL NOP
LHHH×NOP NOP
LHHL×BST NOP
L H L H BA, CA, A10 READ/READ A Begin read
L H L L BA, CA, A10 WRIT/WRIT A Begin write
L L H H BA, RA ACTV Other bank active
ILLEGAL on same bank*3
L L H L BA, A10 PRE, PALL Precharge
LLLH×REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Read H ×××× DESL Continue burst to end
LHHH×NOP Continue burst to end
LHHL×BST Burst stop to full page
L H L H BA, CA, A10 READ/READ A Continue burst read to CAS
latency and New read
L H L L BA, CA, A10 WRIT/WRIT A Term burst read/start write
L L H H BA, RA ACTV Other bank active
ILLEGAL on same bank*3
L L H L BA, A10 PRE, PALL Term burst read and
Precharge
LLLH×REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Read with auto-
precharge H×××× DESL Continue burst to end and
precharge
LHHH×NOP Continue burst to end and
precharge
LHHL×BST ILLEGAL
L H L H BA, CA, A10 READ/READ A ILLEGAL*4
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*4
L L H H BA, RA ACTV Other bank active
ILLEGAL on same bank*3
L L H L BA, A10 PRE, PALL ILLEGAL*4
LLLH×REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
16
Current state CS RAS CAS WE Address Command Operation
Write H ×××× DESL Continue burst to end
LHHH×NOP Continue burst to end
LHHL×BST Burst stop on full page
L H L H BA, CA, A10 READ/READ A Term burst and New read
L H L L BA, CA, A10 WRIT/WRIT A Term burst and New write
L L H H BA, RA ACTV Other bank active
ILLEGAL on same bank*3
L L H L BA, A10 PRE, PALL Term burst write and
Precharge*2
LLLH×REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Write with auto-
precharge H×××× DESL Continue burst to end and
precharge
LHHH×NOP Continue burst to end and
precharge
LHHL×BST ILLEGAL
L H L H BA, CA, A10 READ/READ A ILLEGAL*4
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*4
L L H H BA, RA ACTV Other bank active
ILLEGAL on same bank*3
L L H L BA, A10 PRE, PALL ILLEGAL*4
LLLH×REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Refresh (auto-
refresh) H×××× DESL Enter IDLE after tRC
LHHH×NOP Enter IDLE after tRC
LHHL×BST Enter IDLE after tRC
L H L H BA, CA, A10 READ/READ A ILLEGAL*5
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*5
L L H H BA, RA ACTV ILLEGAL*5
L L H L BA, A10 PRE, PALL ILLEGAL*5
LLLH×REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Notes: 1. H: VIH. L: VIL. ×: VIH or VIL. The other combinations are inhibit.
2. An interval of tDPL is required between the final valid data input and the precharge command.
3. If tRRD is not satisfied, this operation is illegal.
4. Illegal for same bank, except for another bank.
5. Illegal for all banks.
6. NOP for same bank, except for another bank.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
17
From PRECHARGE state, command operation
To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM enters the IDLE state after
tRP has elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]: The SDRAM enters refresh mode (auto-refresh or self-refresh).
To [MRS]: The SDRAM enters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP] or [BST]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.)
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.)
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands set the SDRAM to precharge mode. (However, an interval of tRAS is
required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
To [ACTV]: This command makes other banks bank active. (However, an interval of t RRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop a burst read, and the SDRAM enters precharge mode.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
18
From READ with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and
the SDRAM then enters precharge mode.
To [ACTV]: This command makes other banks bank active. (However, an interval of t RRD is required.)
Attempting to make the currently active bank active results in an illegal command.
From WRITE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: These commands stop a burst and start a read cycle.
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop burst write and the SDRAM then enters precharge mode.
From WRITE with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the
synchronous DRAM enters precharge mode.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
From REFRESH state, command operation
To [DESL], [NOP], [BST]: After an auto-refresh cycle (after tRC), the SDRAM automatically enters the
IDLE state.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
19
Simplified State Diagram
PRECHARGE
WRITE
SUSPEND READ
SUSPEND
ROW
ACTIVE
IDLE
IDLE
POWER
DOWN
AUTO
REFRESH
SELF
REFRESH
MODE
REGISTER
SET
POWER
ON
WRITEA
WRITEA
SUSPEND READA READA
SUSPEND
ACTIVE
CLOCK
SUSPEND
SR ENTRY
SR EXIT
MRS REFRESH
CKE
CKE_
ACTIVE
WRITE READ
WRITE
WITH AP READ
WITH AP
POWER
APPLIED
CKE CKE_
CKE
CKE_
CKE
CKE_
CKE
CKE_
CKE
CKE_
PRECHARGE
AP
READ WRITE
WRITE
WITH
AP
READ
WITH
READ
WITH AP WRITE
WITH AP
PRECHARGE
PRECHARGE PRECHARGE
BST
(on full page)
BST
(on full page)
*1
READ
Read
WRITE
Write
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
20
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The
mode register consists of five sections, each of which is assigned to address pins.
A13, A12, A11, A10, A9, A8: (OPCODE): The SDRAM has two types of write modes. One is the burst
write mode, and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the column
address specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle,
regardless of the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the CAS latency.
A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected.
A2, A1, A0: (BL): These pins specify the burst length.
A2 A1 A0 Burst length
000 1
001 2
010 4
011 8
1 1 1 F.P.
BT=0 BT=1
100 R
110 R
1
2
4
8
R
R
R
A3
0 Sequential
1 Interleave
Burst typeA6 A5 A4 CAS latency
000 R
001 R
010 2
011 3
1XX R
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
OPCODE 0 LMODE BT BL
A9
0
0R
Write mode
A8
0
1Burst read and burst write
1 Burst read and single write
0
1R
1
101 R R
F.P. = Full Page
R is Reserved (inhibit)
X: 0 or 1
A11 A10
A10
X
X
X
A11
X
X
X
00
A12
A13
A13
X
X
X
0A12
X
X
X
0
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
21
Burst Sequence
A2 A1 A0 Addressing(decimal)
000
001
010
011
111
InterleaveSequential
100
110
101
Starting Ad.
0, 1, 2, 3, 4, 5, 6, 7,
1, 2, 3, 4, 5, 6, 7,
2, 3, 4, 5, 6, 7,
3, 4, 5, 6, 7,
4, 5, 6, 7,
5, 6, 7,
6, 7,
7,
0,
0, 1,
0, 1, 2,
0, 1, 2, 3,
0, 1, 2, 3, 4,
0, 1, 2, 3, 4, 5,
0, 1, 2, 3, 4, 5, 6,
0, 1, 2, 3, 4, 5, 6, 7,
1, 0, 3, 2, 5, 4, 7,
2, 3, 0, 1, 6, 7,
3, 2, 1, 0, 7,
4, 5, 6, 7,
5, 4, 7,
6, 7,
7,
6,
4, 5,
6, 5, 4,
0, 1, 2, 3,
6, 1, 0, 3, 2,
4, 5, 2, 3, 0, 1,
6, 5, 4, 3, 2, 1, 0,
Burst length = 8
A1 A0 Addressing(decimal)
00
01
10
11
InterleaveSequential
Starting Ad.
0, 1, 2, 3,
1, 2, 3, 0,
2, 3, 0, 1,
3, 0, 1, 2,
0, 1, 2, 3,
1, 0, 3, 2,
2, 3, 0, 1,
3, 2, 1, 0,
Burst length = 4
A0 Addressing(decimal)
0
1
InterleaveSequential
Starting Ad.
0, 1,
1, 0, 0, 1,
1, 0,
Burst length = 2
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
22
Operation of the SDRAM
Read/Write Operations
Bank active: Before executing a read or write operation, the corresponding bank and the row address must be
activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to
the status of the A12/A13 pin, and the row address (AX0 to AX11) is activated by the A0 to A11 pins at the
bank active command cycle. An interval of tRCD is required between the bank active command input and the
following read/write command input.
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (CAS Latency - 1) cycle after read command set. HM5264165F, HM5264805F series, HM5264405F can
perform a burst read operation.
The burst length can be set to 1, 2, 4, 8 or full-page (256; HM5264165F, 512; HM5264805F, 1024;
HM5264405F). The start address for a burst read is specified by the column address (AY0 to AY7;
HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address
(A12/A13) at the read command set cycle. In a read operation, data output starts after the number of clocks
specified by the CAS Latency. The CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4, 8, the Dout buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The CAS latency and burst length must be specified at the mode register.
CAS Latency
READ
CLK
Command
Dout
ACTV
Row Column
Address
CL = 2
CL = 3
out 0 out 1 out 2 out 3
out 0 out 1 out 2 out 3
tRCD
CL = CAS latency
Burst Length = 4
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
23
Burst Length
READ
CLK
Command
Dout
ACTV
Row Column
out 0
out 6 out 7
out 8
Address
out 0 out 1
out 4 out 5
out 0 out 1 out 2 out 3
BL = 1
out 0 out 1 out 2 out 3
out 0 out 1 out 2 out 3 out 6 out 7
out 4 out 5 out 0-1 out 0 out 1
BL = 2
BL = 4
BL = 8
BL = full page
tRCD
BL : Burst Length
CAS Latency = 2
Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9,
A8) of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write
starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can
be set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column
address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the
bank select address (A12/A13) at the write command set cycle.
WRIT
CLK
Command
Din
ACTV
Row Column
in 0
in 6 in 7
in 8
Address
in 1
in 4 in 5
in 3
BL = 1
in 6 in 7
in 4 in 5 in 0-1 in 0 in 1
BL = 2
BL = 4
BL = 8
BL = full page
tRCD
in 0
in 0
in 0
in 0
in 1
in 1
in 1
in 2
in 2
in 2
in 3
in 3
CAS Latency = 2, 3
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
24
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column address (AY0 to AY7; HM5264165F, AY0 to AY8;
HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13) specified by the write
command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
WRIT
CLK
Command
Din
ACTV
Row Column
in 0
Address
tRCD
Auto Precharge
Read with auto-precharge: In this operation, since precharge is automatically performed after completing a
read operation, a precharge command need not be executed after each read operation. The command executed
for the same bank after the execution of this command must be the bank active (ACTV) command. In
addition, an interval defined by lAPR is required before execution of the next command.
CAS latency Precharge start cycle
3 2 cycle before the final data is output
2 1 cycle before the final data is output
Burst Read (Burst Length = 4)
CLK
lAPR
lRAS
lAPR
CL=2 Command
CL=3 Command
DQ (input)
DQ (input)
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ".
ACTV READ A ACTV
out3out2out1out0
lRAS
ACTV READ A ACTV
out3out2out1out0
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
25
Write with auto-precharge: In this operation, since precharge is automatically performed after completing
a burst write or single write operation, a precharge command need not be executed after each write operation.
The command executed for the same bank after the execution of this command must be the bank active
(ACTV) command. In addition, an interval of lAPW is required between the final valid data input and input of
next command.
Burst Write (Burst Length = 4)
CLK
Command
DQ (input)
lAPW
IRAS
ACTV WRIT A
in0 in1 in2 in3
ACTV
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command
and internal precharge " ".
Single Write
CLK
Command
DQ (input)
lAPW
IRAS
ACTV WRIT A
in
ACTV
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command
and internal precharge " ".
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
26
Full-page Burst Stop
Burst stop command during burst read: The burst stop (BST) command is used to stop data output during
a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. The
timing from command input to the last data changes depending on the CAS latency setting. In addition, the
BST command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8.
CAS latency BST to valid data BST to high impedance
212
323
CAS Latency = 2, Burst Length = full page
l = 1 clock
BSR
CLK
Command
DQ (output) out out outout
l = 2 clocks
BSH
BST
out out
CAS Latency = 3, Burst Length = full page
l = 2 clocks
BSR
CLK
Command
DQ (output) out out outout
l = 3 clocks
BSH
BST
outout out
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
27
Burst stop command at burst write: The burst stop command (BST command) is used to stop data input
during a full-page burst write. No data is written in the same clock as the BST command, and in subsequent
clocks. In addition, the BST command is only valid during full-page burst mode, and is illegal with burst
lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge
command.
Burst Length = full page
t
CLK
Command
DQ (input) in
DPL
in
PRE/PALL
BST
I = 0 clock
BSW
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
28
Command Intervals
Read command to Read command interval:
1. Same bank, same ROW address: When another read command is executed at the same ROW address
of the same bank as the preceding read command execution, the second read can be performed after an
interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data
read by the second command will be valid.
READ to READ Command Interval (same ROW address in same bank)
CLK
Command
Dout out B3
Address
out B1 out B2
BS
ACTV
Row Column A
READ READ
Column B
out A0 out B0
Bank0
Active Column =A
Read Column =B
Read Column =A
Dout Column =B
Dout
CAS Latency = 3
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read
commands cannot be executed; it is necessary to separate the two read commands with a precharge command
and a bank-active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. Even when the first command is a burst
read that is not yet finished, the data read by the second command will be valid.
READ to READ Command Interval (different bank)
CLK
Command
Dout out B3
Address
out B1 out B2
BS
ACTV
Row 0 Row 1
ACTV READ
Column A
out A0 out B0
Bank0
Active Bank3
Active Bank0
Read Bank3
Read
READ
Column B
Bank0
Dout Bank3
Dout CAS Latency = 3
Burst Length = 4
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
29
Write command to Write command interval:
1. Same bank, same ROW address: When another write command is executed at the same ROW address
of the same bank as the preceding write command, the second write can be performed after an interval of no
less than 1 clock. In the case of burst writes, the second write command has priority.
WRITE to WRITE Command Interval (same ROW address in same bank)
CLK
Command
Din
in B3
Address
in B1 in B2
BS
ACTV
Row Column A
WRIT WRIT
Column B
in A0 in B0
Bank0
Active Column =A
Write Column =B
Write
Burst Write Mode
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two write commands with a precharge command and a
bank-active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. In the case of burst write, the second
write command has priority.
WRITE to WRITE Command Interval (different bank)
CLK
Command
Din in B3
Address
in B1 in B2
BS
ACTV
Row 0 Row 1
ACTV WRIT
Column A
in A0 in B0
Bank0
Active Bank3
Active Bank0
Write Bank3
Write
WRIT
Column B
Burst Write Mode
Burst Length = 4
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
30
Read command to Write command interval:
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the
same bank as the preceding read command, the write command can be performed after an interval of no less
than 1 clock. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z
before data input.
READ to WRITE Command Interval (1)
CLK
Command
Dout
in B2 in B3
READ WRIT
in B0 in B1
High-Z
Din
CL=2
CL=3
DQM,
DQMU
/DQML
Burst Length = 4
Burst write
READ to WRITE Command Interval (2)
CLK
Command
Dout
READ WRIT
Din
CL=2
CL=3
DQM,
DQMU/DQML
High-Z
2 clock
High-Z
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. However, DQM, DQMU/DQML must
be set High so that the output buffer becomes High-Z before data input.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
31
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the
same bank as the preceding write command, the read command can be performed after an interval of no less
than 1 clock. However, in the case of a burst write, data will continue to be written until one cycle before the
read command is executed.
WRITE to READ Command Interval (1)
CLK
Command
Din
WRIT READ
in A0
out B1 out B2 out B3
out B0
Dout
Column = A
Write Column = B
Read Column = B
Dout
CAS Latency
DQM,
DQMU/DQML
Burst Write Mode
CAS Latency = 2
Burst Length = 4
Bank 0
WRITE to READ Command Interval (2)
CLK
Command
Din
WRIT READ
in A0
out B1 out B2 out B3
out B0Dout
Column = A
Write Column = B
Read Column = B
Dout
CAS Latency
in A1
DQM,
DQMU/DQML
Burst Write Mode
CAS Latency = 2
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write,
data will continue to be written until one clock before the read command is executed (as in the case of the
same bank and the same address).
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
32
Read with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is
executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by
the second command is valid. The internal auto-precharge of one bank starts at the next clock of the second
command.
Read with Auto Precharge to Read Command Interval (Different bank)
CLK
Command
BS
Dout
READ A READ
out A0 out A1 out B0 out B1
CAS Latency = 3
Burst Length = 4
bank0
Read A bank3
Read
Note: Internal auto-precharge starts at the timing indicated by " ".
2. Same bank: The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is
executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of
one bank starts at the next clock of the second command .
Write with Auto Precharge to Write Command Interval (Different bank)
CLK
Command
BS
Din
WRIT A WRIT
in B1 in B2 in B3in A0 in A1 in B0
Burst Length = 4
bank0
Write A bank3
Write
Note: Internal auto-precharge starts at the timing indicated by " ".
2. Same bank: The consecutive write command (the same bank) is illegal.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
33
Read with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is
executed. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before
data input. The internal auto-precharge of one bank starts at the next clock of the second command.
Read with Auto Precharge to Write Command Interval (Different bank)
CLK
Command
BS
Dout
Din
CL = 2
CL = 3
READ A WRIT
in B0 in B1 in B2 in B3
Burst Length = 4
bank0
Read A bank3
Write
Note: Internal auto-precharge starts at the timing indicated by " ".
DQM,
DQMU/DQML
High-Z
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It
is necessary to separate the two commands with a bank active command.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
34
Write with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is
executed. However, in case of a burst write, data will continue to be written until one clock before the read
command is executed. The internal auto-precharge of one bank starts at the next clock of the second
command.
Write with Auto Precharge to Read Command Interval (Different bank)
CLK
Command
BS
Dout
Din
WRIT A READ
out B0 out B1 out B2 out B3
CAS Latency = 3
Burst Length = 4
bank0
Write A bank3
Read
Note: Internal auto-precharge starts at the timing indicated by " ".
DQM,
DQMU/DQML
in A0
Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. . It is
necessary to separate the two commands with a bank active command.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
35
Read command to Precharge command interval (same bank):
When the precharge command is executed for the same bank as the read command that preceded it, the
minimum interval between the two commands is one clock. However, since the output buffer then becomes
High-Z after the clocks defined by lHZP, there is a case of interruption toburst read data output will be
interrupted, if the precharge command is input during burst read. To read all data by burst read, the clocks
defined by lEP must be assured as an interval from the final data output to precharge command execution.
READ to PRECHARGE Command Interval (same bank): To output all data
CAS Latency = 2, Burst Length = 4
CLK
Command
Dout
READ PRE/PALL
out A0 out A1 out A2 out A3
CL=2 l = -1 cycle
EP
CAS Latency = 3, Burst Length = 4
CLK
Command
Dout
READ PRE/PALL
out A0 out A1 out A2 out A3
CL=3 l = -2 cycle
EP
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
36
READ to PRECHARGE Command Interval (same bank): To stop output data
CAS Latency = 2, Burst Length = 1, 2, 4, 8, full page burst
CLK
Command
Dout
READ PRE/PALL
out A0
lHZP=2
High-Z
CAS Latency = 3, Burst Length = 1, 2, 4, 8, full page burst
CLK
Command
Dout
READ PRE/PALL
out A0
lHZP=3
High-Z
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
37
Write command to Precharge command interval (same bank): When the precharge command is executed
for the same bank as the write command that preceded it, the minimum interval between the two commands is
1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of
DQM, DQMU/DQML for assurance of the clock defined by tDPL.
WRITE to PRECHARGE Command Interval (same bank)
Burst Length = 4 (To stop write operation)
CLK
Command
Din
WRIT PRE/PALL
tDPL
DQM,
DQMU/DQML
CLK
in A0 in A1
Command
Din
WRIT PRE/PALL
DQM,
DQMU/DQML
tDPL
Burst Length = 4 (To write all data)
CLK
in A0 in A1 in A2
Command
Din
WRIT PRE/PALL
in A3
DQM,
DQMU/DQML
tDPL
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
38
Bank active command interval:
1. Same bank: The interval between the two bank-active commands must be no less than tRC.
2. In the case of different bank-active commands: The interval between the two bank-active commands
must be no less than tRRD.
Bank Active to Bank Active for Same Bank
CLK
Command
Address
BS
Bank 0
Active
ACTV
ROW
ACTV
ROW
Bank 0
Active
tRC
Bank Active to Bank Active for Different Bank
CLK
Command
Address
BS
Bank 0
Active Bank 3
Active
ACTV
ROW:0
ACTV
ROW:1
tRRD
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
39
Mode register set to Bank-active command interval: The interval between setting the mode register and
executing a bank-active command must be no less than lRSA.
CLK
Command
Address
Mode
Register Set Bank
Active
MRS ACTV
IRSA
BS & ROWCODE
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
40
DQM Control
The DQM mask the DQ data.
The DQMU and DQML mask the upper and lower bytes of the DQ data, respectively. The timing of
DQMU/DQML is different during reading and writing.
Reading: When data is read, the output buffer can be controlled by DQM, DQMU/DQML. By setting
DQM, DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM,
DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output.
However, internal reading operations continue. The latency of DQM, DQMU/DQML during reading is 2
clocks.
Writing: Input data can be masked by DQM, DQMU/DQML. By setting DQM, DQMU/DQML to Low,
data can be written. In addition, when DQM, DQMU/DQML is set to High, the corresponding data is not
written, and the previous data is held. The latency of DQM, DQMU/DQML during writing is 0 clock.
Reading
CLK
DQ (output) out 0 out 1
l = 2 Latency
out 3
DOD
DQM,
DQMU/DQML High-Z
Writing
CLK
DQ (input) in 0 in 1
l = 0 Latency
in 3
,
DID
DQM,
DQMU/DQML
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
41
Refresh
Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the auto-
refresh command updates the internal counter every time it is executed and determines the banks and the
ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4096
cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer becomes High-
Z after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the
auto-refresh, an additional precharge operation by the precharge command is not required.
Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is held
Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-
refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-refresh
to all refresh addresses in or within 64 ms period on the condition (1) and (2) below.
(1) Enter self-refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal interval to
all refresh addresses are completed.
(2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 µs after
exiting from self-refresh mode.
Others
Power-down mode: The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In
power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down
mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the
power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not
performed.
Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the SDRAM
enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal
state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command
input is enabled from the next clock. For details, refer to the "CKE Truth Table".
Power-up sequence: The SDRAM should be gone on the following sequence with power up.
The CLK, CKE, CS, DQM, DQMU/DQML and DQ pins keep low till power stabilizes.
The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.
The CKE and DQM, DQMU/DQML is driven to high between power stabilizes and the initialization
sequence.
This SDRAM has VCC clamp diodes for CLK, CKE, CS, DQM, DQMU/DQML and DQ pins. If these pins go
high before power up, the large current flows from these pins to VCC through the diodes.
Initialization sequence: When 200 µs or more has past after the above power-up sequence , all banks must
be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands
(REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by
keeping DQM, DQMU/DQML and CKE to High, the output buffer becomes High-Z during Initialization
sequence, to avoid DQ bus contention on memory system formed with a number of device.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
42
VCC, VCCQ
Power up sequence Initialization sequence
100 µs
0 V
Low
Low
Low
CKE, DQM,
DQMU/DQML
CLK
CS, DQ
200 µs
Power stabilize
Absolute Maximum Ratings
Parameter Symbol Value Unit Note
Voltage on any pin relative to VSS VT–0.5 to VCC + 0.5
(≤ 4.6 (max)) V1
Supply voltage relative to VSS VCC –0.5 to +4.6 V 1
Short circuit output current Iout 50 mA
Power dissipation PT1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Note: 1. Respect to VSS.
DC Operating Conditions (Ta = 0 to +70˚C)
Parameter Symbol Min Max Unit Notes
Supply voltage VCC, VCCQ 3.0 3.6 V 1, 2
VSS, VSSQ0 0 V 3
Input high voltage VIH 2.0 VCC + 0.3 V 1, 4
Input low voltage VIL –0.3 0.8 V 1, 5
Notes: 1. All voltage referred to VSS.
2. The supply voltage with all VCC and VCCQ pins must be on the same level.
3. The supply voltage with all VSS and VSSQ pins must be on the same level.
4. VIH (max) = VCC + 2.0 V for pulse width ≤ 3 ns at VCC.
5. VIL (min) = VSS – 2.0 V for pulse width ≤ 3 ns at VSS.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
43
VIL/VIH Clamp
This SDRAM has VIL and VIH clamp for CLK, CKE, CS, DQM and D/Q pins.
Minimum VIL Clamp Current
VIL (V) I (mA)
–2 –32
–1.8 –25
–1.6 –19
–1.4 –13
–1.2 –8
–1 –4
–0.9 –2
–0.8 –0.6
–0.6 0
–0.4 0
–0.2 0
00
VIL (V)
I (mA)
–1.5 –1 –0.5
–5
–15
–10
–25
–20
–30
0
–35
–2
0
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
44
Minimum VIH Clamp Current
VIH (V) I (mA)
VCC + 2 10
VCC + 1.8 8
VCC + 1.6 5.5
VCC + 1.4 3.5
VCC + 1.2 1.5
VCC + 1 0.3
VCC + 0.8 0
VCC + 0.6 0
VCC + 0.4 0
VCC + 0.2 0
VCC + 0 0
VIH (V)
VCC + 0 VCC + 1 VCC + 2VCC + 0.5 VCC + 1.5
I (mA)
8
4
6
0
2
10
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
45
IOL/IOH Characteristics
Output Low Current (IOL)
IOL IOL
Vout (V) Min (mA) Max (mA)
000
0.4 27 71
0.65 41 108
0.85 51 134
1 58 151
1.4 70 188
1.5 72 194
1.65 75 203
1.8 77 209
1.95 77 212
3 80 220
3.45 81 223
IOL (mA)
Vout (V)
250
200
150
100
50
00 0.5 1 1.5 2 2.5 3 3.5
min
max
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
46
Output High Current (IOH) (Ta = 0 to +70˚C, VCC, VCCQ = 3.0 V to 3.45 V, VSS, VSSQ = 0 V)
IOH IOH
Vout (V) Min (mA) Max (mA)
3.45 — –3
3.3 — –28
3 0 –75
2.6 –21 –130
2.4 –34 –154
2 –59 –197
1.8 –67 –227
1.65 –73 –248
1.5 –78 –270
1.4 –81 –285
1 –89 –345
0 –93 –503
IOH (mA)
Vout (V)
0
–100
–200
–300
–500
–600
–400
0.5 1 1.5 2 2.5 3
min
max
3.50
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
47
DC Characteristics (Ta = 0 to +70˚C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
(HM5264165F)
HM5264165F
-75 -A60 -B60
Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes
Operating current
(CAS latency = 2) ICC1 — 65—65—65mABurst length = 1
tRC = min 1, 2, 3
(CAS latency = 3) ICC1 — 65—65—65mA
Standby current in power down ICC2P — 1.5 — 1.5 — 1.5 mA CKE = VIL,
tCK = 12 ns 6
Standby current in power down
(input signal stable) ICC2PS — 1 — 1 — 1 mA CKE = VIL, tCK = ∞7
Standby current in non power
down ICC2N — 10 — 10 — 10 mA CKE, CS = VIH,
tCK = 12 ns 4
Standby current in non power
down (input signal stable) ICC2NS — 5 — 5 — 5 mA CKE = VIH, tCK = ∞9
Active standby current in power
down ICC3P — 4 — 4 — 4 mA CKE = VIL,
tCK = 12 ns 1, 2, 6
Active standby current in power
down (input signal stable) ICC3PS — 3 — 3 — 3 mA CKE = VIL, tCK = ∞2, 7
Active standby current in non
power down ICC3N — 18 — 18 — 18 mA CKE, CS = VIH,
tCK = 12 ns 1, 2, 4
Active standby current in non
power down (input signal
stable)
ICC3NS — 12 — 12 — 12 mA CKE = VIH, tCK = ∞2, 9
Burst operating current
(CAS latency = 2) ICC4 — 65—65—65mAt
CK = min, BL = 4 1, 2, 5
(CAS latency = 3) ICC4 — 80—65—65mA
Refresh current ICC5 — 110 — 110 — 110 mA tRC = min 3
Self refresh current ICC6 —1 —1 —1 mAV
IH ≥ VCC – 0.2 V
VIL ≤ 0.2 V 8
Self refresh current (L-version) ICC6 — 0.4 — 0.4 — 0.4 mA
Input leakage current ILI –1 1 –1 1 –1 1 µA0 ≤ Vin ≤ VCC
Output leakage current ILO –1.5 1.5 –1.5 1.5 –1.5 1.5 µA0 ≤ Vout ≤ VCC
DQ = disable
Output high voltage VOH 2.4 — 2.4 — 2.4 — V IOH = –4 mA
Output low voltage VOL — 0.4 — 0.4 — 0.4 V IOL = 4 mA
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
48
DC Characteristics (Ta = 0 to +70˚C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
(HM5264805F)
HM5264805F
-75 -A60 -B60
Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes
Operating current
(CAS latency = 2) ICC1 — 60—60—60mABurst length = 1
tRC = min 1, 2, 3
(CAS latency = 3) ICC1 — 60—60—60mA
Standby current in power down ICC2P — 1.5 — 1.5 — 1.5 mA CKE = VIL,
tCK = 12 ns 6
Standby current in power down
(input signal stable) ICC2PS — 1 — 1 — 1 mA CKE = VIL, tCK = ∞7
Standby current in non power
down ICC2N — 10 — 10 — 10 mA CKE, CS = VIH,
tCK = 12 ns 4
Standby current in non power
down (input signal stable) ICC2NS — 5 — 5 — 5 mA CKE = VIH, tCK = ∞9
Active standby current in power
down ICC3P — 4 — 4 — 4 mA CKE = VIL,
tCK = 12 ns 1, 2, 6
Active standby current in power
down (input signal stable) ICC3PS — 3 — 3 — 3 mA CKE = VIL, tCK = ∞2, 7
Active standby current in non
power down ICC3N — 18 — 18 — 18 mA CKE, CS = VIH,
tCK = 12 ns 1, 2, 4
Active standby current in non
power down (input signal
stable)
ICC3NS — 12 — 12 — 12 mA CKE = VIH, tCK = ∞2, 9
Burst operating current
(CAS latency = 2) ICC4 — 60—60—60mAt
CK = min, BL = 4 1, 2, 5
(CAS latency = 3) ICC4 — 75—60—60mA
Refresh current ICC5 — 110 — 110 — 110 mA tRC = min 3
Self refresh current ICC6 —1 —1 —1 mAV
IH ≥ VCC – 0.2 V
VIL ≤ 0.2 V 8
Self refresh current (L-version) ICC6 — 0.4 — 0.4 — 0.4 mA
Input leakage current ILI –1 1 –1 1 –1 1 µA0 ≤ Vin ≤ VCC
Output leakage current ILO –1.5 1.5 –1.5 1.5 –1.5 1.5 µA0 ≤ Vout ≤ VCC
DQ = disable
Output high voltage VOH 2.4 — 2.4 — 2.4 — V IOH = –4 mA
Output low voltage VOL — 0.4 — 0.4 — 0.4 V IOL = 4 mA
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
49
DC Characteristics (Ta = 0 to +70˚C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
(HM5264405F)
HM5264405F
-75 -A60 -B60
Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes
Operating current
(CAS latency = 2) ICC1 — 60—60—60mABurst length = 1
tRC = min 1, 2, 3
(CAS latency = 3) ICC1 — 60—60—60mA
Standby current in power down ICC2P — 1.5 — 1.5 — 1.5 mA CKE = VIL,
tCK = 12 ns 6
Standby current in power down
(input signal stable) ICC2PS — 1 — 1 — 1 mA CKE = VIL, tCK = ∞7
Standby current in non power
down ICC2N — 10 — 10 — 10 mA CKE, CS = VIH,
tCK = 12 ns 4
Standby current in non power
down (input signal stable) ICC2NS — 5 — 5 — 5 mA CKE = VIH, tCK = ∞9
Active standby current in power
down ICC3P — 4 — 4 — 4 mA CKE = VIL,
tCK = 12 ns 1, 2, 6
Active standby current in power
down (input signal stable) ICC3PS — 3 — 3 — 3 mA CKE = VIL, tCK = ∞2, 7
Active standby current in non
power down ICC3N — 18 — 18 — 18 mA CKE, CS = VIH,
tCK = 12 ns 1, 2, 4
Active standby current in non
power down (input signal
stable)
ICC3NS — 12 — 12 — 12 mA CKE = VIH, tCK = ∞2, 9
Burst operating current
(CAS latency = 2) ICC4 — 55—55—55mAt
CK = min, BL = 4 1, 2, 5
(CAS latency = 3) ICC4 — 70—55—55mA
Refresh current ICC5 — 110 — 110 — 110 mA tRC = min 3
Self refresh current ICC6 —1 —1 —1 mAV
IH ≥ VCC – 0.2 V
VIL ≤ 0.2 V 8
Self refresh current (L-version) ICC6 — 0.4 — 0.4 — 0.4 mA
Input leakage current ILI –1 1 –1 1 –1 1 µA0 ≤ Vin ≤ VCC
Output leakage current ILO –1.5 1.5 –1.5 1.5 –1.5 1.5 µA0 ≤ Vout ≤ VCC
DQ = disable
Output high voltage VOH 2.4 — 2.4 — 2.4 — V IOH = –4 mA
Output low voltage VOL — 0.4 — 0.4 — 0.4 V IOL = 4 mA
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
50
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. After self refresh mode set, self refresh current.
9. Input signals are VIH or VIL fixed.
Capacitance (Ta = 25°C, VCC, VCCQ = 3.3 V ± 0.3 V)
Parameter Symbol Min Max Unit Notes
Input capacitance (CLK) CI1 2.5 3.5 pF 1, 2, 4
Input capacitance (Input) CI2 2.5 3.8 pF 1, 2, 4
Output capacitance (DQ) CO4 6.5 pF 1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQM, DQMU/DQML = VIH to disable Dout.
4. This parameter is sampled and not 100% tested.
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
51
AC Characteristics (Ta = 0 to +70˚C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
HM5264165F/HM5264805F/HM5264405F
-75 -A60 -B60
Parameter HITACHI
Symbol PC/100
Symbol Min Max Min Max Min Max Unit Notes
System clock cycle time
(CAS latency = 2) tCK Tclk 10 — 10 — 15 — ns 1
(CAS latency = 3) tCK Tclk 7.5 — 10 — 10 — ns
CLK high pulse width tCKH Tch 2.5 — 3 — 3 — ns 1
CLK low pulse width tCKL Tcl 2.5 — 3 — 3 — ns 1
Access time from CLK
(CAS latency = 2) tAC Tac — 6 — 6 — 8 ns 1, 2
(CAS latency = 3) tAC Tac — 5.4 — 6 — 6 ns
Data-out hold time tOH Toh 2.7 — 3 — 3 — ns 1, 2
CLK to Data-out low impedance tLZ 2 — 2 — 2 — ns 1, 2, 3
CLK to Data-out high
impedance
(CAS latency = 2, 3)
tHZ — 5.4 — 6 — 6 ns 1, 4
Input setup time tAS, tCS,
tDS, tCES
Tsi 1.5 — 2 — 2 — ns 1, 5, 6
CKE setup time for power down
exit tCESP Tpde 1.5 — 2 — 2 — ns 1
Input hold time tAH, tCH,
tDH, tCEH
Thi 0.8 — 1 — 1 — ns 1, 5
Ref/Active to Ref/Active
command period tRC Trc 67.5 — 70 — 70 — ns 1
Active to Precharge command
period tRAS Tras 45 120000 50 120000 50 120000 ns 1
Active command to column
command (same bank) tRCD Trcd 20 — 20 — 20 — ns 1
Precharge to active command
period tRP Trp 20 — 20 — 20 — ns 1
Write recovery or data-in to
precharge lead time tDPL Tdpl 10 — 10 — 10 — ns 1
Active (a) to Active (b)
command period tRRD Trrd 15 — 20 — 20 — ns 1
Transition time (rise and fall) tT15 15 15 ns
Refresh period tREF —64 —64 —64 ms
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
52
Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is CL = 50 pF.
3. tLZ (min) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max) defines the time at which the outputs achieves the high impedance state.
5. tCES define CKE setup time to CLK rising edge except power down exit command.
6. tAS/tAH: Address, tCS/tCH: CS, RAS, CAS, WE, DQM, DQMU/DQML
tDS/tDH: Data-in, tCES/tCEH: CKE
Test Conditions
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
t
T
2.4 V
0.4 V 0.8 V
2.0 V
input
tT
I/O
CL
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
53
Relationship Between Frequency and Minimum Latency
HM5264165F/
HM5264805F/
HM5264405F
Parameter -75 -A60/B60
Frequency (MHz) 133 100
tCK (ns) HITACHI
Symbol PC/100
Symbol 7.5 10 Notes
Active command to column command
(same bank) lRCD 321
Active command to active command
(same bank) lRC 97= [l
RAS+ lRP]
1
Active command to precharge command
(same bank) lRAS 651
Precharge command to active command
(same bank) lRP 321
Write recovery or data-in to precharge
command (same bank) lDPL Tdpl 2 1 1
Active command to active command
(different bank) lRRD 221
Self refresh exit time lSREX Tsrx 1 1 2
Last data in to active command
(Auto precharge, same bank) lAPW Tdal 5 3 = [lDPL + lRP]
Self refresh exit to command input lSEC 97= [l
RC]
3
Precharge command to high impedance
(CAS latency = 2) lHZP Troh 2 2
(CAS latency = 3) lHZP Troh 3 3
Last data out to active command
(Auto precharge, same bank) lAPR 11
Last data out to precharge (early precharge)
(CAS latency = 2) lEP –1 –1
(CAS latency = 3) lEP –2 –2
Column command to column command lCCD Tccd 1 1
Write command to data in latency lWCD Tdwd 0 0
DQM to data in lDID Tdqm 0 0
DQM to data out lDOD Tdqz 2 2
CKE to CLK disable lCLE Tcke 1 1
Register set to active command lRSA Tmrd 1 1
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
54
HM5264165F/
HM5264805F/
HM5264405F
Parameter -75 -A60/B60
Frequency (MHz) 133 100
tCK (ns) HITACHI
Symbol PC/100
Symbol 7.5 10 Notes
CS to command disable lCDD 00
Power down exit to command input lPEC 11
Burst stop to output valid data hold
(CAS latency = 2) lBSR 11
(CAS latency = 3) lBSR 22
Burst stop to output high impedance
(CAS latency = 2) lBSH 22
(CAS latency = 3) lBSH 33
Burst stop to write data ignore lBSW 00
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP].
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
55
Timing Waveforms
Read Cycle
Bank 0
Active Bank 0
Read Bank 0
Precharge
CLK
CKE
CS
tRAS
tRCD
tCH
tCS
#
#
,
'./7
'./7
'./
.67=>
.67=>
,
,
08?
08?
,
&'.
&'.
&'.
&-.45<=
&-.45<=
,,
,
,
,
$%+,34
$%+,34
3:;
3:;
%
%,-4;<
,
89
,
89
%&,-34<
%&,-34<
3;<
3;
&
RAS
CAS
WE
BS
*23:
*23:
!"()018!"()018
!"()08
$,-34:;CKL
,
,
"#
6=>
'/67
,
9:
#$+3
#$+3
/7?
,
>
/07?
")*12
,
189
,
,
,
A10
Address
DQM,
DQMU/DQML
DQ (input)
DQ (output)
3:;
:
tCH
tCS
tCKH t
tCK
tAC tAC
CKL
tAC
tOH
tOH tOH
tOH
tRP
tRC
CAS latency = 2
Burst length = 4
Bank 0 access
= V or V
$%+,
0
3
8
:;
?
,
89
tCH
tCS
tCH
tCS
tCH
tCS
tAH
tAS
tAH
tAS
tAH
tAS
tCH
tCS
tCH
tCS
tCH
tCS
tAH
tAS
tAH
tAS
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tCS
tAH
tAS
tAH
tAS
tAH
tAS
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tCS
tAH
tAS
tAH
tAS
tAH
tAS
tAC
#$*+2:
tLZ
VIH
IH IL
34
tHZ
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
56
Write Cycle
CLK
CKE
CS
tRAS
tRCD
$,-4
"
#$+
,
#
RAS
CAS
WE
BS
,
,
,
,
,
A10
Address
DQ (input)
DQ (output)
tCH
tCS
tCKH t
tCK
tDH tDH
CKL
tDH tDH
tDS
tDS tDS
tDS
tRP
tRC
tDPL
Bank 0
Write
tCH
tCS
Bank 0
Active Bank 0
Precharge
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tCS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tCH
tCS
tAH
tAS
tCH
tCS
tCH
tCS
tCH
tCS
tAH
tAS
tCH
tCS
tAH
tAS
tCH
tCS
tCH
tCS
tCH
tCS
tAH
tAS
tAH
tAS
!"
!")*018
!
!()0
7>?
/
&./56<=
&'/
'(/
2:;
$
78?
$%,-34;<
,
8
%&-.45;<
&
,
;
'.
./67=>
,
%-
,
8?
VIH
CAS latency = 2
Burst length = 4
Bank 0 access
= V or V
!
IH IL
DQM,
DQMU/DQML
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
57
Mode Register Set Cycle
MN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CLK
CKE
CS
RAS
CAS
WE
BS
Address
DQM,
DQMU/DQML
DQ (input)
DQ (output)
,
@HI
,
,
,
&'/0
MN
,
,
,
,
HP
,
./7@
,
&'/
,
,
%-.
-6>?G
GOP
CDLM
%&
High-Z
bb+3 b’ b’+1 b’+2 b’+3
l
valid C: b’
RSA
code
lRCD
lRP
Precharge
If needed Mode
register
Set
Bank 3
Active Bank 3
Read
,
?@HI
,
/89@A
/78@
,
DLM
,
'(/09
(
,
6?@H
6?GHP
,
,,
%./7
,
%&/
,
,
R: b C: b
,
.7?@HP
,
,
4=>EF
,
Output mask
VIH
l = 3
CAS latency = 3
Burst length = 4
= V or V
IH IL
RCD
Read Cycle/Write Cycle
0 1 2 3 4 5 6 7 8 9 1011121314151617181920
,
R:a C:a R:b C:b C:b' C:b"
a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3
CKE
RAS
CS
CAS
WE
Address
DQM,
DQMU/DQML
DQ (output)
DQ (input)
CLK
BS
,
,
=FO
<=E
=EF
FO
=EFO
,
,
R:a C:a R:b C:b C:b' C:b"
a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1b"+2 b"+3
,
,
,
,
HI
,
HI
AJ
8AIJ
78@AI
AIJ
8@AI
IJ
@HI
IJ
@HI
9:B
09B
089
/089
/08A
1:
'01
'0
01
'0
5>FG
45=F
+45=
5=>FG
5=>F
-56>
+,45
5>
,5>
,45
$%-6
#$,5
#,5
$-5
$,5
$%
$
$
$
%
'(
)
!)
()1:
()1
'(1
'(
KL
BKL
BJK
BJK
J
ABJK
Bank 0
Active Bank 0
Read Bank 3
Active Bank 3
Read Bank 3
Read Bank 3
Read
Bank 0
Precharge Bank 3
Precharge
Bank 0
Active Bank 0
Write Bank 3
Active Bank 3
Write Bank 3
Write Bank 3
Write
Bank 0
Precharge Bank 3
Precharge
CKE
RAS
CS
CAS
WE
Address
DQM,
DQMU/DQML
DQ (input)
DQ (output)
BS
High-Z
High-Z
45=EF
,
$
%&
/78@I
19:BCK
VIH
VIH
Read cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= V or V
IH IL
Write cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= V or V
!
IH IL
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
58
Read/Single Write Cycle
+45=
*+3
+34=
+34
45=>
#,45>
#+,4
#+,45
"#+4
@AHI
7@HI
0 1 2 3 4 5 6 7 8 9 1011121314151617181920
,
?H
NO
R:a C:a R:b C:a'
,
HI
,
HI
ENO
R:a C:a C:a
NO
,
a
a
a
a
7?@H
AIJ
@AIJ
8ABJ
8@AJ
/8@A
/78@
.78
,
Bank 0
Active Bank 0
Read Bank 3
Active Bank 0
Write Bank 0
Precharge Bank 3
Precharge
Bank 0
Active Bank 0
Read Bank 0
Write Bank 0
Precharge
N
"#+
R:b
Bank 3
Active
$
#
#
#
#
129:C
(19:
(019
'(019
,
I
,
HI
&'./8
&'/08
'(/08
'(0189
(0189B
C:a
Bank 0
Read
a a+1 a+2 a+3
@AI
'(/089A
9BCK
9ABK
089AB
089A
J
AJ
AIJ
@AIJ
Bank 0
Write Bank 0
Write
CKE
RAS
CS
CAS
WE
Address
DQM,
DQMU/DQML
DQ (input)
DQ (output)
CLK
BS
CKE
RAS
CS
CAS
WE
Address
DQM,
DQMU/DQML
BS
EMN
)
C:b
bc
a+1 a+3
a+1 a+2 a+3
C:c
GOP
EFMN
FNO
$,5>
,"
:;CDKL
VIH
VIH
Read/Single write
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= V or V
IH IL
DQ (input)
DQ (output)
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
59
Read/Burst Write Cycle
!)*3
)
!)*
!)
!*+3
!"+
!
!"
!
%.
%&.
%&./
&'./
2:;CDKL
CLM
LM
-67?
$-6>G
0 1 2 3 4 5 6 7 8 9 1011121314151617181920
?GHP
>FG
,
,
<DE
<EN
R:a C:a R:b C:a'
GP
>FGP
;<D
,
,
,
R:a C:a C:a
&/078?@I
&./78?@
%&-.67?
,
?HP
;<DE
,
a a+1 a+2 a+3
a+1
a a+1 a+2 a+3
,
,
,
,
-56>
67?@H
67?H
.7@
%.7
%-.7
$%-.
$%-
Bank 0
Active Bank 0
Read Bank 0
Write Bank 0
Precharge
LM
MN
DM
;DM
;CDM
%
R:b
Bank 3
Active
&'0
&'
&
&
%&-.6?
,
?@HI
,
?@HP
6?@HP
6?GP
6>?GOP
CKE
RAS
CS
CAS
WE
Address
DQM,
DQMU/DQML
CLK
BS
CKE
RAS
CS
CAS
WE
Address
DQM,
DQMU/DQML
BS
a+1 a+2 a+3
a a+3
a
&./67?@
DMN
)
KL
Bank 0
Active Bank 0
Read Bank 3
Active Clock
suspend Bank 0
Write Bank 0
Precharge Bank 3
Precharge
%
-6>?GOP
VIH
Read/Burst write
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= V or V
,
IH IL
DQ (input)
DQ (output)
DQ (input)
DQ (output)
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
60
Full Page Read/Write Cycle
High-Z
,
PZ[
R:a C:a R:b
,
Z[
DENO
:DN
:DEN
ENO
DEN
R:a C:a R:b
High-Z
,
Z[
R[\
QR[
GPQ[
R[\
GQR[
RS\
HQR
GH
HR\
GHQR
2;<EO
1:;E
1:;
2;EO
1;E
(2<
'(1
(2
(12
(1
$
$
Bank 0
Active Bank 0
Read Bank 3
Active Burst stop Bank 3
Precharge
Bank 0
Active Bank 0
Write Bank 3
Active Burst stop Bank 3
Precharge
6?@IRS
56?@HIR
56>?HIR
+56>?HR
+45>?H
"#+,56
#,-67@
#,-56@
"#,-56
#$
#$
#
IJST]
JST]
JT]^
T]^
S\]
"+,5
]^
]^
S]
()
()
(
(
(
IJRS\]
CKE
RAS
CS
CAS
WE
Address
DQM,
DQMU/DQML
DQ (input)
DQ (output)
CLK
BS
CKE
RAS
CS
CAS
WE
Address
DQM,
DQMU/DQML
BS
1:;DEMN
CDLMVW
4=>GHQ
VIH
VIH
a a+1 a+2 a+3
Read cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = full page
= V or V
IH IL
Write cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = full page
= V or V
IH IL
a a+1 a+2 a+3 a+6a+5a+4
DQ (input)
DQ (output)
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
61
Auto Refresh Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CLK
CKE
CS
CAS
WE
BS
Address
DQM,
DQMU/DQML
DQ (input)
DQ (output)
,
&'/078?@HI
,
,
DMN
%&
78@AHI
,
,
High-Z
RP
,
!)*12
19:C
P
,
8@AHI
,
,
/08
"+
?H
45
4<=EFMN
6?H
&'/
,
Precharge
If needed Auto Refresh Active
Bank 0
tRC
tRC
t
Auto Refresh Read
Bank 0
,
,
R:a C:a
A10=1
RAS
,
,
!)*2;
:;CL
,
,
8ABIJ
,
,
,
,
,
#$,45
9
<=
B
F
JK
,
,
a a+1
VIH
Refresh cycle and
Read cycle
RAS-CAS delay = 2
CAS latency = 2
Burst length = 4
= V or V
IH IL
Self Refresh Cycle
%&-.
CLK
CKE
CS
RAS
CAS
WE
BS
Address
DQM,
DQMU/DQML
DQ (input)
DQ (output)
$
)
,-
2
5
:;
>
BCKL
,
,
.78?@
,
/78?@I
,
,
*23;
2:;CD
:BCKL
,
$,5=>FNO
6?@H
.7?@H
(
-5>
$-
Precharge command
If needed Self refresh entry
command Auto
refresh
Self refresh exit
ignore command
or No operation
,
>GOP
(1
7@HI
FO
?@HI
FNO
,
CKE Low
,!"*23
7
:;
@
C
HI
L
A10=1
RC
t
RP
t
$
$,5=>EFNO
$,45=>EFMN
Self refresh cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= V or V
IH IL
High-Z
Next
clock
enable
6>FGOP
5=>FGO
,5=>EFO
RC
t
Next
clock
enable
lSREX
Self refresh entry
command
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
62
Clock Suspend Mode
DEMN
'(/09
(
LM
<DELM
!*+23
+34<=
GHP
0 1 2 3 4 5 6 7 8 9 1011121314151617181920
&
K
"+4
!")*23
+,4
R:a C:a R:b
a a+1 a+2 a+3 b b+1 b+2
!"*+
,
,
?H
,
,
R:a C:a R:b C:b
,
?HP
,
?HP
a a+1 a+2 b b+1 b+2 b+3
&
,
"*+
,
H
,
,
,
,
C:b
BKL
Bank0
Active Active clock
suspend start Active clock
supend end
Bank0
Read
Bank3
Active
Read suspend
start Read suspend
end Bank0
Precharge
Bank3
Read Earliest Bank3
Precharge
Bank0
Write
Bank0
Active Active clock
suspend start Active clock
suspend end Bank3
Active
Write suspend
start Write suspend
end Bank3
Write Bank0
Precharge Earliest Bank3
Precharge
,
,
,
L
L
KL
b+3
+34<
*+3<
,
,
;<DLM
;<CDL
2:;CDL
2:;BCL
78?@HI
%.67?H
.67?@H
78@AHI
'(/08
&'/08
&./
.78?@H
&'./8
%&
%
CKE
RAS
CS
CAS
WE
Address
DQM,
DQMU/DQML
CLK
BS
CKE
RAS
CS
CAS
WE
Address
DQM,
DQMU/DQML
BS
a+3
High-Z
High-Z
,"#,
5=>
,
,
()129:BK
./78@
,
,
tCES tCEH tCES
Read cycle
RAS-CAS delay = 2
CAS latency = 2
Burst length = 4
= V or V
IH IL
Write cycle
RAS-CAS delay = 2
CAS latency = 2
Burst length = 4
= V or V
IH IL
78@AHI
DQ (output)
DQ (input)
DQ (output)
DQ (input)
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
63
Power Down Mode
CLK
CKE
CS
RAS
CAS
WE
BS
Address
DQM,
DQMU/DQML
DQ (input)
DQ (output)
$,45=>EFNO
&'/08
&'/
!"
,
,
./67?@HP
,
,
,
,
!"+
,
,
,
,
%-.6>?GOP
!
%&
,
,
,
$%-56=>FGNO
%
Precharge command
If needed Power down entry
Active Bank 0
Power down
mode exit
8AIJ
,
'(/089
,
/89@AHIJ
"#+
/78?@H
,
/78?@HI
,
/78?@HI
CKE Low
R: a
,
,
,
A10=1
RP
t
,#
,
,
High-Z
Power down cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= V or V
IH IL
Initialization Sequence
78910 52 53 54
48 49 50 51
,
,
!()12:
GOP
Auto Refresh Bank active
If needed
RC
t
RC
t
Auto Refresh
Valid
CKL
0123456
CLK
CKE
CS
RAS
CAS
WE
Address
DQM,
DQMU/DQML
DQ
89ABJ
AIJ
7@AHI
.7?@H
t
valid
RSA
tRP
All banks
Precharge Mode register
Set
@AI
,
/89A
V
IH
V
IH
!*
!
!)
55
High-Z
'(/089A
,
,
,
34;<DEM
4<=DEMN
,
/78A
,
)
BCK
9BCK
6?GP
code
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
64
Package Dimensions
HM5264165FTT/FLTT
HM5264805FTT/FLTT
HM5264405FTT/FLTT Series (TTP-54D)
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
TTP-54D
—
—
0.53 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.13 M
0.10
0.80
54 28
127
22.22
22.72 Max
1.20 Max
10.16
0.13 ± 0.05
11.76 ± 0.20 0° – 5°
0.91 Max
*0.145 ± 0.05
0.28 ± 0.05
0.125 ± 0.04
*0.30+0.10
–0.05
0.50 ± 0.10
0.68
0.80
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
65
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
URL NorthAmerica : http:semiconductor.hitachi.com/
Europe : http://www.hitachi-eu.com/hel/ecg
Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm
Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan : http://www.hitachi.co.jp/Sicd/indx.htm
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Hitachi Europe GmbH
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
For further information write to:
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
66
Revision Record
Rev. Date Contents of Modification Drawn by Approved by
0.0 Jul. 17, 1998 Initial issue M. Takahashi J. Kitano
0.1 Dec. 28, 1998 Addition of HM5264165/HM5264805/
HM5264405FTT/FLTT-75 (133MHz)
Unification with HM5264165/HM5264805/
HM5264405FTT/FLTT-B6
Change of part number to HM5264165/HM5264805/
HM5264405F-75/A60/B60
Change figure of mode register configuration
DC Operating conditions
Change of notes 4 to 5
DC Characteristics (Common)
ICC2N max: —/20/— mA to 16/16/16 mA
ICC3P max: —/TBD/— mA to 4/4/4 mA
ICC3PS max: —/TBD/— mA to 3/3/3 mA
ICC3N max: —/30/— mA to 20/20/20 mA
ICC3NS max: —/20/— mA to 15/15/15 mA
ICC5 max: —/140/— mA to 115/115/115 mA
ICC6 max: —/TBD/— mA to 0.4/0.4/0.4 mA
DC Characteristics (HM5264165F)
ICC1 max(CL = 2): —/100/— mA to 85/75/70 mA
ICC1 max(CL = 3): —/100/— mA to 85/75/75 mA
ICC4 max (CL = 2): —/120/— mA to 90/90/70 mA
ICC4 max (CL = 3): —/120/— mA to 110/90/90 mA
DC Characteristics (HM5264805F)
ICC1 max(CL = 2): —/90/— mA to 80/70/65 mA
ICC1 max(CL = 3): —/90/— mA to 80/70/70 mA
ICC4 max (CL = 2): —/100/— mA to 80/80/65 mA
ICC4 max (CL = 3): —/100/— mA to 100/80/80 mA
DC Characteristics (HM5264405F)
ICC1 max(CL = 2): —/90/— mA to 80/70/65 mA
ICC1 max(CL = 3): —/90/— mA to 80/70/70 mA
ICC4 max (CL = 2): —/90/— mA to 70/70/60 mA
ICC4 max (CL = 3): —/90/— mA to 90/70/70 mA
AC Characteristics
tDPL min: —/15/— ns to 10/10/10 ns
Relationship between frequency and minimum latency
lDPL: —/2 to 2/1
lHZP (CL = 2): —/— to 2/2
lEP (CL = 2): —/— to –1/–1
lBSR (CL = 2): —/— to 1/1
lBSH (CL = 2): —/— to 2/2
K. Nishimoto J. Kitano
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
67
Revision Record (cont.)
Rev. Date Contents of Modification Drawn by Approved by
1.0 Nov. 10, 1999 Ordering information
Addition of notes 1 and 2
CKE Truth table
Clock suspend mode entry
CS: H to ×
Addition of description to clock suspend mode entry
DC Characteristics (common)
ICC2P max: 3/3/3 mA to 1.5/1.5/1.5 mA
ICC2PS max: 2/2/2 mA to 1/1/1 mA
ICC2N max: 16/16/16 mA to 10/10/10 mA
ICC2NS max: 9/9/9 mA to 5/5/5 mA
ICC3N max: 20/20/20 mA to 18/18/18 mA
ICC3NS max: 15/15/15 mA to 12/12/12 mA
ICC5 max:115/115/115 mA to 110/110/110 mA
DC Characteristics (HM5264165F)
ICC1 max (CL = 2): 85/75/70 mA to 65/65/65 mA
ICC1 max (CL = 3): 85/75/75 mA to 65/65/65 mA
ICC4 max (CL = 2): 90/90/70 mA to 65/65/65 mA
ICC4 max (CL = 3): 110/90/90 mA to 80/65/65 mA
DC Characteristics (HM5264805F)
ICC1 max (CL = 2): 80/70/65 mA to 60/60/60 mA
ICC1 max (CL = 3): 80/70/70 mA to 60/60/60 mA
ICC4 max (CL = 2): 80/80/65 mA to 60/60/60 mA
ICC4 max (CL = 3): 100/80/80 mA to 75/60/60 mA
DC Characteristics (HM5264405F)
ICC1 max (CL = 2): 80/70/65 mA to 60/60/60 mA
ICC1 max (CL = 3): 80/70/70 mA to 60/60/60 mA
ICC4 max (CL = 2): 70/70/60 mA to 55/55/55 mA
ICC4 max (CL = 3): 90/70/70 mA to 70/55/55 mA
Capacitance
CI1 max: 4 pF to 3.5 pF
CI2 max: 5 pF to 3.8 pF
Relationship Between Frequency and Minimum Latency
lAPW (-A60/B60): 4 to 3
