MAX13037/MAX13038
Automotive Contact Monitor and
Level Shifters with LDO Regulator
14 ______________________________________________________________________________________
Wetting Current (WET)
The MAX13037/MAX13038 feature adjustable wetting
current to any closed switch to clean switch contacts
that are exposed to adverse conditions. The wetting
current is set by connecting a 30kΩto 330kΩresistor
from WET to ground. A 30kΩresistor corresponds to a
wetting current of 40mA (typ) and a 330kΩresistor cor-
responds to a 4mA (typ) wetting current. See the
Typical Operating Characteristics
section for the rela-
tionship between the wetting current and RWET.
The WEN and WEND bits in the command register
enable and disable the wetting currents and the
WTOFF bit allows the wetting current to be activated for
a duration of 20ms (typ) (see the
Command Register
section). Disabling wetting currents, or limiting the
active wetting current time reduces power consump-
tion. The default state upon power-up is all wetting cur-
rents disabled.
Wetting current is activated on closed switches just
after the debounce time. The wetting current pulse
starts after the debounce time. A wetting current pulse
is provided to all closed switches when a valid input
change is detected. Wetting current rise and fall times
are controlled to enhance EMC performance. There is
one wetting current timer for all switch inputs.
Therefore, it is possible to observe wetting pulses
longer than expected whenever two switches turn on in
sequence and are spaced out less than tWET. In scan
mode, the wetting current is enabled during the polling
pulse only.
When using wetting currents, special care must be
taken to avoid exceeding the maximum power dissipa-
tion of the MAX13037/MAX13038 (see the
Applications
Information
section).
Switch Outputs (DO0, DO1)
DO0 and DO1 are direct level-shifted outputs of the
switch inputs IN0 and IN1 when the WEND bit of the
command register is cleared and when operating in
normal mode. When configured as direct inputs, the
wetting currents and sensing resistors are disabled on
IN0 and IN1. DO0 and DO1 are three-stated when the
WEND bit is set or when operating in scan mode.
When programmed as direct inputs, the status of IN0
and IN1 are not reflected in the status register and
interrupts are not allowed on these inputs.
Interrupt Output (
INT
)
INT is an active-low, open-drain output that asserts
when any of the switch inputs change state, as long as
the particular input is enabled for interrupts (set by
clearing P7–P0 in the command register). INT also
asserts when the first watchdog timeout period elapses
(tWD1). A pullup resistor to VLO is needed on INT. INT is
cleared when CS is driven low for a read/write operation.
The INT output still asserts when VLO is disabled pro-
vided that it is pulled up to a different supply voltage.
Thermal Protection (
OT
)
The MAX13037/MAX13038 feature a two-level thermal
protection strategy that prevents the device from being
damaged by overheating. At the initial warning temper-
ature of +135°C (typ), only wetting currents are dis-
abled. The MAX13037/MAX13038 return to normal
operation after the internal temperature decreases
below +120°C (typ). This protection feature is disabled
when WEN = 0 or when all inputs are open. At the sec-
ond thermal warning temperature of +170°C (typ), the
LDO is shut down. Because a µC is often supplied by
the LDO, an overheating event caused by excessive
power dissipation related to I/O wetting currents is nor-
mally resolved without affecting the µC status.
An open-drain, active-low output (OT) asserts low when
the internal temperature of the device rises above the
thermal warning threshold. OT is immediately cleared
when the CS input is driven low for read/write opera-
tions, regardless of whether the temperature is above
the threshold, or not. The overtemperature status of the
MAX13037/MAX13038 can also be monitored by read-
ing the OT bit in the status register. The OT bit is set
when the internal temperature rises above the tempera-
ture threshold, and it is cleared when the temperature
falls below the temperature hysteresis level. This allows
a µC to monitor the overtemperature status, even if the
OT output has been cleared. See Figure 6 for an exam-
ple timing diagram of the overtemperature alerts.
If desired, the OT and INT outputs can be connected
to the same µC GPIO in a wired-OR configuration to
save a µC pin. The OT output still asserts when VLis
absent provided that it is pulled up to a different sup-
ply voltage.