64Mb: 3V Embedded Parallel NOR Flash Features Parallel NOR Flash Embedded Memory M29W640GH, M29W640GL M29W640GT, M29W640GB Features * Common Flash interface - 64-bit security code * 128-word extended memory block - Extra block used as security block or to store additional information * Low power consumption: Standby and automatic mode * 100,000 PROGRAM/ERASE cycles per block * Electronic signature - Manufacturer code: 0020h * Device summary: part number and device code - M29W640GH: uniform, last block protected by VPP/WP# - 227Eh + 220Ch + 2201h - M29W640GL: uniform, first block protected by VPP/WP# - 227Eh + 220Ch + 2200h - M29W640GT: top boot block - 227Eh + 2210h + 2201h - M29W640GB: bottom boot block - 227Eh + 2210h + 2200h * RoHS-compliant packages - 48-pin TSOP (N/NA) 12mm x 20mm - 56-pin TSOP (NB) 14mm x 20mm - 48-ball TFBGA (ZA) 6mm x 8mm - 64-ball FBGA (ZS) 11mm x 13mm - 64-ball TBGA (ZF) 10mm x 13mm * Automotive certified parts available * Supply voltage - VCC = 2.7-3.6V (program, erase, read) - VPP = 12V for fast program (optional) * Asynchronous random/page read - Page width: 4 words - Page access: 25ns - Random access: 60ns, 70ns, 90ns * Fast program commands - 2-word/4-byte program (without V PP = 12V) - 4-word/8-byte program (with V PP = 12V) - 16-word/32-byte write buffer * Programming time - 10s per byte/word TYP - Chip program time: 10 s (4-word program) - Double word/quadruple byte program * Memory organization - M29W640GH/L 128 main blocks, 64KB each - M29W640GT/B 127 main blocks, 64KB each and 8 boot blocks, 8KB each * Program/erase controller - Embedded byte/word program algorithms * Program/erase suspend and resume - Read from any block during a PROGRAM SUSPEND operation - Read or program another block during an ERASE SUSPEND operation * Hardware block protection - VPP/WP# pin for fast program and write protect - Temporary block unprotect mode Part Numbering Information Available with extended memory block prelocked by Micron. Devices are shipped from the factory with memory content bits erased to 1. For available options, such as packages or speed, or for further information, contact your Micron sales representative. Part numbers can be verified at www.micron.com. Feature and specification comparison by device type is available at www.micron.com/products. Contact the factory for devices not found. Table 1: Part Number Information Part Number Category Device Type Category Details M29 = Parallel Flash memory PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 64Mb: 3V Embedded Parallel NOR Flash Features Table 1: Part Number Information (Continued) Part Number Category Category Details Operating Voltage W = 2.7 to 3.6V Device Function 640G = 64Mb (x8/x16) boot block, uniform or boot block Array Matrix T = Top boot B = Bottom boot L = First block protected by VPP/WP# H = Last block protected by VPP/WP# Speed 60 = 60ns (in conjunction with temperature range 6; denotes industrial grade -40C to 85C parts) 6A = 60ns (in conjunction with temperature range 6; denotes automotive grade -40C to 85C parts) 7A = 70ns (in conjunction with temperature range 6; denotes automotive grade -40C to 85C parts) 70 = 70ns (in conjunction with temperature range 6; denotes industrial grade -40C to 85C parts; temperature range = 3 denotes automotive grade -40C to 125C parts) 90 = 90ns (in conjunction with temperature range 6; denotes industrial grade -40C to 85C parts) Package N/NA = 48-pin TSOP, 12mm x 20mm NB = 56-pin TSOP, 14mm x 20mm (available upon request) ZA = 48-ball TFBGA, 6mm x 8mm, 0.8mm pitch ZS = 64-ball FBGA, 11mm x 13mm, 1mm pitch ZF = 64-ball TBGA, 10mm x 13mm, 1mm pitch (available upon request) Temperature Range 6 = -40C to 85C Shipping Options E = RoHS-compliant package, standard packing 3 = -40C to 125C (Automotive) F = RoHS-compliant package, tape and reel packing PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Features Contents Important Notes and Warnings ......................................................................................................................... 7 General Description ......................................................................................................................................... 8 Signal Assignments ......................................................................................................................................... 11 Signal Descriptions ......................................................................................................................................... 15 Memory Organization .................................................................................................................................... 18 Memory Configuration ............................................................................................................................... 18 Uniform Block Memory Map, x16 - 64Mb Density ........................................................................................ 18 Uniform Block Memory Map, x8 - 64Mb Density ......................................................................................... 18 Bus Operations ............................................................................................................................................... 19 Read .......................................................................................................................................................... 19 Write .......................................................................................................................................................... 19 Standby and Automatic Standby ................................................................................................................. 19 Output Disable ........................................................................................................................................... 20 Status Register ................................................................................................................................................ 20 Data Polling Bit (DQ7) ................................................................................................................................ 20 Toggle Bit (DQ6) ......................................................................................................................................... 20 Error Bit (DQ5) ........................................................................................................................................... 20 Erase Timer Bit (DQ3) ................................................................................................................................. 21 Alternative Toggle Bit (DQ2) ........................................................................................................................ 21 Write to Buffer and Program Abort Bit (DQ1) ............................................................................................... 21 READ Operations ........................................................................................................................................... 24 READ/RESET Command ............................................................................................................................ 24 READ CFI Command .................................................................................................................................. 25 AUTO SELECT Operations .............................................................................................................................. 26 AUTO SELECT Command ........................................................................................................................... 26 Command Interface ....................................................................................................................................... 29 READ/RESET Command ............................................................................................................................ 29 AUTO SELECT Command ........................................................................................................................... 29 READ CFI QUERY Command ...................................................................................................................... 29 PROGRAM Command ................................................................................................................................ 30 PROGRAM SUSPEND Command ................................................................................................................ 30 PROGRAM RESUME Command .................................................................................................................. 31 Fast Program Commands ............................................................................................................................ 31 DOUBLE BYTE PROGRAM Command ......................................................................................................... 31 QUADRUPLE BYTE PROGRAM Command .................................................................................................. 31 OCTUPLE BYTE PROGRAM Command ....................................................................................................... 31 DOUBLE WORD PROGRAM Command ....................................................................................................... 32 QUADRUPLE WORD PROGRAM Command ................................................................................................ 32 WRITE TO BUFFER AND PROGRAM Command .......................................................................................... 33 WRITE TO BUFFER AND PROGRAM CONFIRM Command .......................................................................... 34 WRITE TO BUFFER AND PROGRAM ABORT AND RESET Command ............................................................ 34 UNLOCK BYPASS Command ...................................................................................................................... 34 UNLOCK BYPASS PROGRAM Command ..................................................................................................... 34 UNLOCK BYPASS RESET Command ............................................................................................................ 35 CHIP ERASE Command .............................................................................................................................. 35 BLOCK ERASE Command ........................................................................................................................... 35 ERASE SUSPEND Command ....................................................................................................................... 36 ERASE RESUME Command ........................................................................................................................ 36 ENTER EXTENDED BLOCK Command ....................................................................................................... 36 EXIT EXTENDED BLOCK Command ........................................................................................................... 36 PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Features BLOCK PROTECT and CHIP UNPROTECT Commands ................................................................................ BLOCK PROTECT Command ...................................................................................................................... Programmer Technique .............................................................................................................................. In-System Technique .................................................................................................................................. Common Flash Interface ................................................................................................................................ Absolute Ratings and Operating Conditions ..................................................................................................... DC Characteristics .......................................................................................................................................... Read AC Characteristics .................................................................................................................................. Write AC Characteristics ................................................................................................................................. Toggle and Alternative Toggle AC Characteristics ............................................................................................. Program/Erase Characteristics ........................................................................................................................ Reset Characteristics ...................................................................................................................................... Package Dimensions ....................................................................................................................................... Revision History ............................................................................................................................................. Rev. E - 2/18 ............................................................................................................................................... Rev. D - 03/15 ............................................................................................................................................. Rev. C - 07/13 ............................................................................................................................................. Rev. B - 06/13 ............................................................................................................................................. Rev. A - 11/12 ............................................................................................................................................. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 4 37 37 37 40 47 52 54 55 58 62 64 68 69 74 74 74 74 74 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Features List of Figures Figure 1: Logic Diagram ................................................................................................................................... 9 Figure 2: 48-Pin TSOP .................................................................................................................................... 11 Figure 3: 56-Pin TSOP .................................................................................................................................... 12 Figure 4: 48-Ball TFBGA ................................................................................................................................. 13 Figure 5: 64-Ball TFBGA ................................................................................................................................. 14 Figure 6: Data Polling Flowchart .................................................................................................................... 23 Figure 7: Data Toggle Flowchart ..................................................................................................................... 24 Figure 8: Programmer Equipment Block Protect Flowchart ............................................................................. 38 Figure 9: Programmer Equipment Chip Unprotect Flowchart .......................................................................... 39 Figure 10: In-System Equipment Block Protect Flowchart ............................................................................... 41 Figure 11: In-System Equipment Chip Protect Flowchart ................................................................................ 42 Figure 12: AC Measurement Load Circuit ....................................................................................................... 53 Figure 13: AC Measurement I/O Waveform ..................................................................................................... 53 Figure 14: Random AC Timing ....................................................................................................................... 56 Figure 15: Page Read AC Timing ..................................................................................................................... 57 Figure 16: WE#-Controlled AC Timing ............................................................................................................ 59 Figure 17: CE#-Controlled AC Timing ............................................................................................................. 61 Figure 18: Toggle/Alternative Toggle, CE# Controlled ...................................................................................... 62 Figure 19: Toggle/Alternative Toggle, OE# Controlled ...................................................................................... 63 Figure 20: WE# Controlled Program Waveform ............................................................................................... 65 Figure 21: CE# Controlled Program Waveform ................................................................................................ 66 Figure 22: Chip/Block Erase Waveform .......................................................................................................... 67 Figure 23: Reset/Block Temporary Unprotect AC Waveforms ........................................................................... 68 Figure 24: Accelerated Programming Timing Waveform .................................................................................. 68 Figure 25: 48-Pin TSOP - 12mm x 20mm ........................................................................................................ 69 Figure 26: 56-Pin TSOP - 14mm x 20mm ........................................................................................................ 70 Figure 27: 48-Ball TFBGA - 6mm x 8mm ......................................................................................................... 71 Figure 28: 64-Ball TBGA - 10mm x 13mm ....................................................................................................... 72 Figure 29: 64-Ball FBGA - 11mm x 13mm ....................................................................................................... 73 PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Features List of Tables Table 1: Part Number Information ................................................................................................................... 1 Table 2: Signal Names ...................................................................................................................................... 9 Table 3: Protection Granularity on the M29W640GH and M29W640GL .............................................................. 9 Table 4: Protection Granularity on the M29W640GT ....................................................................................... 10 Table 5: Protection Granularity on the M29W640GB ....................................................................................... 10 Table 6: Signal Descriptions ........................................................................................................................... 15 Table 7: Hardware Protection ......................................................................................................................... 17 Table 8: x16 Uniform Blocks [127:0] ................................................................................................................ 18 Table 9: x8 Uniform Blocks [127:0] ................................................................................................................. 18 Table 10: Bus Operations ............................................................................................................................... 19 Table 11: Status Register Bits .......................................................................................................................... 21 Table 12: Read Electronic Signature ............................................................................................................... 26 Table 13: Block Protection ............................................................................................................................. 27 Table 14: Programmer Technique Bus Operations ........................................................................................... 40 Table 15: Commands - 16-Bit Mode (BYTE# = V IH) .......................................................................................... 43 Table 16: Commands - 8-Bit Mode (BYTE# = V IL) ............................................................................................ 45 Table 17: Query Structure Overview ............................................................................................................... 47 Table 18: CFI Query Identification String ........................................................................................................ 47 Table 19: CFI Query System Interface Information .......................................................................................... 48 Table 20: Device Geometry Definition ............................................................................................................ 48 Table 21: Primary Algorithm-Specific Extended Query Table ........................................................................... 49 Table 22: Security Code Area .......................................................................................................................... 51 Table 23: Absolute Maximum/Minimum Ratings ............................................................................................ 52 Table 24: Operating Conditions ...................................................................................................................... 52 Table 25: Input/Output Capacitance .............................................................................................................. 53 Table 26: DC Current Characteristics .............................................................................................................. 54 Table 27: DC Voltage Characteristics .............................................................................................................. 54 Table 28: Read AC Characteristics .................................................................................................................. 55 Table 29: WE#-Controlled Write AC Characteristics ......................................................................................... 58 Table 30: CE#-Controlled Write AC Characteristics ......................................................................................... 60 Table 31: Toggle and Alternative Toggle AC Characteristics .............................................................................. 62 Table 32: Program/Erase Times and Endurance Cycles ................................................................................... 64 Table 33: Reset/Block Temporary Unprotect AC Characteristics ...................................................................... 68 PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Important Notes and Warnings Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash General Description General Description The M29W640G is a 64Mb (8Mb x8 or 4Mb x16) nonvolatile memory that can be read, erased, and reprogrammed. These operations can be performed using a single low voltage (2.7-3.6V) supply. Upon power-up, the device defaults to read mode. The memory is divided into blocks that can be erased independently so that valid data can be preserved while old data is erased. PROGRAM and ERASE commands are written to the command interface of the memory. An on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all special operations required to update the memory contents. The end of a PROGRAM or ERASE operation can be detected and any error condition can be identified. The command set required to control the device is consistent with JEDEC standards. The M29W640GH and M29W640GL memory array is organized into 128 uniform blocks of 64KB each (or 32Kwords each). The M29W640GT and M29W640GB feature an asymmetric memory block, each having an array of 135 blocks divided into 8 parameter blocks of 8KB each (or 4 Kwords each), and 127 main blocks of 64KB each (or 32Kwords each). The M29W640GT has the parameter blocks at the top of the memory array whereas the M29W640GB locates the parameter blocks starting from the bottom. Blocks are protected by groups to prevent accidental PROGRAM or ERASE commands from modifying the memory. The M29W640G supports asynchronous random read and page read from all blocks of the array. Chip enable, output enable, and write enable signals control the bus operation. They enable simple connection to most microprocessors, often without additional logic. The V PP/WP# signal is used to enable faster programming of the device. Protection from PROGRAM/ERASE commands can be obtained by holding V PP/WP# to V SS: * On the M29W640GH and M29W640GL, the last and first blocks are protected. * On the M29W640GT and M29W640GB, the last two and first two boot blocks are protected. The M29W640G devices feature a full set of fast program commands to improve programming throughput: * 2-byte PROGRAM (it is not necessary to raise V PP/WP# to 12V before issuing this command) * 2 words/4-byte PROGRAM (it is not necessary to raise V PP/WP# to 12V before issuing this command) * 4 word/8-byte PROGRAM (VPP/WP# must be raised to 12V before issuing this command) * WRITE TO BUFFER and PROGRAM (enables program in one shot a buffer of 16 words/32 bytes) The M29W640G has an extra block, the extended block, of 128 words in x16 mode or 256 bytes in x8 mode that can be accessed using a dedicated command. The extended block can be protected, and therefore, is useful for storing security information. However, protection is not reversible; once protected, the protection cannot be undone. The memory is delivered with all bits erased (set to 1). PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash General Description Figure 1: Logic Diagram VCC VPP/WP# 15 22 DQ[14:0] A[21:0] DQ15/A-1 WE# CE# BYTE# OE# RY/BY# RST# VSS Table 2: Signal Names Name Description A0-A21 Direction Address inputs Inputs CE# Chip enable Input OE# Output enable Input WE# Write enable Input RP# Reset/Block temporary unprotect Input RY/BY# Ready/Busy Input BYTE# Byte/Word organization select Input DQ0-DQ7 Data input/outputs I/O DQ8-DQ14 Data input/outputs I/O Data input/output or address input (or data I/O) I/O DQ15A-1 (or DQ15) VCC VPP/WP# Supply voltage Supply voltage Supply voltage for FAST PROGRAM (optional) or WRITE PROTECT command Supply voltage VSS Ground - NC Not connected internally - Note: 1. VPP/WP# may be left floating because it is internally connected to a pull-up resistor to enable PROGRAM/ERASE commands. Table 3: Protection Granularity on the M29W640GH and M29W640GL Block 0 to 3 KB/Kwords 4 x 64/32 PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN Protection Block Group (x8) (x16) Block level 000000h-03FFFFh1 000000h-01FFFFh1 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash General Description Table 3: Protection Granularity on the M29W640GH and M29W640GL (Continued) Block KB/Kwords Protection Block Group (x8) (x16) 4 to 7 4 x 64/32 Protection group 040000h-07FFFFh 020000h-03FFFFh - - - - - 120 to 123 4 x 64/32 Protection group 780000h-7BFFFFh 3C0000h-3DFFFFh 124 to 127 4 x 64/32 Block level 7C0000h-7FFFFFh 3E0000h-3FFFFFh Note: 1. Used as the extended block addresses in extended block mode. Table 4: Protection Granularity on the M29W640GT Block KB/Kwords Protection Block Group (x8) (x16) 000000h-01FFFFh1 020000h-03FFFFh 0 to 3 4 x 64/32 Protection group 000000h-03FFFFh1 4 to 7 4 x 64/32 Protection group 040000h-07FFFFh - - - - - 120 to 123 4 x 64/32 Protection group 780000h-7BFFFFh 3C0000h-3DFFFFh 124 to 126 3 x 64/32 Protection group 7C0000h-7EFFFFh 3E0000h-3F7FFFh Block level 7F0000h-7FFFFFh 3F8000h-3FFFFFh 127 to 134 8x 8/42 Notes: 1. Used as the extended block addresses in extended block mode. 2. Boot blocks. Table 5: Protection Granularity on the M29W640GB Block KB/Kwords 0 to 7 8x 8/41 Protection Block Group (x8) (x16) Block level 000000h-00FFFFh2 000000h-007FFFh2 8 to 10 3 x 64/32 Protection group 010000h-03FFFFh 008000h-01FFFFh 11 to 14 4 x 64/32 Protection group 040000h-07FFFFh 020000h-03FFFFh - - - - - 127 to 130 4 x 64/32 Protection group 780000h-7BFFFFh 3C0000h-3DFFFFh 131 to 134 4 x 64/32 Protection group 7C0000h-7FFFFFh 3E0000h-3FFFFFh Notes: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. Boot blocks. 2. Used as the extended block addresses in extended block mode. 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Signal Assignments Signal Assignments Figure 2: 48-Pin TSOP A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RST# A21 VPP/WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 1. RFU = reserved for future use. 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Signal Assignments Figure 3: 56-Pin TSOP RFU RFU A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RST# A21 VPP/WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 RFU RFU 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN RFU RFU A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 RFU VCC 1. RFU = reserved for future use. 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Signal Assignments Figure 4: 48-Ball TFBGA 1 2 3 4 5 6 6 5 4 3 2 1 A A A7 RY/BY# WE# A3 A9 A13 A13 A9 WE# RY/BY# A7 A3 B B A4 A17 VPP/WP# RST# A8 A12 A12 A8 RST# VPP/WP# A17 A4 C C A2 A6 A18 A21 A10 A14 A14 A10 A21 A18 A6 A2 D D A1 A5 A20 A19 A11 A15 A15 A11 A19 A20 A5 A1 E E A0 D0 D2 D5 D7 A16 A16 D7 D5 D2 D0 A0 F F D8 CE# D10 D12 D14 BYTE# BYTE# D14 D12 D10 D8 CE# G G D9 OE# D11 VCC D13 D15/A-1 D15/A-1 D13 VCC D11 D9 OE# H H VSS D1 D3 D4 D6 VSS VSS Top view - ball side down Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN D6 D4 D3 D1 VSS Bottom view - ball side up 1. RFU = reserved for future use. 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Signal Assignments Figure 5: 64-Ball TFBGA 1 2 RFU A3 3 4 5 6 7 8 8 7 6 A9 A13 RFU RFU A13 A9 5 4 3 2 1 A3 RFU A A A7 RY/BY# WE# WE# RY/BY# A7 B B RFU A4 A17 VPP/WP# RST# A8 A12 RFU RFU A12 A8 RST# VPP/WP# A17 A4 RFU RFU A2 A6 A18 A10 A14 RFU RFU A14 A10 A21 A2 RFU VCC 1 VSS C C A21 A18 A6 D D RFU A1 A5 A20 A19 A11 A15 VCC1 RFU A0 D0 D2 D5 D7 A16 VSS A15 A11 A19 A20 A5 A1 RFU A16 D7 D5 D2 D0 A0 RFU 1 E E F F VCC1 CE# D8 D10 D12 D14 BYTE# RFU RFU BYTE# D14 D12 D10 D8 CE# VCC RFU OE# D9 D11 VCC D13 D15/A-1 RFU RFU D15/A-1 D13 VCC D11 D9 OE# RFU G G H H RFU VSS D1 D3 D4 D6 VSS RFU RFU Top view - ball side down Notes: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN VSS D6 D4 D3 D1 VSS RFU Bottom view - ball side up 1. RFU = reserved for future use. 2. Pads D8 and F1 are connected on the M29W640GT and M29W640GB devices. 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Signal Descriptions Signal Descriptions The following table is a comprehensive list of signals for this device family. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device. Table 6: Signal Descriptions Name Type Description A[MAX:0] Input Address: Select the cells in the memory array to access during bus READ operations. During bus WRITE operations they control the commands sent to the command interface of the program/erase controller. CE# Input Chip enable: Activates the memory, allowing bus READ and bus WRTE operations to be performed. When CE# is HIGH, all other pins are ignored. OE# Input Output enable: Controls the bus READ operation of the memory. WE# Input Write enable: Controls the bus WRITE operation of the memory's command interface. VPP/WP# Input VPP/WP#: Provides two functions: VPP enables the memory to use an external high-voltage power supply to reduce the time required for UNLOCK BYPASS PROGRAM operations. WP# performs hardware protection by protection the last block at the end of the addressable area (M29W640GH) or the first block at the beginning of the addressable area (M29W640GL). It protects the last two blocks at the end of the addressable area (M29W640GT) and the first two boot blocks at the beginning of the addressable area (M29W640GB). VPP/WP# may be left floating or unconnected (see DC Characteristics). When VPP/WP# is LOW, the last or first block in the M29W640GH and M29W640GL, respectively, and the last or first two blocks in the M29W640GT and M29W640GB, respectively, are protected. PROGRAM and ERASE operations in this block are ignored while VPP/WP# is LOW, even when RST# is at VID. When VPP/WP# is HIGH, VIH, the device reverts to the previous protection status of the outermost blocks. PROGRAM and ERASE operations can now modify the data in the outermost blocks unless the block is protected using block protection. Applying 12V to VPP/WP# will temporarily unprotect any block previously protected (including the outermost blocks) using a high-voltage block protection technique (in-system or programmer technique). (See Hardware Protection for details. When VPP/WP# is raised to VPP, the device automatically enters the unlock bypass mode. When VPP/WP# returns to VIH or VIL, normal operation resumes. During UNLOCK BYPASS PROGRAM operations, the device draws IPP from the pin to supply the programming circuits. (See UNLOCK BYPASS Command.) The transitions from VIH to VPP and from VPP to VIH must be slower than tVHVPP (See the Accelerated Program Timing waveforms). Never raise VPP/WP# to VPP from any mode except read mode; otherwise, the device may be left in an indeterminate state. A 0.1F capacitor should be connected between VPP/WP# and the VSS ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during an UNLOCK BYPASS PROGRAM operation, IPP. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Signal Descriptions Table 6: Signal Descriptions (Continued) Name Type DQ15/A-1 I/O Description Data I/O or address input: When HIGH, behaves as a data I/O pin (as DQ8-DQ14). When LOW, behaves as an address pin; DQ15A-1 LOW will select the LSB of the addressed word; DQ15A-1 HIGH will select the MSB. Throughout the text, consider references to the data I/O to include this pin when BYTE# is HIGH and references to the address inputs to include this pin when BYTE# is LOW, except when stated explicitly otherwise. RST# Input Reset/Block temporary unprotect: Applies a hardware reset to the memory or temporarily unprotect all blocks that have been protected. Note that if VPP/WP is at VIL, then the last and the first block in the M29W640GH and M29W640GL, respectively, and the last two and first two blocks in the M29W640GT and M29W640GB, respectively, will remain protected, even if RST# is at VID. A hardware reset is achieved by holding RST# LOW for at least tPLPX. After RST# goes HIGH, the memory will be ready for bus READ and bus WRITE operations after tPHEL or tRHEL, whichever occurs last. (See Reset Characteristics for more details.) Holding RST# at VID will temporarily unprotect the protected blocks in the memory. PROGRAM and ERASE operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. DQ[14:8] I/O Data I/O: Outputs the data stored at the selected address during a bus READ operation when BYTE# is HIGH. When BYTE# is LOW, these pins are not used and are High-Z. During bus WRITE operations, the command register does not use these bits. When reading the status register these bits should be ignored. DQ[7:0] I/O Data I/O: Outputs the data stored at the selected address during a bus READ operation. During bus WRITE operations, they represent the commands sent to the command interface of the program/erase controller. RY/BY# Output Ready busy: Open-drain output that identifies when the device is performing a PROGRAM or ERASE operation. During PROGRAM or ERASE operations, RY/BY# is LOW, and is High-Z during read mode, auto select mode, and erase suspend mode. After a hardware reset, bus READ and WRITE operations cannot begin until RY/BY# becomes High-Z. (See Reset Characteristics for more details.) The use of an open-drain output enables RY/BY# pins from several devices to be connected to a single pull-up resistor. A LOW will then indicate that one, or more, of the devices is busy. BYTE# Input PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN BYTE#/Word organization select: Switches between the x8 and x16 bus modes of the device. When LOW, the device is in x8 mode; when HIGH, it is in x16 mode. 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Signal Descriptions Table 6: Signal Descriptions (Continued) Name Type VCC Supply Description Supply voltage: Provides the power supply for all operations (READ, PROGRAM, and ERASE). The command interface is disabled when the VCC supply voltage is less than the lockout voltage, VLKO. This prevents bus WRITE operations from accidentally damaging the data during power-up, power-down, and power surges. If the program/erase controller is programming or erasing during this time, then the operation aborts and the memory contents being altered will be invalid. A 0.1 F capacitor should be connected between the VCC supply voltage pin and the VSS ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during PROGRAM and ERASE operations, ICC3. VSS Supply RFU - Ground: Reference for all voltage measurements. The device features two VSS pins which must be both connected to the system ground. Reserved for future use: RFUs should be not connected. Table 7: Hardware Protection VPP/WP# VIL RST# VIH Function M29W640GT Last 2 blocks at the end of the addressable area (M29W640GT) and first 2 blocks at and the beginning of the addressable area (M29W640GB) protected from program/ M29W640GB erase operations M29W640GH Last block at the end of the addressable area (M29W640GH) and first block at the and beginning of the addressable area (M29W640GL) protected from program/erase M29W640GL operations VID M29W640GT All blocks temporarily unprotected except the last 2 blocks at the end of the adand dressable area (M29W640GT) and first 2 blocks at the beginning of the addressaM29W640GB ble area (M29W640GB) M29W640GH All blocks temporarily unprotected except the last block at the end of the addressand able area (M29W640GH) and first block at the beginning of the addressable area M29W640GL (M29W640GL) VIH or VID VID All blocks temporarily unprotected VPP VIH or VID All blocks temporarily unprotected PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Memory Organization Memory Organization Memory Configuration The memory array for M29W640GH and M29W640GL devices is organized into 128 uniform blocks of 64KB each for x8 and 32KW each for x16. Uniform Block Memory Map, x16 - 64Mb Density Table 8: x16 Uniform Blocks [127:0] Address Range Block Block Size Start End 127 32KW 003F 8000 003F FFFF 126 32KW 003F 0000 003F 7FFF 125 32KW 003E 8000 003E FFFF 124 32KW 003E 0000 003E 7FFF 3 32KW 0001 8000 0001 FFFF 2 32KW 0001 0000 0001 7FFF 1 32KW 0000 8000 0000 FFFF 0 32KW 0000 0000 0000 7FFF Note: Notes 1 1. Used as the extended block addresses when the device is in extended block mode. Uniform Block Memory Map, x8 - 64Mb Density Table 9: x8 Uniform Blocks [127:0] Address Range Block Block Size Start End 127 64KB 007F 0000 007F FFFF 126 64KB 007E 0000 007E FFFF 125 64KB 007D 0000 007D FFFF 124 64KB 007C 0000 007C FFFF 3 64KB 0003 0000 0003 FFFF 2 64KB 0002 0000 0002 FFFF 1 64KB 0001 0000 0001 FFFF 0 64KB 0000 0000 0000 FFFF Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN Notes 1 1. Used as the extended block addresses when the device is in extended block mode. 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Bus Operations Bus Operations Table 10: Bus Operations Notes 1 and 2 apply to entire table 8-Bit Mode Operation READ CE# OE# L 16-Bit Mode WE# A[MAX:0], DQ15/A-1 DQ[14:8] DQ[7:0] A[MAX:0] DQ15/A-1, DQ[14:0] H Cell address High-Z Data output Cell address Data output input4 Command address Data input4 L WRITE L H L Command address High-Z STANDBY H X X X High-Z High-Z X High-Z OUTPUT DISABLE X H H X High-Z High-Z X High-Z Notes: Data 1. Typical glitches of less than 5ns on CE# and WE# are ignored by the device and do not affect bus operations. 2. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW. 3. If WP# = LOW, the highest/lowest block remains protected, depending on the line item. 4. Data input is required when issuing a command sequence or performing data polling or block protection. Read Bus READ operations read from the memory cells, registers, or CFI space. A valid READ operation requires setting the appropriate address on the address inputs, taking CE# and OE# LOW and holding WE# HIGH. Data I/O signals output the value. Write Bus WRITE operations write to the command interface. A valid WRITE operation requires setting the appropriate address on the address inputs. These are latched by the command interface on the falling edge of CE# or WE#, whichever occurs last. Values on data I/O signals are latched by the command interface on the rising edge of CE# or WE#, whichever occurs first. OE# must remain HIGH during the entire operation. Standby and Automatic Standby When the device is in read mode, driving CE# HIGH places the device in standby mode and drives data I/Os to High-Z. Supply current is reduced to standby (ICC2), by holding CE# within V CC 0.2V. During PROGRAM or ERASE operations, the device continues to use the program/erase supply current (ICC3) until the operation completes. Automatic standby enables low power consumption during read mode. When CMOS levels (VCC 0.2 V) drive the bus, and following a READ operation and a period of inactivity specified in DC Characteristics, the memory enters automatic standby as internal supply current is reduced to ICC2. Data I/O signals still output data if a READ operation is in progress. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Status Register Output Disable Data I/Os are High-Z when OE# is HIGH. Status Register Bus READ operations from any address, always read the status register during PROGRAM and ERASE operations. It is also read during erase suspend when an address within a block being erased is accessed. Data Polling Bit (DQ7) The data polling bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. The data polling bit is output on DQ7 when the status register is read. During PROGRAM operations, DQ7 outputs the complement of the bit being programmed to DQ7. After successful completion of the PROGRAM operation, the memory returns to read mode and bus READ operations from the address just programmed output DQ7, not its complement. During ERASE operations DQ7 outputs 0, the complement of the erased state of DQ7. After successful completion of the ERASE operation the memory returns to read mode. In erase suspend mode, DQ7 will output a 1 during a bus READ operation within a block being erased. DQ7 will change from a 0 to a 1 when the program/erase controller has suspended the ERASE operation. The Data Polling Flowchart gives an example of how to use DQ7. A valid address is the address being programmed or an address within the block being erased. Toggle Bit (DQ6) The toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. The toggle bit is output on DQ6 when the status register is read. During PROGRAM and ERASE operations, DQ6 changes from 0 to 1 to 0, and so forth, with successive bus READ operations at any address. After successful completion of the operation, the memory returns to read mode. During erase suspend mode, DQ6 will output when addressing a cell within a block being erased. DQ6 will stop toggling when the program/erase controller has suspended the ERASE operation. The Data Toggle Flowchart gives an example of how to use DQ6 and the toggle and alternative toggle waveforms describe toggle bit timing. Error Bit (DQ5) The error bit can be used to identify errors detected by the program/erase controller. DQ5 is set to 1 when a PROGRAM, BLOCK ERASE, or CHIP ERASE operation fails to write the correct data to the memory. If DQ5 is set, a READ/RESET command must be issued before other commands are issued. The error bit is output on DQ5 when the status register is read. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Status Register Note that the PROGRAM command cannot change a bit set to 0 back to 1 and attempting to do so will set DQ5 to 1. A bus READ operation to that address will show the bit remains 0. One of the ERASE commands must be used to set all the bits in a block or in the whole memory from 0 to 1. Erase Timer Bit (DQ3) The erase timer bit can be used to identify the start of program/erase controller operation during a BLOCK ERASE command. After the program/erase controller starts erasing, DQ3 is set to 1. Before the program/erase controller starts, DQ3 is set to 0 and additional blocks to be erased may be written to the command interface. The erase timer bit is output on DQ3 when the status register is read. Alternative Toggle Bit (DQ2) The alternative toggle bit can be used to monitor the program/erase controller during ERASE operations. It is output on DQ2 when the status register is read. During CHIP ERASE and BLOCK ERASE operations, DQ2 changes from 0 to 1 to 0, and so forth, with successive bus READ operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. After the operation completes, the memory returns to read mode. During erase suspend, DQ2 changes from 0 to 1 to 0, and so forth, with successive bus READ operations from addresses within the blocks being erased. Bus READ operations to addresses within blocks not being erased will output the memory cell data as if in read mode. After an ERASE operation that causes DQ5 to be set, DQ2 can be used to identify which block or blocks have caused the error. DQ2 changes from 0 to 1 to 0, and so forth, with successive bus READ operations from addresses within blocks that have not erased correctly. DQ2 does not change if the addressed block has erased correctly. Write to Buffer and Program Abort Bit (DQ1) DQ1 is set to 1 when a WRITE TO BUFFER AND PROGRAM operation aborts. Otherwise, DQ1 is set to 0. The WRITE TO BUFFER AND PROGRAM ABORT AND RESET command must be issued to return the device to read mode (see Command Interface for more information). Table 11: Status Register Bits Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/BY# PROGRAM Any address DQ7# Toggle 0 - - 0 0 PROGRAM DURING ERASE SUSPEND Any address DQ7# Toggle 0 - - - 0 WRITE TO BUFFER AND PROGRAM ABORT Any address DQ7# Toggle 0 - - 1 0 WRITE TO BUFFER AND PROGRAM Any address DQ7# Toggle 0 - - 0 0 PROGRAM ERROR Any address DQ7# Toggle 1 - - - High-Z PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Status Register Table 11: Status Register Bits (Continued) Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/BY# CHIP ERASE Any address 0 Toggle 0 1 Toggle - 0 BLOCK ERASE BEFORE TIMEOUT Erasing block 0 Toggle 0 0 Toggle - 0 Non-erasing block 0 Toggle 0 0 No Toggle - 0 BLOCK ERASE ERASE SUSPEND Erasing block 0 Toggle 0 1 Toggle - 0 Non-erasing block 0 Toggle 0 1 No Toggle - 0 Erasing block 1 No Toggle 0 - Toggle - High-Z - High-Z Non-erasing block ERASE ERROR Data read as normal Good block address 0 Toggle 1 1 No Toggle - High-Z Faulty block address 0 Toggle 1 1 Toggle - High-Z Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. Unspecified data bits should be ignored. 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Status Register Figure 6: Data Polling Flowchart Start Read DQ7 and DQ5 at valid 1 address Yes DQ7 = Data No No DQ5 = 1 Yes Read DQ7 at valid address DQ7 = Data Yes No Failure PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN Success 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash READ Operations Figure 7: Data Toggle Flowchart Start Read DQ6 at valid address Read DQ6 and DQ5 at valid address DQ6 = Toggle No Yes No DQ5 = 1 Yes Read DQ6 (twice) at valid address DQ6 = Toggle No Yes Failure Success READ Operations READ/RESET Command The READ/RESET (F0h) command returns the device to read mode and resets the errors in the status register. One or three bus WRITE operations can be used to issue the READ/RESET command. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash READ Operations To return the device to read mode, this command can be issued between bus WRITE cycles before the start of a PROGRAM or ERASE operation. If the READ/RESET command is issued during the timeout of a BLOCK ERASE operation, the device requires up to 10s to abort, during which time no valid data can be read. READ CFI Command The READ CFI (98h) command puts the device in read CFI mode and is valid only when the device is in read array or auto select mode. One bus WRITE cycle is required to issue the command. Once in read CFI mode, bus READ operations will output data from the CFI memory area. A READ/RESET command must be issued to return the device to the previous mode (read array or auto select ). A second READ/RESET command is required to put the device in read array mode from auto select mode. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash AUTO SELECT Operations AUTO SELECT Operations AUTO SELECT Command At power-up or after a hardware reset, the device is in read mode. It can then be put in auto select mode by issuing an AUTO SELECT (90h) command or by applying V ID to A9. Auto select mode enables the following device information to be read: * Electronic signature, which includes manufacturer and device code information. * Block protection, which includes the block protection status and extended memory block protection indicator. Electronic signature or block protection information is read by executing a READ operation with control signals and addresses set. Auto select mode can be used by the programming equipment to automatically match a device with the application code to be programmed. Three consecutive bus WRITE operations are required to issue an AUTO SELECT command. The device remains in auto select mode until a READ/RESET or READ CFI command is issued. The device cannot enter auto select mode when a PROGRAM or ERASE operation is in progress (RY/BY# LOW). However, auto select mode can be entered if the PROGRAM or ERASE operation has been suspended by issuing a PROGRAM SUSPEND or ERASE SUSPEND command. To enter auto select mode by applying V ID to A9 (see the following tables). Auto select mode is exited by performing a reset. The device returns to read mode unless it entered auto select mode after an ERASE SUSPEND or PROGRAM SUSPEND command, in which case it returns to erase or program suspend mode. Table 12: Read Electronic Signature Note 1 applies to entire table READ Cycle Signal Manufactur- Device Code er Code 1 Device Code 2 Device Code 3 GH/GL GT/GB GH/GT GL/GB CE# L L L L L L OE# L L L L L L WE# H H H H H H X X X X X X A9 VID VID VID VID VID VID A8 X X X X A[7:5] L L L L A4 X X X X A[3:1] L L H H A0 L H L H Note s Address Input, 8-Bit and 16-Bit A[MAX:10] 2 Address Input, 8-Bit Only PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash AUTO SELECT Operations Table 12: Read Electronic Signature (Continued) Note 1 applies to entire table READ Cycle Manufactur- Device Code er Code 1 Signal DQ[15]/A-1 Device Code 2 GH/GL Note s Device Code 3 GT/GB GH/GT GL/GB X X X X DQ[14:8] X X X X DQ[7:0] 20h 7Eh 0Ch 10h 01h 00h 0020h 227Eh 220Ch 2210h 2201h 2200h Data I/O, 8-Bit Only Data I/O, 16-Bit Only DQ[15]/A-1, and DQ[14:0] Notes: 1. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW. 2. When using the AUTO SELECT command to enter auto select mode, applying VID to A9 is not required. A9 can be either VIL or VIH. Table 13: Block Protection Note 1 applies to entire table Address Input Operation CE# OE# WE # BLOCK PROTECT (Group) L VID LP CHIP UNPROTECT VID VID LP VERIFY BLOCK PROTECTION L L H VERIFY BLOCK UNPROTECT L L READ BLOCK PROTECTION STATUS L L PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN A[MA A[14:1 X] A15 3] A12 Data I/O A[11:1 A[8:7 A[5:4 A[3: DQ[15]/A-1, 0] A9 ] A6 ] 2] A1 A0 DQ[14:0] Block address X VID X X X VID X X Block address X VID X L X L H L Pass = xx01h Retry = xx00h H Block address X VID X H X L H L Retry = xx01h Pass = xx00h H Block address X VID X L X L H L Protected (x8) = 01h Unprotected (x8) = 00h Protected (x16) = 0001h Unprotected (x16) = 0000h X H X H 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash AUTO SELECT Operations Table 13: Block Protection (Continued) Note 1 applies to entire table Address Input Operation CE# OE# WE # A[MA A[14:1 X] A15 3] A12 Data I/O A[11:1 A[8:7 A[5:4 A[3: DQ[15]/A-1, 0] A9 ] A6 ] 2] A1 A0 DQ[14:0] GL, GT, GB READ EXTENDED MEMORY BLOCK verify CODE L L H Block address X VID X L X L H H Factorylocked = 98h Customerlockable = 18h L L H Block address X VID X L X L H H Factorylocked = 81h Customerlockable = 01h GH READ EXTENDED memory BLOCK verify CODE Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW. 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface Command Interface All bus WRITE operations to the memory are interpreted by the command interface. Commands consist of one or more sequential bus WRITE operations. Failure to observe a valid sequence of bus WRITE operations will result in the memory returning to read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16-bit or 8-bit mode. See the x8 and x16 command tables, depending on the configuration that is being used, for a summary of the commands. READ/RESET Command The READ/RESET command returns the memory to its read mode. It also resets the errors in the status register. Either one or three bus WRITE operations can be used to issue the READ/RESET command. The READ/RESET command can be issued, between bus WRITE cycles before the start of a PROGRAM or ERASE operation, to return the device to read mode. If the READ/ RESET command is issued during the timeout of a BLOCK ERASE operation, then the device will take up to 10s to abort. During the abort period, no valid data can be read from the device. The READ/RESET command will not abort an ERASE operation when issued while in erase suspend. AUTO SELECT Command The AUTO SELECT command is used to read the manufacturer code, the device code, the block protection status, and the extended memory block verify code. Three consecutive bus WRITE operations are required to issue the AUTO SELECT command. After the AUTO SELECT command is issued, the memory remains in auto select mode until a READ/RESET command is issued. READ CFI QUERY and READ/RESET commands are accepted in auto select mode, all other commands are ignored. In auto select mode, the manufacturer code and the device code can be read by using a bus READ operation with addresses and control signals set, as shown Bus Operations, except for A9 (which is "Don't Care"). The block protection status of each block can be read using a bus READ operation with addresses and control signals set, as shown in Bus Operations, except for A9 (which is "Don't Care"). If the addressed block is protected, then 01h is output on DQ0-DQ7; otherwise, 00h is output (in 8-bit mode). The protection status of the extended memory block, or extended memory block verify code, can be read using a bus READ operation with addresses and control signals, except for A9 (which is "Don't Care"). If the extended block is "factory-locked." then 80h is output on DQ0-DQ7; otherwise, 00h is output (8-bit mode). READ CFI QUERY Command The READ CFI QUERY command is used to read data from the CFI. This command is valid when the device is in the read array mode, or when the device is in auto select mode. One bus WRITE cycle is required to issue the READ CFI QUERY command. After the command is issued, subsequent bus READ operations read from the CFI. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface The READ/RESET command must be issued to return the device to the previous mode (the read array mode or auto select mode). A second READ/RESET command would be needed if the device is to be put in the read array mode from auto selected mode. PROGRAM Command The PROGRAM command can be used to program a value to one address in the memory array at a time. The command requires four bus WRITE operations; the final WRITE operation latches the address and data, and starts the program/erase controller. Programming can be suspended and then resumed by issuing a PROGRAM SUSPEND command and a PROGRAM RESUME command, respectively. If the address falls in a protected block, then the PROGRAM command is ignored, the data remains unchanged. The status register is never read and no error condition is given. During a PROGRAM operation, the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Bus READ operations during the PROGRAM operation will output the status register on the data I/Os. (See Status Register for more details.) After the PROGRAM operation has completed, the memory will return to the read mode, unless an error has occurred. When an error occurs, the memory will continue to output the status register. A READ/RESET command must be issued to reset the error condition and return to read mode. Note that the PROGRAM command cannot change a bit set to 0 back to 1. One of the ERASE commands must be used to set all the bits in a block or in the whole memory from 0 to 1. (Refer to Program/Erase Characteristics.) PROGRAM SUSPEND Command The PROGRAM SUSPEND command allows the system to interrupt a PROGRAM operation so that data can be read from any block. When the PROGRAM SUSPEND command is issued during a PROGRAM operation, the device suspends the PROGRAM operation within the program suspend latency time and updates the status register bits (see Program/Erase Characteristics). After the PROGRAM operation has been suspended, the system can read array data from any address. However, data read from program-suspended addresses is not valid. The PROGRAM SUSPEND command may also be issued during a PROGRAM operation while an erase is suspended. In this case, data may be read from any addresses not in ERASE SUSPEND or PROGRAM SUSPEND. If a read is needed from the extended block area (one-time program area), the user must use the proper command sequences to enter and exit this region. The system may also issue the AUTO SELECT command sequence when the device is in the program suspend mode. The system can read as many auto select codes as required. When the device exits the auto select mode, the device reverts to the program suspend mode, and is ready for another valid operation. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface PROGRAM RESUME Command After the PROGRAM RESUME command is issued, the device reverts to programming. The controller can determine the status of the PROGRAM operation using the DQ7 or DQ6 status bits, just as in the standard PROGRAM operation. The system must write the PROGRAM RESUME command, to exit the program suspend mode and to continue the programming operation. Further issuing of the RESUME command is ignored. Another PROGRAM SUSPEND command can be written after the device has resumed programming. Fast Program Commands There are five fast program commands available to improve the programming throughput, by writing several adjacent words or bytes in parallel: * QUADRUPLE and OCTUPLE BYE PROGRAM, available for x8 operations * DOUBLE and QUADRUPLE WORD PROGRAM, available for x16 operations * WRITE TO BUFFER AND PROGRAM Fast program commands can be suspended and then resumed by issuing a PROGRAM SUSPEND command and a PROGRAM RESUME command, respectively. DOUBLE BYTE PROGRAM Command The DOUBLE BYTE PROGRAM command is used to write a page of two adjacent bytes in parallel. The two bytes must differ only in DQ15A-1. Three bus WRITE cycles are necessary to issue the DOUBLE BYTE PROGRAM command: The first bus cycle sets up the DOUBLE BYTE PROGRAM command; the second bus cycle latches the address and the data of the first byte to be written; and the third bus cycle latches the address and the data of the second byte to be written. It is not necessary to raise V PP/WP# to 12V before issuing this command. QUADRUPLE BYTE PROGRAM Command The QUADRUPLE BYTE PROGRAM command is used to write a page of four adjacent bytes in parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles are necessary to issue the QUADRUPLE BYTE PROGRAM command: The first bus cycle sets up the QUADRUPLE BYTE PROGRAM command; the second bus cycle latches the address and the data of the first byte to be written; the third bus cycle latches the address and the data of the second byte to be written; the fourth bus cycle latches the address and the data of the third byte to be written; and the fifth bus cycle latches the address and the data of the fourth byte to be written and starts the program/ erase controller. It is not necessary to raise V PP/WP# to 12V before issuing this command. OCTUPLE BYTE PROGRAM Command This is used to write eight adjacent bytes, in x8 mode, simultaneously. The addresses of the eight bytes must differ only in A1, A0 and DQ15A-1. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface 12V must be applied to V PP/Wp# prior to issuing an OCTUPLE BYTE PROGRAM command. Care must be taken because applying a 12V voltage to V PP/WP#, because it will temporarily unprotect any protected block. Nine bus WRITE cycles are necessary to issue the command: The first bus cycle sets up the command; the second bus cycle latches the address and the data of the first byte to be written; the third bus cycle latches the address and the data of the second byte to be written; the fourth bus cycle latches the address and the data of the third byte to be written, the fifth bus cycle latches the address and the data of the fourth byte to be written; the sixth bus cycle latches the address and the data of the fifth byte to be written; the seventh bus cycle latches the address and the data of the sixth byte to be written; the eighth bus cycle latches the address and the data of the seventh byte to be written; and the ninth bus cycle latches the address and the data of the eighth byte to be written and starts the program/erase controller. DOUBLE WORD PROGRAM Command The DOUBLE WORD PROGRAM command is used to write a page of two adjacent words in parallel. The two words must differ only for the address A0. Three bus WRITE cycles are necessary to issue the DOUBLE WORD PROGRAM command: The first bus cycle sets up the DOUBLE WORD PROGRAM command; the second bus cycle latches the address and the data of the first word to be written; and the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller. After the PROGRAM operation has completed, the memory will return to the read mode, unless an error has occurred. When an error occurs, bus READ operations will continue to output the status register. A READ/RESET command must be issued to reset the error condition and return to read mode. Note that the fast program commands cannot change a bit set to 0 back to 1. One of the ERASE commands must be used to set all the bits in a block or in the whole memory from 0 to 1. Typical program times are given in Program/Erase Characteristics. Note: It is not necessary to raise V PP/WP# to 12V before issuing this command. QUADRUPLE WORD PROGRAM Command This is used to write a page of four adjacent words (or 8 adjacent bytes), in x16 mode, simultaneously. The addresses of the four words must differ only in A1 and A0. 12V must be applied to V PP/WP# prior to issuing a QUADRUPLE BYTE PROGRAM command. Care must be taken because applying a 12V voltage to V PP/WP#, because it will temporarily unprotect any protected block. Five bus WRITE cycles are necessary to issue the command: The first bus cycle sets up the command; the second bus cycle latches the address and the data of the first word to be written; the third bus cycle latches the address and the data of the second word to be written; the fourth bus cycle latches the address and the PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface data of the third word to be written; and the fifth bus cycle latches the address and the data of the fourth word to be written and starts the program/erase controller. WRITE TO BUFFER AND PROGRAM Command The WRITE TO BUFFER AND PROGRAM command makes use of the device's 32-byte write buffer to speed up programming. 16 words/32 bytes can be loaded into the write buffer. Each write buffer has the same A4-A22 addresses. The WRITE TO BUFFER AND PROGRAM command dramatically reduces system programming time compared to the standard nonbuffered PROGRAM command. When issuing a WRITE TO BUFFER AND PROGRAM command, V PP/WP# can be either held HIGH or raised to V PPH. Five successive steps are required to issue the WRITE TO BUFFER AND PROGRAM command: The WRITE TO BUFFER AND PROGRAM command starts with two UNLOCK cycles. The third bus WRITE cycle sets up the WRITE TO BUFFER AND PROGRAM command. The setup code can be addressed to any location within the targeted block. The fourth bus WRITE cycle sets up the number of words to be programmed. Value n is written to the same block address, where n + 1 is the number of words to be programmed. The value of n + 1 must not exceed the size of the write buffer or the operation will abort. The fifth cycle loads the first address and data to be programmed. The value of n bus WRITE cycles is used to load the address and data for each word into the write buffer. Addresses must lie within the range from the start address+1 to the start address + n - 1. Optimum performance is obtained when the start address corresponds to a 64-byte boundary. If the start address is not aligned to a 64-byte boundary, the total programming time is doubled. All the addresses used in the WRITE TO BUFFER AND PROGRAM operation must lie within the same page. If an address is written several times during a WRITE TO BUFFER AND PROGRAM operation, the address/data counter will be decremented at each data load operation, and the data will be programmed to the last word loaded into the buffer. Invalid address combinations or failing to follow the correct sequence of bus WRITE cycles will abort the WRITE TO BUFFER AND PROGRAM operation. DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status during a WRITE TO BUFFER AND PROGRAM operation. It is possible to detect PROGRAM operation fails when changing programmed data from 0 to 1; that is, when reprogramming data in a portion of memory already programmed. The resulting data will be the logical OR between the previous value and the current value. To program the content of the write buffer, this command must be followed by a WRITE TO BUFFER AND PROGRAM CONFIRM command. A WRITE TO BUFFER AND PROGRAM ABORT AND RESET command must be issued to abort the WRITE TO BUFFER AND PROGRAM operation and reset the device in read mode. The write buffer programming sequence can be aborted in the following ways: * Load a value that is greater than the page buffer size during the number of locations to program step * Write to an address in a block different than the one specified during the WRITE-BUFFER-LOAD command * Write an address/data pair to a different write-buffer-page than the one selected by the starting address during the write buffer data loading stage of the operation PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface * Write data other than the CONFIRM command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5 = 0. A WRITE TO BUFFER ABORT AND RESET command sequence must be written to reset the device for the next operation. Note that the full three-cycle WRITE TO BUFFER ABORT AND RESET command sequence is required when using write-buffer-programming features in unlock bypass mode. WRITE TO BUFFER AND PROGRAM CONFIRM Command The WRITE TO BUFFER AND PROGRAM CONFIRM command is used to confirm a WRITE TO BUFFER AND PROGRAM command and to program the n + 1 words loaded in the write buffer by this command. WRITE TO BUFFER AND PROGRAM ABORT AND RESET Command The WRITE TO BUFFER AND PROGRAM ABORT AND RESET command is used to reset the device after a WRITE TO BUFFER AND PROGRAM command has been aborted. UNLOCK BYPASS Command The UNLOCK BYPASS command is used in conjunction with the UNLOCK BYPASS PROGRAM command to program the memory faster than with the standard PROGRAM commands. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three bus WRITE operations are required to issue the UNLOCK BYPASS command. After the UNLOCK BYPASS command has been issued, the memory will only accept the UNLOCK BYPASS PROGRAM command and the UNLOCK BYPASS RESET command. The memory can be read as if in read mode. When V PP is applied to V PP/WP#, the memory automatically enters the unlock bypass mode and the UNLOCK BYPASS PROGRAM command can be issued immediately. UNLOCK BYPASS PROGRAM Command The UNLOCK BYPASS command is used in conjunction with the UNLOCK BYPASS PROGRAM command to program the memory. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three bus WRITE operations are required to issue the UNLOCK BYPASS command. After the UNLOCK BYPASS command has been issued, the memory will only accept the UNLOCK BYPASS PROGRAM command and the UNLOCK BYPASS RESET command. The memory can be read as if in read mode. The memory offers accelerated PROGRAM operations through V PP/WP#. When the system asserts V PP on V PP/WP#, the memory automatically enters the unlock bypass mode. The system may then write the two-cycle UNLOCK BYPASS PROGRAM command sequence. The memory uses the higher voltage on V PP/WP# to accelerate the UNLOCK BYPASS PROGRAM operation. Never raise V PP/WP# to V PP from any mode except read mode; otherwise, the memory may be left in an indeterminate state. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface UNLOCK BYPASS RESET Command The UNLOCK BYPASS RESET command can be used to return to read/reset mode from unlock bypass mode. Two bus WRITE operations are required to issue the UNLOCK BYPASS RESET command. A READ/RESET command does not exit from unlock bypass mode. CHIP ERASE Command The CHIP ERASE command can be used to erase the entire chip. Six bus WRITE operations are required to issue the CHIP ERASE command and start the program/erase controller. If any blocks are protected, then these are ignored and all the other blocks are erased. If all of the blocks are protected the CHIP ERASE operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the ERASE operation the memory will ignore all commands, including the ERASE SUSPEND command. It is not possible to issue any command to abort the operation. All bus READ operations during the CHIP ERASE operation will output the status register on the data I/Os. After the CHIP ERASE operation has completed, the memory will return to the read mode, unless an error has occurred. When an error occurs the memory will continue to output the status register. A READ/RESET command must be issued to reset the error condition and return to read mode. The CHIP ERASE command sets all of the bits in unprotected blocks of the memory to 1. All previous data is lost. BLOCK ERASE Command The BLOCK ERASE command can be used to erase a list of one or more blocks. Six bus WRITE operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth bus WRITE operation using the address of the additional block. The BLOCK ERASE operation starts the program/erase controller about 50s after the last bus WRITE operation. After the program/erase controller starts, it is not possible to select any more blocks. Each additional block must therefore be selected within 50s of the last block. The 50s timer restarts when an additional block is selected. The status register can be read after the sixth bus WRITE operation. ( See the status register section for details on how to identify whether the program/ erase controller has started the BLOCK ERASE operation.) If any selected blocks are protected, then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected, the BLOCK ERASE operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the BLOCK ERASE operation, the memory will ignore all commands except the ERASE SUSPEND command. (Typical block erase times are given in the Program/Erase Characteristics.) All bus READ operations during the BLOCK ERASE operation will output the status register on the data I/Os. After the BLOCK ERASE operation has completed, the memory will return to the read mode, unless an error has occurred. When an error occurs, the memory will continue to PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface output the status register. A READ/RESET command must be issued to reset the error condition and return to read mode. The BLOCK ERASE command sets all of the bits in the unprotected selected blocks to 1. All previous data in the selected blocks is lost. ERASE SUSPEND Command The ERASE SUSPEND command may be used to temporarily suspend a BLOCK ERASE operation and return the memory to read mode. The command requires one bus WRITE operation. The program/erase controller will suspend within the erase suspend latency time of the ERASE SUSPEND command being issued. After the program/erase controller has stopped, the memory will be set to read mode and the erase will be suspended. If the ERASE SUSPEND command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts), then the erase is suspended immediately and will start immediately when the ERASE RESUME command is issued. It is not possible to select any further blocks to erase after the ERASE RESUME. During ERASE SUSPEND, it is possible to read and program cells in blocks that are not being erased; both READ and PROGRAM operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block, then the PROGRAM command is ignored and the data remains unchanged. The status register is not read and no error condition is given. Reading from blocks that are being erased will output the status register. It is also possible to issue the AUTO SELECT, READ CFI QUERY, and UNLOCK BYPASS commands during an ERASE SUSPEND. The READ/RESET command must be issued to return the device to read array mode before the RESUME command will be accepted. ERASE RESUME Command The ERASE RESUME command must be used to restart the program/erase controller after an erase suspend. The device must be in read array mode before the RESUME command will be accepted. An erase can be suspended and resumed more than once. ENTER EXTENDED BLOCK Command The device has an extra 256-byte block (extended block) that can only be accessed using the ENTER EXTENDED BLOCK command. Three bus WRITE cycles are required to issue the ENTER EXTENDED BLOCK command. After the command has been issued, the device enters extended block mode where all bus READ or WRITE operations to the boot block addresses access the extended block. The extended block (with the same address as the boot blocks) cannot be erased, and can be treated as OTP memory. In extended block mode, the boot blocks are not accessible. The extended block can be protected; however, once protected, the protection cannot be undone. EXIT EXTENDED BLOCK Command The EXIT EXTENDED BLOCK command is used to exit from the extended block mode and return the device to read mode. Four bus WRITE operations are required to issue the command. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface BLOCK PROTECT and CHIP UNPROTECT Commands Groups of blocks can be protected against accidental program or erase. (See Memory Organization for the protection groups.) The whole chip can be unprotected to allow the data inside the blocks to be changed. BLOCK PROTECT Command Block protection can be used to prevent any operation from modifying the data stored in the Flash. Each block can be protected individually. Once protected, PROGRAM and ERASE operations on the block fail to change the data. There are three techniques that can be used to control block protection. These are programmer technique, in-system technique, and temporary unprotect. Temporary unprotect is controlled by RST#. Unlike the command interface of the program/erase controller, the techniques for protecting and unprotecting blocks change between different Flash memory suppliers. Care should be taken when changing drivers for one part to work on another. Programmer Technique The programmer technique uses high voltage levels (VID) on some of the bus pins. These cannot be achieved using a standard microprocessor bus; therefore, the technique is recommended only for use in programming equipment. To protect a block, follow the steps in the following figure. To unprotect the whole chip, it is necessary to protect all of the blocks first, then all blocks can be unprotected at the same time. (See the Programmer Equipment Chip Protect Flowchart.) The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface Figure 8: Programmer Equipment Block Protect Flowchart START Set-up ADDRESS = BLOCK ADDRESS WE# = VIH n=0 OE#, A9 = VID , CE# = V IL Protect Wait 4 s WE# = VIL Wait 100 s WE# = VIH CE#, OE# = VIH ; A0, A2, A3, A6 = V IL ; A1 = VIH ; A9 = V ID ; others = X CE# = VIL Wait 4 s Verify OE# = V IL Wait 60ns Read DATA DATA = 01h NO YES A9 = V IH CE#, OE# = V IH ++n = 25 NO End YES PASS A9 = V IH CE#, OE# = VIH FAIL PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface Figure 9: Programmer Equipment Chip Unprotect Flowchart START Set-up PROTECT ALL BLOCKS n=0 CURRENT BLOCK = 0 A6, A12, A15 = V IH CE#, OE#, A9 = V ID Unprotect Wait 4s WE# = V IL Wait 10ms WE# = V IH CE#, OE# = V IH ADDRESS = CURRENT BLOCK ADDRESS A0, A2, A3 = V IL ; A1, A6 = V IH ; A9 = VID ; Others = X CE# = VIL Wait 4s OE# = VIL INCREMENT CURRENT BLOCK Verify Wait 60ns Read DATA NO NO DATA = 00h LAST ++n YES YES End NO BLOCK = 1000 PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN YES A9 = VIH CE#, OE# = V IH A9 = VIH CE#, OE# = V IH FAIL PASS 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface Table 14: Programmer Technique Bus Operations Notes 1 and 2 apply to entire table Operation Address Inputs Data I/Os CE# OE# WE# A[MAX:0] DQ15/A-1, DQ[14:0] BLOCK PROTECT L VID L pulse A9 = VID A[21:12] block addresses others = X X CHIP UNPROTECT VID VID L pulse A9 = VID A12 = VIH A15 = VIH others = X X BLOCK PROTECTION VERIFY L L VIH A0, A2, A3 = VIL A1 = VIH A6 = VIL A9 = VID A[21:12] block addresses others = X Pass = XX01h Retry = XX00h BLOCK UNPROTECT VERIFY L L VIH A0, A2, A3 = VIL A1 = VIH A6 = VIH A9 = VID A[21:12] block addresses others = X Retry = XX01h Pass = XX00h 1. Typical glitches of less than 5ns on CE# and WE# are ignored by the device and do not affect bus operations. 2. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW. Notes: In-System Technique The in-system technique requires a high-voltage level on RST#. This can be achieved without violating the maximum ratings of the components on the microprocessor bus; therefore, this technique is suitable for use after the Flash has been fitted to the system. To protect a block, follow the steps in the following figure. To unprotect the whole chip, it is necessary to protect all of the blocks first, then all the blocks can be unprotected at the same time. (See the In-System Equipment Chip Unprotect Flowchart.) The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface Figure 10: In-System Equipment Block Protect Flowchart Set-up START n=0 RST# = VID WRITE 60h ADDRESS = BLOCK ADDRESS A0, A2, A3 = VIL ; A1 = VIH ; A6 = VIL Protect WRITE 60h ADDRESS = BLOCK ADDRESS A0, A2, A3 = VIL ; A1 = VIH ; A6 = VIL Wait 100s WRITE 40h ADDRESS = BLOCK ADDRESS Verify A0, A2, A3 = VIL ; A1 = VIH ; A6 = VIL Wait 4s READ DATA ADDRESS = BLOCK ADDRESS A0, A2, A3 = VIL ; A1 = VIH ; A6 = VIL DATA = 01h NO YES ++n End RST# = VIH ISSUE READ/RESET COMMAND PASS NO = 25 YES RST# = VIH ISSUE READ/RESET COMMAND FAIL PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface Figure 11: In-System Equipment Chip Protect Flowchart START PROTECT ALL BLOCKS Set-up n=0 CURRENT BLOCK = 0 RST# = VID WRITE 60h ANY ADDRESS WITH A0, A2, A3 = VIL ; A1 = VIH ; A6 = VIH WRITE 60h Unprotect ANY ADDRESS WITH A0, A2, A3 = VIL ; A1 = VIH ; A6 = VIH Wait 10ms WRITE 40h ADDRESS = CURRENT BLOCK ADDRESS Verify A0, A2, A3 = VIL ; A1 = VIH ; A6 = VIH Wait 4s INCREMENT CURRENT BLOCK READ DATA ADDRESS = CURRENT BLOCK ADDRESS A0, A2, A3 = VIL ; A1 = VIH ; A6 = VIH NO End NO DATA = 00h ++n LAST = 1000 BLOCK YES NO YES RST# = VIH RST# = VIH ISSUE READ/RESET COMMAND ISSUE READ/RESET COMMAND PASS FAIL PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN YES 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface Table 15: Commands - 16-Bit Mode (BYTE# = VIH) Bus WRITE Operations 1st 2nd Command Length Addr Data READ/RESET 1 X F0 3rd Addr Data Addr 4th Data 3 555 AA 2AA 55 X F0 AUTO SELECT 3 555 AA 2AA 55 555 90 READ CFI QUERY 1 55 98 PROGRAM 4 555 AA 2AA 55 555 A0 DOUBLE WORD PROGRAM 3 555 50 PA0 PD0 PA1 PD1 QUADRUPLE WORD PROGRAM 5 555 56 PA0 PD0 PA1 PD1 UNLOCK BYPASS 3 555 AA 2AA 55 555 20 UNLOCK BYPASS PROGRAM 2 X A0 PA PD UNLOCK BYPASS RESET 2 X 90 X 00 WRITE TO BUFFER AND PROGRAM N+5 555 AA 2AA 55 BA 25 5th Addr Data PA PD PA2 BA 6th Addr Data PD2 PA3 PD3 N PA PD #ID1-389 #ID1-389 WRITE TO BUFFER AND PROGRAM ABORT AND RESET 3 WRITE TO BUFFER AND PROGRAM CONFIRM 1 555 AA BA 29 2AA 55 555 F0 2AA 55 555 80 Addr Data WBL PD #ID1-389 / / / note_98 note_0B note_0E4 C39A774 6F5BDF5 1314B3A A2647E7 13B4BD5 C04D50A A884636 B3607A8 C51D0FA F7461B6 8ABAC28 1046037 DA BF AA 2AA 2 #ID1-389 / note_565 5C246AF 734A209 3427626 3BD0616 3 CHIP ERASE 6 PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 555 AA 43 555 55 555 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface Table 15: Commands - 16-Bit Mode (BYTE# = VIH) (Continued) Bus WRITE Operations 1st 2nd 3rd 4th 5th 6th Command Length Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data BLOCK ERASE 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 PROGRAM/ ERASE SUSPEND 1 X B0 PROGRAM/ ERASE RESUME 1 X 30 ENTER EXTENDED BLOCK 3 555 AA 2AA 55 555 88 EXIT EXTENDED BLOCK 4 555 AA 2AA 55 555 90 X 00 Notes: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. X = " Don't Care;" PA = Program address; PD = Program data; BA = Any address in the block. All values in the table are in hexadecimal. The command interface only uses A-1; A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are "Don't Care." DQ15A-1 is A-1 when BYTE# is VIL or DQ15 when BYTE# is VIH. 2. The maximum number of cycles in the command sequence is 36. N + 1 is the number of words to be programmed during the WRITE TO BUFFER AND PROGRAM operation. 3. Each buffer has the same A4-A22 addresses. A0-A3 are used to select a word within the N + 1 word page. 4. The 6th cycle has to be issued N time. WBL scans the word inside the page. 5. BA must be identical to the address loaded during the WRITE TO BUFFER AND PROGRAM 3rd and 4th cycles. 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface Table 16: Commands - 8-Bit Mode (BYTE# = VIL) Bus WRITE Operations 1st Command Data 3rd 4th Addr Data Addr Data AA 555 55 X F0 AAA AA 555 55 AAA 90 1 AA 98 PROGRAM 4 AAA AA 555 55 AAA A0 DOUBLE BYTE PROGRAM 3 AAA 50 PA0 PD0 PA1 PD1 QUADRUPLE BYTE PROGRAM 5 AAA 56 PA0 PD0 PA1 OCTUPLE BYTE PROGRAM 9 AAA 8B PA0 PD0 WRITE TO BUFFER AND PROGRAM N+5 AAA AA 555 WRITE TO BUFFER AND PROGRAM ABORT AND RESET 3 AAA AA WRITE TO BUFFER AND PROGRAM CONFIRM 1 BA 6 29 UNLOCK BYPASS 3 AAA UNLOCK BYPASS PROGRAM 2 UNLOCK BYPASS RESET 5th Addr Data PA PD PD1 PA2 PA1 PD1 55 BA 25 555 55 AAA F0 AA 555 55 AAA 20 X A0 PA PD 2 X 90 X 00 CHIP ERASE 6 AAA AA 555 55 AAA BLOCK ERASE 6+ AAA AA 555 55 AAA PROGRAM/ ERASE SUSPEND 1 X B0 PROGRAM/ ERASE RESUME 1 X 30 READ/RESET Length Addr 2nd 1 X F0 3 AAA AUTO SELECT 3 READ CFI QUERY PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 45 6th Addr Data Addr Data PD2 PA3 PD3 PA2 PD2 PA3 PD3 PA4 PD4 2 BA N2 PA 4 PD WBL 5 PD 80 AAA AA 555 55 AAA 10 80 AAA AA 555 55 BA 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Command Interface Table 16: Commands - 8-Bit Mode (BYTE# = VIL) (Continued) Bus WRITE Operations 1st Command Length Addr 2nd 3rd 4th Data Addr Data Addr Data ENTER EXTENDED BLOCK 3 AAA AA 555 55 AAA 88 EXIT EXTENDED BLOCK 4 AAA AA 555 55 AAA 90 Notes: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 5th Addr Data X 00 Addr Data 6th Addr Data 1. X = " Don't Care;" PA = Program address; PD = Program data; BA = Any address in the block. All values in the table are in hexadecimal. The command interface only uses A-1, A0-A10, and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14, and DQ15 are "Don't Care." DQ15A-1 is A-1 when BYTE# is VIL or DQ15 when BYTE# is VIH. 2. The following is content for address: Data cycles 7 through 10: PA5-PD5, PA6-PD6, PA7- PD7, PA8-PD8. 3. The maximum number of cycles in the command sequence is 68. N + 1 is the number of words to be programmed during the WRITE TO BUFFER AND PROGRAM operation. 4. Each buffer has the same A4-A22 addresses. A0-A3 and DQ15A-1 are used to select a word within the N + 1 word page. 5. The 6th cycle has to be issued N time. WBL scans the word inside the page. 6. BA must be identical to the address loaded during the WRITE TO BUFFER AND PROGRAM 3rd and 4th cycles. 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Common Flash Interface Common Flash Interface The common Flash interface (CFI) is a JEDEC-approved, standardized data structure that can be read from the Flash memory device. It allows a system's software to query the device to determine various electrical and timing parameters, density information, and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the READ CFI command is issued, the device enters CFI query mode and the data structure is read from memory. The following tables show the addresses (A-1, A[7:0]) used to retrieve the data. The query data is always presented on the lowest order data outputs (DQ[7:0]), and the other data outputs (DQ[15:8]) are set to 0. Table 17: Query Structure Overview Note 1 applies to the entire table Address x16 x8 Subsection Name Description 10h 20h CFI query identification string Command set ID and algorithm data offset 1Bh 36h System interface information Device timing and voltage information 27h 4Eh Device geometry definition Flash device layout 40h 80h Primary algorithm-specific extended query table Additional information specific to the primary algorithm (optional) 61h C2h Security code area 64-bit unique device number Note: 1. Query data are always presented on the lowest order data outputs (DQ[7:0]). DQ[15:8] are set to 0. Table 18: CFI Query Identification String Note 1 applies to the entire table Address x16 x8 Data Description 10h 20h 0051h Query unique ASCII string "QRY" 11h 22h 0052h "R" 12h 24h 0059h "Y" 13h 14h 26h 28h 0002h 0000h Primary algorithm command set and control interface ID code 16-bit ID code defining a specific algorithm 15h 16h 2Ah 2Ch 0040h 0000h Address for primary algorithm extended query table (see the Primary Algorithm-Specific Extended Query Table) 17h 18h 2Eh 30h 0000h 0000h Alternate vendor command set and control interface ID code second vendor-specified algorithm supported - 19h 1Ah 32h 34h 0000h 0000h Address for alternate algorithm extended query table - Note: 1. Query data are always presented on the lowest order data outputs (DQ[7:0]). DQ[15:8] are set to 0. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN Value 47 "Q" AMD compatible P = 40h Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Common Flash Interface Table 19: CFI Query System Interface Information Note 1 applies to the entire table Address x16 x8 Data Description Value 1Bh 36h 0027h VCC logic supply minimum program/erase voltage Bits[7:4] BCD value in volts Bits[3:0] BCD value in 100mV 2.7V 1Ch 38h 0036h VCC logic supply maximum program/erase voltage Bits[7:4] BCD value in volts Bits[3:0] BCD value in 100mV 3.6V 1Dh 3Ah 00B5h VPPH (programming) supply minimum program/erase voltage Bits[7:4] hex value in volts Bits[3:0] BCD value in 100mV 11.5V 1Eh 3Ch 00C5h VPPH (programming) supply maximum program/erase voltage Bits[7:4] hex value in volts Bits[3:0] BCD value in 100mV 12.5V 1Fh 3Eh 0004h Typical timeout for single byte/word program = 2ns 16s 20h 40h 0004h Typical timeout for maximum size buffer program = 21h 42h 000Ah Typical timeout per individual block erase = 2nms 22h 23h 44h 0000h 46h 0004h Typical timeout for full chip erase = 2ns 2nms 2n times typical 24h 48h 0004h Maximum timeout for buffer program = 25h 4Ah 0003h Maximum timeout per individual block erase = 2n times typical 26h 4Ch 0000h Note: Maximum timeout for chip erase = 2n 1s - Maximum timeout for byte/word program = 2n 16s times typical times typical 256s 200s 8s - 1. The values in this table are valid for both packages. Table 20: Device Geometry Definition Address x16 x8 Data Description 27h 4Eh 0017h Device size = 2n in number of bytes 28h 29h 50h 52h 0002h 0000h Flash device interface code description 2Ah 2Bh 54h 56h 0005h 0000h Maximum number of bytes in multi-byte program or page = 2n 32 2Ch 58h 0001h Number of erase block regions. It specifies the number of regions containing contiguous erase blocks of the same size. M29W640GH and M29W640GL devices only 1 0002h Number of erase block regions. It specifies the number of regions containing contiguous erase blocks of the same size. M29W640GT and M29W640GB devices only 2 0007h 0000h Region 1 information Number of identical-size erase blocks = 007Fh + 1 M29W640GH and M29W640GL devices only 2Dh 2Eh 5Ah 5Ch PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN Value 48 8MB x8, x16 asynchronous 128 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Common Flash Interface Table 20: Device Geometry Definition (Continued) Address x16 x8 Data Description Value 2Fh 30h 5Eh 60h 0000h 0000h Region 1 information Block size in region 1 = 0100h x 256 bytes M29W640GH and M29W640GL devices only 64KB 2Dh 2Eh 5Ah 5Ch 0007h 0000h Region 1 information Number of identical-size erase blocks = 0007h + 1 M29W640GT and M29W640GB devices only 2Fh 30h 5Eh 60h 0020h 0000h Region 1 information Block size in region 1 = 0200h x 256 bytes M29W640GT and M29W640GB devices only 8KB 31h 32h 62h 64h 007Eh 0000h Region 2 information Number of identical-size erase blocks = 007Eh + 1 M29W640GT and M29W640GB devices only 127 33h 34h 66h 68h 0000h 0001h Region 2 information Block size in region 2 = 0100h x 256 bytes M29W640GT and M29W640GB devices only 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0000h 0000h Region 3 information Number of identical-size erase blocks = 0000h + 1 Region 3 information Block size in region 3 = 0000h x 256 bytes M29W640GT and M29W640GB devices only 0 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h Region 4 information Number of identical-size erase blocks = 0000h + 1 Region 4 information Block size in region 4 = 0000h x 256 bytes M29W640GT and M29W640GB devices only 0 Note: 8 64KB 1. For bottom boot devices, erase block region 1 is located from address 000000h to 007FFFh and erase block region 2 from address 008000h to 3FFFFFh. For top boot devices, erase block region 1 is located from address 000000h to 3F7FFFh and erase block region 2 from address 3F8000h to 3FFFFFh. Table 21: Primary Algorithm-Specific Extended Query Table Note 1 applies to the entire table Address x16 x8 Data Description 40h 80h 0050h Primary algorithm extended query table unique ASCII string "PRI" 41h 82h 0052h "R" 42h 84h 0049h "I" 43h 86h 0031h Major version number, ASCII "1" 44h 88h 0033h Minor version number, ASCII "3" PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN Value 49 "P" Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Common Flash Interface Table 21: Primary Algorithm-Specific Extended Query Table (Continued) Note 1 applies to the entire table Address x16 x8 Data Description 45h 8Ah 0000h Address sensitive unlock (bits[1:0]): 00 = Required 01 = Not required Silicon revision number (bits[7:2]) 00 46h 8Ch 0002h Erase suspend: 00 = Not supported 01 = Read only 02 = Read and write 2 47h 8Eh 0004h Block protection: 00 = Not supported x = Number of blocks per group 4 48h 90h 0001h Temporary block unprotect: 00 = Not supported 01 = Supported 01 49h 92h 0004h Block protect/unprotect 04 4Ah 94h 0000h Simultaneous operations: Not supported 4Bh 96h 0000h Burst mode: 00 = Not supported 01 = Supported 00 4Ch 98h 0001h Page mode: 00 = Not supported 01 = 4-word page; 02 = 8-word page 01 4Dh 9Ah 00B5h VPPH supply minimum program/erase voltage: Bits[7:4] hex value in volts Bits[3:0] BCD value in 100mV 11.5V 4Eh 9Ch 00C5h VPPH supply maximum program/erase voltage: Bits[7:4] hex value in volts Bits[3:0] BCD value in 100mV 12.5V 4Fh 9Eh 00xxh Top/bottom boot block flag: xx = 02h: M29W640GB bottom boot device xx = 03h M29W640GT top boot device xx = 04h M29W640GL first block protected by VPP/WP# xx = 05h: M29W640GH, last block protected by VPP/WP# 50h A0h 0001h Program suspend: 00 = Not supported 01 = Supported Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN Value - Uniform + VPP/WP# protecting highest or lowest block 01 1. The values in this table are valid for both packages. 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Common Flash Interface Table 22: Security Code Area Address x16 x8 Data Description 61h C3h, C2h XXXX 64-bit unique device number 62h C5h, C4h XXXX 63h C7h, C6h XXXX 64h C9h, C8h XXXX PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Absolute Ratings and Operating Conditions Absolute Ratings and Operating Conditions Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 23: Absolute Maximum/Minimum Ratings Parameter Symbol Min Max Unit Temperature under bias TBIAS -50 125 C Storage temperature TSTG -65 150 C Input/output voltage VIO -0.6 VCC + 0.6 V Supply voltage VCC -0.6 4 V Program voltage VPP -0.6 13.5 V Identification voltage VID -0.6 13.5 V Notes: Notes 1, 2 3 1. During signal transitions, minimum voltage may undershoot to -2V for periods less than 20ns. 2. During signal transitions, maximum voltage may overshoot to VCC + 2V for periods less than 20ns. 3. VPP must not remain at 12V for more than a total of 80 hours. Table 24: Operating Conditions M29W640GT/B and M29W640GH/L Parameter Symbol Min Max Unit Supply voltage VCC 2.7 3.6 V -40 Ambient operating temperature TA Load capacitance CL Input rise and fall times - Input pulse voltages - 0 to VCC V Input and output timing reference voltages - VCC/2 V Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 85/125 30 - C Notes 1 pF 10 ns 1. 85C = industrial part; 125C = autograde part. 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Absolute Ratings and Operating Conditions Figure 12: AC Measurement Load Circuit VCC VCC VPP 25k Device under test CL 0.1F Note: 25k 0.1F 1. CL includes jig capacitance. Figure 13: AC Measurement I/O Waveform VCCQ VCCQ/2 0V Table 25: Input/Output Capacitance Parameter Input capacitance Output capacitance Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN Symbol Test Condition Min Max Unit CIN VIN = 0V - 6 pF COUT VOUT = 0V - 12 pF 1. Sampled only, not 100% tested. 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash DC Characteristics DC Characteristics Table 26: DC Current Characteristics Parameter Input leakage current Symbol Conditions Typ Max Unit Notes ILI 0V VIN VCC - 1 A 1 - Output leakage current ILO 0V VOUT VCC 1 A Read current ICC1 CE# = VIL, OE# = VIH, f = 6 MHz 10 mA Standby current ICC2 CE# = VCC 0.2V RST# = VCC 0.2V 100 A 2 Program/Erase current ICC3 Program/Erase controller active: VPP/WP# = VIL or VIH; VPP/WP# = VPP - 20 mA 3 Current for VPP/WP# program acceleration IPP VCC = 2.7V 10% - 15 mA Notes: 1. The maximum input leakage current is 5uA on VPP/WP#. 2. When the bus is inactive for 300ns or more, the memory enters automatic standby. 3. Sampled only; not 100% tested. Table 27: DC Voltage Characteristics Parameter Symbol Conditions Min Max Unit Input LOW voltage VIL - -0.5 0.8 V Input HIGH voltage VIH - 0.7 VCC VCC + 0.3 V Voltage for VPP/WP# program acceleration VPP VCC = 2.7V 10% 11.5 12.5 V Output LOW voltage VOL IOL = 1.8mA - 0.45 V Output HIGH voltage VOH IOH = -100A VCC - 0.4 - V Identification voltage VID - 11.5 12.5 V VLKO - 1.8 2.3 V Program/erase lockout supply voltage Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN Notes 1 1. Sampled only; not 100% tested. 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Read AC Characteristics Read AC Characteristics Table 28: Read AC Characteristics Symbol Parameter Legacy JEDEC Condition Min/Max 60ns 70ns 90ns Unit tRC tAVAV CE# = VIL, OE# = VIL Min 60 70 90 ns Address valid to output valid tACC tAVQV CE# = VIL, OE# = VIL Max 60 70 90 ns Address valid to output valid (page) tPAGE tAVQV1 CE# = VIL, OE# = VIL Max 25 30 30 ns CE# LOW to output transition tLZ tELQX OE# = VIL Min 0 0 0 ns CE# LOW to output valid tCE tELQV OE# = VIL Max 60 70 90 ns tOLZ tGLQX CE# = VIL Min 0 0 0 ns OE# LOW to output valid tOE tGLQV CE# = VIL Max 25 30 30 ns CE# HIGH to output High-Z tHZ tEHQZ OE# = VIL Max 25 30 30 ns 1 OE# HIGH to output High-Z tDF tGHQZ CE# = VIL Max 25 30 30 ns 1 CE#, OE#, or address transition to output transition tOH tEHQX, - Min 0 0 0 ns Address valid to next address valid OE# LOW to output transition Notes 1 1 tGHQX, tAXQX CE# to BYTE# LOW tELFL tELBL - Max 5 5 5 ns CE# to BYTE# HIGH tELFH tELBH - Max 5 5 5 ns BYTE# LOW to output High-Z tFLQZ tBLQZ - Max 25 25 25 ns BYTE# HIGH to output valid tFHQV tBHQV - Max 25 30 30 ns Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. Sampled only; not 100% tested. 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Read AC Characteristics Figure 14: Random AC Timing tRC A[MAX:0]/A-1 Valid tACC tOH CE# tCE tOH tHZ tLZ OE# tOH tOLZ tOE DQ[7:0]/ DQ[15:8] tDF Valid tFHQV BYTE# tELFL/ tELFH Notes: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN tFHQZ 1. Data are output on DQ0-DQ15. DQ8-DQ14 are High-Z in 8-bit mode. 2. Addresses differ in x8 mode. 3. BYTE# = VIL in x8 mode. 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Read AC Characteristics Figure 15: Page Read AC Timing A[MAX:2] Valid A[1:0]/A-1 Valid Valid Valid Valid tACC CE# tCE tOH tHZ OE# tOH tOE DQ[15:0] tPAGE Valid Notes: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN tDF Valid Valid Valid 1. Data are output on DQ0-DQ15. DQ8-DQ14 are High-Z in 8-bit mode. 2. Addresses differ in x8 mode. 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Write AC Characteristics Write AC Characteristics Table 29: WE#-Controlled Write AC Characteristics Symbol Parameter Legacy JEDEC Min/Max 60ns 70ns 90ns Unit tWC tAVAV Min 60 70 90 ns CE# LOW to WE# LOW tCS tELWL Min 0 0 0 ns WE# LOW to WE# HIGH tWP tWLWH Min 35 35 35 ns Input valid to WE# HIGH tDS tDVWH Min 30 30 30 ns WE# HIGH to input transition tDH tWHDX Min 0 0 0 ns WE# HIGH to CE# HIGH tCH tWHEH Min 0 0 0 ns WE# HIGH to WE# LOW tWPH tWHWL Min 25 25 25 ns Address valid to WE# LOW tAS tAVWL Min 0 0 0 ns WE# LOW to address transition tAH tWLAX Min 45 45 45 ns OE# HIGH to WE# LOW - tGHWL Min 0 0 0 ns WE# HIGH to OE# LOW tOEH tWHGL1 Min 0 0 0 ns Program/erase valid to RY/BY# LOW tBUSY tWHRL1 Max 0 0 0 ns tVCS tVCHEL Min 50 50 50 s Address valid to next address valid VCC HIGH to CE# LOW Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN Notes 1 1. Sampled only; not 100% tested. 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Write AC Characteristics Figure 16: WE#-Controlled AC Timing tWC A[MAX:0]/ A-1 Valid tAH tAS tCH CE# tCS OE# tGHWL tOEH tWP WE# tWPH tDS DQ[7:0]/ DQ[15:8] tDH Valid VCC tVCS RY/BY# tBUSY Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. Addresses differ in x8 mode. 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Write AC Characteristics Table 30: CE#-Controlled Write AC Characteristics Symbol Parameter Legacy JEDEC Min/Max 60ns 70ns 90ns Unit Address valid to next address valid tWC tAVAV Min 60 70 90 ns WE# LOW to CE# LOW tWS tWLEL Min 0 0 0 ns CE# LOW to CE# HIGH tCP tELEH Min 35 35 35 ns Input valid to CE# HIGH tDS tDVEH Min 30 30 30 ns CE# HIGH to input transition tDH tEHDX Min 0 0 0 ns CE# HIGH to WE# HIGH tWH tEHWH Min 0 0 0 ns CE# HIGH to CE# LOW tCPH tEHEL1 Min 25 25 25 ns Address valid to CE# LOW tAS tAVEL Min 0 0 0 ns CE# LOW to address transition tAH tELAX Min 45 45 45 ns OE# HIGH to CE# LOW - tGHEL Min 0 0 0 ns CE# HIGH to OE# LOW tOEH tEHGL1 Min 0 0 0 ns Program/Erase valid to RY/BY# LOW tBUSY tEHRL Max 0 0 0 ns tVCS tVCHWL Min 50 50 50 ns VCC HIGH to WE# LOW Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN Notes 1 1. Sampled only; not 100% tested. 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Write AC Characteristics Figure 17: CE#-Controlled AC Timing tWC A[MAX:0]/ A-1 Valid tAH tAS tWH WE# tWS OE# tGHEL tOEH tCP CE# tCPH tDS DQ[7:0]/ DQ[15:8] tDH Valid VCC tVCS RY/BY# tBUSY Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. Addresses differ in x8 mode. 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Toggle and Alternative Toggle AC Characteristics Toggle and Alternative Toggle AC Characteristics Table 31: Toggle and Alternative Toggle AC Characteristics Symbol Parameter Legacy JEDEC Min/Max 60ns 70ns 90ns Unit Address setup time to OE# LOW during toggle bit polling tASO tAXGL Min 10 10 10 ns Address hold time from OE# during toggle bit polling tAHT tGHAX Min 10 10 10 ns tEHAX Min 10 10 10 ns CE# HIGH during toggle bit polling tCEPH tEHEL2 Min 10 10 10 ns Output hold time during data and toggle bit polling tOEH tWHGL2 Min 20 20 20 ns tGHGL2 Min 20 20 20 ns Note: 1. Data for tELQV and tGLQV are in the Read AC Characteristics table. Figure 18: Toggle/Alternative Toggle, CE# Controlled tWHEH tEHQZ tGHQZ tELQV CE# tGLQV OE# tWHGL2 WE# tWHWH1 or tWHWH2 DQ7 DQ6-DQ0 DATA DQ7= Valid data DQ7 DQ6-DQ0= Output flag DATA DQ6-DQ0= Valid data Hi-Z Hi-Z tWHRL RY/BY# Notes: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. DQ7 returns valid data bit when the ongoing PROGRAM or ERASE command is completed. 2. See the AC Characteristics for specifications. 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Toggle and Alternative Toggle AC Characteristics Figure 19: Toggle/Alternative Toggle, OE# Controlled A0-A20/ A- 1 tGHAX tAXGL CE# tWHGL2 tAVEL tEHAX WE# tEHEL2 tGHGL2 tGHGL2 OE# tGLQV tWHDX Data DQ6/DQ2 Toggle tELQV Toggle Toggle Stop toggling Output Valid tWHRL RY/BY# Notes: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. DQ6 stops toggling when the ongoing PROGRAM or ERASE command is completed. DQ2 stops toggling when the ongoing CHIP ERASE or BLOCK ERASE command is completed. 2. Addresses differ in x8 mode. 3. See the AC Characteristics for specifications. 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Program/Erase Characteristics Program/Erase Characteristics Table 32: Program/Erase Times and Endurance Cycles Notes 1 and 2 apply to the entire table Parameter Symbol Min Typ Max tWHWH2 - 80 400 s 3 - 0.5 - s 4, 5 Erase suspend latency time - - 50 s 6 Program (byte or word) - 10 200 s 3 Program (double byte) 10 200 s 3 Program (double word/quadruple byte) 10 200 s 3 10 200 s 3 10 s 3, 7 Program (32-byte 16-word using Write to Buffer and Program) 180 s Program (32-byte 16-word using Write to Buffer and Program, VPP/WP# = 12V) 45 s Chip erase Block erase (64KB) Program (quadruple word/octuple byte) Program (single byte and word) tWHWH1 - Chip program (byte by byte) - Unit Notes 80 400 s 3 Chip program (word by word) 40 200 s 3 Chip program (double word/quadruple byte) 20 100 s 3 3 Chip program (quadruple word/octuple byte) - 10 50 s Program suspend latency time - - 4 s 100,000 - - cycles 20 - - years PROGRAM/ERASE cycles (per block) Data retention Notes: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. Typical values measured at room temperature and nominal voltages and for not cycled devices. 2. Sampled, but not 100% tested. 3. Maximum value measured at worst case conditions for both temperature and VCC after 100,000 PROGRAM/ERASE cycles. 4. Time does not include pre-programming time. 5. Block erase polling cycle time. 6. Maximum value measured at worst case conditions for both temperature and VCC. 7. Programming polling cycle time. 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Program/Erase Characteristics Figure 20: WE# Controlled Program Waveform 3rd cycle 4th cycle A0-A20/ A- 1 Read cycle Data Polling tAVAV tAVAV 555h PA PA tAVWL tWLAX tELQV tWHEH tELWL CE# tGLQV tGHWL OE# tWLWH tWHWL WE# tDVWH DQ0-DQ7/ AOh DQ8-DQ15 tGHQZ tWHWH1 PD DQ7 D OUT tAXQX D OUT tWHDX Notes: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of status register data polling bit and by a read operation that outputs the data, DOUT, programmed by the previous Program command. 2. PA is address of the memory location to be programmed. PD is the data to be programmed. 3. DQ7# is the complement of the data bit being programmed to DQ7. 4. Addresses differ in x8 mode. 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Program/Erase Characteristics Figure 21: CE# Controlled Program Waveform 3rd cycle 4th cycle Data Polling tAVAV A0-A20/ 555h A- 1 PA PA tAVEL tELAX tEHWH tWLEL WE# tGHEL OE# tELEH tEHEL1 CE# tDVEH DQ0-DQ7/ DQ8-DQ15 tWHWH1 AOh PD DQ7 D OUT tEHDX Notes: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of status register data polling bit. 2. PA is address of the memory location to be programmed. PD is the data to be programmed. 3. DQ7# is the complement of the data bit being programmed to DQ7. 4. Addresses differ in x8 mode. 66 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Program/Erase Characteristics Figure 22: Chip/Block Erase Waveform tAVAV A0-A20/ A- 1 555h 2AAh tAVWL 555h 555h 2AAh 555h/BA (1) tWLAX tWHEH tELWL CE# tGHWL OE# tWLWH tWHWL WE# tDVWH DQ0-DQ7/ AAh DQ8-DQ15 55h 80h AAh 55h 10h/ 30h tWHDX Notes: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. For a Chip Erase command, addresses and data are 555h and 10h, respectively, while they are BA and 30h for a Block Erase command. 2. BA is the block address. 3. Addresses differ in x8 mode. 67 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Reset Characteristics Reset Characteristics Table 33: Reset/Block Temporary Unprotect AC Characteristics Symbol Condition/Parameter Legacy JEDEC tRH RST# HIGH to WE# LOW, CE# LOW, OE# LOW tPHWL Min/Max 60, 70, 90ns Unit Notes Min 50 ns 1 Min 0 ns 1 tPHEL tPHGL tRB RY/BY# HIGH to WE# LOW, CE# LOW, OE# LOW tRHWL tRHEL tRHGL tRP tPLPX Min 500 ns tREADY tPLYH Max 50 s 1 RST# rise time to VID tVIDR tPHPHH Min 500 ns 1, 2 VPP rise and fall time - tVHVPP Min 500 ns 1 RST# pulse width RST# LOW to read mode Notes: 1. Sampled only; not 100% tested. 2. For fast program operations using VPP/WP# at 12V. Figure 23: Reset/Block Temporary Unprotect AC Waveforms WE#, CE#, OE# tRH RY/BY# tRB tRP RST# tVIDR tREADY Figure 24: Accelerated Programming Timing Waveform V PP V PP /WP# V IL or V IH PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN tVHVPP tVHVPP 68 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Package Dimensions Package Dimensions Figure 25: 48-Pin TSOP - 12mm x 20mm 1 48 0.50 TYP 12.00 + 0.10 0.22 + 0.05 24 0.80 TYP 25 1.00 + 0.05 18.40 + 0.10 1.20 MAX 20.00 + 0.20 0.10 + 0.05 Die 0.10 MIN/ 0.21 MAX o 3 o+ 2 o 3 0.60 + 0.10 0.10 MAX Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. All dimensions are in millimeters. 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Package Dimensions Figure 26: 56-Pin TSOP - 14mm x 20mm 2X O1.2 Pin A1 ID 1.1 0.1 56 1 0.5 TYP 11.8 CTR 56X 0.22 0.05 28 14 0.1 29 56X 0.1 0.05 16.2 CTR 18.4 0.1 20 0.2 Plating material composition: Ni/Pd/Au. Plastic package material: epoxy novolac. Package width and length include mold flash. 0.1 A 0.15 0.05 See Detail A 0.25 gage plane Seating plane (0.1 0.05) A 0.6 0.1 Detail A Notes: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. All dimensions are in millimeters. 2. For the lead width value of 0.22 0.05, there is also a legacy value of 0.15 0.05. 70 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Package Dimensions Figure 27: 48-Ball TFBGA - 6mm x 8mm 6.00 + 0.10 4.00 TYP 0.40 TYP 1.00 TYP 1.20 TYP 0.40 TYP 8.00 + 0.10 Ball A1 5.60 TYP 0.10 MAX 0.80 TYP 0.80 TYP 0.35 MIN/ 0.45 MAX 0.90 MAX 1.20 MAX Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 0.26 MIN 1. All dimensions are in millimeters. 71 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Package Dimensions Figure 28: 64-Ball TBGA - 10mm x 13mm 10.00 0.10 1.50 TYP 7.00 TYP 3.00 TYP 0.50 TYP 7.00 TYP 0.50 TYP 13.00 0.10 0.10 MAX BALL "A1" 1.00 TYP 0.35 MIN/ 0.50 MAX 0.30 -0.10 +0.05 1.20 MAX Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 0.80 TYP 1. All dimensions are in millimeters. 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Package Dimensions Figure 29: 64-Ball FBGA - 11mm x 13mm 11.00 + 0.10 7.00 TYP 2.00 TYP 3.00 TYP 0.50 TYP 0.50 TYP 13.00 + 0.10 7.00 TYP 0.15 MAX Ball A1 1.00 TYP 0.55 MIN/ 0.65 MAX 0.48 + 0.05 0.80 TYP 1.40 MAX Note: PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 1. All dimensions are in millimeters. 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. 64Mb: 3V Embedded Parallel NOR Flash Revision History Revision History Rev. E - 2/18 * Added Important Notes and Warnings section for further clarification aligning to industry standards Rev. D - 03/15 * Updated MPN decoder * Updated 56-pin TSOP 14mm x 20mm package Rev. C - 07/13 * Updated Command Interface and Command tables Rev. B - 06/13 * Removed Part Numbers by Array Matrix table in Features Rev. A - 11/12 * Initial Micron brand release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef84e35115 m29W_640GH/L_GT/B.pdf - Rev. E 02/18 EN 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved.