MSP2020
Released
MSP for Secure VoIP Gateways and Phones, Wired and Wireless
Multi-Service Processor
PMC-2041689 PROPRIET ARY AND CONFIDENTIAL TO PMC-SIERRA, INC., © Copyright PMC-Sierra, Inc. 2004
Issue 1 AND FOR ITS CUSTOMERS’ INTERNAL USE All rights reserved.
GENERAL
The MSP2020 belongs to a full family of
Multi-Se rvi ce Proc essors designed to
meet th e perfor mance, QoS and security
needs of communications equipment
use d within the customer premise. The
MSP2020 is an ide al sol uti on for VoIP
Gateway s and Secure Wire d and
Wireless IP Phones. As shown below, it
includes a MIPS CPU, three 10/100
Ethe rnet MACs, TDM inter face, PCI
interface, and a security engine.
The MSP2020 provides a new level of
price performance for VoIP Gateways,
and Secure Wired and Wireless IP
Phones. Because the MSP2020 elimi-
nates th e need for a s eparate proces sor,
voice pro cessing DSP, security ch ip and
multiple Ethernet MACs, systems can
now be built with fewer chips at a very
affordable price point.
The MSP2020 has a unique systems
architecture that provides wire-speed
performance. This architecture includes
a powerful MIPS CPU, a 4.25 Gbps bus,
16KB Scrat chpad, and intel ligent conte xt
aware DMA engines. Together, this
results in an extremely cost effective
VoIP solution that includes security.
Integration of 802.11a, b, and g wireless
LANs is easily facilitated through the
PCI interface.
To reduce time-to-market, PMC-Sierra
offers comprehensive support for the
MSP2020, including evaluation boards,
software, application engineering
support, training, and documentation
that together accelerate the product
development process. In addition, the
MSP2020 supports Linux, VxWorks, or
custom operati ng systems.
ADVANTAGES
• Cost effective VoIP solutions
• Versatile PCI and ELB Buses
• Support for Global IP Sound
technology
• 3 10/100 Ethernet MACs
• Flexible GPIO architecture to easily
support key pa d scan
• High performance systems
architecture with on-chip security
engine
• Significant cost reduction through
integration of multiple processors and
discrete parts on a single chip
• Architecture that scales to voice and
data applic ati ons
• Easy porting of customer and third
party software and protocol stacks
APPLICATIONS
• 1-port Secure VoIP Gateway , Wired
and Wireless
• IP Phones, Wired and Wirele ss
• TDM Ethe rnet Bridge
BLOCK DIAGRAM
4.25 Gbit/s Multi-Service Bus
(MS Bus)
External Local Bus
UART
Memory Controller
High Performance
MIPS32 4Km
MSP2020
WAN
LAN
Serial
Display
LAN
SDRAM
UART
USB
PCI
Scratch Pad
802.11
SPI/MPI
Two-Wire
10/100 MAC
10/100 MAC
10/100 MAC
TDM
GIPO I/O
SLIC/CODEC or
Audio CODEC
Security Engine
Head Office:
PMC-Sierra, Inc.
8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 1.604.415.6000
Fax: 1.604.415.6200
MSP for Secure VoIP Gateways and Phones, Wired and Wireless
To order documentation,
send emai l to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
PMC-2041689 (R1)
© Copyright PMC-Sierra, Inc. 2004. All
rights reserved.
For a complete list of PMC-Sierra’s
trademarks and registered trademarks,
visit: http://www.pmc-sierra.com/legal/
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
MSP2020 Multi-Service Processor
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corpor ate information,
send emai l to:
info@pmc-sierra.com
ELECTRICAL
• 276 pin PBGA
• Vcc 3.3V I/O, 1.8V core
• Power consumption 1.4W
SYSTEM PROCESSOR
• High performance MIPS32 4Km
process or at 170 MH z
• 16 KB instruction cache, 16 KB data
cache
• 16 KB Scratchpad
ULTRAFAST MULTI-SERVICE
BUS (MS BUS)
• Peak bandwidth of 4.25 Gbps
• True parallel processing
LAN INTERFACE
• 3 Independe nt 10/1 00 Ethernet MACs
•MII/RMII
• Suppo rts VLAN taggi ng
VOICE INTERFACE
• TDM Interface
SECURITY ENGINE
• Hardware accelerator for AES, DES,
3DES, HMAC-MD5, and HMAC-SHA-1
• 32 Bit true random number generator
• IPSe c com pl iant
HIGH PERFORMANCE SYSTEM
BUSES
• PCI interface (32-bit, 33 MHz)
•PCI V2.1 and V2.2 compatible
• Flexible external local bus interface
•Up to 25 MBps data throughput
SYSTEM CONTROL
• Four interrupt inputs
•55 GPIOs
• MIPS timer, 2 system timers, and
watchdog timer
• Block copy engine
MISCELLANEOUS INTERFACES
• 2 UARTs
• SPI/MPI
• Two-wire serial
MEMORY CONTROLLER
• Glueless interface to 256 MB of
SDRAM
• Glueless interface to 32 MB of flash
SOFTWARE
• APIs: MACs, VoIP, Security engine,
and Block C opy
• Board support package
DEV E LO PMEN T TO O LS
• Support for Linux and VxWorks
• Evaluation boards
• Third pa rty tool chains
THIRD PARTY SUPPORT
• Voice Processing
•GIPS™ - Global IP Sound - NetEq
•RADVISION™ - H.323, SIP, MGCP
• EJTAG Debuggers
•EPI - MAJIC probe
•WindRiver - visionICE II
