VNN1NV04P-E, VNS1NV04P-E OMNIFET II fully autoprotected Power MOSFET Features Parameter Symbol Value Max on-state resistance (per ch.) RON 250 m Current limitation (typ) ILIMH 1.7 A VCLAMP 40 V Drain-source clamp voltage 2 1 2 3 SOT-223 Linear current limitation Thermal shutdown Short circuit protection Integrated clamp Low current drawn from input pin Diagnostic feedback through input pin ESD protection Direct access to the gate of the Power MOSFET (analog driving) Compatible with standard Power MOSFET SO-8 Description The VNN1NV04P-E, VNS1NV04P-E are monolithic devices designed in STMicroelectronics VIPower M0-3 Technology, intended for replacement of standard Power MOSFETs from DC up to 50 kHz applications. Built in thermal shutdown, linear current limitation and overvoltage clamp protect the chip in harsh environments. Fault feedback can be detected by monitoring the voltage at the input pin. Table 1. Device summary Order codes Package Tube October 2009 Tape and reel SOT-223 VNN1NV04P-E VNN1NV04PTR-E SO-8 VNS1NV04P-E VNS1NV04PTR-E Doc ID 15586 Rev 2 1/28 www.st.com 28 Contents VNN1NV04P-E, VNS1NV04P-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 6 2/28 4.1 SOT-223 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 SO8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 SOT-223 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4 SO8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 15586 Rev 2 VNN1NV04P-E, VNS1NV04P-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SOT-223 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SO-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 15586 Rev 2 3/28 List of figures VNN1NV04P-E, VNS1NV04P-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. 4/28 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Switching time test circuit for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Test circuit for diode recovery times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Unclamped inductive load test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input charge test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Unclamped inductive waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Source-drain diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Static drain-source on resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Static drain-source on resistance vs input voltage (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . 12 Static drain-source on resistance vs input voltage (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . 12 Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Static drain-source on resistance vs Id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Turn-on current slope (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Turn-on current slope (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input voltage vs input charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Turn-off drain source voltage slope (part 1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Turn-off drain-source voltage slope (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Capacitance variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Switching time resistive load (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Switching time resistive load (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Normalized on resistance vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Normalized input threshold voltage vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Normalized current limit vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Step response current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SOT-223 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SOT-223 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . 17 SOT-223 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . 18 SOT-223 thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SO-8 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . 19 SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SO-8 thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SOT-223 mechanical data and package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SO-8 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SOT-223 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SO-8 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Doc ID 15586 Rev 2 VNN1NV04P-E, VNS1NV04P-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram DRAIN 2 Overvoltage Clamp INPUT Gate Control 1 Linear Current Limiter Over Temperature 3 SOURCE Figure 2. Configuration diagram (top view) (a) SOURCE 1 8 DRAIN SOURCE INPUT DRAIN DRAIN SOURCE 4 5 DRAIN a. For the pins configuration related to SOT-223 see outline at page 1. Doc ID 15586 Rev 2 5/28 Electrical specifications 2 VNN1NV04P-E, VNS1NV04P-E Electrical specifications Figure 3. Current and voltage conventions ID VDS DRAIN IIN RIN INPUT SOURCE VIN 2.1 Absolute maximum ratings Stress values that exceed those listed in the "Absolute maximum ratings" table can cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions greater than those, indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics sure program and other relevant quality documents. Table 2. Absolute maximum ratings Symbol Value SOT-223 SO-8 Unit VDSn Drain-source voltage (VINn=0 V) Internally clamped V VINn Input voltage Internally clamped V IINn Input current +/-20 mA 330 Internally limited A -3 A RIN MINn Minimum input series impedance IDn Drain current IRn Reverse DC output current VESD1 Electrostatic discharge (R=1.5 K, C=100 pF) 4000 V VESD2 Electrostatic discharge on output pins only (R=330 , C=150 pF) 16500 V Ptot Total dissipation at Tc=25 C 7 8.3 W Tj Operating junction temperature Internally limited C Tc Case operating temperature Internally limited C -55 to 150 C Tstg 6/28 Parameter Storage temperature Doc ID 15586 Rev 2 VNN1NV04P-E, VNS1NV04P-E 2.2 Electrical specifications Thermal data Table 3. Thermal data Max value Symbol Parameter Unit SOT-223 Rthj-case Thermal resistance junction-case Rthj-lead Thermal resistance junction-lead Rthj-amb SO-8 18 C/W 15 (1) Thermal resistance junction-ambient (1) 70 65 C/W C/W 1. When mounted on a standard single-sided FR4 board with 50 mm2 of Cu (at least 35 m thick) connected to all DRAIN pins 2.3 Electrical characteristics Table 4. Electrical characteristics Symbol Parameter Test conditions Min Typ Max Unit 45 55 V Off (-40 C<Tj<150 C, unless otherwise specified) VCLAMP Drain-source clamp voltage VIN=0 V; ID=0.5 A 40 VCLTH Drain-source clamp threshold voltage VIN=0 V; ID=2 mA 36 VINTH Input threshold voltage VDS=VIN; ID=1 mA 0.5 Supply current from input pin VDS=0 V; VIN=5 V VINCL Input-source clamp voltage IIN=1 mA IIN=-1 mA IDSS Zero input voltage drain current VDS=13 V; VIN=0 V; Tj=25 C (VIN=0 V) VDS=25 V; VIN=0 V IISS 6 -1.0 V 2.5 V 100 150 A 6.8 8 -0.3 V 30 75 A 250 500 m On (-40 C<Tj<150 C, unless otherwise specified) RDS(on) Static drain-source on resistance VIN=5 V; ID=0.5 A; Tj=25 C VIN=5 V; ID=0.5 A Dynamic (Tj=25 C, unless otherwise specified) gfs (1) Forward transconductance VDD=13 V; ID=0.5 A 2 S COSS Output capacitance VDS=13 V; f=1 MHz; VIN=0 V 90 pF Switching (Tj=25 C, unless otherwise specified) td(on) tr td(off) tf Turn-on delay time Rise time Turn-off delay time VDD=15 V; ID=0.5 A Vgen=5 V; Rgen=RIN MIN=330 (see Figure 4) Fall time Doc ID 15586 Rev 2 70 200 ns 170 500 ns 350 1000 ns 200 600 ns 7/28 Electrical specifications Table 4. Electrical characteristics (continued) Symbol td(on) tr td(off) tf (dI/dt)on Qi VNN1NV04P-E, VNS1NV04P-E Parameter Test conditions Min Turn-on delay time Rise time Turn-off delay time VDD=15 V; ID=0.5 A Vgen=5 V; Rgen=2.2 K (see Figure 4) Fall time Typ Max Unit 0.25 1.0 s 1.3 4.0 s 1.8 5.5 s 1.2 4.0 s Turn-on current slope VDD=15 V; ID=1.5 A Vgen=5 V; Rgen=RIN MIN=330 5 A/s Total input charge VDD=12 V; ID=0.5 A; VIN=5 V Igen=2.13 mA (see Figure 7) 5 nC Source drain diode (Tj=25 C, unless otherwise specified) VSD(1) Forward on voltage ISD=0.5 A; VIN=0 V 0.8 V trr Reverse recovery time 205 ns Qrr Reverse recovery charge 100 nC IRRM Reverse recovery current ISD=0.5 A; dI/dt=6 A/s VDD=30 V; L=200 H (see Figure 5) 0.7 A Protections (-40 C<Tj<150 C, unless otherwise specified) Ilim Drain current limit VIN=5 V; VDS=13 V tdlim Step response current limit VIN=5 V; VDS=13 V Tjsh Over temperature shutdown 150 Tjrs Over temperature reset 135 Igf Fault sink current Eas Starting Tj=25 C; VDD=24 V VIN=5 V Rgen=RIN MIN=330 ; Single pulse avalanche energy L=50 mH (see Figure 6 and Figure 8) VIN=5 V; VDS=13 V; Tj=Tjsh 1. Pulsed: pulse duration = 300 s, duty cycle 1.5 % 8/28 Doc ID 15586 Rev 2 1.7 3.5 2.0 10 55 175 A s 200 C C 15 20 mA mJ VNN1NV04P-E, VNS1NV04P-E Figure 4. Electrical specifications Switching time test circuit for resistive load VD Rgen Vgen ID 90% tr tf 10% t Vgen td(on) td(off) t Doc ID 15586 Rev 2 9/28 Electrical specifications Figure 5. VNN1NV04P-E, VNS1NV04P-E Test circuit for diode recovery times A A D I FAST DIODE OMNIFET S L=100uH B B 330 D Rgen VDD I OMNIFET Vgen S 8.5 Figure 6. Unclamped inductive load test circuits RGEN VIN PW 10/28 Doc ID 15586 Rev 2 VNN1NV04P-E, VNS1NV04P-E Figure 7. Electrical specifications Input charge test circuit VIN GEN ND8003 Figure 8. Unclamped inductive waveforms Doc ID 15586 Rev 2 11/28 Electrical specifications VNN1NV04P-E, VNS1NV04P-E 2.4 Electrical characteristics curves Figure 9. Source-drain diode forward characteristics Figure 10. Static drain-source on resistance Vsd (mV) Rds(on) (ohms) 1000 4.5 Tj=-40C 4 950 Vin=2.5V 3.5 Vin=0V 3 900 2.5 850 2 1.5 800 Tj=25C 1 750 Tj=150C 0.5 0 700 0 2 4 6 8 10 12 0 14 0.05 0.1 0.15 Figure 11. 0.2 0.25 0.3 Id(A) Id (A) Derating curve Figure 12. Static drain-source on resistance vs input voltage (part 1/2) Rds(on) (mohms) 500 450 Id=0.5A 400 Tj=150C 350 300 250 200 Tj=25C 150 Tj=-40C 100 50 0 3 3.5 4 4.5 5 5.5 6 6.5 7 Vin(V) Figure 13. Static drain-source on resistance vs input voltage (part 2/2) Rds(on) (mohms) Gfs (S) 500 450 Figure 14. Transconductance 6 Tj=150C 5.5 Id=1.5A Id=1A 350 Tj=25C 4.5 4 300 Tj=150C 3.5 Tj=25C 250 3 2.5 200 Id=1.5A Id=1A Tj=-40C 150 2 1.5 Id=1.5A Id=1A 100 1 50 0.5 0 0 3 3.5 4 4.5 5 5.5 6 6.5 0 0.25 0.5 0.75 1 Id(A) Vin(V) 12/28 Tj=-40C Vds=13V 5 400 Doc ID 15586 Rev 2 1.25 1.5 1.75 2 VNN1NV04P-E, VNS1NV04P-E Electrical specifications Figure 15. Static drain-source on resistance vs Id Figure 16. Transfer characteristics Rds(on) (mohms) Idon(A) 500 2.25 Vin=3.5V 450 Tj=25C 2 Vds=13.5V Tj=150C 400 1.75 Vin=5V 350 1.5 300 1.25 250 Vin=3.5V 1 Vin=5V Vin=3.5V 0.75 Tj=25C 200 150 Tj=-40C Tj=-40C 0.5 Vin=5V 100 Tj=150C 0.25 50 0 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 1.5 2 2 1.75 Id(A) 2.5 2.25 3 3.5 2.75 3.25 4 3.75 4.5 4.25 5 4.75 Vin(V) Figure 17. Turn-on current slope (part 1/2) Figure 18. Turn-on current slope (part 2/2) di/dt(A/us) di/dt(A/us) 6 1.4 5 1.2 Vin=5V Vdd=15V Id=1.5A 4 Vin=3.5V Vdd=15V Id=1.5A 1 3 0.8 2 0.6 1 0.4 0 0.2 0 500 1000 1500 2000 2500 0 500 Rg(ohm) 1000 1500 2000 2500 Rg(ohm) Figure 19. Input voltage vs input charge Figure 20. Turn-off drain source voltage slope (part 1/2) Vin (V) dv/dt(V/us) 6 350 300 5 Vds=12V Id=0.5A Vin=5V Vdd=15V Id=0.5A 250 4 200 3 150 2 100 1 50 0 0 1 2 3 4 5 6 0 Qg (nC) 0 500 1000 1500 2000 2500 Rg(ohm) Doc ID 15586 Rev 2 13/28 Electrical specifications VNN1NV04P-E, VNS1NV04P-E Figure 21. Turn-off drain-source voltage slope Figure 22. Capacitance variations (part 2/2) C(pF) dv/dt(V/us) 225 350 200 300 Vin=3.5V Vdd=15V Id=0.5A 250 f=1MHz Vin=0V 175 200 150 150 125 100 100 50 75 50 0 0 500 1000 1500 2000 0 2500 5 10 15 20 25 30 35 Vds(V) Rg(ohm) Figure 23. Switching time resistive load (part 1/2) Figure 24. Switching time resistive load (part 2/2) t(ns) t(us) 550 2 500 1.75 Vdd=15V Id=0.5A Vin=5V 1.5 Vdd=15V Id=0.5A Rg=330ohm tr 450 td(off) 400 tr 1.25 350 td(off) 300 tf 1 250 0.75 tf 200 150 0.5 td(on) 0.25 td(on) 100 50 0 250 0 500 0 750 1000 1250 1500 1750 2000 2250 2500 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 Vin(V) Rg(ohm) Figure 25. Output characteristics Figure 26. Normalized on resistance vs temperature ID(A) Rds(on) (mOhm) 2.25 2.4 2.2 Vin=5.5V 2 Vin=4.5V 2 Vin=5V Id=0.5A Vin=3.5V 1.8 1.75 1.6 1.5 1.4 1.2 1.25 1 0.8 1 0.6 0.4 0.75 Vin=3V 0.2 0.5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 14/28 -50 -25 0 25 50 75 Tc (C) VDS(V) Doc ID 15586 Rev 2 100 125 150 175 VNN1NV04P-E, VNS1NV04P-E Electrical specifications Figure 27. Normalized input threshold voltage Figure 28. Normalized current limit vs junction vs temperature temperature Vinth (V) Ilim (A) 2 5 1.8 4.5 Vds=Vin Id=1mA 1.6 Vin=5V Vds=13V 4 1.4 3.5 1.2 3 1 2.5 0.8 2 0.6 1.5 0.4 1 0.2 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 29. Step response current limit Tdlim(us) 2.4 2.3 Vin=5V Rg=330ohm 2.2 2.1 2 1.9 5 10 15 20 25 30 35 Vdd(V) Doc ID 15586 Rev 2 15/28 Protection features 3 VNN1NV04P-E, VNS1NV04P-E Protection features During normal operation, the input pin is electrically connected to the gate of the internal Power MOSFET through a low impedance path. The device then behaves like a standard Power MOSFET and can be used as a switch from DC up to 50 kHz. The only difference from the user's standpoint is that a small DC current IISS (typ. 100 A) flows into the input pin in order to supply the internal circuitry. The device integrates: Overvoltage clamp protection: internally set at 45 V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. Linear current limiter circuit: limits the drain current ID to Ilim whatever the input pin voltages. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the over temperature threshold Tjsh. Over temperature and short circuit protection: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Over temperature cutout occurs in the range 150 to 190 C, a typical value being 170 C. The device is automatically restarted when the chip temperature falls of about 15 C below shutdown temperature. Status feedback: in the case of an over temperature fault condition (Tj > Tjsh), the device tries to sink a diagnostic current Igf through the input pin in order to indicate fault condition. If driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. If the drive impedance is high enough so that the input pin driver is not able to supply the current Igf, the input pin will fall to 0 V. This will not however affect the device operation: no requirement is put on the current capability of the input pin driver except to be able to supply the normal operation drive current IISS. Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL logic circuit. 16/28 Doc ID 15586 Rev 2 VNN1NV04P-E, VNS1NV04P-E Package and PCB thermal data 4 Package and PCB thermal data 4.1 SOT-223 thermal data Figure 30. SOT-223 PC board . Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm,PCB thickness = 2 mm, Cu thickness=35 m, Copper areas: from minimum pad layout to 0.8 cm2). Figure 31. SOT-223 Rthj-amb vs PCB copper area in open box free air condition 140 footprint 130 120 110 100 90 80 70 60 0 0,5 1 1,5 2 2,5 PCB Cu heat sink area ( cm^ 2) - ( refer t o PCB layout ) Doc ID 15586 Rev 2 17/28 Package and PCB thermal data VNN1NV04P-E, VNS1NV04P-E Figure 32. SOT-223 thermal impedance junction ambient single pulse ZTH ( C/ W) 1000 Footprint 100 2 cm2 10 1 0,1 0,0001 0,001 0,01 0,1 1 Time ( s) 10 100 1000 Equation 1: pulse calculation formula Z TH = R TH +Z THtp (1 - ) where = tP/T Figure 33. SOT-223 thermal fitting model of a single channel Table 5. 18/28 SOT-223 thermal parameter Area/island (cm2) FP R1 (C/W) 0.8 R2 (C/W) 1.6 R3 (C/W) 4.5 R4 (C/W) 24 R5 (C/W) 0.1 R6 (C/W) 100 Doc ID 15586 Rev 2 2 45 VNN1NV04P-E, VNS1NV04P-E Table 5. 4.2 Package and PCB thermal data SOT-223 thermal parameter (continued) Area/island (cm2) FP C1 (W*s/C) 0.00006 C2 (W*s/C) 0.0005 C3 (W*s/C) 0.03 C4 (W*s/C) 0.16 C5 (W*s/C) 1000 C6 (W*s/C) 0.5 2 2 SO-8 thermal data Figure 34. SO-8 PC board Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm,PCB thickness = 2 mm, Cu thickness=35 m, Copper areas: from minimum pad layout to 2 cm2). Figure 35. SO-8 Rthj-amb vs PCB copper area in open box free air condition 105 footprint 95 85 75 65 0 0,5 1 1,5 2 2,5 PCB Cu heat sink area ( cm^ 2) - ( refer t o PCB layout ) Doc ID 15586 Rev 2 19/28 Package and PCB thermal data VNN1NV04P-E, VNS1NV04P-E Figure 36. SO-8 thermal impedance junction ambient single pulse ZTH (C/ W ) 1000 Footprint 100 2 cm2 10 1 0,1 0,0001 0,001 0,01 0,1 1 10 100 1000 Time (s) Equation 2: pulse calculation formula Z TH = R TH +Z THtp (1 - ) where = tP/T Figure 37. SO-8 thermal fitting model of a single channel Table 6. 20/28 SO-8 thermal parameter Area/island (cm2) FP R1 (C/W) 0.8 R2 (C/W) 2.6 R3 (C/W) 3.5 R4 (C/W) 21 Doc ID 15586 Rev 2 2 VNN1NV04P-E, VNS1NV04P-E Table 6. Package and PCB thermal data SO-8 thermal parameter (continued) Area/island (cm2) FP R5 (C/W) 16 R6 (C/W) 58 C1 (W*s/C) 0.00006 C2 (W*s/C) 0.0005 C3 (W*s/C) 0.0075 C4 (W*s/C) 0.045 C5 (W*s/C) 0.35 C6 (W*s/C) 1.05 Doc ID 15586 Rev 2 2 28 2 21/28 Package and packing information 5 VNN1NV04P-E, VNS1NV04P-E Package and packing information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 5.1 SOT-223 mechanical data Figure 38. SOT-223 mechanical data and package outline 22/28 Doc ID 15586 Rev 2 VNN1NV04P-E, VNS1NV04P-E 5.2 Package and packing information SO8 mechanical data Table 7. SO-8 mechanical data mm Dim. Min. Typ. A Max. 1.75 A1 0.10 A2 1.25 b 0.28 0.48 c 0.17 0.23 (1) 4.80 4.90 5.00 E 5.80 6.00 6.20 3.80 3.90 4.00 D (2) E1 e 0.25 1.27 h 0.25 0.50 L 0.40 1.27 L1 k 1.04 0 ccc 8 0.10 1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both side). 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. Doc ID 15586 Rev 2 23/28 Package and packing information VNN1NV04P-E, VNS1NV04P-E Figure 39. SO-8 package dimension 0016023 D 24/28 Doc ID 15586 Rev 2 VNN1NV04P-E, VNS1NV04P-E 5.3 Package and packing information SOT-223 packing information Figure 40. SOT-223 tape and reel shipment (suffix "TR") Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 12.4 60 18.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D (+ 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2 All dimensions are in mm. End Start Top cover tape No components Components No components 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed Doc ID 15586 Rev 2 25/28 Package and packing information 5.4 VNN1NV04P-E, VNS1NV04P-E SO8 packing information Figure 41. SO-8 tube shipment (no suffix) B Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) C A 100 2000 532 3.2 6 0.6 All dimensions are in mm. Figure 42. SO-8 tape and reel shipment (suffix "TR") REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D (+ 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2 All dimensions are in mm. End Start Top cover tape No components Components 500mm min Empty components pockets saled with cover tape. User direction of feed 26/28 Doc ID 15586 Rev 2 No components 500mm min VNN1NV04P-E, VNS1NV04P-E 6 Revision history Revision history Table 8. Document revision history Date Revision Changes 16-May-2009 1 Initial release. 29-Sep-2009 2 Removed target specification on cover page. Doc ID 15586 Rev 2 27/28 VNN1NV04P-E, VNS1NV04P-E Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 28/28 Doc ID 15586 Rev 2