1
LT1641-1/LT1641-2
164112fc
Positive High Voltage
Hot Swap Controllers
The LT
®
1641-1/LT1641-2 are 8-pin Hot Swap
TM
control-
lers that allow a board to be safely inserted and removed
from a live backplane. Using an external N-channel pass
transistor, the board supply voltage can be ramped up at
a programmable rate. A high side switch driver controls an
N-channel gate for supply voltages ranging from 9V to
80V.
The chips feature a programmable analog foldback cur-
rent limit circuit. If the chips remain in current limit for
more than a programmable time, the N-channel pass
transistor is either latched off (LT1641-1) or is set to
automatically restart after a time-out delay (LT1641-2).
The PWRGD output indicates when the output voltage,
sensed by the FB pin, is within tolerance. The ON pin
provides programmable undervoltage lockout.
The LT1641-1/LT1641-2 are available in the 8-lead SO
package.
■
Hot Board Insertion
■
Electronic Circuit Breaker
■
Industrial High Side Switch/Circuit Breaker
■
24V/48V Industrial/Alarm Systems
■
Allows Safe Board Insertion and Removal from a
Live Backplane
■
Controls Supply Voltage from 9V to 80V
■
Programmable Analog Foldback Current Limiting
■
High Side Drive for an External N-Channel
■
Latched Operation Mode (LT1641-1)
■
Automatic Retry (LT1641-2)
■
User Programmable Supply Voltage Power-Up Rate
■
Undervoltage Lockout
■
Overvoltage Protection
■
Both are available in 8-Lead SO Package
*SMAT70A
*DIODES, INC.
V
IN
24V
SHORT
PIN
GND
V
CC
TIMER
SENSE GATE
D1
CMPZ
5248B
GND
PWRGD PWRGD
FB
R5
10Ω
5%
ON
R1
49.9k
1%
1641-1 TA01
R2
3.4k
1%
C2
0.68µF
R6,
1k, 5%
R
S
0.01Ω
C1
10nF
R3
59k
1%
R4
3.57k
1%
R7
24k
5%
C
L
V
OUT
LT1641-1/LT1641-2
Q1
IRF530
24V Input Voltage Application
APPLICATIO S
U
FEATURES
TYPICAL APPLICATIO
U
DESCRIPTIO
U
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
2
LT1641-1/LT1641-2
164112fc
Supply Voltage (V
CC
) ...............................–0.3V to 100V
Input Voltage (SENSE).............................–0.3V to 100V
Input Voltage (TIMER) ...............................–0.3V to 44V
Input Voltage (FB, ON)...............................– 0.3V to 60V
Output Voltage (PWRGD) ........................– 0.3V to 100V
Output Voltage (GATE) ............................– 0.3V to 100V
Operating Temperature Range
LT1641-1C, LT1641-2C ........................... 0°C to 70°C
LT1641-1I, LT1641-2I ........................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
(Note 1)
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Vcc = 24V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
V
CC
Operating Range ●980V
I
CC
V
CC
Supply Current ON = 3V ●2 5.5 mA
V
LKO
V
CC
Undervoltage Lockout ●7.5 8.3 8.8 V
V
FBH
FB Pin High Voltage Threshold FB Low to High Transition ●1.280 1.313 1.345 V
V
FBL
FB Pin Low Voltage Threshold FB High to Low Transition ●1.221 1.233 1.245 V
V
FBHST
FB Pin Hysteresis Voltage 80 mV
I
INFB
FB Pin Input Current V
FB
= GND –1 µA
∆V
FB
FB Pin Threshold Line Regulation 9V ≤ V
CC
≤ 80V ●0.05 mV/V
V
SENSETRIP
SENSE Pin Trip Voltage (V
CC
– V
SENSE
)V
FB
= 0V ●81217 mV
V
FB
= 1V ●39 47 55 mV
I
GATEUP
GATE Pin Pull-Up Current Charge Pump On, V
GATE
= 7V ●–5 –10 –20 µA
I
GATEDN
GATE Pin Pull-Down Current Any Fault Condition, V
GATE
= 2V ●35 70 100 mA
∆V
GATE
External N-Channel Gate Drive V
GATE
– V
CC
, V
CC
= 10.8V to 20V ●4.5 18 V
V
CC
= 20V to 80V ●10 18 V
I
TIMERUP
TIMER Pin Pull-Up Current V
TIMER
= 0V ●– 24 – 80 – 132 µA
I
TIMERON
TIMER Pin Pull-Down Current V
TIMER
= 1V ●1.5 3 5 µA
V
ONH
ON Pin High Threshold ON Low to High Transition ●1.280 1.313 1.345 V
V
ONL
ON Pin Low Threshold ON High to Low Transition ●1.221 1.233 1.245 V
V
ONHYST
ON Pin Hysteresis 80 mV
I
INON
ON Pin Input Current V
ON
= GND –1 µA
V
OL
PWRGD Output Low Voltage I
O
= 2mA ●0.4 V
I
O
= 4mA ●2.5 V
I
OH
PWRGD Pin Leakage Current V
PWRGD
= 80V ●10 µA
DC ELECTRICAL CHARACTERISTICS
T
JMAX
= 125°C, θ
JA
= 110°C/W
16411
16411I
16412
16412I
LT1641-1CS8
LT1641-1IS8
LT1641-2CS8
LT1641-2IS8
1
2
3
4
8
7
6
5
TOP VIEW
VCC
SENSE
GATE
TIMER
ON
FB
PWRGD
GND
S8 PACKAGE
8-LEAD PLASTIC SO
ORDER PART NUMBER S8 PART MARKING
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
3
LT1641-1/LT1641-2
164112fc
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
PHLON
ON Low to GATE Low Figures 1, 2 6 µs
t
PLHON
ON High to GATE High Figures 1, 2 1.7 µs
t
PHLFB
FB Low to PWRGD Low Figures 1, 3 3.2 µs
t
PLHFB
FB High to PWRGD High Figures 1, 3 1.5 µs
t
PHLSENSE
(V
CC
– SENSE) High to GATE Low Figures 1, 4 0.5 1 2 µs
AC ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
TA = 25°C, VCC = 24V
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VCC (V)
020 40 60 80 100
ICC (mA)
1641-1 G01
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
85°C
25°C
–45°C
TEMPERATURE (°C)
–50 –25 0 25 50 75 100
ICC (mA)
1641-1 G02
3.0
2.5
2.0
1.5
1.0
0.5
0
48V
24V
TEMPERATURE (°C)
–50 –25 0 25 50 75 100
FB PIN LOW VOLTAGE THRESHOLD (V)
1641-1 G03
1.250
1.245
1.240
1.235
1.230
1.225
1.220
1.215
1.210
1.205
1.200
V
CC
= 48V
TEMPERATURE (°C)
–50 –25 0 25 50 75 100
FB PIN HIGH VOLTAGE THRESHOLD (V)
1641-1 G04
1.335
1.330
1.325
1.320
1.315
1.310
1.305
1.300
1.295
1.290
1.285
1.280
V
CC
= 48V
TEMPERATURE (°C)
–50 –25 0 25 50 75 100
FB PIN HYSTERESIS (V)
1641-1 G05
0.100
0.095
0.090
0.085
0.080
0.075
0.070
0.065
0.060
0.055
0.050
0.045
0.040
V
CC
= 48V
TEMPERATURE (°C)
–50 –25 0 25 50 75 100
IGATE PULL UP (µA)
1641-1 G06
–5
–6
–7
–8
–9
–10
–11
–12
–13
VCC = 48V
ICC vs VCC ICC vs Temperature
FB Pin Low Voltage Threshold vs
Temperature
FB Pin High Voltage Threshold vs
Temperature FB Pin Hysteresis vs Temperature IGATE Pull Up vs Temperature
4
LT1641-1/LT1641-2
164112fc
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
–50 –25 0 25 50 75 100
GATE DRIVE (VGATE – VCC) (V)
1641-1 G07
16
15
14
13
12
11
10
9
8
7
6
VCC = 48V
VCC = 10.8V
VCC (V)
020 40 60 80
GATE DRIVE (VGATE – VCC) (V)
1641-1 G08
16
14
12
10
8
6
TA = 25°C
TEMPERATURE (°C)
–50 –25 0 25 50 75 100
TIMER PIN PULL UP CURRENT (µA)
1641-1 G09
–40
–50
–60
–70
–80
–90
–100
–110
VCC = 48V
VCC (V)
10 30 50 70 90
TIMER PIN PULL UP CURRENT (µA)
1641-1 G10
16
14
12
10
8
6
TA = –45°C
TA = 0°C
TA = 25°C
TA = 85°C
TEMPERATURE (°C)
–50 –25 0 25 50 75 100
ON PIN HIGH VOLTAGE THRESHOLD (V)
1641-1 G11
1.335
1.330
1.325
1.320
1.315
1.310
1.305
1.300
1.295
1.290
1.285
V
CC
= 48V
TEMPERATURE (°C)
–50 –25 0 25 50 75 100
ON PIN LOW VOLTAGE THRESHOLD (V)
1641-1 G12
1.239
1.237
1.235
1.233
1.231
1.229
1.227
1.225
1.223
V
CC
= 48V
TEMPERATURE (°C)
–50 –25 0 25 50 75 100
ON PIN LOW VOLTAGE HYSTERESIS (V)
1641-1 G13
0.100
0.090
0.080
0.070
0.060
0.050
V
CC
= 48V
ILOAD (mA)
10 30 50 70 90
PWRGD VOUT LOW (V)
1641-1 G14
20
18
16
14
12
10
8
6
4
2
0
TA = –45°C
VCC = 48V
TA = 85°C
TA = 25°C
VFEEDBACK (V)
00.2 0.4 0.6 0.8 1
SENSE PIN REGULATION VOLTAGE (mV)
1641-1 G15
50
45
40
35
30
25
20
15
10
5
0
VCC = 48V
TA = 25°C
Gate Drive vs Temperature Gate Drive vs VCC
TIMER Pin Pull Up Current vs
Temperature
TIMER Pin Pull Up Current vs VCC
ON Pin High Voltage Threshold vs
Temperature
ON Pin Low Voltage Threshold vs
Temperature
ON Pin Voltage Hysteresis vs
Temperature PWRGD VOUT Low vs ILOAD
SENSE Pin Regulation Voltage vs
VFEEDBACK
5
LT1641-1/LT1641-2
164112fc
PI FU CTIO S
UUU
ON (Pin 1): The ON pin is used to implement undervoltage
lockout. When the ON pin is pulled below the 1.233V High-
to-Low threshold voltage, an undervoltage condition is
detected and the GATE pin is pulled low to turn the
MOSFET off. When the ON pin rises above the 1.313V
Low-to-High threshold voltage, the MOSFET is turned on
again.
Pulsing the ON pin low after a current limit fault will reset
the fault latch and allow the part to turn back on.
FB (Pin 2): Power Good Comparator Input. It monitors the
output voltage with an external resistive divider. When the
voltage on the FB pin is lower than the High-to-Low
threshold of 1.233V, the PWRGD pin is pulled low and
released when the FB pin is pulled above the 1.313V Low-
to-High threshold.
The FB pin also effects foldback current limit (see Figure 7
and related discussion).
PWRGD (Pin 3): Open Collector Output to GND. The
PWRGD pin is pulled low whenever the voltage at the FB
pin falls below the High-to-Low threshold voltage. It goes
into a high impedance state when the voltage on the FB pin
exceeds the Low-to-High threshold voltage. An external
pull-up resistor can pull the pin to a voltage higher or lower
than V
CC
.
GND (Pin 4): Chip Ground.
TIMER (Pin 5): Timing Input. An external timing capacitor
at this pin programs the maximum time the part is allowed
to remain in current limit.
When the part goes into current limit, an 77µA pull-up
current source starts to charge the timing capacitor. When
the voltage on the TIMER pin reaches 1.233V, the GATE
pin is pulled low; the pull-up current will be turned off and
the capacitor is discharged by a 3µA pull-down current.
When the TIMER pin falls below 0.5V, the GATE pin either
turns on automatically (LT1641-2) or turns on once the
ON pin is pulsed low to reset the internal fault latch
(LT1641-1). If the ON pin is not cycled low, the GATE pin
remains latched off. Use no less than 1.5nF for the timing
capacitor, C2.
GATE (Pin 6): The High Side Gate Drive for the External
N-Channel. An internal charge pump guarantees at least
10V of gate drive for supply voltages above 20V and 4.5V
gate drive for supply voltages between 10.8V and 20V. The
rising slope of the voltage at the GATE is set by an external
capacitor connected from the GATE pin to GND and an
internal 10µA pull-up current source from the charge
pump output.
When the current limit is reached, the GATE pin voltage will
be adjusted to maintain a constant voltage across the
sense resistor while the timer capacitor starts to charge.
If the TIMER pin voltage exceeds 1.233V, the GATE pin will
be pulled low.
The GATE pin is pulled to GND whenever the ON pin is
pulled low, the V
CC
supply voltage drops below the 8.3V
undervoltage lockout threshold or the TIMER pin rises
above 1.233V.
SENSE (Pin 7): The Current Limit Sense Pin. A sense
resistor must be placed in the supply path between V
CC
and SENSE. The current limit circuit will regulate the
voltage across the sense resistor (V
CC
– V
SENSE
) to 47mV
when V
FB
is 0.5V or higher. If V
FB
drops below 0.5V, the
voltage across the sense resistor decreases linearly and
stops at 12mV when V
FB
is 0V.
To defeat current limit, short the SENSE pin to the V
CC
pin.
V
CC
(Pin 8): The Positive Supply Input ranges from 9V to
80V for normal operation. I
CC
is typically 2mA. An internal
undervoltage lockout circuit disables the chip for inputs
less than 8.3V.
6
LT1641-1/LT1641-2
164112fc
TEST CIRCUIT
V
CC
SENSE
GATE
TIMER
ON
FB
PWRGD
GND
5k 10nF
24V
1641-1 F01
V
+
5V
+
–
Figure 1
BLOCK DIAGRA
W
–
+
+
–
–
+
–
+
80µA
V
P
V
P
LOGIC
1.233V
0.5V
12mV ~ 47mV
UNDERVOLTAGE LOCKOUT
8.3V
V
CC
GND
0.5V
1.233V
–
+
–
+
1.233V
PWRGD
TIMER
1641-1 BD
V
CC
SENSE
V
P
GEN
FB
ON
3µA
GATE
+
–
CHARGE
PUMP
AND
GATE
DRIVER
REF GEN
7
LT1641-1/LT1641-2
164112fc
ON
1641-1 F02
GATE
5V
t
PLHON
1.313V
1V
t
PHLON
1.233V
FB
1641-1 F03
PWRGD 1V
tPLHFB
1.313V
1V
tPHLFB
1.233V
V
CC
– SENSE
1641-1 F04
GATE
V
CC
t
PHLSENSE
47mV
TI I G DIAGRA S
WUW
Figure 2. ON to GATE Timing Figure 3. FB to PWRGD Timing
Figure 4. SENSE to GATE Timing
APPLICATIO S I FOR ATIO
WUUU
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors on the boards draw high peak
currents from the backplane power bus as they charge up.
The transient currents can permanently damage the con-
nector pins and glitch the system supply, causing other
boards in the system to reset.
The chip is designed to turn on a board’s supply voltage in
a controlled manner, allowing the board to be safely
inserted or removed from a live backplane. The chip also
provides undervoltage and overcurrent protection while a
power good output signal indicates when the output
supply voltage is ready.
Power-Up Sequence
The power supply on a board is controlled by placing an
external N-channel pass transistor (Q1) in the power path
(Figure 5). Resistor R
S
provides current detection and
capacitor C1 provides control of the GATE slew rate.
Resistor R6 provides current control loop compensation
while R5 prevents high frequency oscillations in Q1.
Resistors R1 and R2 provide undervoltage sensing.
After the power pins first make contact, transistor Q1 is
turned off. If the voltage at the ON pin exceeds the turn-on
threshold voltage, the voltage on the V
CC
pin exceeds the
undervoltage lockout threshold, and the voltage on the
TIMER pin is less than 1.233V, transistor Q1 will be turned
on (Figure 6). The voltage at the GATE pin rises with a slope
equal to 10µA/C1 and the supply inrush current is set at
I
INRUSH
= C
L
• 10µA/C1. If the voltage across the current
sense resistor R
S
gets too high, the inrush current will then
be limited by the internal current limit circuitry which
adjusts the voltage on the GATE pin to maintain a constant
voltage across the sense resistor.
Once the voltage at the output has reached its final value,
as sensed by resistors R3 and R4, the PWRGD pin goes
high.
8
LT1641-1/LT1641-2
164112fc
Short-Circuit Protection
The chip features a programmable foldback current limit
with an electronic circuit breaker that protects against
short-circuits or excessive supply currents. The current
limit is set by placing a sense resistor between V
CC
(Pin 8)
and SENSE (Pin 7).
To prevent excessive power dissipation in the pass tran-
sistor and to prevent voltage spikes on the input supply
during short-circuit conditions at the output, the current
folds back as a function of the output voltage, which is
sensed at the FB pin (Figure 7).
When the voltage at the FB pin is 0V, the current limit
circuit drives the GATE pin to force a constant 12mV drop
across the sense resistor. As the output voltage at the FB
pin increases, the voltage across the sense resistor in-
creases until the FB pin reaches 0.5V, at which point the
voltage across the sense resistor is held constant at 47mV.
The maximum current limit is calculated as:
I
LIMIT
= 47mV/R
SENSE
For a 0.025Ω sense resistor, the current limit is set at
1.88A and folds back to 480mA when the output is shorted
to ground.
The IC also features a variable overcurrent response time.
The time required to regulate Q1’s drain current depends
on: Q1’s input capacitance; gate capacitor C1 and com-
pensation resistor R6; and the internal delay from the
SENSE to the GATE pin. Figure 8 shows the delay from a
voltage step at the SENSE pin until the GATE voltage starts
falling, as a function of overdrive.
TIMER
The TIMER pin (Pin 5) provides a method for program-
ming the maximum time the chip is allowed to operate in
current limit. When the current limit circuitry is not active,
the TIMER pin is pulled to GND by a 3µA current source.
After the current limit circuit becomes active, an 80µA pull-
up current source is connected to the TIMER pin and the
voltage will rise with a slope equal to 77µA/C
TIMER
as long
as the current limit circuit remains active. Once the desired
maximum current limit time is set, the capacitor value is:
C(nF) = 62 • t(ms).
If the current limit circuit turns off, the TIMER pin will be
discharged to GND by the 3µA current source.
Whenever the TIMER pin reaches 1.233V, either the inter-
nal fault latch is set (LT1641-1) or the autorestart latch is
set (LT1641-2). The GATE pin is immediately pulled to
GND and the TIMER pin is pulled back to GND by the 3µA
APPLICATIO S I FOR ATIO
WUUU
SHORT
PIN
V
CC
TIMER
SENSE GATE
876
54
21
3
D1
CMPZ
5248B
GND
PWRGD PWRGD
FB
R5
10Ω
5%
ON
R1
49.9k
1%
V
IN
24V
GND 1641-1 F05
R2
3.4k
1%
C2
0.68µF
R6,
1k, 5%
R
S
0.025Ω
C1
10nF
R3
59k
1%
R4
3.57k
1%
R7
24k
5%
+C
L
V
OUT
LT1641-1
Q1
IRF530
Figure 5. Typical Application Figure 6. Power-Up Waveforms
9
LT1641-1/LT1641-2
164112fc
APPLICATIO S I FOR ATIO
WUUU
Figure 8. Response Time to Overcurrent
12mV
0V 0.5V V
FB
1641-1 F07
47mV
V
CC
– V
SENSE
Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage
50mV 100mV 150mV 200mV
1641-1 F08
12µs
10µs
8µs
6µs
4µs
2µs
PROPAGATION DELAY
V
CC
– V
SENSE
current source. When the TIMER pin falls below 0.5V, the
GATE pin either turns on automatically (LT1641-2) or once
the ON pin is pulsed low to reset the internal fault latch
(LT1641-1).
The waveform in Figure 9 shows how the output latches off
following a short-circuit. The drop across the sense resis-
tor is held at 12mV as the timer ramps up. Since the output
did not rise bringing FB above 0.5V, the circuit latches off.
For Figure 9, C
T
= 100nF.
Undervoltage and Overvoltage Detection
The ON pin can be used to detect an undervoltage condi-
tion at the power supply input. The ON pin is internally
connected to an analog comparator with 80mV of hyster-
esis. If the ON pin falls below its threshold voltage (1.233V),
the GATE pin is pulled low and is held low until ON is high
again.
Figure 10 shows an overvoltage detection circuit. When
the input voltage exceeds the Zener diode’s breakdown
voltage, D2 turns on and starts to pull the TIMER pin high.
After the TIMER pin is pulled higher than 1.233V, the fault
latch is set and the GATE pin is pulled to GND immediately,
turning off transistor Q1. The waveforms are shown in
Figure 11. Operation is restored either by interrupting
power or by pulsing ON low.
Power Good Detection
The chip includes a comparator for monitoring the output
voltage. The noninverting input (FB pin) is compared
against an internal 1.233V precision reference and exhib-
its 80mV hysteresis. The comparator’s output (PWRGD
pin) is an open collector capable of operating from a pull-
up as high as 100V.
The PWRGD pin can be used to directly enable/disable a
power module with an active high enable input. Figure 12
shows how to use the PWRGD pin to control an active low
enable input power module. Signal inversion is accom-
plished by transistor Q2 and R7.
Supply Transient Protection
The IC is 100% tested and guaranteed to be safe from
damage with supply voltages up to 100V. However, spikes
above 100V may damage the part. During a short-circuit
condition, the large change in currents flowing through
the power supply traces can cause inductive voltage
spikes which could exceed 100V. To minimize the spikes,
the power trace parasitic inductance should be minimized
by using wider traces or heavier trace plating and a 0.1µF
bypass capacitor placed between V
CC
and GND. A surge
suppressor at the input can also prevent damage from
voltage surges.
10
LT1641-1/LT1641-2
164112fc
SHORT
PIN
V
CC
TIMER
SENSE GATE
876
54
21
3
D1
CMPZ
5248B
GND
PWRGD PWRGD
FB
R5
10Ω
5%
ON
R1
49.9k
1%
V
IN
24V
GND 1641-1 F10
R2
3.4k
1%
C2
0.68µF
D2
30V
1N5256B
R6,
1k, 5%
R
S
0.025Ω
C1
10nF
R3
59k
1%
R4
3.57k
1%
R7
24k
5%
+C
L
V
OUT
LT1641-1
Q1
IRF530
Figure 10. Overvoltage Detection
Figure 11. Overvoltage Waveforms
APPLICATIO S I FOR ATIO
WUUU
Figure 9. Short-Circuit Waveforms
GATE Pin Voltage
A curve of gate drive vs V
CC
is shown in Figure 13. The
GATE pin is clamped to a maximum voltage of 18V above
the input voltage. At minimum input supply voltage of 9V,
the minimum gate drive voltage is 4.5V. When the input
supply voltage is higher than 20V, the gate drive voltage is
at least 10V and a regular N-FET can be used. In applica-
tions over a 9V to 24V range, a logic level N-FET must be
used with a proper protection Zener diode between its gate
and source (as D1 shown is Figure 5).
11
LT1641-1/LT1641-2
164112fc
APPLICATIO S I FOR ATIO
WUUU
VCC
TIMER
SENSE GATE
876
54
21
3
D1
CMPZ
5248B
GND
PWRGD
FB
R5
10Ω
5%
ON
R1
294k
1%
VIN
48V
UV = 37V
GND
1641-1 F12
R2
10.2k
1%
C2
0.68µF
R6,
1k, 5%
RS
0.01Ω
C1
10nF
R3
143k
1%
R4
4.22k
1%
R7
47k
5%
+
CL
220µF
Q2
MMBT5551LT1
VOUT
LT1641-1
ACTIVE LOW
ENABLE MODULE
VOUT–
VOUT+
VIN–
ON/OFF
VIN+
Q1
IRF530
SHORT
PIN
Figure 12. Active Low Enable Module
R1
SENSE
RESISTOR, R
S
1641-1 F14
R2
V
CC
SENSE
ON
GND
LT1641-1
I
LOAD
I
LOAD
Figure 14. Recommended Layout for R1, R2 and RS
Figure 13. Gate Drive vs Supply Voltage
V
CC
(V)
8
V
GATE
– V
CC
(V)
18
16
14
12
10
8
6
4
2
0
1641-1 F13
13 18 23
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is recommended. The minimum trace width for 1oz cop-
per foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. 0.03" per amp or wider is recom-
mended. Note that 1oz copper exhibits a sheet resistance
of about 530µΩ/. Small resistances add up quickly in
high current applications. To improve noise immunity, put
the resistor divider to the ON pin close to the chip and keep
traces to V
CC
and GND short. A 0.1µF capacitor from the
ON pin to GND also helps reject induced noise. Figure 14
shows a layout that addresses these issues.
12
LT1641-1/LT1641-2
164112fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2001
LT/LWI 0706 REV C • PRINTED IN USA
PACKAGE DESCRIPTIO
U
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1640A Negative High Voltage Hot Swap Controller Controls an N-FET at Negative Side to – 80V
LTC1421 Dual Channel Hot Swap Controller Operates Two Supplies from 3V to 12V and a Third to –12V
LTC1422 High Side Drive Hot Swap Controller in SO-8 System Reset Output with Programmable Delay
LTC1643 PCI Hot Swap Controller 3.3V, 5V, 12V, –12V Supplies for PCI Bus
LTC1642 Fault Protected Hot Swap Controller Operates from 3V to 16.5V, Handles Surges to 33V
LT4250 Negative 48V Hot Swap Controller Active Current Limiting for Supplies from –20V to –80V
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
