RT8068A
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Applications
zPortable Instruments
zBattery Powered Equipment
zNotebook Computers
zDistrib uted Power Systems
zIP Phones
zDigital Cameras
Pin Configurations
(TOP VIEW)
WDFN-10L 3x3
3A, 1MHz, Synchronous Step-Down Converter
General Description
The RT8068A is a high efficiency synchronous, step-down
DC/DC converter. It's input voltage range from 2.7V to 5.5V
that provides an adjustable regulated output voltage from
0.6V to VIN while delivering up to 3A of output current.
The internal synchronous low on resistance power
switches increase efficiency and eliminate the need for
an external Schottky diode. The switching frequency is
fixed internally at 1MHz. The 100% duty cycle provides
low dropout operation, hence extending battery life in
portable systems. Current mode operation with internal
compensation allows the transient response to be
optimized over a wide range of loads and output capacitors.
The RT8068A is available in WDFN-10L 3x3 and SOP-8
(Exposed Pad) packages.
Ordering Information
Note :
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Features
zz
zz
zHigh Efficiency : Up to 95%
zz
zz
zLow RDS(ON) Internal Switches : 69m ΩΩ
ΩΩ
Ω/49mΩΩ
ΩΩ
Ω at VIN
= 5V
zz
zz
zFixed Frequency : 1MHz
zz
zz
zNo Schottky Diode Required
zz
zz
zInternal Compensation
zz
zz
z0.6V Reference Allows Low Output Voltage
zz
zz
zLow Dropout Operation : 100% Duty Cycle
zz
zz
zOCP, UVP, OVP, OTP
zz
zz
zRoHS Compliant and Halogen Free
SOP-8 (Exposed Pad)
9
8
7
1
2
3
4
5
10
6
GND
11
LX
PGOOD
LX
EN
LX
PVIN
NC
PVIN
SVIN
FB
LX
LX
PGOOD
EN
PVIN
PVIN
FB
SVIN
GND
2
3
45
6
7
8
9
Marking Information
13 : Product Code
YMDNN : Date Code
RT8068AZQW
RT8068AZSP : Product Code
YMDNN : Date Code
RT8068AZSP
RT8068A
ZSPYMDNN
13 YM
DNN
Package Type
QW : WDFN-10L 3x3 (W-Type)
SP : SOP-8 (Exposed Pad-Option 2)
RT8068A
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)
RT8068A
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Pin No.
WDFN-10L SOP-8
(Exposed Pad)
Pin
Name Pin Function
1, 2, 3 1, 2 LX Switch Node. Connect this pin to the inductor.
4 3 PGOOD
Power Good Indicator. This pin is an open drain logic output that is
pulled to ground when the output voltage is less than 90% of the
target output voltage. Hysteresis = 5%.
5 4 EN Enable Control. Pull high to turn on. Do not float.
6 5 FB
Feedback Pin. This pin receives the feedback voltage from a
resistive voltage divider connected across the output.
7 -- NC No Internal Connection.
8 6 SVIN
Signal Input Pin. Decouple this pin to GND with at least 1μF ceramic
cap.
9,10 7,8 PVIN
Power Input Pin. Decouple this pin to GND with at least 4.7μF
ceramic cap.
11
(Exposed Pad)
9
(Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
Functional Pin Description
Typical Application Circuit
Table 1. Recommended Component Selection
VOUT (V ) RFB1 (k Ω) RFB2 (kΩ) CFF (pF) L (μH) COUT (μF)
3.3 229.5 51 22 2 22 x 2
2.5 161.5 51 22 2 22 x 2
1.8 102 51 22 1.5 22 x 2
1.5 76.5 51 22 1.5 22 x 2
1.2 51 51 22 1.5 22 x 2
1.0 34 51 22 1.5 22 x 2
L
GND
LX
RT8068A
VOUT
PVIN
FB
VIN RFB1
RFB2
CIN
CFF
PGOOD
EN
R1 COUT
SVIN
C1
PGOOD
Chip Enable
100k
10µF
1µF
RT8068A
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Function Block Diagram
Driver
NISEN
Control
Logic
Zero Current
0.72V
0.54V
0.4V
OC
Limit
ISEN
Slope
Com
OSC
Output
Clamp
EA
0.6V
Int-SS
POR
OTP
EN
FB
PVIN
SVIN
EN
LX
PGOOD
PGOOD
VREF
OV
UV
PGOOD
RT8068A
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DS8068A-03 May 2011www.richtek.com
Parameter Symbol Test Conditions Min Typ Max Unit
Feedback Reference Voltage VREF 0.594 0.6 0.606 V
Feedback Leakage Current IFB -- 0.1 0.4 μA
Active , VFB = 0.7V, Not
Switching -- 110 140
DC Bias Current
Shutdown -- -- 1
μA
Output Voltage Line Regulation VIN = 2.7V to 5.5V
IOU T = 0A -- 0.3 -- %/V
Output Voltage Load Regulation IOU T = 0A to 3A −1 -- 1 %
Switch Leakage Current -- -- 1 μA
Switching Frequency 0.8 1 1.2 MHz
Switch On Resistance, High RDS(ON)_P V
IN = 5V -- 69 -- mΩ
Switch On Resistance, Low RDS(ON)_N VIN = 5V -- 49 -- mΩ
P-MOSFET Current Limit ILIM 4 -- -- A
VIN Rising 2.2 2.4 2.6
Under Voltage Lockout
Threshold VUVLO VIN Falling 2 2.2 2.4 V
(VIN = 3.3V, TA = 25°C, unless otherwise specified)
Electrical Characteristics
Recommended Operating Conditions (Note 4)
zSupply Input Voltage, PVIN, SVIN --------------------------------------------------------------------------------- 2.7V to 5.5V
zJunction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C
zAmbient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C
Absolute Maximum Ratings (Note 1)
zSupply Input Voltage, PVIN, SVIN --------------------------------------------------------------------------------- −0.3V to 6.5V
zLX Pin
DC ------------------------------------------------------------------------------------------------------------------------- (VIN + 0.3V) to 6.8V
< 20ns ------------------------------------------------------------------------------------------------------------------- −2.5V to 9V
zOther I/O Pin Voltage ------------------------------------------------------------------------------------------------- −0.3V to 6.5V
z Power Dissipation, PD @ TA = 25°C
WDFN-10L 3x3 --------------------------------------------------------------------------------------------------------- 1.429W
SOP-8 (Exposed Pad) ----------------------------------------------------------------------------------------------- 1.333W
zPackage Thermal Resistance (Note 2)
WDFN-10L 3x3, θJA --------------------------------------------------------------------------------------------------- 70°C/W
WDFN-10L 3x3, θJC --------------------------------------------------------------------------------------------------- 8.2°C/W
SOP-8 (Exposed Pad), θJA ------------------------------------------------------------------------------------------ 75°C/W
SOP-8 (Exposed Pad), θJC ----------------------------------------------------------------------------------------- 15°C/W
zLead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C
zJunction Temperature ------------------------------------------------------------------------------------------------- 150°C
zStorage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C
zESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV
MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V
To be continued
RT8068A
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Parameter Symbol Test Conditions Min Typ Max Unit
Logic-High VIH 1.6 -- --
EN Input
Threshold Voltage Logic-Low VIL -- -- 0.4
V
EN Pull Low Resistance -- 500 -- kΩ
Over Temperature Protection TSD -- 150 -- °C
Over Temperature Protection
Hysteresis -- 20 -- °C
Soft-Start Time tSS 500 -- -- μs
VOUT Discharge Resistance -- 100 -- Ω
VOUT Over Voltage Protection
(Latch-Off, Delay Time = 10μs) 115 120 130 %
VOUT Under Voltage Lock Out
(Latch-Off) 57 66 75 %
Power Good Measured FB, With Respect to
VREF 85 90 -- %
Power Good Hysteresis -- 5 -- %
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of
JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the
packages.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
RT8068A
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Typical Operating Characteristics
Output Voltage vs. Output Current
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
0 0.5 1 1.5 2 2.5 3
Output Current (A)
Output Voltage (V)
VIN = 5V
VOUT = 1.8V
VIN = 3.3V
Current Limit vs. Input Voltage
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
2.533.544.555.5
Input Voltage (V)
Current Limit (A)
VOUT = 1.05V
Current Limit vs . Te m perature
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Current Limit (A)
VIN = 5V
VOUT = 1.05V
VIN = 3.3V
Efficiency vs. Load Curre nt
0
10
20
30
40
50
60
70
80
90
100
00.511.522.53
Load Current (A)
Efficiency (%)
VOUT = 1.05V
VIN = 3.3V
VIN = 5V
Efficiency vs. Load Current
0
10
20
30
40
50
60
70
80
90
100
0 0.5 1 1.5 2 2.5 3
Load Current (A)
Efficiency (%)
VOUT = 3.3V
VIN = 4.2V
VIN = 5V
Efficiency vs. Load Current
0
10
20
30
40
50
60
70
80
90
100
00.511.522.53
Load Current (A)
Efficiency (%)
VOUT = 1.8V
VIN = 3.3V
VIN = 5V
RT8068A
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RDS(ON) vs. Temperature
35
40
45
50
55
60
65
70
75
80
85
90
-50 -25 0 25 50 75 100 125
Temperature (°C)
RDS(ON) (mΩ )
Ω
P-MOSFET
VIN = 5V
N-MOSFET
Over Voltage Protection
Time (10μs/Div)
VIN = 5V, VOUT = 1.8V, IOUT = 1A
VOUT
(1V/Div)
VLX
(2V/Div)
Load Transient Response
Time (50μs/Div)
VIN = 5V, VOUT = 1.8V, IOUT = 0.5A to 3A
IOUT
(2A/Div)
VOUT
(50mV/Div)
Load Transient Response
Time (50μs/Div)
VIN = 5V, VOUT = 1.8V, IOUT = 1.5A to 3A
IOUT
(2A/Div)
VOUT
(50mV/Div)
Switching
Time (500ns/Div)
VIN = 5V, VOUT = 1.8V, IOUT = 3A
ILX
(2A/Div)
VLX
(5V/Div)
VOUT
(5mV/Div)
Switching
Time (500ns/Div)
VIN = 5V, VOUT = 1.8V, IOUT = 1.5A
ILX
(1A/Div)
VLX
(5V/Div)
VOUT
(5mV/Div)
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Over Current Protection
Time (2.5μs/Div)
VIN = 5V, VOUT = 1.8V
VOUT
(1V/Div)
VLX
(2V/Div)
ILX
(5A/Div)
Power On from VIN
Time (2.5ms/Div)
VOUT = 1.8V, IOUT = 3A
ILX
(2A/Div)
VOUT
(1V/Div)
VIN
(2V/Div)
Power Off from VIN
Time (2.5ms/Div)
VOUT = 1.8V, IOUT = 3A
ILX
(2A/Div)
VOUT
(1V/Div)
VIN
(2V/Div)
Power On from EN
Time (200μs/Div)
VOUT
(1V/Div)
VEN
(5V/Div)
ILX
(2A/Div)
VIN = 5V, VOUT = 1.8V, IOUT = 3A
Power Off from EN
Time (40μs/Div)
VOUT
(1V/Div)
VEN
(5V/Div)
ILX
(2A/Div)
VIN = 5V, VOUT = 1.8V, IOUT = 3A
Under Voltage Protection
Time (5μs/Div)
VIN = 5V, VOUT = 1.8V
VOUT
(1V/Div)
VLX
(2V/Div)
RT8068A
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Application Information
The RT8068A is a single-phase buck converter. It provides
single feedback loop, current mode control with fast
transient response. An internal 0.6V reference allows the
output voltage to be precisely regulated for low output
voltage applications. A fixed switching frequency (1MHz)
oscillator and internal compensation are integrated to
minimize external component count. Protection features
include over current protection, under voltage protection,
over voltage protection and over temperature protection.
Output Voltage Setting
Connect a resistive voltage divider at the FB between VOUT
and GND to adjust the output voltage. The output voltage
is set according to the following equation :
Chip Enable and Disable
The EN pin allows for power sequencing between the
controller bias voltage and another voltage rail. The
RT8068A remains in shutdown if the EN pin is lower than
400mV. When the EN pin rises above the VEN trip point,
the RT8068A begins a new initialization and soft-start cycle.
Internal Soft-Start
The RT8068A provides an internal soft-start function to
prevent large inrush current and output voltage overshoot
when the converter starts up. The soft-start (SS)
automatically begins once the chip is enabled. During soft-
start, the internal soft-start capacitor becomes charged
and generates a linear ramping up voltage across the
capacitor. This voltage clamps the voltage at the FB pin,
causing PWM pulse width to increase slowly and in turn
reduce the output surge current. The internal 0.6V
reference takes over the loop control once the internal
ramping-up voltage becomes higher than 0.6V.
FB1
OUT REF FB2
R
V = V 1 + R
⎛⎞
×⎜⎟
⎝⎠
where VREF is 0.6V (typ.).
Figure 1. Setting VOUT with a Voltage Divider
UVLO Protection
The RT8068A has input Under Voltage Lockout protection
(UVLO). If the input voltage exceeds the UVLO rising
threshold voltage (2.4V typ.), the converter resets and
prepares the PWM for operation. If the input voltage falls
below the UVLO falling threshold voltage during normal
operation, the device will stop switching. The UVLO rising
and falling threshold voltage has a hysteresis to prevent
noise-caused reset.
Inductor Selection
The switching frequency (on-time) and operating point (%
ripple or LIR) determine the inductor value as shown below:
(
)
OUT IN OUT
SW LOAD(MAX) IN
VV V
L = f LIR I V
×−
×× ×
where LIR is the ratio of the peak-to-peak ripple current to
the average inductor current.
Find a low loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and can work well at 200kHz. The core must
be large enough not to saturate at the peak inductor current
(IPEAK) :
PEAK LOAD(MAX) LOAD(MAX)
LIR
I = I + I
2
⎛⎞
×
⎜⎟
⎝⎠
The calculation above serves as a general reference. To
further improve transient response, the output inductor
can be further reduced. This relation should be considered
along with the selection of the output capacitor.
Input Capacitor Selection
High quality ceramic input decoupling capacitor, such as
X5R or X7R, with values greater than 20μF are
recommended for the input capacitor. The X5R and X7R
ceramic capacitors are usually selected for power regulator
capacitors because the dielectric material has less
capacitance variation and more temperature stability.
Voltage rating and current rating are the key parameters
when selecting an input capacitor. Generally, selecting an
input capacitor with voltage rating 1.5 times greater than
the maximum input voltage is a conservatively safe design.
FB
GND
VOUT
RFB1
RFB2
RT8068A
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OUT OUT
IN_RMS LOAD IN IN
VV
I = I 1
VV
⎛⎞
××−
⎜⎟
⎝⎠
The next step is selecting a proper capacitor for RMS
current rating. One good design is using more than one
capacitor with low equivalent series resistance (ESR) in
parallel to form a capacitor bank.
The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be
approximately calculated using the following equation :
OUT(MAX)
IN IN SW
I0.25
V = Cf
×
Δ×
For example, if IOUT_MAX = 3A, CIN = 20μF, fSW = 1MHz,
the input voltage ripple will be 37.5mV.
Output Capacitor Selection
The output capacitor and the inductor form a low pass
filter in the buck topology. In steady state condition, the
ripple current flowing into/out of the capacitor results in
ripple voltage. The output voltage ripple (VP-P) can be
calculated by the following equation :
P_P LOAD(MAX) OUT SW
1
V= LIRI ESR + 8C f
⎛⎞
××
⎜⎟
××
⎝⎠
For a given output voltage sag specification, the ESR value
can be determined.
Another parameter that has influence on the output voltage
sag is the equivalent series inductance (ESL). The rapid
change in load current results in di/dt during transient.
Therefore, the ESL contributes to part of the voltage sag.
Using a capacitor with low ESL can obtain better transient
performance. Generally, using several capacitors
connected in parallel can have better transient performance
than using a single capacitor for the same total ESR.
Unlike the electrolytic capacitor, the ceramic capacitor has
relatively low ESR and can reduce the voltage deviation
When load transient occurs, the output capacitor supplies
the load current before the controller can respond.
Therefore, the ESR will dominate the output voltage sag
during load transient. The output voltage undershoot (VSAG)
can be calculated by the following equation :
SAG LOAD
V = I ESRΔ×
The input capacitor is used to supply the input RMS
current, which can be approximately calculated using the
following equation :
during load transient. However, the ceramic capacitor can
only provide low capacitance value. Therefore, use a mixed
combination of electrolytic capacitor and ceramic capacitor
to obtain better transient performance.
Power Good Output (PGOOD)
PGOOD is an open-drain type output and requires a pull-
up resistor. PGOOD is actively held low in soft-start,
standby, and shutdown. It is released when the output
voltage rises above 90% of nominal regulation point. The
PGOOD signal goes low if the output is turned off or is
10% below its nominal regulation point.
Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage. When under voltage protection is enabled, both
UGATE and LGATE gate drivers will be forced low if the
output is less than 66% of its set voltage threshold. The
UVP will be ignored for at least 3ms (typ.) after start up or
a rising edge on the EN threshold. Toggle EN threshold or
cycle VIN to reset the UVP fault latch and restart the
controller.
Over Voltage Protection (OVP)
The RT8068A is latched once OVP is triggered and can
only be released by toggling EN threshold or cycling VIN.
There is a 10μs delay built into the over voltage protection
circuit to prevent false transition.
Over Current Protection (OCP)
The RT8068A provides over current protection by detecting
high side MOSFET peak inductor current. If the sensed
peak inductor current is over the current limit threshold
(4A typ.), the OCP will be triggered. When OCP is tripped,
the RT8068A will keep the over current threshold level
until the over current condition is removed.
Thermal Shutdown (OTP)
The device implements an internal thermal shutdown
function when the junction temperature exceeds 150°C.
The thermal shutdown forces the device to stop switching
when the junction temperature exceeds the thermal
shutdown threshold. Once the die temperature decreases
below the hysteresis of 20°C, the device reinstates the
power up sequence.
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Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications of
the RT8068A, the maximum junction temperature is 125°C
and TA is the ambient temperature. The junction to ambient
thermal resistance, θJA, is layout dependent. For SOP-8
(Exposed Pad) packages, the thermal resistance, θJA, is
75°C/W on a standard JEDEC 51-7 four-layer thermal test
board. For WDFN-10L 3x3 packages, the thermal
resistance, θJA, is 70°C/W on a standard JEDEC 51-7
four-layer thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by the following
formulas :
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) package
PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for
WDFN-10L 3x3 package
Figure 2. Derating Curves for RT8068A Packages
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
Four-Layer PCB
WDFN-10L 3x3
SOP-8 (Exposed Pad)
Layout Considerations
Layout is very important in high frequency switching
converter design. The PCB can radiate excessive noise
and contribute to converter instability with improper layout.
Certain points must be considered before starting a layout
using the RT8068A.
Make the traces of the main current paths as short and
wide as possible.
Put the input capacitor as close as possible to the device
pins (VIN and GND).
LX node encounters high frequency voltage swings so it
should be kept in a small area. Keep sensitive
components away from the LX node to prevent stray
capacitive noise pick-up.
Ensure all feedback network connections are short and
direct. Place the feedback network as close to the chip
as possible.
The GND pin and Exposed Pad should be connected to
a strong ground plane for heat sinking and noise
protection.
An example of PCB layout guide is shown in Figure 3.
for reference.
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. For the RT8068A package, the derating
curves in Figure 2 allow the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
Figure 3. PCB Layout Guide
R1
R2
CIN2
CIN1
REN
RPGOOD
VIN
VOUT
COUT
GND
VOUT
Input capacitor must be placed
as close to the IC as possible.
LX should be connected to
inductor by wide and short trace.
Keep sensitive components
away from this trace.
The output capacitor must
be placed near the IC.
The voltage divider must
be connected as close to
the device as possible.
9
8
7
1
2
3
4
5
10
6
GND
11
LX
PGOOD
LX
EN
LX
PVIN
NC
PVIN
SVIN
FB
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Outline Dimension
Dimensions In Millime ters Dimensions In Inches
Sym bol Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 2.950 3.050 0.116 0.120
D2 2.300 2.650 0.091 0.104
E 2.950 3.050 0.116 0.120
E2 1.500 1.750 0.059 0.069
e 0.500 0.020
L 0.350 0.450
0.014 0.018
W-Type 10L DFN 3x3 Package
11
2
2
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
DETAIL A
Pin #1 ID and Tie Bar Mark Options
D
1
E
A3
A
A1
D2
E2
L
b
e
SEE DETAIL A
RT8068A
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Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
A
B
J
F
H
M
C
D
I
Y
X
EXPOSED THERMAL PAD
(Bottom of Package)
8-Lead SOP (Exposed Pad) Plastic Package
Dimensions In Millimeters Dimensions In Inc hes
Symbol Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 4.000 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.510 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.000 0.152 0.000 0.006
J 5.791 6.200 0.228 0.244
M 0.406 1.270 0.016 0.050
X 2.000 2.300 0.079 0.091
Option 1 Y 2.000 2.300 0.079 0.091
X 2.100 2.500 0.083 0.098
Option 2 Y 3.000 3.500 0.118 0.138
