LTC2430/LTC2431
1
24301f
The LTC
®
2430/LTC2431 are 2.7V to 5.5V micropower
20-bit differential ∆Σ analog-to-digital converters with an
integrated oscillator, 3ppm INL and 0.56ppm RMS noise.
They use delta-sigma technology and provide single cycle
settling time for multiplexed applications. Through a
single pin, the
LTC2430/LTC2431
can be configured for
better than 110dB differential mode rejection at 50Hz or
60Hz ±2%, or they can be driven by an external oscillator
for a user-defined rejection frequency. The internal oscil-
lator requires no external frequency setting components.
The converters accept any external differential reference
voltage from 0.1V to V
CC
for flexible ratiometric and
remote sensing measurement configurations. The full-
scale differential input range is from –0.5V
REF
to 0.5V
REF
.
The reference common mode voltage, V
REFCM
, and the
input common mode voltage, V
INCM
, may be indepen-
dently set anywhere within GND to V
CC
. The DC common
mode input rejection is better than 120dB.
The LTC
2430/LTC2431
communicate through a flexible
3-wire digital interface that is compatible with SPI and
MICROWIRE
TM
protocols.
■
Direct Sensor Digitizer
■
Weight Scales
■
Direct Temperature Measurement
■
Gas Analyzers
■
Strain Gauge Transducers
■
Instrumentation
■
Data Acquisition
■
Industrial Process Control
■
DVMs and Meters
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Low Supply Current (200µA in Conversion Mode
and 4µA in Autosleep Mode)
■
Differential Input and Differential Reference
with GND to V
CC
Common Mode Range
■
3ppm INL, No Missing Codes
■
10ppm Full-Scale Error and 1ppm Offset
■
0.56ppm Noise, 20.8 ENOBs
■
No Latency: Digital Filter Settles in a Single Cycle.
Each Conversion Is Accurate, Even After an
Input Step
■
Single Supply 2.7V to 5.5V Operation
■
Internal Oscillator—No External Components
Required
■
110dB Min, 50Hz/60Hz Notch Filter
■
Pin Compatible with 24-Bit LTC2410/LTC2411
20-Bit No Latency ∆Σ
TM
ADCs
with Differential Input and
Differential Reference
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
V
CC
F
O
64
12
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
0.1µF
0.1µF
LTC2431
24301 TA01
4.7µF
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
V
CC
LT1790
(V
OUT
+ 0.25V) TO 20V
V
OUT
3V TO 5V
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO S
U
INPUT VOLTAGE (V)
–2.5
TUE (ppm OF V
REF
)
1
3
5
1.5
24301 G01
–1
–3
0
2
4
–2
–4
–5 –1.5–2 –0.5–1 0.5 1 2
02.5
V
CC
= 5V
V
REF
= 5V
V
INCM
= V
INCM
= 2.5V
F
O
= GND
85°C25°C
–45°C
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
LTC2430/LTC2431
2
24301f
2430
2430I
(Notes 1, 2)
ORDER PART NUMBER
Supply Voltage (V
CC
) to GND.......................–0.3V to 7V
Analog Input Pins Voltage
to GND......................................... –0.3V to (V
CC
+ 0.3V)
Reference Input Pins Voltage
to GND......................................... –0.3V to (V
CC
+ 0.3V)
Digital Input Voltage to GND........ –0.3V to (V
CC
+ 0.3V)
T
JMAX
= 125°C, θ
JA
= 120°C/W
LTC2430CGN
LTC2430IGN
GN PART MARKING
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
1
2
3
4
5
VCC
REF+
REF–
IN+
IN–
10
9
8
7
6
FO
SCK
SDO
CS
GND
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Digital Output Voltage to GND ..... –0.3V to (V
CC
+ 0.3V)
Operating Temperature Range
LTC2430C/LTC2431C .............................. 0°C to 70°C
LTC2430I/LTC2431I ........................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
LTXD
LTXE
ORDER PART NUMBER
LTC2431CMS
LTC2431IMS
MS PART MARKING
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
GND
V
CC
REF
+
REF
–
IN
+
IN
–
GND
GND
GND
GND
F
O
SCK
SDO
CS
GND
GND
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤ V
REF
≤ V
CC
, –0.5 • V
REF
≤ V
IN
≤ 0.5 • V
REF
(Note 5) ●20 Bits
Integral Nonlinearity 4.5V ≤ V
CC
≤ 5.5V, REF
+
= 2.5V, REF
–
= GND, V
INCM
= 1.25V (Note 6) 2 ppm of V
REF
5V ≤ V
CC
≤ 5.5V, REF
+
= 5V, REF
–
= GND, V
INCM
= 2.5V (Note 6) ●3 20 ppm of V
REF
REF
+
= 2.5V, REF
–
= GND, V
INCM
= 1.25V (Note 6) 10 ppm of V
REF
Offset Error 2.5V ≤ REF
+
≤ V
CC
, REF
–
= GND, ●520 µV
GND ≤ IN
+
= IN
–
≤ V
CC
(Note 14)
Offset Error Drift 2.5V ≤ REF
+
≤ V
CC
, REF
–
= GND, 50 nV/°C
GND ≤ IN
+
= IN
–
≤ V
CC
Positive Full-Scale Error 2.5V ≤ REF
+
≤ V
CC
, REF
–
= GND, ●10 20 ppm of V
REF
IN
+
= 0.75REF
+
, IN
–
= 0.25 • REF
+
Positive Full-Scale Error Drift 2.5V ≤ REF
+
≤ V
CC
, REF
–
= GND, 0.1 ppm of V
REF
/°C
IN
+
= 0.75REF
+
, IN
–
= 0.25 • REF
+
Negative Full-Scale Error 2.5V ≤ REF
+
≤ V
CC
, REF
–
= GND, ●10 20 ppm of V
REF
IN
+
= 0.25 • REF
+
, IN
–
= 0.75 • REF
+
Negative Full-Scale Error Drift 2.5V ≤ REF
+
≤ V
CC
, REF
–
= GND, 0.1 ppm of V
REF
/°C
IN
+
= 0.25 • REF
+
, IN
–
= 0.75 • REF
+
Total Unadjusted Error 4.5V ≤ V
CC
≤ 5.5V, REF
+
= 2.5V, REF
–
= GND, V
INCM
= 1.25V 3 ppm of V
REF
5V ≤ V
CC
≤ 5.5V, REF
+
= 5V, REF
–
= GND, V
INCM
= 2.5V 6 ppm of V
REF
REF
+
= 2.5V, REF
–
= GND, V
INCM
= 1.25V 15 ppm of V
REF
Output Noise 5V ≤ V
CC
≤ 5.5V, REF
+
= 5V, V
REF
– = GND, 2.8 µV
RMS
GND ≤ IN
–
= IN
+
≤ 5V, (Note 13)
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
ELECTRICAL CHARACTERISTICS
T
JMAX
= 125°C, θ
JA
= 110°C/W
LTC2430/LTC2431
3
24301f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IN
+
Absolute/Common Mode IN
+
Voltage ●GND – 0.3V V
CC
+ 0.3V V
IN
–
Absolute/Common Mode IN
–
Voltage ●GND – 0.3V V
CC
+ 0.3V V
V
IN
Input Differential Voltage Range ●–V
REF
/2 V
REF
/2 V
(IN
+
– IN
–
)
REF
+
Absolute/Common Mode REF
+
Voltage ●0.1 V
CC
V
REF
–
Absolute/Common Mode REF
–
Voltage ●GND V
CC
– 0.1V V
V
REF
Reference Differential Voltage Range ●0.1 V
CC
V
(REF
+
– REF
–
)
C
S
(IN
+
)IN
+
Sampling Capacitance 1.5 pF
C
S
(IN
–
)IN
–
Sampling Capacitance 1.5 pF
C
S
(REF
+
)REF
+
Sampling Capacitance 1.5 pF
C
S
(REF
–
)REF
–
Sampling Capacitance 1.5 pF
I
DC_LEAK
(IN
+
)IN
+
DC Leakage Current CS = V
CC
, IN
+
= GND ●–10 1 10 nA
I
DC_LEAK
(IN
–
)IN
–
DC Leakage Current CS = V
CC
, IN
–
= V
CC
●–10 1 10 nA
I
DC_LEAK
(REF
+
)REF
+
DC Leakage Current CS = V
CC
, REF
+
= V
CC
●–10 1 10 nA
I
DC_LEAK
(REF
–
)REF
–
DC Leakage Current CS = V
CC
, REF
–
= GND ●–10 1 10 nA
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Common Mode Rejection DC 2.5V ≤ REF
+
≤ V
CC
, REF
–
= GND, ●110 120 dB
GND ≤ IN
–
= IN
+
≤ 5V (Note 5)
Input Common Mode Rejection 2.5V ≤ REF
+
≤ V
CC
, REF
–
= GND, ●140 dB
60Hz ±2% GND ≤ IN
–
= IN
+
≤ 5V, (Notes 5, 7)
Input Common Mode Rejection 2.5V ≤ REF
+
≤ V
CC
, REF
–
= GND, ●140 dB
50Hz ±2% GND ≤ IN
–
= IN
+
≤ 5V, (Notes 5, 8)
Input Normal Mode Rejection (Notes 5, 7) ●110 140 dB
60Hz ±2%
Input Normal Mode Rejection (Notes 5, 8) ●110 140 dB
50Hz ±2%
Reference Common Mode 2.5V ≤ REF
+
≤ V
CC
, GND ≤ REF
–
≤ 2.5V, ●130 140 dB
Rejection DC V
REF
= 2.5V, IN
–
= IN
+
= GND (Note 5)
Power Supply Rejection, DC REF
+
= 2.5V, REF
–
= GND, IN
–
= IN
+
= GND 110 dB
Power Supply Rejection, 60Hz ±2% REF
+
= 2.5V, REF
–
= GND, IN
–
= IN
+
= GND, (Note 7) 120 dB
Power Supply Rejection, 50Hz ±2% REF
+
= 2.5V, REF
–
= GND, IN
–
= IN
+
= GND, (Note 8) 120 dB
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
CO VERTER CHARACTERISTICS
U
A ALOG I PUT A D REFERE CE
UU
U
U
LTC2430/LTC2431
4
24301f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
Supply Voltage ●2.7 5.5 V
I
CC
Supply Current
Conversion Mode CS = 0V (Note 12) ●200 300 µA
Sleep Mode CS = V
CC
(Note 12) ●410 µA
Sleep Mode CS = V
CC
, 2.7V ≤ V
CC
≤ 3.3V 2 µA
(Note 12)
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage 2.7V ≤ V
CC
≤ 5.5V ●2.5 V
CS, F
O
2.7V ≤ V
CC
≤ 3.3V 2.0 V
V
IL
Low Level Input Voltage 4.5V ≤ V
CC
≤ 5.5V ●0.8 V
CS, F
O
2.7V ≤ V
CC
≤ 5.5V 0.6 V
V
IH
High Level Input Voltage 2.7V ≤ V
CC
≤ 5.5V (Note 9) ●2.5 V
SCK 2.7V ≤ V
CC
≤ 3.3V (Note 9) 2.0 V
V
IL
Low Level Input Voltage 4.5V ≤ V
CC
≤ 5.5V (Note 9) ●0.8 V
SCK 2.7V ≤ V
CC
≤ 5.5V (Note 9) 0.6 V
I
IN
Digital Input Current 0V ≤ V
IN
≤ V
CC
●–10 10 µA
CS, F
O
I
IN
Digital Input Current 0V ≤ V
IN
≤ V
CC
(Note 9) ●–10 10 µA
SCK
C
IN
Digital Input Capacitance 10 pF
CS, F
O
C
IN
Digital Input Capacitance (Note 9) 10 pF
SCK
V
OH
High Level Output Voltage I
O
= –800µA●V
CC
– 0.5V V
SDO
V
OL
Low Level Output Voltage I
O
= 1.6mA ●0.4 V
SDO
V
OH
High Level Output Voltage I
O
= –800µA (Note 10) ●V
CC
– 0.5V V
SCK
V
OL
Low Level Output Voltage I
O
= 1.6mA (Note 10) ●0.4 V
SCK
I
OZ
Hi-Z Output Leakage ●–10 10 µA
SDO
DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
POWER REQUIRE E TS
WU
LTC2430/LTC2431
5
24301f
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2;
VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2.
Note 4: FO pin tied to GND or to VCC or to external conversion clock
source with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is calculated as the measured code minus the
expected value.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
EOSC
External Oscillator Frequency Range ●5 2000 kHz
t
HEO
External Oscillator High Period ●0.25 200 µs
t
LEO
External Oscillator Low Period ●0.25 200 µs
t
CONV
Conversion Time F
O
= 0V ●130.86 133.53 136.20 ms
F
O
= V
CC
●157.03 160.23 163.44 ms
External Oscillator (Note 11) ●20510/f
EOSC
(in kHz) ms
f
ISCK
Internal SCK Frequency Internal Oscillator (Note 10) 19.2 kHz
External Oscillator (Notes 10, 11) f
EOSC
/8 kHz
D
ISCK
Internal SCK Duty Cycle (Note 10) ●45 55 %
f
ESCK
External SCK Frequency Range (Note 9) ●2000 kHz
t
LESCK
External SCK Low Period (Note 9) ●250 ns
t
HESCK
External SCK High Period (Note 9) ●250 ns
t
DOUT_ISCK
Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12) ●1.22 1.25 1.28 ms
External Oscillator (Notes 10, 11) ●192/f
EOSC
(in kHz) ms
t
DOUT_ESCK
External SCK 24-Bit Data Output Time (Note 9) ●24/f
ESCK
(in kHz) ms
t
1
CS ↓ to SDO Low Z ●0 200 ns
t
2
CS ↑ to SDO High Z ●0 200 ns
t
3
CS ↓ to SCK ↓(Note 10) ●0 200 ns
t
4
CS ↓ to SCK ↑(Note 9) ●50 ns
t
KQMAX
SCK ↓ to SDO Valid ●220 ns
t
KQMIN
SDO Hold After SCK ↓(Note 5) ●15 ns
t
5
SCK Set-Up Before CS ↓●50 ns
t
6
SCK Hold After CS ↓●50 ns
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
TI I G CHARACTERISTICS
UW
LTC2430/LTC2431
6
24301f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
INPUT VOLTAGE (V)
–2.5
TUE (ppm OF V
REF
)
1
3
5
1.5
24301 G01
–1
–3
0
2
4
–2
–4
–5 –1.5–2 –0.5–1 0.5 1 2
02.5
V
CC
= 5V
V
REF
= 5V
V
INCM
= V
INCM
= 2.5V
F
O
= GND
85°C25°C
–45°C
INPUT VOLTAGE (V)
–1.25
TUE (ppm OF V
REF
)
1
3
5
0.75
24301 G02
–1
–3
0
2
4
–2
–4
–5 –0.75–1 –0.25–0.5 0.25 0.5 1
01.25
V
CC
= 5V
V
REF
= 2.5V
V
INCM
= V
INCM
= 1.25V
F
O
= GND
85°C
–45°C
25°C
INPUT VOLTAGE (V)
–1.25
TUE (ppm OF V
REF
)
20
15
10
5
0
–5
–10
–15
–20 0.75
24301 G03
0.25 1.250.5–1 0 1
V
CC
= 2.7V
V
REF
= 2.5V
V
INCM
= V
INCM
= 1.25V
F
O
= GND
85°C
–45°C
25°C
–0.75 –0.25–0.5
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V) Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
INPUT VOLTAGE (V)
–2.5
INL (ppm OF V
REF
)
1
3
5
1.5
24301 G04
–1
–3
0
2
4
–2
–4
–5 –1.5–2 –0.5–1 0.5 1 2
02.5
V
CC
= 5V
V
REF
= 5V
V
INCM
= V
INCM
= 2.5V
F
O
= GND
85°C
25°C
–45°C
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
INPUT VOLTAGE (V)
–1.25
INL (ppm OF V
REF
)
1
3
5
0.75
24301 G05
–1
–3
0
2
4
–2
–4
–5 –1 0.25 0.5 1
01.25
V
CC
= 5V
V
REF
= 2.5V
V
INCM
= V
INCM
= 1.25V
F
O
= GND
85°C
–45°C
25°C
–0.75 –0.25–0.5
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
INPUT VOLTAGE (V)
–1.25
INL (ppm OF V
REF
)
20
15
10
5
0
–5
–10
–15
–20 0.75
24301 G06
0.25 1.250.5–1 0 1
V
CC
= 2.7V
V
REF
= 2.5V
V
INCM
= V
INCM
= 1.25V
F
O
= GND
85°C
–45°C
25°C
–0.75 –0.25–0.5
Noise Histogram (Output Rate =
7.5Hz, VCC = 5V, VREF = 5V)
OUTPUT CODE (ppm OF VREF)
–2.5
NUMBER OF READINGS (%)
40
35
30
25
20
15
10
5
01.5
24301 G07
–1.5 –0.5 0.5 2.51–2 –1 0 2
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
VINCM = 2.5V
FO = GND
TA = 25°C
GAUSSIAN
DISTRIBUTION
m = –0.25ppm
σ = 0.550ppm
Noise Histogram (Output Rate =
7.5Hz, VCC = 2.7V, VREF = 2.5V)
OUTPUT CODE (ppm OF V
REF
)
–4
NUMBER OF READINGS (%)
12
16
20
4
24301 G08
8
4
10
14
18
6
2
0–2–3 0–1 23 5
16
10,000 CONSECUTIVE
READINGS
V
CC
= 2.7V
V
REF
= 2.5V
V
IN
= 0V
V
INCM
= 2.5V
F
O
= GND
T
A
= 25°C
GAUSSIAN
DISTRIBUTION
m = –1.07ppm
σ = 1.06ppm
RMS Noise
vs Input Differential Voltage
INPUT DIFFERENTIAL VOLTAGE (V)
–2.5
RMS NOISE (ppm OF V
REF
)
0.6
0.8
1.0
1.5
24301 G10
0.4
0.2
0.5
0.7
0.9
0.3
0.1
0–1.5–2 –0.5–1 0.5 1 2
02.5
V
CC
= 5V
V
REF
= 5V
V
INCM
= 2.5V
F
O
= GND
T
A
= 25°C
LTC2430/LTC2431
7
24301f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
RMS Noise vs VINCM RMS Noise vs Temperature (TA)
V
INCM
(V)
–1 0
2.4
RMS NOISE (µV)
2.8
3.4
134
24301 G11
2.6
3.2
3.0
256
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
V
IN
= 0V
V
INCM
= GND
F
O
= GND
T
A
= 25°C
TEMPERATURE (°C)
–50
2.4
RMS NOISE (µV)
2.6
2.8
3.0
3.2
3.4
–25 02550
24301 G12
75 100
VCC = 5V
VREF = 5V
VIN = 0V
VINCM = GND
FO = GND
RMS Noise vs VCC
V
CC
(V)
2.7 3.1
2.4
RMS NOISE (µV)
2.8
3.4
3.5 4.3 4.7
24301 G13
2.6
3.2
3.0
3.9 5.1 5.5
REF
+
= 2.5V
REF
–
= GND
V
IN
= 0V
V
INCM
= GND
F
O
= GND
T
A
= 25°C
RMS Noise vs VREF
V
REF
(V)
0
RMS NOISE (µV)
3.0
3.2
3.4
4
24301 G14
2.8
2.6
2.4 1235
V
CC
= 5V
REF
–
= GND
V
IN
= 0V
V
INCM
= GND
F
O
= GND
T
A
= 25°C
Offset Error vs VINCM
V
INCM
(V)
–1
–1.0
OFFSET ERROR (ppm OF V
REF
)
–0.8
–0.4
–0.2
0
1.0
0.4
134
24301 G15
–0.6
0.6
0.8
0.2
0256
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
V
IN
= 0V
F
O
= GND
T
A
= 25°C
Offset Error vs Temperature
Offset Error vs VREF
TEMPERATURE (°C)
–45
–1.0
OFFSET ERROR (ppm OF V
REF
)
–0.8
–0.4
–0.2
0
1.0
0.4
–15 15 30 90
24301 G16
–0.6
0.6
0.8
0.2
–30 0 45 60 75
V
CC
= 5V
V
REF
=5V
V
IN
= 0V
V
INCM
= GND
F
O
= GND
Offset Error vs VCC
V
CC
(V)
2.7
–1.0
OFFSET ERROR (ppm OF V
REF
)
–0.8
–0.4
–0.2
0
1.0
0.4
3.5 4.3 4.7
24301 G17
–0.6
0.6
0.8
0.2
3.1 3.9 5.1 5.5
REF
+
= V
CC
REF
–
= GND
V
IN
= 0V
V
INCM
= GND
F
O
= GND
T
A
= 25°C
V
REF
(V)
0
OFFSET ERROR (ppm OF V
REF
)
1
3
5
4
24301 G18
–1
–3
0
2
4
–2
–4
–5 1235
V
CC
= 5V
REF
–
= GND
V
IN
= 0V
V
INCM
= GND
F
O
= GND
T
A
= 25°C
Full-Scale Error vs Temperature
TEMPERATURE (°C)
–45
–20
FULL-SCALE ERROR (ppm OF V
REF
)
–10
0
10
20
–30 –15 0 15
24301 G19
30 45 60 75 90
+FS ERROR
–FS ERROR
V
CC
= 5V
V
REF
= 5V
F
O
= GND
V
INCM
= 2.5V
LTC2430/LTC2431
8
24301f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
PSRR vs Frequency at VCC
Conversion Current vs Temperature
Full-Scale Error vs VREF
VREF (V)
0
FULL-SCALE ERROR (ppm OF VREF)
20
15
10
5
0
–5
–10
–15
–20 4
24301 G20
123 53.50.5 1.5 2.5 4.5
+FS ERROR
–FS ERROR
VCC = 5V
REF– = GND
FO = GND
VINCM = 0.5VREF
TA = 25°C
Full-Scale Error vs VCC
V
CC
(V)
2.7
–5
FULL-SCALE ERROR (ppm OF V
REF
)
–4
–2
–1
0
5
2
3.5 4.3 4.7
24301 G21
–3
3
4
1
3.1 3.9 5.1 5.5
+FS ERROR
–FS ERROR
V
REF
= 2.5V
REF
–
= GND
F
O
= GND
V
INCM
= 0.5V
REF
T
A
= 25°C
FREQUENCY AT V
CC
(Hz)
0
–140
REJECTION (dB)
–120
–80
–60
–40
0
20 100 140
24301 G22
–100
–20
80 180 220200
40 60 120 160
V
CC
= 4.1V
DC
±1.4V
REF
+
= 2.5V
REF
–
= GND
IN
+
= GND
IN
–
= GND
F
O
= GND
T
A
= 25°C
PSRR vs Frequency at VCC PSRR vs Frequency at VCC
FREQUENCY AT V
CC
(Hz)
15170
–60
–40
0
15320
24301 G24
–80
–100
15220 15270 15370
–120
–140
–20
REJECTION (dB)
V
CC
= 4.1V
DC
±0.7V
REF
+
= 2.5V
REF
–
= GND
IN
+
= GND
IN
–
= GND
F
O
= GND
T
A
= 25°C
TEMPERATURE (°C)
–45
CONVERSION CURRENT (µA)
200
210
220
75
24301 G25
190
180
160 –15 15 45–30 9003060
170
240
230 V
CC
= 5.5V
V
CC
= 2.7V
V
CC
= 5V
V
CC
= 3V
F
O
= GND
CS = GND
SCK = NC
SDO = NC
Conversion Current
vs Output Data Rate
OUTPUT DATA RATE (READINGS/SEC)
0
100
SUPPLY CURRENT (µA)
200
400
500
600
60 70 80 90
1000
24301 G26
300
10 20 30 40 50 100
700
800
900 V
CC
= 5V
V
CC
= 3V
V
REF
= V
CC
IN
+
= GND
IN
–
= GND
SCK = NC
SDO = NC
SDI = GND
CS = GND
F
O
= EXT OSC
T
A
= 25°C
Sleep Mode Current
vs Temperature
TEMPERATURE (°C)
–45
0
SLEEP MODE CURRENT (µA)
1
3
4
5
–15 15 30 90
24301 G27
2
–30 0 45 60 75
6
V
CC
= 5.5V
V
CC
= 2.7V
V
CC
= 5V
V
CC
= 3V
F
O
= GND
CS = V
CC
SCK = NC
SDO = NC
FREQUENCY AT V
CC
(Hz)
1
0
–20
–40
–60
–80
–100
–120
–140 1k 100k
24301 G23
10 100 10k 1M
REJECTION (dB)
V
CC
= 4.1V
DC
REF
+
= 2.5V
REF
–
= GND
IN
+
= GND
IN
–
= GND
F
O
= GND
T
A
= 25°C
LTC2430/LTC2431
9
24301f
V
CC
(Pin 1): Positive Supply Voltage. Bypass to GND
(Pin␣ 6) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
REF
+
(Pin 2), REF
–
(Pin 3): Differential Reference Input.
The voltage on these pins can have any value between GND
and V
CC
as long as the reference positive input, REF
+
, is
maintained more positive than the reference negative
input, REF
–
, by at least 0.1V.
IN
+
(Pin 4), IN
–
(Pin 5): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and V
CC
+ 0.3V. Within these limits, the
converter bipolar input range (V
IN
= IN
+
– IN
–
) extends
from –0.5 • (V
REF
) to 0.5 • (V
REF
). Outside this input
range, the converter produces unique overrange and
underrange output codes.
GND (Pin 6): Ground. Connect this pin to a ground plane
through a low impedance connection.
CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
UU
U
PI FU CTIO S
GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground
pins internally connected for optimum ground current flow
and V
CC
decoupling. Connect each one of these pins to a
ground plane through a low impedance connection. All seven
pins must be connected to ground for proper operation.
V
CC
(Pin 2): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with 0.1µF ceramic
capacitor as close to the part as possible.
REF
+
(Pin 3), REF
–
(Pin 4): Differential Reference Input.
The voltage on these pins can have any value between GND
and V
CC
as long as the reference positive input, REF
+
, is
maintained more positive than the reference negative
input, REF
–
, by at least 0.1V.
IN
+
(Pin 5), IN
–
(Pin 6): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and V
CC
+ 0.3V. Within these limits the
converter bipolar input range (V
IN
= IN
+
– IN
–
) extends
from –0.5 • (V
REF
) to 0.5 • (V
REF
). Outside this input range
the converter produces unique overrange and underrange
output codes.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
CC
) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
F
O
(Pin 14): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the F
O
pin is connected to V
CC
(F
O
= V
CC
), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the F
O
pin is connected
to GND (F
O
= OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When F
O
is driven by an external clock signal with a frequency f
EOSC
,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency f
EOSC
/2560.
(LTC2430)
(LTC2431)
LTC2430/LTC2431
10
24301f
Figure 1
UU
W
FU CTIO AL BLOCK DIAGRA
AUTOCALIBRATION
AND CONTROL
DAC
DECIMATING FIR
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
ADC
∑
∫∫∫
GND
V
CC
IN
+
IN
–
SDO
SCK
REF
+
REF
–
CS
F
O
(INT/EXT)
2431 FD
+
–
TEST CIRCUITS
1.69k
SDO
2431 TA03
Hi-Z TO V
OH
V
OL
TO V
OH
V
OH
TO Hi-Z
C
LOAD
= 20pF
1.69k
SDO
2431 TA04
Hi-Z TO V
OL
V
OH
TO V
OL
V
OL
TO Hi-Z
C
LOAD
= 20pF
V
CC
SDO (Pin 8): Three-State Digital Output. During the Data
Output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = V
CC
), the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
output for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as the digital input for the external serial
interface clock during the Data Output period. A weak
internal pull-up is automatically activated in Internal Serial
Clock Operation mode. The Serial Clock Operation mode is
determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.
F
O
(Pin 10): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the F
O
pin is connected to V
CC
(F
O
= V
CC
), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the F
O
pin is connected
to GND (F
O
= OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When F
O
is driven by an external clock signal with a frequency f
EOSC
,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency f
EOSC
/2560.
UU
U
PI FU CTIO S
(LTC2431)
LTC2430/LTC2431
11
24301f
CONVERTER OPERATION
Converter Operation Cycle
The LTC2430/LTC2431 are low power, delta-sigma analog-
to-digital converters with an easy-to-use 3-wire serial inter-
face (see Figure 1). Their operation is made up of three states.
The converters’ operating cycle begins with the conversion,
followed by the low power sleep state and ends with the data
output (see Figure 2). The 3-wire interface consists of serial
data output (SDO), serial clock (SCK) and chip select (CS).
Initially, the LTC2430/LTC2431 perform a conversion.
Once the conversion is complete, the device enters the
sleep state. The part remains in the sleep state as long as
CS is HIGH. While in this sleep state, power consumption
is reduced by nearly two orders of magnitude. The conver-
sion result is held indefinitely in a static shift register while
the converter is in the sleep state.
Once CS is pulled LOW, the device exits the low power mode
and enters the data output state. If CS is pulled HIGH be-
fore the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still held
in the internal static shift register. If CS remains LOW after
the first rising edge of SCK, the device begins outputting
the conversion result. Taking CS high at this point will
terminate the data output state and start a new conversion.
There is no latency in the conversion result. The data out-
put corresponds to the conversion just performed. This
result is shifted out on the serial data out pin (SDO) under
the control of the serial clock (SCK). Data is updated on the
falling edge of SCK allowing the user to reliably latch data
on the rising edge of SCK (see Figure 3). The data output
state is concluded once 24 bits are read out of the ADC or
when CS is brought HIGH. The device automatically initiates
a new conversion and the cycle repeats.
Through timing control of the CS and SCK pins, the
LTC2430/LTC2431 offer several flexible modes of
operation (internal or external SCK and free-running
conversion modes). These various modes do not require
programming configuration registers; moreover, they do
not disturb the cyclic operation described above. These
modes of operation are described in detail in the Serial
Interface Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz or
60Hz plus their harmonics. The filter rejection perfor-
mance is directly related to the accuracy of the converter
system clock. The LTC2430/LTC2431 incorporate a highly
accurate on-chip oscillator. This eliminates the need for
external frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the LTC2430/
LTC2431 achieve a minimum of 110dB rejection at the line
frequency (50Hz or 60Hz ±2%).
Ease of Use
The
LTC2430/LTC2431
data output has no latency, filter
settling delay or redundant data associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog inputs is easy.
The LTC2430/LTC2431 perform offset and full-scale cali-
brations in every conversion cycle. This calibration is trans-
parent to the user and has no effect on the cyclic operation
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage change and temperature
drift.
Figure 2. LTC2430/LTC2431 State Transition Diagram
CONVERT
SLEEP
DATA OUTPUT
2431 F02
TRUE
FALSE CS = LOW
AND
SCK
APPLICATIO S I FOR ATIO
WUUU
LTC2430/LTC2431
12
24301f
Power-Up Sequence
The LTC2430/LTC2431 automatically enter an internal
reset state when the power supply voltage V
CC
drops
below approximately 2V. This feature guarantees the
integrity of the conversion result and of the serial interface
mode selection. (See the 2-wire I/O sections in the Serial
Interface Timing Modes section.)
When the VCC voltage rises above this critical threshold,
the LTC2430 or LTC2431 creates an internal power-on-
reset (POR) signal with a duration of approximately 1ms.
The POR signal clears all internal registers. Following the
POR signal, the converter starts a normal conversion
cycle and follows the succession of states described
above. The first conversion result following POR is accu-
rate within the specifications of the device if the power
supply voltage is restored within the operating range
(2.7V to 5.5V) before the end of the POR time interval.
Reference Voltage Range
The LTC2430/LTC2431 accept a differential external refer-
ence voltage. The absolute/common mode voltage speci-
fication for the REF
+
and REF
–
pins covers the entire range
from GND to V
CC
. For correct converter operation, the
REF
+
pin must always be more positive than the REF
–
pin.
The LTC2430/LTC2431 can accept a differential reference
voltage from 0.1V to V
CC
. The converter (LTC2430 or
LTC2431) output noise is determined by the thermal noise
of the front-end circuits, and, as such, its value in micro-
volts is nearly constant with reference voltage. A decrease
in reference voltage will not significantly improve the
converter’s effective resolution. On the other hand, a re-
duced reference voltage will improve the converter’s over-
all INL performance. A reduced reference voltage will also
improve the converter performance when operated with
an external conversion clock (external F
O
signal) at sub-
stantially higher output data rates.
Input Voltage Range
The analog input is truly differential with an absolute/com-
mon mode range for the IN
+
and IN
–
input pins extending
from GND – 0.3V to V
CC
+ 0.3V. Outside these limits, the
ESD protection devices begin to turn on and the errors due
to input leakage current increase rapidly. Within these lim-
its, the LTC2430 or LTC2431 converts the bipolar differen-
tial input signal, V
IN
= IN
+
– IN
–
, from –FS = –0.5 • V
REF
to +FS = 0.5 • V
REF
where V
REF
= REF
+
– REF
–
. Outside this
range the converter indicates the overrange or the
underrange condition using distinct output codes.
Input signals applied to IN
+
and IN
–
pins may extend by
300mV below ground and above V
CC
. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN
+
and IN
–
pins without affecting the performance
of the device. In the physical layout, it is important to main-
tain the parasitic capacitance of the connection between
these series resistors and the corresponding pins as low
as possible; therefore, the resistors should be located as
close as practical to the pins. In addition, series resistors
will introduce a temperature dependent offset error due to
the input leakage current. A 1nA input leakage current will
develop a 1ppm offset error on a 5k resistor if V
REF
= 5V.
This error has a very strong temperature dependency.
Output Data Format
The LTC2430/LTC2431 serial output data stream is 24 bits
long. The first 3 bits represent status information indicat-
ing the sign and conversion state. The next 21 bits are the
conversion result, MSB first. The third and fourth bits to-
gether are also used to indicate an underrange condition
(the differential input voltage is below – FS) or an overrange
condition (the differential input voltage is above +FS).
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW.
Bit 20 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 21 also
provides the underrange or overrange indication. If both
Bit 21 and Bit 20 are HIGH, the differential input voltage is
APPLICATIO S I FOR ATIO
WUUU
LTC2430/LTC2431
13
24301f
above +FS. If both Bit 21 and Bit 20 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2430/LTC2431 Status Bits
Bit 23 Bit 22 Bit 21 Bit 20
Input Range EOC DMY SIG MSB
V
IN
≥ 0.5 • V
REF
0011
0V ≤ V
IN
< 0.5 • V
REF
0010
–0.5 • V
REF
≤ V
IN
< 0V 0 0 0 1
V
IN
< –0.5 • V
REF
0000
Bits 20-0 are the 21-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 23 (EOC) can be captured on the first rising
edge of SCK. Bit 22 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 23rd SCK and may be latched on
the rising edge of the 24th SCK pulse. On the falling edge
of the 24th SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 22) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN
+
and IN
–
pins is maintained
within the –0.3V to (V
CC
+ 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage V
IN
from –FS = –0.5 • V
REF
to
+FS = 0.5 • V
REF
. For differential input voltages greater than
Table 2. LTC2430/LTC2431 Output Data Format
Differential Input Voltage Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 … Bit 0
V
IN
* EOC DMY SIG MSB LSB
V
IN
* ≥ 0.5 • V
REF
** 00110 0 0…0
0.5 • V
REF
** – 1LSB 00101 1 1…1
0.25 • V
REF
** 00101 0 0…0
0.25 • V
REF
** – 1LSB 00100 1 1…1
0 00100 0 0…0
–1LSB 0 0011 1 1…1
–0.25 • V
REF
** 00011 0 0…0
–0.25 • V
REF
** – 1LSB 00010 1 1…1
–0.5 • V
REF
** 00010 0 0…0
V
IN
* < –0.5 • V
REF
** 00001 1 1…1
*The differential input voltage V
IN
= IN
+
– IN
–
.
**The differential reference voltage V
REF
= REF
+
– REF
–
.
Figure 3. Output Data Timing
MSBSIG“0”
1234524
BIT 0
LSB
BIT 19BIT 20BIT 21BIT 22
SDO
SCK
CS
EOC
BIT 23
SLEEP DATA OUTPUT CONVERSION
2431 F03
Hi-Z
APPLICATIO S I FOR ATIO
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LTC2430/LTC2431
14
24301f
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Frequency Rejection Selection (F
O
)
The LTC2430/LTC2431 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz ±2% or 60Hz ±2%. For
60Hz rejection, F
O
should be connected to GND while for
50Hz rejection the F
O
pin should be connected to V
CC
.
The selection of 50Hz or 60Hz rejection can also be made
by driving F
O
to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2430 or
LTC2431 can operate with an external conversion clock.
The converter automatically detects the presence of an
external clock signal at the F
O
pin and turns off the internal
oscillator. The frequency f
EOSC
of the external signal must
be at least 5kHz to be detected. The external clock signal
duty cycle is not significant as long as the minimum and
maximum specifications for the high and low periods t
HEO
and t
LEO
are observed.
While operating with an external conversion clock of a
frequency f
EOSC
, the LTC2430 or LTC2431 provides better
than 110dB normal mode rejection in a frequency range
f
EOSC
/2560 ±4% and its harmonics. The normal mode
rejection as a function of the input frequency deviation
from f
EOSC
/2560 is shown in Figure 4.
Whenever an external clock is not present at the F
O
pin, the
converter (LTC2430 or LTC2431) automatically activates
its internal oscillator and enters the Internal Conversion
Clock mode. Its operation will not be disturbed if the
change of conversion clock source occurs during the
sleep state or during the data output state while the con-
verter uses an external serial clock. If the change occurs
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected. If the change occurs
during the data output state and the converter is in the
Internal SCK mode, the serial clock duty cycle may be
affected but the serial data stream will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of F
O
.
SERIAL INTERFACE PINS
The LTC2430/LTC2431 transmit the conversion results
and receives the start of conversion command through a
synchronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK is used to synchro-
nize the data transfer. Each bit of data is shifted out the
SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the converter (LTC2430 or LTC2431) creates
its own serial clock by dividing the internal conversion clock
by 8. In the External SCK mode of operation, the SCK pin
is used as input. The internal or external SCK mode is
selected on power-up and then reselected every time a
HIGH-to-LOW transition is detected at the CS pin. If SCK
Figure 4. LTC2430/LTC2431 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
APPLICATIO S I FOR ATIO
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DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
EOSC
/2560(%)
–12–8–404812
NORMAL MODE REJECTION (dB)
2431 F04
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
LTC2430/LTC2431
15
24301f
Table 3. LTC2430/LTC2431 State Duration
State Operating Mode Duration
CONVERT Internal Oscillator F
O
= LOW 133ms, Output Data Rate ≤ 7.5 Readings/s
(60Hz Rejection)
F
O
= HIGH 160ms, Output Data Rate ≤ 6.2 Readings/s
(50Hz Rejection)
External Oscillator F
O
= External Oscillator 20510/f
EOSC
s, Output Data Rate ≤ f
EOSC
/20510 Readings/s
with Frequency f
EOSC
kHz
(f
EOSC
/2560 Rejection)
SLEEP As Long As CS = HIGH
DATA OUTPUT Internal Serial Clock F
O
= LOW/HIGH As Long As CS = LOW But Not Longer Than 1.25ms
(Internal Oscillator) (24 SCK cycles)
F
O
= External Oscillator with As Long As CS = LOW But Not Longer Than 192/f
EOSC
ms
Frequency f
EOSC
kHz (24 SCK cycles)
External Serial Clock with As Long As CS = LOW But Not Longer Than 24/f
SCK
ms
Frequency f
SCK
kHz (24 SCK cycles)
is HIGH or floating at power-up or during this transition, the
converter enters the internal SCK mode. If SCK is LOW at
power-up or during this transition, the converter enters the
external SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO, provides the result of the
last conversion as a serial bit stream (MSB first) during the
data output state. In addition, the SDO pin is used as an end
of conversion indicator during the conversion and sleep
states.
When CS is HIGH, the SDO driver is switched to a high
impedance state. This allows sharing the serial interface
with other devices. If CS is LOW during the convert or
sleep state, SDO will output EOC. If CS is LOW during the
conversion phase, the EOC bit appears HIGH on the SDO
pin. Once the conversion is complete, EOC goes LOW.
Chip Select Input (CS)
The active LOW chip select, CS, is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The converter (LTC2430 or LTC2431)
will abort any serial data transfer in progress and start a
new conversion cycle anytime a LOW-to-HIGH transition
is detected at the CS pin after the converter has entered the
data output state (i.e., after the first rising edge of SCK
occurs with CS␣ =␣ LOW).
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO.
SERIAL INTERFACE TIMING MODES
The LTC2430/LTC2431’s 3-wire interface is SPI and
MICROWIRE compatible. This interface offers several
flexible modes of operation. These include internal/exter-
nal serial clock, 2- or 3-wire I/O, single cycle conversion.
The following sections describe each of these serial inter-
face timing modes in detail. In all these cases, the
converter can use the internal oscillator (F
O
= LOW or F
O
= HIGH) or an external oscillator connected to the F
O
pin.
Refer to Table␣ 4 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
APPLICATIO S I FOR ATIO
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LTC2430/LTC2431
16
24301f
EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
TEST EOC
LSBMSBSIG
BIT 0BIT 19 BIT 18BIT 20BIT 21BIT 22
SLEEP SLEEP
TEST EOC
DATA OUTPUT CONVERSION
2431 F05
CONVERSION
Hi-ZHi-ZHi-Z
TEST EOC
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
1µF
2.7V TO 5.5V
LTC2430/
LTC2431
3-WIRE
SPI INTERFACE
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
TEST EOC
Table 4. LTC2430/LTC2431 Interface Timing Modes
Conversion Data Connection
SCK Cycle Output and
Configuration Source Control Control Waveforms
External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 5, 6
External SCK, 2-Wire I/O External SCK SCK Figure 7
Internal SCK, Single Cycle Conversion Internal CS ↓CS ↓Figures 8, 9
Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 10
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC␣ =␣ 1 while a conversion is in progress and EOC = 0 if
the conversion is over. With CS HIGH, the device auto-
matically enters the low power sleep state once the con-
version is complete.
When CS is low, the device enters the data output mode.
The result is held in the internal static shift register until
the first SCK rising edge is seen while CS is LOW. Data is
shifted out the SDO pin on each falling edge of SCK. This
enables external circuitry to latch the output on the rising
edge of SCK. EOC can be latched on the first rising edge
of SCK and the last bit of the conversion result can be
latched on the 24th rising edge of SCK. On the 24th falling
edge of SCK, the device begins a new conversion. SDO
goes HIGH (EOC = 1) indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the 24th
falling edge of SCK, see Figure 6. On the rising edge of CS,
APPLICATIO S I FOR ATIO
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Figure 5. External Serial Clock, Single Cycle Operation
LTC2430/LTC2431
17
24301f
EOC␣ =␣ 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. Data is shifted out the SDO pin on each
falling edge of SCK enabling external circuitry to latch data
on the rising edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 24th falling edge of SCK, SDO
goes HIGH (EOC␣ =␣ 1) indicating a new conversion has
begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
Figure 6. External Serial Clock, Reduced Data Output Length
APPLICATIO S I FOR ATIO
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SDO
SCK
(EXTERNAL)
CS
DATA
OUTPUT
CONVERSION
SLEEP SLEEP
SLEEP
TEST EOC
(OPTIONAL)
TEST EOC
DATA OUTPUT
Hi-Z Hi-ZHi-Z
CONVERSION
2431 F06
MSBSIG
BIT 8BIT 19 BIT 9BIT 20BIT 21BIT 22
EOC
BIT 23BIT 0
EOC
Hi-Z
TEST EOC
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
1µF
2.7V TO 5.5V
LTC2430/
LTC2431
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
the device aborts the data output state and immediately
initiates a new conversion. This is useful for systems not
requiring all 24 bits of output data, aborting an invalid con-
version cycle or synchronizing the start of a conversion.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V
CC
exceeds 2V. The level applied
to SCK at this time determines if SCK is internal or external.
SCK must be driven LOW prior to the end of POR in order
to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
LTC2430/LTC2431
18
24301f
Figure 7. External Serial Clock, CS = 0 Operation
Figure 8. Internal Serial Clock, Single Cycle Operation
APPLICATIO S I FOR ATIO
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EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
MSBSIG
BIT 0
LSB
BIT 19 BIT 18BIT 20BIT 21BIT 22
DATA OUTPUT CONVERSION
2431 F07
CONVERSION
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
2-WIRE I/O
1µF
2.7V TO 5.5V
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
LTC2430/
LTC2431
SDO
SCK
(INTERNAL)
CS
MSBSIG
BIT 0
LSB
TEST EOC
BIT 19 BIT 18BIT 20BIT 21BIT 22
EOC
BIT 23
SLEEP
SLEEP
TEST EOC
(OPTIONAL)
DATA OUTPUT CONVERSIONCONVERSION
2431 F08
<tEOCtest
VCC
10k
Hi-Z Hi-Z Hi-Z Hi-Z
VCC FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
3-WIRE
SPI INTERFACE
1µF
2.7V TO 5.5V
LTC2430/
LTC2431
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
TEST EOC
LTC2430/LTC2431
19
24301f
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to allow the device to
return to the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
EOCtest
after the falling edge of CS
(if EOC = 0) or t
EOCtest
after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of t
EOCtest
is 23µs
if the device is using its internal oscillator (F
O
= logic LOW
or HIGH). If F
O
is driven by an external oscillator of
frequency f
EOSC
, then t
EOCtest
is 3.6/f
EOSC
. If CS is pulled
HIGH before time t
EOCtest
, the device returns to the sleep
state. The conversion result is held in the internal static
shift register.
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 24th
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 24th rising edge of
SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 24 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
Figure 9. Internal Serial Clock, Reduced Data Output Length
APPLICATIO S I FOR ATIO
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SDO
SCK
(INTERNAL)
CS
>t
EOCtest
MSBSIG
BIT 8
TEST EOC BIT 19 BIT 18BIT 20BIT 21BIT 22
EOC
BIT 23
EOC
BIT 0
SLEEP
TEST EOC
(OPTIONAL)
SLEEP DATA OUTPUT
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DATA
OUTPUT
CONVERSION
CONVERSION
SLEEP
2431 F09
<t
EOCtest
V
CC
10k
TEST EOC
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
1µF
2.7V TO 5.5V
LTC2430/
LTC2431
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
LTC2430/LTC2431
20
24301f
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the
LTC2430/LTC2431
’s internal
pull-up at pin SCK is disabled. Normally, SCK is not exter-
nally driven if the device is in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If this driver goes Hi-Z after outputting a LOW
signal, the
LTC2430/LTC2431
’s internal pull-up remains
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK timing
mode. By adding an external 10k pull-up resistor to SCK,
this pin goes HIGH once the external driver goes Hi-Z. On
the next CS falling edge, the device will remain in the in-
ternal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V
CC
exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
APPLICATIO S I FOR ATIO
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SDO
SCK
(INTERNAL)
CS
MSBSIG
BIT 0
LSB
BIT 19 BIT 18BIT 20BIT 21BIT 22
EOC
BIT 23
DATA OUTPUT CONVERSIONCONVERSION
2431 F10
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
1µF
2.7V TO 5.5V
2-WIRE I/O
LTC2430/
LTC2431
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
LTC2430/LTC2431
21
24301f
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data output
cycle begins on the first rising edge of SCK and ends after
the 24th rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used
to shift the conversion result into external circuitry. EOC
can be latched on the first rising edge of SCK and the last
bit of the conversion result can be latched on the 24th
rising edge of SCK. After the 24th rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
PRESERVING THE CONVERTER ACCURACY
The LTC2430/LTC2431 are designed to reduce as much as
possible the conversion result sensitivity to device
decoupling, PCB layout, antialiasing circuits, line fre-
quency perturbations and so on. Nevertheless, in order to
preserve the extreme accuracy capability of this part,
some simple precautions are desirable.
Digital Signal Levels
The LTC2430/LTC2431’s digital interface is easy to use.
The digital inputs (F
O
, CS and SCK in External SCK mode
of operation) accept standard TTL/CMOS logic levels and
the internal hysteresis receivers can tolerate edge rates as
slow as 100µs. However, some considerations are required
to take advantage of the exceptional accuracy and low
supply current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC␣ –␣ 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (FO, CS and SCK
in External SCK mode of operation) is within this range,
the
LTC2430/LTC2431
power supply current may in-
crease even if the signal in question is at a valid logic level.
For micropower operation, it is recommended to drive all
digital input signals to full CMOS levels [VIL < 0.4V and
VOH > (VCC – 0.4V)].
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the
LTC2430/
LTC2431
pins may severely disturb the analog to digital
conversion process. Undershoot and overshoot can oc-
cur because of the impedance mismatch at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver to
LTC2430/LTC2431
. For reference, on a regular FR-4 board,
signal propagation velocity is approximately 183ps/inch
for internal traces and 170ps/inch for surface traces.
Thus, a driver generating a control signal with a minimum
transition time of 1ns must be connected to the converter
pin through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines
are used and multiple reflections may occur. The solution
is to carefully terminate all transmission lines close to
their characteristic impedance.
Parallel termination near the LTC2430/LTC2431 pin will
eliminate this problem but will increase the driver power
dissipation. A series resistor between 27Ω and 56Ω
placed near the driver or near the LTC2431 pin will also
eliminate this problem without additional power dissipa-
tion. The actual resistor value depends upon the trace
impedance and connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The differential input and refer-
ence architecture reduce substantially the converter’s
sensitivity to ground currents.
Particular attention must be given to the connection of the
F
O
signal when the converter (LTC2430 or LTC2431) is
used with an external conversion clock. This clock is active
during the conversion time and the normal mode rejection
provided by the internal digital filter is not very high at this
frequency. A normal mode signal of this frequency at the
converter reference terminals may result into DC gain and
INL errors. A normal mode signal of this frequency at the
converter input terminals may result into a DC offset error.
Such perturbations may occur due to asymmetric capaci-
tive coupling between the F
O
signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
APPLICATIO S I FOR ATIO
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LTC2430/LTC2431
22
24301f
between the F
O
signal trace and the input/reference sig-
nals. When the F
O
signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formed by the F
O
connection trace, the termination and the
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the F
O
signal as well as the loop area for
the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the converter (LTC2430 or
LTC2431) are directly connected to a network of sampling
capacitors. Depending upon the relation between the dif-
ferential input voltage and the differential reference volt-
age, these capacitors are switching between these four
pins transfering small amounts of charge in the process.
A simplified equivalent circuit is shown in Figure 11.
For a simple approximation, the source impedance R
S
driving an analog input pin (IN
+
, IN
–
, REF
+
or REF
–
) can be
considered to form, together with R
SW
and C
EQ
(see
Figure␣ 11), a first order passive network with a time
constant τ = (R
S
+ R
SW
) • C
EQ
. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
When using the internal oscillator (F
O
= LOW or HIGH), the
LTC2430/LTC2431’s front-end switched-capacitor net-
work is clocked at 76800Hz corresponding to a 13µs
sampling period. Thus, for settling errors of less than
1ppm, the driving source impedance should be chosen
such that τ ≤ 13µs/14 = 920ns. When an external oscillator
of frequency f
EOSC
is used, the sampling period is 2/f
EOSC
and, for a settling error of less than 1ppm, τ ≤ 0.14/f
EOSC
.
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 11 shows the
mathematical expressions for the average bias currents
flowing through the IN
+
and IN
–
pins as a result of the
APPLICATIO S I FOR ATIO
WUUU
Figure 11. LTC2430/LTC2431 Equivalent Analog Input Circuit
V
REF
+
V
IN
+
V
CC
R
SW
(TYP)
20k
I
LEAK
I
LEAK
V
CC
I
LEAK
I
LEAK
V
CC
R
SW
(TYP)
20k
C
EQ
6pF
(TYP)
R
SW
(TYP)
20k
I
LEAK
I
IN
+
V
IN
–
I
IN
–
I
REF
+
I
REF
–
2431 F11
I
LEAK
V
CC
I
LEAK
I
LEAK
SWITCHING FREQUENCY
f
SW
= 76800Hz INTERNAL OSCILLATOR (F
O
= LOW OR HIGH)
f
SW
= 0.5 • f
EOSC
EXTERNAL OSCILLATOR
V
REF
–
R
SW
(TYP)
20k
IIN VV V
R
IIN VV V
R
IREF VV V
R
V
VR
I REF VV V
R
V
VR
WHERE
AVG
IN INCM REFCM
EQ
AVG
IN INCM REFCM
EQ
AVG
REF INCM REFCM
EQ
IN
REF EQ
AVG
REF INCM REFCM
EQ
IN
REF EQ
+
−
+
−
()
=+−
•
()
=−+ −
•
()
=•− +
•−•
()
=−• − +
•+•
05
05
15
05
15
05
2
2
.
.
.
.
.
.
::
.
.
./
V REF REF
VREF REF
VININ
VIN IN
R M INTERNAL OSCILLATOR Hz Notch F LOW
R M INTERNAL OSCILLATOR Hz Notch F HIGH
R f EXTERNAL OSCILLATOR
REF
REFCM
IN
INCM
EQ O
EQ O
EQ EOSC
=−
=+
=−
=−
==
()
==
()
=•
()
+−
+−
+−
+−
2
2
43 2 60
52 0 50
666 10
12
Ω
Ω
LTC2430/LTC2431
23
24301f
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The C
PAR
capacitor
includes the LTC2430/LTC2431 pin capacitance (5pF typi-
cal) plus the capacitance of the test fixture used to obtain
the results shown in Figures 13 and 14. A careful imple-
mentation can bring the total input capacitance (C
IN
+
C
PAR
) closer to 5pF thus achieving better performance
than the one predicted by Figures 13 and 14. For simplic-
ity, two distinct situations can be considered.
F
or relatively small values of input capacitance (CIN <
0.01µF), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for CIN will deteriorate the converter offset and gain
performance without significant benefits of signal filter-
ing and the user is advised to avoid them. Nevertheless,
when small values of CIN are unavoidably present as
parasitics of input multiplexers, wires, connectors or
sensors, the LTC2430 or LTC2431 can maintain its excep-
tional accuracy while operating with relative large values
of source resistance as shown in Figures 13 and 14. These
measured results may be slightly different from the first
order approximation suggested earlier because they in-
clude the effect of the actual second order input network
together with the nonlinear settling process of the input
amplifiers. For small CIN values, the settling on IN+ and
IN– occurs almost independently and there is little benefit
in trying to match the source impedance for the two pins.
Larger values of input capacitors (C
IN
> 0.01µF) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When F
O
= LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 21.6MΩ which will
generate a gain error of approximately 0.023ppm for each
ohm of source resistance driving IN
+
or IN
–
. When F
O
=
HIGH (internal oscillator and 50Hz notch), the typical
differential input resistance is 26MΩ which will generate
a gain error of approximately 0.019ppm for each ohm of
source resistance driving IN
+
or IN
–
. When F
O
is driven by
an external oscillator with a frequency f
EOSC
(external
conversion clock operation), the typical differential input
resistance is 3.3 • 10
12
/f
EOSC
Ω and each ohm of source
resistance driving IN
+
or IN
–
will result in 0.15 • 10
–6
•
f
EOSC
ppm gain error. The effect of the source resistance on
the two input pins is additive with respect to this gain error.
APPLICATIO S I FOR ATIO
WUUU
Figure 12. An RC Network at IN
+
and IN–
Figure 13. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)
Figure 14. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)
C
IN
2431 F12
V
INCM
+ 0.5V
IN
R
SOURCE
C
PAR
≅20pF
C
IN
V
INCM
– 0.5V
IN
R
SOURCE
C
PAR
≅20pF
IN
+
IN
–
LTC2430/
LTC2431
R
SOURCE
(Ω)
1 10 100 1k 10k 100k
+FS ERROR (ppm)
2431 F13
50
40
30
20
10
0
–10
V
CC
= 5V
V
REF
+
= 5V
V
REF
–
= GND
V
IN
+
= 3.75V
V
IN
–
= 1.25V
F
O
= GND
T
A
= 25°C
C
IN
=
0.01µF
C
IN
=
0pF
C
IN
=
0.001µF
C
IN
=
100pF
R
SOURCE
(Ω)
1
–50
–FS ERROR (ppm)
–40
–30
–20
–10
0
10
10 100 1k 10k
2431 F14
100k
V
CC
= 5V
V
REF
+
= 5V
V
REF
–
= GND
V
IN
+
= 1.25V
V
IN
–
= 3.75V
F
O
= GND
T
A
= 25°C
C
IN
=
0.01µF
C
IN
=
0pF
C
IN
=
0.001µF
C
IN
=
100pF
LTC2430/LTC2431
24
24301f
The typical +FS and –FS errors as a function of the sum of
the source resistance seen by IN
+
and IN
–
for large values
of C
IN
are shown in Figure 15.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN
+
and IN
–
and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the
converter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large C
IN
capacitor
values, it is advisable to carefully match the source imped-
ance seen by the IN
+
and IN
–
pins. When F
O
= LOW
(internal oscillator and 60Hz notch), every 1Ω mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.023ppm. When F
O
= HIGH (internal oscillator and 50Hz
notch), every 1Ω mismatch in source impedance trans-
forms a full-scale common mode input signal into a
differential mode input signal of 0.019ppm. When F
O
is
driven by an external oscillator with a frequency f
EOSC
,
every 1Ω mismatch in source impedance transforms a
full-scale common mode input signal into a differential
mode input signal of 0.15 • 10
–6
• f
EOSC
ppm. Figure 16
shows the typical offset error due to input common mode
voltage for various values of source resistance imbalance
between the IN
+
and IN
–
pins when large C
IN
values are
used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 1%. Such
APPLICATIO S I FOR ATIO
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Figure 15a. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
Figure 15b. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
R
SOURCE
(Ω)
0
+FS ERROR (ppm)
10
15
800
2431 F15a
5
0200 400 500 1000
20
600
100 300 900
700
C
IN
= 0.01µF
C
IN
= 0.1µF
C
IN
= 1µF, 10µF
V
CC
= 5V
V
REF
+
= 5V
V
REF
–
= GND
V
IN
+
= 3.75V
V
IN
–
= 1.25V
F
O
= GND
T
A
= 25°C
R
SOURCE
(Ω)
0
–FS ERROR (ppm)
–10
–5
800
2431 F15b
–15
–20 200 400 500 1000
0
600
100 300 900
700
C
IN
= 0.01µF
C
IN
= 0.1µF
C
IN
= 1µF, 10µF
V
CC
= 5V
V
REF
+
= 5V
V
REF
–
= GND
V
IN
+
= 1.25V
V
IN
–
= 3.75V
F
O
= GND
T
A
= 25°C
Figure 16. Offset Error vs Common Mode Voltage
(VINCM = VIN+ = VIN–) and Input Source Resistance Imbalance
(∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF)
V
INCM
(V)
0
OFFSET ERROR (ppm)
0
20
4
–20
–40 122.5 5
40
A
B
C
D
E
F
G
3
0.5 1.5 4.5
3.5
V
CC
= 5V
V
REF+
= 5V
V
REF–
= GND
V
IN+
= V
IN–
= V
INCM
F
O
= GND
R
SOURCEIN–
= 500Ω
C
IN
= 10µF
T
A
= 25°C
2431 F16
A: ∆R
IN
= +1k
B: ∆R
IN
= +500Ω
C: ∆R
IN
= +200Ω
D: ∆R
IN
= 0Ω
E: ∆R
IN
= –200Ω
F: ∆R
IN
= –500Ω
G: ∆R
IN
= –1k
LTC2430/LTC2431
25
24301f
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN
+
and
IN
–
, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 100Ω source resistance will create
a 0.1µV typical and 1µV maximum offset voltage.
Reference Current
In a similar fashion, the LTC2430 or LTC2431 samples the
differential reference pins REF
+
and REF
–
transfering small
amount of charge to and from the external driving circuits
thus producing a dynamic reference current. This current
does not change the converter offset, but it may degrade
the gain and INL performance. The effect of this current
can be analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (C
REF
< 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C
REF
will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (C
REF
> 0.01µF)
may be required as reference filters in certain configura-
tions. Such capacitors will average the reference sam-
pling charge and the external source resistance will see a
quasi constant reference differential impedance. When
F
O
= LOW (internal oscillator and 60Hz notch), the typical
differential reference resistance is 15.6MΩ which will
generate a gain error of approximately 0.032ppm for each
ohm of source resistance driving REF
+
or REF
–
. When F
O
= HIGH (internal oscillator and 50Hz notch), the typical
differential reference resistance is 18.7MΩ which will
generate a gain error of approximately 0.027ppm for each
ohm of source resistance driving REF
+
or REF
–
. When F
O
is driven by an external oscillator with a frequency f
EOSC
(external conversion clock operation), the typical differ-
ential reference resistance is 2.4 • 10
12
/f
EOSC
Ω and each
ohm of source resistance drving REF
+
or REF
–
will result
in 0.206 • 10
–6
• f
EOSC
ppm gain error. The effect of the
source resistance on the two reference pins is additive
with respect to this gain error. The typical FS errors for
various combinations of source resistance seen by the
REF
+
and REF
–
pins and external capacitance C
REF
con-
nected to these pins are shown in Figures 17 and 18.
Typical –FS errors are similar to +FS errors with opposite
polarity.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When F
O
= LOW (internal oscillator and 60Hz notch), every
100Ω of source resistance driving REF
+
or REF
–
translates
APPLICATIO S I FOR ATIO
WUUU
Figure 17b. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
Figure 17a. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
RSOURCE (Ω)
1
–50
+FS ERROR (ppm)
–40
–30
–20
–10
0
10
10 100 1k 10k
2431 F17a
100k
VCC = 5V
VREF+ = 5V
VREF– = GND
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
CREF = 0.01µF
CREF = 0pF
CREF = 0.001µF
CREF = 100pF
R
SOURCE
(Ω)
1
–10
–FS ERROR (ppm)
0
10
20
30
40
50
10 100 1k 10k
2431 F17b
100k
V
CC
= 5V
V
REF
+
= 5V
V
REF
–
= GND
V
IN
+
= 1.25V
V
IN
–
= 3.75V
F
O
= GND
T
A
= 25°C
C
REF
=
0.01µF
C
REF
=
0pF
C
REF
=
0.001µF
C
REF
=
100pF
LTC2430/LTC2431
26
24301f
into about 0.11ppm additional INL error. When F
O
= HIGH
(internal oscillator and 50Hz notch), every 100Ω of source
resistance driving REF
+
or REF
–
translates into about
0.092ppm additional INL error. When F
O
is driven by an
external oscillator with a frequency f
EOSC
, every 100Ω of
source resistance driving REF
+
or REF
–
translates into
about 0.73 • 10
–6
• f
EOSC
ppm additional INL error. Fig-
ure␣ 19 shows the typical INL error due to the source
resistance driving the REF
+
or REF
–
pins when large C
REF
values are used. The effect of the source resistance on the
two reference pins is additive with respect to this INL error.
In general, matching of source impedance for the REF
+
APPLICATIO S I FOR ATIO
WUUU
and REF
–
pins does not help the gain or the INL error. The
user is thus advised to minimize the combined source
impedance driving the REF
+
and REF
–
pins rather than to
try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
1%. Such a specification can also be easily achieved by an
external clock. When relatively stable resistors (50ppm/°C)
are used for the external source impedance seen by REF
+
and REF
–
, the expected drift of the dynamic current gain
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications, a one-time calibration operation
may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(±10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05µV typical and 0.5µV maxi-
mum full-scale error.
Figure 18a. +FS Error vs RSOURCE at REF+ or REF– (Large CREF)
Figure 18b. –FS Error vs RSOURCE at REF+ or REF– (Large CREF)
R
SOURCE
(Ω)
–50
–60
+FS ERROR (ppm)
–30
–10
0
–40
–20
200 400 600 800
2431 F18a
10001000 300 500 700 900
C
REF
= 1µF, 10µFC
REF
= 0.1µF
C
REF
= 0.01µF
V
CC
= 5V
V
REF
+
= 5V
V
REF
–
= GND
V
IN
+
= 3.75V
V
IN
–
= 1.25V
F
O
= GND
T
A
= 25°C
R
SOURCE
(Ω)
10
0
–FS ERROR (ppm)
30
50
60
20
40
200 400 600 800
2431 F18b
10001000 300 500 700 900
C
REF
= 1µF, 10µF
C
REF
= 0.1µF
C
REF
= 0.01µF
V
CC
= 5V
V
REF
+
= 5V
V
REF
–
= GND
V
IN
+
= 1.25V
V
IN
–
= 3.75V
F
O
= GND
T
A
= 25°C
Figure 19. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and REF–)
for Large CREF Values (CREF ≥ 1µF)
VINDIF/VREFDIF
–0.5
INL (ppm OF VREF)
3
9
15
0.3
2431 F19
–3
–9
0
6
12
–6
–12
–15 –0.3–0.4 –0.1–0.2 0.1 0.2 0.4
00.5
RSOURCE = 1k
RSOURCE = 10k
RSOURCE = 5k
VCC = 5V
VREF+ = 5V
VREF– = GND
VINCM = 0.5(VIN+ + VIN–) = 2.5V
FO = GND
CREF = 10µF
TA = 25°C
LTC2430/LTC2431
27
24301f
APPLICATIO S I FOR ATIO
WUUU
Output Data Rate
When using the internal oscillator, the LTC2430/LTC2431
can produce up to 7.5 readings per second with a notch
frequency of 60Hz (F
O
= LOW) and 6.25 readings per
second with a notch frequency of 50Hz (F
O
= HIGH). The
actual output data rate will depend upon the length of the
sleep and data output phases which are controlled by the
user and which can be made insignificantly short. When
operated with an external conversion clock (F
O
connected
to an external oscillator), the LTC2430/LTC2431 output
data rate can be increased as desired. The duration of the
conversion phase is 20510/f
EOSC
. If f
EOSC
= 153600Hz, the
converter behaves as if the internal oscillator is used and
the notch is set at 60Hz. There is no significant difference
in the LTC2430/LTC2431 performance between these two
operation modes.
An increase in f
EOSC
over the nominal 153600Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is nevertheless
accompanied by three potential effects, which must be
carefully considered.
First, a change in f
EOSC
will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent perfor-
mance degradation can be substantially reduced by rely-
ing upon the LTC2430/LTC2431’s exceptional common
mode rejection and by carefully eliminating common
mode to differential mode conversion sources in the input
circuit. The user should avoid single-ended input filters
and should maintain a very high degree of matching and
symmetry in the circuits driving the IN
+
and IN
–
pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (C
IN
, C
REF
) are used, the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter perfor-
mance for any value of f
EOSC
. If small external input and/
or reference capacitors (C
IN
, C
REF
) are used, the effect of
the external source resistance upon the LTC2430/LTC2431
typical performance can be inferred from Figures 13, 14
and 17 in which the horizontal axis is scaled by
153600/f
EOSC
.
Third, an increase in the frequency of the external oscilla-
tor above 1.6MHz (a more than 10× increase in the output
data rate) will start to decrease the effectiveness of the
internal autocalibration circuits. This will result in a progres-
sive degradation in the converter accuracy and linearity.
Typical measured performance curves for output data rates
up to 100 readings per second are shown in Figures␣ 20 to
27. In order to obtain the highest possible level of accuracy
from this converter at output data rates above 50 readings
per second, the user is advised to maximize the power
supply voltage used and to limit the maximum ambient
operating temperature. The accuracy is also sensitive to the
clock signal levels and edge rate as discussed in the sec-
tion Digital Signal Levels. In certain circumstances, a re-
duction of the differential reference voltage may be
beneficial.
Input Bandwidth
The combined effect of the internal sinc4 digital filter and
of the analog and digital autocalibration circuits deter-
mines the LTC2430/LTC2431 input bandwidth. When the
internal oscillator is used, the 3dB input bandwidth of the
LTC2430/LTC2431 is 3.63Hz for 60Hz notch frequency
(FO = LOW) and 3.02Hz for 50Hz notch frequency
(FO = HIGH). If an external conversion clock generator of
frequency fEOSC is connected to the FO pin, the 3dB input
bandwidth is 2.36 • 10–5 • fEOSC.
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled very
accurately by a first order filter with the pole located at the
3dB frequency. When the internal oscillator is used, the
shape of the LTC2430/LTC2431 input bandwidth is shown
in Figure␣ 28. When an external oscillator of frequency
f
EOSC
is used, the shape of the LTC2430/LTC2431 input
bandwidth can be derived from Figure␣ 28, F
O
= LOW curve
of the LTC2411 in which the horizontal axis is scaled by
f
EOSC
/153600.
The conversion noise (2.8µV
RMS
typical for V
REF
= 5V) can
be modeled as a white noise source connected to a noise
free converter. The noise spectral density is 67nV/√Hz for
LTC2430/LTC2431
28
24301f
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Figure 23. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 24. Resolution (INLRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 21. +FS Error vs Output Data Rate and Temperature
Figure 22. –FS Error vs Output Data Rate and Temperature
Figure 20. Offset Error vs Output Data Rate and Temperature
Figure 25. Offset Error vs Output
Data Rate and VCC
OUTPUT DATA RATE (READINGS/SEC)
0
OFFSET ERROR (ppm OF VREF)
6
8
10
80
2431 F20
4
2
5
7
9
3
1
020 40 60
10 90
30 50 70 100
VINCM = VREFCM
VCC = VREF = 5V
VIN = 0V
FO = EXT OSC
TA = 85°C
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
0
–30
+FS ERROR (ppm OF V
REF
)
–25
–15
–10
–5
5
10 50 70
2431 F21
–20
0
40 90 100
20 30 60 80
V
INCM
= V
REFCM
V
CC
= V
REF
= 5V
F
O
= EXT OSC
T
A
= 85°C
T
A
= 25°C
OUTPUT DATA RATE (READINGS/SEC)
0
–5
–FS ERROR (ppm OF VREF)
0
10
15
20
30
10 50 70
2431 F22
5
25
40 90 100
20 30 60 80
VINCM = VREFCM
VCC = VREF = 5V
FO = EXT OSC
TA = 85°C
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
0
15
RESOLUTION (BITS)
16
18
19
20
22
10 50 70
2431 F23
17
21
40 90 100
20 30 60 80
VINCM = VREFCM
VCC = VREF = 5V
VIN = 0V
FO = EXT OSC
REF– = GND
RES = LOG2 (VREF/NOISERMS)
TA = 85°C
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
0
15
RESOLUTION (BITS)
16
18
19
20
22
10 50 70
2430 F24
17
21
40 90 100
20 30 60 80
VINCM = VREFCM
VCC = VREF = 5V
FO = EXT OSC
REF– = GND
RES = LOG2(VREF/INLMAX)
TA = 85°C
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
10
OFFSET ERROR (ppm OF V
REF
)
1
3
5
90
2431 F25
–1
–3
0
2
4
–2
–4
–5 30 50 70
200 100
40 60 80
V
INCM
= V
REFCM
V
IN
= 0V
REF
–
= GND
F
O
= EXT OSC
T
A
= 25°CV
CC
= V
REF
= 5V
V
CC
= 2.7V
V
REF
= 2.5V
LTC2430/LTC2431
29
24301f
an infinite bandwidth source and 216nV/√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the
simultaneous requirements of very low bandwidth (just a
few Hz) in order to reduce the output referred noise and
relatively high bandwidth (at least 500kHz) necessary to
drive the input switched-capacitor network. A possible
solution is a high gain, low bandwidth amplifier stage
followed by a high bandwidth unity-gain buffer.
When external amplifiers are driving the LTC2430/
LTC2431, the ADC input referred system noise calculation
can be simplified by Figure 29. The noise of an amplifier
driving the LTC2430/LTC2431 input pin can be modeled
as a band-limited white noise source. Its bandwidth can be
approximated by the bandwidth of a single pole lowpass
filter with a corner frequency f
i
. The amplifier noise spec-
tral density is n
i
. From Figure␣ 29, using f
i
as the x-axis
selector, we can find on the y-axis the noise equivalent
bandwidth freq
i
of the input driving amplifier. This band-
width includes the band limiting effects of the ADC internal
calibration and filtering. The noise of the driving amplifier
referred to the converter input and including all these
effects can be calculated as N␣ = n
i
• √freq
i
. The total system
noise (referred to the LTC2430/LTC2431 input) can now
be obtained by summing as square root of sum of squares
the three ADC input referred noise sources: the LTC2430/
LTC2431 internal noise (2.8µV), the noise of the IN
+
driving amplifier and the noise of the IN
–
driving amplifier.
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Figure 28. Input Signal Bandwidth Using the Internal Oscillator
Figure 26. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and V
CC
OUTPUT DATA RATE (READINGS/SEC)
0
15
RESOLUTION (BITS)
16
18
19
20
22
10 50 70
2430 F26
17
21
40 90 100
20 30 60 80
VINCM = VREFCM
VIN = 0V
FO = EXT OSC
REF– = GND
TA = 25°C
RES = LOG2(VREF/NOISERMS)
VCC = VREF = 5V
VCC = 2.7V
VREF = 2.5V
Figure 27. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and V
CC
OUTPUT DATA RATE (READINGS/SEC)
0
15
RESOLUTION (BITS)
16
18
19
20
22
10 50 70
2430 F27
17
21
40 90 100
20 30 60 80
VINCM = VREFCM
VIN = 0V
FO = EXT OSC
REF– = GND
TA = 25°C
RES = LOG2(VREF/INLMAX)
VCC = VREF = 5V
VCC = 2.7V
VREF = 2.5V
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
INPUT SIGNAL ATTENUATION (dB)
–3
–2
–1
0
4
2431 F28
–4
–5
–6 1235
F
O
= HIGH F
O
= LOW
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
1
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
10
100
1000
10 100 1k 10k 100k 1M
2431 G29
0.10.1 1
F
O
= LOW
F
O
= HIGH
Figure 29. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
LTC2430/LTC2431
30
24301f
If the F
O
pin is driven by an external oscillator of frequency
f
EOSC
, Figure 29 can still be used for noise calculation if the
x-axis is scaled by f
EOSC
/153600. For large values of the
ratio f
EOSC
/153600, the Figure 29 plot accuracy begins to
decrease, but in the same time the LTC2430/LTC2431
noise floor rises and the noise contribution of the driving
amplifiers lose significance.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2430/LTC2431 signifi-
cantly simplifies antialiasing filter requirements.
The sinc
4
digital filter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (f
S
). The
LTC2430/LTC2431’s autocalibration circuits further sim-
plify the antialiasing requirements by additional normal
mode signal filtering both in the analog and digital domain.
Independent of the operating mode, f
S
= 256 • f
N
= 2048
• f
OUTMAX
where f
N
is the notch frequency and f
OUTMAX
is
the maximum output data rate. In the internal oscillator
mode, f
S
= 12,800Hz with a 50Hz notch setting and f
S
=
15,360Hz with a 60Hz notch setting. In the external
oscillator mode, f
S
= f
EOSC
/10.
The combined normal mode rejection performance is
shown in Figure␣ 30 for the internal oscillator with 50Hz
notch setting (FO = HIGH) and in Figure␣ 31 for the internal
oscillator with FO = LOW and for the external oscillator
mode. The regions of low rejection occurring at integer
multiples of fS have a very narrow bandwidth. Magnified
details of the normal mode rejection curves are shown in
Figure␣ 32 (rejection near DC) and Figure␣ 33 (rejection at
fS
= 256f
N
) where f
N
represents the notch frequency.
These curves have been derived for the external oscillator
mode but they can be used in all operating modes by
appropriately selecting the f
N
value.
The user can expect to achieve in practice this level of
performance using the internal oscillator as it is demon-
strated by Figures 34 to 36. Typical measured values of the
normal mode rejection of the LTC2430/LTC2431 operat-
ing with an internal oscillator and a 60Hz notch setting are
shown in Figure 34 superimposed over the theoretical
calculated curve. Similarly, typical measured values of the
normal mode rejection of the LTC2430/LTC2431 operat-
ing with an internal oscillator and a 50Hz notch setting are
shown in Figure 35 superimposed over the theoretical
calculated curve.
As a result of these remarkable normal mode specifica-
tions, minimal (if any) antialias filtering is required in front
of the LTC2430/LTC2431. If passive RC components are
placed in front of the LTC2430/LTC2431, the input dy-
namic current should be considered (see Input Current
section). In cases where large effective RC time constants
are used, an external buffer amplifier may be required to
minimize the effects of dynamic input current.
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Figure 30. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch Figure 31. Input Normal Mode Rejection, Internal
Oscillator and FO = LOW or External Oscillator
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0f
S
2f
S
3f
S
4f
S
5f
S
6f
S
7f
S
8f
S
9f
S
10f
S
11f
S
12f
S
INPUT NORMAL MODE REJECTION (dB)
2431 F30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
F
O
= HIGH
F
O
= LOW OR
F
O
= EXTERNAL OSCILLATOR,
f
EOSC
= 10 • f
S
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0f
S
INPUT NORMAL MODE REJECTION (dB)
2431 F31
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 2f
S
3f
S
4f
S
5f
S
6f
S
7f
S
8f
S
9f
S
10f
S
LTC2430/LTC2431
31
24301f
Traditional high order delta-sigma modulators, while pro-
viding very good linearity and resolution, suffer from
potential instabilities at large input signal levels. The pro-
prietary architecture used for the LTC2430/LTC2431 third
order modulator resolves this problem and guarantees a
predictable stable behavior at input signal levels of up to
150% of full scale. In many industrial applications, it is
not uncommon to have to measure microvolt level sig-
nals superimposed over volt level perturbations and
LTC2430/LTC2431 are eminently suited for such tasks.
When the perturbation is differential, the specification of
interest is the normal mode rejection for large input sig-
nal levels. With a reference voltage V
REF
␣ =␣ 5V, the
LTC2430/LTC2431 have a full-scale differential input range
of 5V peak-to-peak. Figures 36 and 37 show measure-
ment results for the LTC2430/LTC2431 normal mode re-
jection ratio with a 7.5V peak-to-peak (150% of full scale)
input signal superimposed over the more traditional nor-
mal mode rejection ratio results obtained with a 5V peak-
to-peak (full scale) input signal. It is clear that the LTC2430/
LTC2431 rejection performance is maintained with no
compromises in this extreme situation. When operating
with large input signal levels, the user must observe that
such signals do not violate the device absolute maximum
ratings.
APPLICATIO S I FOR ATIO
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INPUT SIGNAL FREQUENCY (Hz)
INPUT NORMAL MODE REJECTION (dB)
2431 F32
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 f
N
0 2f
N
3f
N
4f
N
5f
N
6f
N
7f
N
8f
N
Figure 32. Input Normal Mode Rejection
INPUT SIGNAL FREQUENCY (Hz)
250f
N
252f
N
254f
N
256f
N
258f
N
260f
N
262f
N
INPUT NORMAL MODE REJECTION (dB)
2431 F33
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
Figure 33. Input Normal Mode Rejection
INPUT FREQUENCY (Hz)
0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
NORMAL MODE REJECTION (dB)
2431 F34
0
–20
–40
–60
–80
–100
–120
V
CC
= 5V
V
REF
= 5V
V
INCM
= 2.5V
V
IN(P-P)
= 5V
F
O
= GND
T
A
= 25°C
MEASURED DATA
CALCULATED DATA
Figure 34. Input Normal Mode Rejection vs Input Frequency Figure 35. Input Normal Mode Rejection vs Input Frequency
INPUT FREQUENCY (Hz)
0 25 50 75 100 125 150 175 200
NORMAL MODE REJECTION (dB)
2431 F35
0
–20
–40
–60
–80
–100
–120
V
CC
= 5V
V
REF
= 5V
V
INCM
= 2.5V
V
IN(P-P)
= 5V
F
O
= 5V
T
A
= 25°C
MEASURED DATA
CALCULATED DATA
LTC2430/LTC2431
32
24301f
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INPUT FREQUENCY (Hz)
0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
NORMAL MODE REJECTION (dB)
2431 F36
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VINCM = 2.5V
FO = GND
TA = 25°C
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
INPUT FREQUENCY (Hz)
0
NORMAL MODE REJECTION (dB)
2431 F37
0
–20
–40
–60
–80
–100
–120
V
CC
= 5V
V
REF
= 5V
V
INCM
= 2.5V
F
O
= 5V
T
A
= 25°C
V
IN(P-P)
= 5V
V
IN(P-P)
= 7.5V
(150% OF FULL SCALE)
25 50 75 100 125 150 175 200
Figure 36. Measured Input Normal Mode Rejection
vs Input Frequency Figure 37. Measured Input Normal Mode Rejection
vs Input Frequency
BRIDGE APPLICATIONS
Typical strain gauge based bridges deliver only 2mV/Volt
of excitation. As the maximum reference voltage of the
LTC2430/LTC2431 is 5V, remote sensing of applied exci-
tation without additional circuitry requires that excitation
be limited to 5V. This gives only 10mV full scale, which can
be resolved to 1 part in 3500 without averaging. For many
solid state sensors, this is comparable to the sensor. Av-
eraging 128 samples however reduces the noise level by
a factor of eight, bringing the resolving power to 1 part in
40000, comparable to better weighing systems. Hysteresis
and creep effects in the load cells are typically much greater
than this. Most applications that require strain measure-
ments to this level of accuracy are measuring slowly chang-
ing phenomena, hence the time required to average a large
number of readings is usually not an issue. For those sys-
tems that require accurate measurement of a small incre-
mental change on a significant tare weight, the lack of history
effects in the LTC2400 family is of great benefit.
For those applications that cannot be fulfilled by the
LTC2430/LTC2431 alone, compensating for error in exter-
nal amplification can be done effectively due to the “no
latency” feature of the LTC2430/LTC2431. No
latency operation allows samples of the amplifier offset
and gain to be interleaved with weighing measurements.
The use of correlated double sampling allows suppression
of 1/f noise, offset and thermocouple effects within the
bridge. Correlated double sampling involves alternating
the polarity of excitation and dealing with the reversal of
input polarity mathematically. Alternatively, bridge excita-
tion can be increased to as much as ±10V, if one of several
precision attenuation techniques is used to produce a
precision divide operation on the reference signal. An-
other option is the use of a reference within the 5V input
range of the LTC2430/LTC2431 and developing excitation
via fixed gain, or LTC1043 based voltage multiplication,
along with remote feedback in the excitation amplifiers, as
shown in Figures 43 and 45.
Figure 38 shows an example of a simple bridge connec-
tion. Note that it is suitable for any bridge application
REF
+
REF
–
SDO
SCK
IN
+
IN
–
CS
GND
V
CC
F
O
R1 0.1µF10µF 0.1µF
350Ω
BRIDGE
2431 F38
+
R2
R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS
LT1019
LTC2430/
LTC2431
Figure 38. Simple Bridge Connection
LTC2430/LTC2431
33
24301f
where measurement speed is not of the utmost impor-
tance. For many applications where large vessels are
weighed, the average weight over an extended period of
time is of concern and short term weight is not readily
determined due to movement of contents, or mechanical
resonance. Often, large weighing applications involve load
cells located at each load bearing point, the output of
which can be summed passively prior to the signal pro-
cessing circuitry, actively with amplification prior to the
ADC, or can be digitized via multiple ADC channels and
summed mathematically. The mathematical summation
of the output of multiple LTC2430/LTC2431’s provide the
benefit of a root square reduction in noise. The low power
consumption of the LTC2430/LTC2431 make it attractive
for multidrop communication schemes where the ADC is
located within the load-cell housing.
A direct connection to a load cell is perhaps best incorpo-
rated into the load-cell body, as minimizing the distance to
the sensor largely eliminates the need for protection
devices, RFI suppression and wiring. The LTC2430/
LTC2431 exhibit extremely low temperature dependent
drift. As a result, exposure to external ambient tempera-
ture ranges does not compromise performance. The in-
corporation of any amplification considerably complicates
thermal stability, as input offset voltages and currents,
temperature coefficient of gain settling resistors all be-
come factors.
The circuit in Figure 39 shows an example of a simple
amplification scheme. This example produces a differen-
tial output with a common mode voltage of 2.5V, as
determined by the bridge. The use of a true three amplifier
instrumentation amplifier is not necessary, as the LTC2430/
LTC2431 have common mode rejection far beyond that of
most amplifiers. The LTC1051 is a dual autozero amplifier
that can be used to produce a gain of 10 before its input
referred noise dominates the LTC2430/LTC2431 noise.
This example shows a gain of 34, that is determined by a
feedback network built using a resistor array containing
eight individual resistors. The resistors are organized to
optimize temperature tracking in the presence of thermal
gradients. The second LTC1051 buffers the low noise
input stage from the transient load steps produced during
conversion.
The gain stability and accuracy of this approach is very
good, due to a statistical improvement in resistor match-
ing due to individual error contribution being reduced. A
gain of 34 may seem low, when compared to common
APPLICATIO S I FOR ATIO
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0.1µF
8
0.1µF0.1µF
REF
+
REF
–
SDO
SCK
IN
+
IN
–
CS
GND
V
CC
F
O
5V
REF
350Ω
BRIDGE
2431 F39
RN1 = 5k × 8 RESISTOR ARRAY
U1A, U1B, U2A, U2B = 1/2 LTC1051
–
+
3
28
4
U1A
4
5V
+
–
6
5
RN1
1
16
15
2
611
7
1
14
3
710
4
13
89
512
U1B
–
+
2
3U2A
5V
1
–
+
6
5U2B 7
LTC2430/
LTC2431
Figure 39. Using Autozero Amplifiers to Reduce Input Referred Noise
LTC2430/LTC2431
34
24301f
practice in earlier generations of load-cell interfaces, how-
ever the accuracy of the LTC2430/LTC2431 changes the
rationale. Achieving high gain accuracy and linearity at
higher gains may prove difficult, while providing little
benefit in terms of noise reduction.
At a gain of 100, the gain error that could result from
typical open-loop gain of 160dB is –1ppm, however,
worst-case is at the minimum gain of 116dB, giving a gain
error of –158ppm. Worst-case gain error at a gain of 34,
is –54ppm. The use of the LTC1051A reduces the worst-
case gain error to –33ppm. The advantage of gain higher
than 34, then becomes dubious, as the input referred
noise sees little improvement and gain accuracy is poten-
tially compromised.
Note that this 4-amplifier topology has advantages over
the typical integrated 3-amplifier instrumentation ampli-
fier in that it does not have the high noise level common in
the output stage that usually dominates when an instru-
mentation amplifier is used at low gain. If this amplifier is
used at a gain of 10, the gain error is only 10ppm and input
referred noise is reduced to 0.28µV
RMS
. The buffer stages
can also be configured to provide gain of up to 50 with high
gain stability and linearity.
Figure 40 shows an example of a single amplifier used to
produce single-ended gain. This topology is best used in
applications where the gain setting resistor can be made
to match the temperature coefficient of the strain gauges.
If the bridge is composed of precision resistors, with only
one or two variable elements, the reference arm of the
bridge can be made to act in conjunction with the feedback
resistor to determine the gain. If the feedback resistor is
incorporated into the design of the load cell, using resis-
tors which match the temperature coefficient of the load-
cell elements, good results can be achieved without the
need for resistors with a high degree of absolute accuracy.
The common mode voltage in this case, is again a function
of the bridge output. Differential gain as used with a 350Ω
bridge is:
ARR
R
V
==+
+Ω
995 12
1 175
.
Common mode gain is half the differential gain. The
maximum differential signal that can be used is 1/4 V
REF
,
as opposed to 1/2 V
REF
in the 2-amplifier topology above.
Remote Half Bridge Interface
As opposed to full bridge applications, typical half bridge
applications must contend with nonlinearity in the bridge
output, as signal swing is often much greater. Applications
include RTD’s, thermistors and other resistive elements
that undergo significant changes over their span. For
APPLICATIO S I FOR ATIO
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0.1µF
5V
REF
+
REF
–
IN
+
IN
–
GND
V
CC
3
2
4
6
7
350Ω
BRIDGE
2431 F40
–
+
LTC1050
5V
0.1µV
R2
46.4k
20k
20k
175Ω
1µF
10µF
R1
4.99k
A
V
= 9.95 = R1 + R2
R1 + 175Ω
+
+
1µF
+
LTC2430/
LTC2431
Figure 40. Bridge Amplification Using a Single Amplifier
LTC2430/LTC2431
35
24301f
single variable element bridges, the nonlinearity of the half
bridge output can be eliminated completely; if the refer-
ence arm of the bridge is used as the reference to the ADC,
as shown in Figure 41. The LTC2430/LTC2431 can accept
inputs up to 1/2 V
REF
. Hence, the reference resistor R1
must be at least 2× the highest value of the variable
resistor.
In the case of 100Ω platinum RTD’s, this would suggest a
value of 800Ω for R1. Such a low value for R1 is not
advisable due to self-heating effects. A value of 25.5k is
shown for R1, reducing self-heating effects to acceptable
levels for most sensors.
The basic circuit shown in Figure 41 shows connections
for a full 4-wire connection to the sensor, which may be
located remotely. The differential input connections will
reject induced or coupled 60Hz interference, however, the
reference inputs do not have the same rejection. If 60Hz or
other noise is present on the RTD, a low pass filter is
recommended as shown in Figure 42. Note that you
cannot place a large capacitor directly at the junction of R1
and R2, as it will store charge from the sampling process.
A better approach is to produce a low pass filter decoupled
from the input lines with a high value resistor (R3).
The use of a third resistor in the half bridge, between the
variable and fixed elements gives essentially the same
result as the two resistor version, but has a few benefits.
If, for example, a 25k reference resistor is used to set the
excitation current with a 100Ω RTD, the negative
reference input is sampling the same external node as the
positive input, but may result in errors if used with a long
cable. For short cable applications, the errors may be
acceptably low. If instead the single 25k resistor is
replaced with a 10k 5% and a 10k 0.1% reference
resistor, the noise level introduced at the reference, at
least at higher frequencies, will be reduced. A filter can be
introduced into the network, in the form of one or more
capacitors, or ferrite beads, as long as the sampling
pulses are not translated into an error. The reference
voltage is also reduced, but this is not undesirable, as it
will decrease the value of the LSB, although, not the input
referred noise level.
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2431 F41
REF
–
IN
+
IN
–
GND
V
CC
V
S
2.7V TO 5.5V
PLATINUM
100Ω
RTD
R1
25.5k
0.1%
4
3
2
1
REF
+
LTC2430/
LTC2431
Figure 41. Remote Half Bridge Interface
REF
+
REF
–
IN
–
GND
V
CC
5V
2431 F42
–
+
LTC1050
5V
PLATINUM
100Ω
RTD
560Ω
R3
10k
5%
R1
10k, 5%
R2
10k
0.1%
1µF
IN
+
10k
10k
4
3
2
1
LTC2430/
LTC2431
Figure 42. Remote Half Bridge Sensing with Noise Supression on Reference
LTC2430/LTC2431
36
24301f
The circuit shown in Figure 42 shows a more rigorous
example of Figure 41, with increased noise suppression
and more protection for remote applications.
Figure 43 shows an example of gain in the excitation circuit
and remote feedback from the bridge. The LTC1043s
provide voltage multiplication, providing ±10V from a 5V
reference with only 1ppm error. The amplifiers are used at
unity-gain and, hence, introduce a very little error due to
gain error or due to offset voltages. A 1µV/°C offset voltage
APPLICATIO S I FOR ATIO
WUUU
drift translates into 0.05ppm/°C gain error. Simpler alter-
natives, with the amplifiers providing gain using resistor
arrays for feedback, can produce results that are similar to
bridge sensing schemes via attenuators. Note that the
amplifiers must have high open-loop gain or gain error will
be a source of error. The fact that input offset voltage has
relatively little effect on overall error may lead one to use
low performance amplifiers for this application. Note that
the gain of a device such as an LF156, (25V/mV over
350Ω
BRIDGE
0.1µF
1µF
15V15V
–15V
38
14
7
4
13
12
11
10V 5V
15V
U1
LTC1043
6
2
7
4
7
4
–
+
REF
+
REF
–
IN
+
IN
–
GND
V
CC
2431 F43
5V
47µF 0.1µF
10V
+
17
5
15
6
18
3
2
U2
LTC1043
1µF
FILM
8
14
7
4
13
12
11
*
*
*
5V
U2
LTC1043
17
–10V
–10V
LT1236-5
1k
33Ω
Q1
2N3904
0.1µF
15V
–15V
–15V
3
6
2
–
+
1k
33Ω
–10V
10V
Q2
2N3906
*FLYING CAPACITORS ARE
1µF FILM (MKP OR EQUIVALENT)
SEE LTC1043 DATA SHEET FOR
DETAILS ON UNUSED HALF OF U1
LTC1150
LTC1150
20Ω
200Ω
20Ω
200Ω
0.1µF
10µF
+
LTC2430/
LTC2431
Figure 43. LTC1043 Provides Precise 4× Reference for Excitation Voltages
LTC2430/LTC2431
37
24301f
temperature) will produce a worst-case error of –180ppm
at a noise gain of 3, such as would be encountered in an
inverting gain of 2, to produce –10V from a 5V reference.
The error associated with the 10V excitation would be
–80ppm. Hence, overall reference error could be as high
as 130ppm, the average of the two.
Figure 45 shows a similar scheme to provide excitation
using resistor arrays to produce precise gain. The circuit
is configured to provide 10V and –5V excitation to the
bridge, producing a common mode voltage at the input to
the LTC2430/LTC2431 of 2.5V, maximizing the AC input
range for applications where induced 60Hz could reach
amplitudes up to 2V
RMS
.
The circuits in Figures 43 and 45 could be used where
multiple bridge circuits are involved and bridge output can
be multiplexed onto a single LTC2430/LTC2431, via an
inexpensive multiplexer such as the 74HC4052.
Figure 44 shows the use of an LTC2430/LTC2431 with a
differential multiplexer. This is an inexpensive multiplexer
that will contribute some error due to leakage if used
directly with the output from the bridge, or if resistors are
inserted as a protection mechanism from overvoltage.
Although the bridge output may be within the input range
of the A/D and multiplexer in normal operation, some
thought should be given to fault conditions that could
result in full excitation voltage at the inputs to the multi-
plexer or ADC. The use of amplification prior to the
multiplexer will largely eliminate errors associated with
channel leakage developing error voltages in the source
impedance.
Complete 20-Bit Data Acquistion System in 0.1 Inch
2
The LTC2430/LTC2431 provide 20-bit accuracy while
consuming a maximum of 300µA. The MS package of the
LTC2431 makes it especially attractive in applications
where very limited space is available. A complete 20-bit
data acquisition system in 0.1 inch
2
is shown in Figure 46
where the LTC2431 is powered by the LT1790 reference
family in an S6 package. A supply voltage from 0.25V
above the LT1790 output level to 20V enables the LT1790
to source up to 1mA and ensure the solid performance of
the LT2431.
The 3V, 3.3V, 4.096V and 5V versions of the LT1790 can
power the LTC2430/LTC2431 directly. Lower voltage ver-
sions will require a separate V
CC
supply of 2.7V to 5.5V for
the LTC2430/LTC2431.
2431 F44
REF+
REF–
IN+
IN–
A0
A1
VCC
GND
13
3
6
12 47µF
14
1
5
10
16
5V
15
11
2
TO OTHER
DEVICES 4
98
5V
+
74HC4052 LTC2430/
LTC2431
Figure 44. Use a Differential Mulitplexer to Expand Channel Capability
APPLICATIO S I FOR ATIO
WUUU
LTC2430/LTC2431
38
24301f
APPLICATIO S I FOR ATIO
WUUU
C1
0.1µF
15V 3
1
2
3
21
65
4
–
+
REF
+
REF
–
IN
+
IN
–
GND
V
CC
2431 F45
LT1236-5
RN1
10k
22Ω
10V
350Ω BRIDGE
TWO ELEMENTS
VARYING
RN1
10k
Q1
2N3904
1/2
LT1112
C2
0.1µF
15V
–5V
–15V –15V
6
7
5
8
7
+
–
RN1
10k
RN1 IS CADDOCK T914 10K-010-02
Q2, Q3
2N3906
×2
1/2
LT1112
RN1
10k
33Ω
×2
C3
47µFC1
0.1µF
5V
5V
8
4
20Ω
20Ω
+
LTC2430/
LTC2431
Figure 45. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier
LTC2430/LTC2431
39
24301f
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
U
PACKAGE DESCRIPTIO
MSOP (MS) 0802
0.53 ± 0.01
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.13 ± 0.076
(.005 ± .003)
0.86
(.034)
REF
0.50
(.0197)
BSC
12345
4.90 ± 0.15
(1.93 ± .006)
0.497 ± 0.076
(.0196 ± .003)
REF
8910 76
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
GN16 (SSOP) 0502
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.053 – .068
(1.351 – 1.727)
.008 – .012
(0.203 – 0.305)
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 TYP.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
LTC2430/LTC2431
40
24301f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
LT/TP 0303 2K • PRINTED IN USA
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LT1025 Micropower Thermocouple Cold Junction Compensator 80µA Supply Current, 0.5°C Initial Accuracy
LTC1050 Precision Chopper Stabilized Op Amp No External Components 5µV Offset, 1.6µV
P-P
Noise
LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460 Micropower Series Reference 0.075% Max Initial Accuracy, 10ppm/°C Max Drift
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LTC2400 24-Bit, No Latency ∆Σ ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency ∆Σ ADC 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410 24-Bit, Fully Differential, No Latency ∆Σ ADC 0.16ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2411 24-Bit, Fully Differential, No Latency ∆Σ ADC in MS10 0.29ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2413 24-Bit, Fully Differential, No Latency ∆Σ ADC Simultaneous 50Hz and 60Hz Rejection, 800nV
RMS
Noise
LTC2414/LTC2418 8-/16-Channel 24-Bit Differential, No Latency ∆Σ ADC 0.2ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error
LTC2415 24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate Pin Compatible with the LTC2410
LTC2420 20-Bit, No Latency ∆Σ ADC in SO-8 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2421/LTC2422 1-/2-Channel, 20-Bit, No Latency ∆Σ ADC in MSOP-10 1.2ppm Noise, Low Power 2.7V to 5.5V Supply, 200µA
LTC2424/LTC2428 4-/8-Channel, 20-Bit, No Latency ∆Σ ADC 1.2ppm Noise, Pin Compatible with LTC2404/LTC2408
LTC2440 24-Bit, High Speed, Low Noise ∆Σ ADC 200nV
RMS
Noise, 4000Hz Output Rate
U
TYPICAL APPLICATIO
Figure 46. Complete 20-Bit Data Acquisition System in 0.1 inch2
V
CC
F
O
64
12
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
THE LT1790 IS AVAILABLE WITH 1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V AND 5V OUTPUTS
THE LTC2431 MAY BE POWERED BY THE LT1790 3V, 3.3V, 4.096V AND 5V VERSIONS
3-WIRE
SPI INTERFACE
0.1µF
0.1µF
LTC2431
24301 TA05
4.7µF
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
V
CC
LT1790
LT1790
V
OUT
SUPPLY VOLTAGE RANGE:
(V
OUT
+ 0.25V) TO 20V
Relative Size of Components
