ADS1258
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
16-CHANNEL, 24-BIT ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS1258-EP
1FEATURES APPLICATIONS
• Medical, Avionics, and Process Control
23• 24 Bits, No Missing Codes • Machine and System Monitoring
• Fixed-Channel or Automatic Channel Scan • Fast Scan Multi-Channel Instrumentation
• Fixed-Channel Data Rate: 125 kSPS • Industrial Systems
• Auto-Scan Data Rate: 23.7 kSPS/Channel • Test and Measurement Systems
• Single-Conversion Settled Data
• 16 Single-Ended or 8 Differential Inputs SUPPORTS DEFENSE, AEROSPACE,
• Unipolar (5 V) or Bipolar (±2.5 V) Operation AND MEDICAL APPLICATIONS
• Low Noise: 2.8 μVRMS at 1.8kSPS • Controlled Baseline
• 0.0003% Integral Nonlinearity • One Assembly/Test Site
• One Fabrication Site
• DC Stability (typical):
0.02 μV/°C Offset Drift, 0.4 ppm/°C Gain Drift • Available in Military (–55°C/125°C) and
Industrial (–40°C/105°C) Temperature Ranges(1)
• Open-Sensor Detection • Extended Product Life Cycle
• Conversion Control Pin • Extended Product-Change Notification
• Multiplexer Output for External Signal • Product Traceability
Conditioning
• On-Chip Temperature, Reference, Offset, Gain,
and Supply Voltage Readback
• 42-mW Power Dissipation
• Standby, Sleep, and Power-Down Modes
• 8 General-Purpose Inputs/Outputs (GPIO)
• 32.768-kHz Crystal Oscillator or External Clock (1) Custom temperature ranges available
DESCRIPTION
The ADS1258 is a 16-channel (multiplexed), low-noise, 24-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC)
that provides single-cycle settled data at channel scan rates from 1.8k to 23.7k samples per second (SPS) per
channel. A flexible input multiplexer accepts combinations of eight differential or 16 single-ended inputs with a
full-scale differential range of 5 V or true bipolar range of ±2.5 V when operating with a 5-V reference. The
fourth-order delta-sigma modulator is followed by a fifth-order sinc digital filter optimized for low-noise
performance.
The differential output of the multiplexer is accessible to allow signal conditioning prior to the input of the ADC.
Internal system monitor registers provide supply voltage, temperature, reference voltage, gain, and offset data.
An onboard PLL generates the system clock from a 32.768-kHz crystal, or can be overridden by an external
clock source. A buffered system clock output (15.7 MHz) is provided to drive a microcontroller or additional
converters.
Serial digital communication is handled via an SPI™ -compatible interface. A simple command word structure
controls channel configuration, data rates, digital I/O, monitor functions, etc.
Programmable sensor bias current sources can be used to bias sensors or verify sensor integrity.
The ADS1258 operates from a unipolar 5-V or bipolar ±2.5-V analog supply and a digital supply compatible with
interfaces ranging from 2.7 V to 5.25 V. The ADS1258 is available in QFN-48 and QFP-48 packages.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SPI is a trademark of Motorola, Inc.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
24−Bit
ADC Digital
Filter
Internal
Monitoring
16:1
Analog
Input
MUX
1
16
AINCOM
…
ADC
IN Extclk
In/Out
AVSS DGND
32.768kHz
AVDD DVDD
MUX
OUT
SPI
Interface
CS
DRDY
SCLK
DIN
DOUT
ControlOscillator
GPIO
START
RESET
PWDN
GPIO[7:0]VREF
ADS1258
Analog Inputs
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
ORDERABLE PART TOP-SIDE MARKING
TAPackage(2) NUMBER
48/RTC Tape & Reel of 250 ADS1258MRTCTEP 1258MEP
–55°C to 125°C 48/PHP Tray of 250 ADS1258MPHPTEP ADS1258MEP
–40°C to 105°C 48/PHP Tape & Reel 1000 ADS1258IPHPREP ADS1258IEP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).(1)
ADS1258 UNIT
AVDD to AVSS –0.3 to 5.5 V
AVSS to DGND –2.8 to 0.3 V
DVDD to DGND –0.3 to 5.5 V
Input Current 100, Momentary mA
Input Current 10, Continuous mA
Analog Input Voltage AVSS – 0.3 to AVDD + 0.3 V
Digital Input Voltage to DGND –0.3 to DVDD + 0.3 V
Maximum Junction Temperature 150 °C
Storage Temperature Range –60 to 150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
ELECTRICAL CHARACTERISTICS
All specifications at TA= –55°C to 125°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 16 MHz (external clock) or fCLK = 15.729
MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREF = 4.096 V, and VREFN = –2.5 V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP(1) MAX UNIT
Analog Multiplexer Inputs
AIN0–AIN15, AVSS – AVDD +
Absolute Input Voltage AINCOM with respect to V
100 mV 100mV
DGND
On-Channel Resistance 80 Ω
Crosstalk fIN = 1 kHz –110 dB
SBCS[1:0] = 01 1.5
Sensor Bias (Current Source) μA
SBCS[1:0] = 11 24
1.5 μA:24 μA Ratio Error 1 %
ADC Input
Full-Scale Input Voltage (VIN = ADCINP – ADCINN) ±1.0 6 VREF V
Absolute Input Voltage (ADCINP, ADCINN) AVSS – AVDD + V
100 mV 100mV
Differential Input Impedance 65 kΩ
System Performance
Resolution No Missing Codes 24 Bits
Data Rate, Fixed-Channel Mode 1.953 125 kSPS
Data Rate, Auto-Scan Mode 1.805 23.739 kSPS
Integral Nonlinearity (INL)(2) Differential Input 0.0003 0.0010 % of
FSR(3)
Chopping Off 20
Offset Error Shorted TA= –40°C to 105°C 1 10 μV
Chopping On Inputs TA= –55°C to 125°C -650 650
Chopping Off 0.5
Offset Drift Shorted Inputs μV/°C
Chopping On 0.02 0.1
TA= –40°C to 105°C 0.1 0.5
Gain Error %
TA= –55°C to 125°C -0.5 0.1 0.5
TA= –40°C to 105°C 0.4 2
Gain Drift ppm/°C
TA= –55°C to 125°C 0.4
Noise (see Table 4)
Common-Mode Rejection fCM = 60 Hz 90 100 dB
AVDD, AVSS 70 85
Power-Supply Rejection fPS = 60 Hz dB
DVDD 80 95
Voltage Reference Input
Reference Input Voltage (VREF = VREFP – VREFN) 0.5 4.096 AVDD – V
AVSS
Negative Reference Input (VREFN) AVSS – 0.1 V VREFP – 0.5 V
Positive Reference Input (VREFP) VREFN + 0.5 AVDD + 0.1V V
Reference Input Impedance 40 kΩ
System Parameters
External Reference Reading Error 1 3 %
Analog Supply Reading Error 1 3 %
Voltage TA= 25°C 168 mV
Temperature Sensor Reading Coefficient 394 μV/°C
Digital Input/Output
(1) TA= 25°C for typical parameters.
(2) Best straight line fit method.
(3) FSR = Full-scale range = 2.13 VREF.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): ADS1258-EP
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA= –55°C to 125°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 16 MHz (external clock) or
fCLK = 15.729 MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREF = 4.096 V, and VREFN =
–2.5 V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP(1) MAX UNIT
VIH 0.7 DVDD DVDD V
VIL DGND 0.3 DVDD V
Logic Levels VOH IOH = 2 mA 0.8 DVDD DVDD V
VOL IOL = 2 mA DGND 0.2 DVDD V
Input Leakage VIN = DVDD, GND 10 μA
Frequency 0.1 16 MHz
Master Clock Input (CLKIO) Duty Cycle 40 60 %
Crystal Frequency 32.768 kHz
Clock Output Frequency 15.729 MHz
Crystal Oscillator
(see the Crystal Oscillator Start-Up Time (Clock Output 150 mS
section) Valid)
Clock Output Duty Cycle 40 60 %
Power Supply
DVDD 2.7 5.25 V
AVSS –2.6 0 V
AVDD AVSS + 4.75 AVSS + 5.25 V
External TA= –40°C to 105°C 0.25 0.6
Clock mA
TA= –55°C to 125°C 0.25 0.75
Operation
Internal Oscillator Operation, 0.04 mA
DVDD Supply Current Clock Output Disabled
Internal Oscillator Operation, 1.4 mA
Clock Output Enabled(4)
Power-Down(5) 1 25 µA
Converting 8.2 12 mA
Standby 5.6 mA
AVDD, AVSS Supply Current Sleep 2.1 mA
Power-Down 2 85 µA
Converting 42 62 mW
Standby 29 mW
Power Dissipation Sleep 11 mW
Power-Down 14 μW
(4) CLKIO load = 20 pF.
(5) No clock applied to CLKIO.
4Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
Top View QFN
36
35
34
33
32
31
30
29
28
27
26
25
AIN12
AIN13
AIN14
AIN15
AINCOM
VREFP
VREFN
DGND
DVDD
CS
START
DRDY
AIN4
AIN5
AIN6
AIN7
MUXOUTP
MUXOUTN
ADCINP
ADCINN
AIN8
AIN9
AIN10
AIN11
CLKIO
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
SCLK
DIN
DOUT
1
2
3
4
5
6
7
8
9
10
11
12
AIN3
AIN2
AIN1
AIN0
AVSS
AVDD
PLLCAP
XTAL1
XTAL2
PWDN
RESET
CLKSEL
48 47 46 45 44 43 42 41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
ADS1258
36
35
34
33
32
31
30
29
28
27
26
25
AIN12
AIN13
AIN14
AIN15
AINCOM
VREFP
VREFN
DGND
DVDD
CS
START
DRDY
AIN4
AIN5
AIN6
AIN7
MUXOUTP
MUXOUTN
ADCINP
ADCINN
AIN8
AIN9
AIN10
AIN11
CLKIO
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
SCLK
DIN
DOUT
1
2
3
4
5
6
7
8
9
10
11
12
AIN3
AIN2
AIN1
AIN0
AVSS
AVDD
PLLCAP
XTAL1
XTAL2
PWDN
RES ET
CLKSEL
48 47 46 45 44 43 42 41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
ADS1258
Top View QFP
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
PIN CONFIGURATION
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): ADS1258-EP
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
PIN ASSIGNMENTS
ANALOG/DIGITAL
PIN # NAME INPUT/OUTPUT DESCRIPTION
1 AIN3 Analog Input Analog Input 3: Single-Ended Channel 3, Differential Channel 1 (–)
2 AIN2 Analog Input Analog Input 2: Single-Ended Channel 2, Differential Channel 1 (+)
3 AIN1 Analog Input Analog Input 1: Single-Ended Channel 1, Differential Channel 0 (–)
4 AIN0 Analog Input Analog Input 0: Single-Ended Channel 0, Differential Channel 0 (+)
Negative Analog Power Supply: 0V for unipolar operation, –2.5 V for bipolar operation.
5 AVSS Analog (Internally connected to exposed thermal pad of QFN package.)
6 AVDD Analog Positive Analog Power Supply: 5 V for unipolar operation, 2.5 V for bipolar operation.
7 PLLCAP Analog PLL Bypass Capacitor: Connect 22nF capacitor to AVSS when using crystal oscillator.
8 XTAL1 Analog 32.768-kHz Crystal Oscillator Input 1; see the Chrystal Oscillator section.
9 XTAL2 Analog 32.768-kHz Crystal Oscillator Input 2; see the Chrystal Oscillator section.
10 PWDN Digital Input Power-Down Input: Hold low for minimum of two fCLK cycles to engage low-power mode.
11 RESET Digital Input Reset Input: Hold low for minimum of two fCLK cycles to reset the device.
Clock Select Input: Low = Activates Crystal Oscillator, fCLK output on CLKIO.
12 CLKSEL Digital Input High = Disables Crystal Oscillator, apply fCLK to CLKIO.
13 CLKIO Digital I/O System Clock Input/Output (See CLKSEL pin.)
14 GPIO0 Digital I/O General-Purpose Digital Input/Output 0
15 GPIO1 Digital I/O General-Purpose Digital Input/Output 1
16 GPIO2 Digital I/O General-Purpose Digital Input/Output 2
17 GPIO3 Digital I/O General-Purpose Digital Input/Output 3
18 GPIO4 Digital I/O General-Purpose Digital Input/Output 4
19 GPIO5 Digital I/O General-Purpose Digital Input/Output 5
20 GPIO6 Digital I/O General-Purpose Digital Input/Output 6
21 GPIO7 Digital I/O General-Purpose Digital Input/Output 7
22 SCLK Digital Input SPI Interface Clock Input: Data clocked in on rising edge, clocked out on falling edge.
23 DIN Digital Input SPI Interface Data Input: Data is input to the device.
24 DOUT Digital Output SPI Interface Data Output: Data is output from the device.
25 DRDY Digital Output Data Ready Output: Active low.
26 START Digital Input Start Conversion Input: Active high.
27 CS Digital Input SPI Interface Chip Select Input: Active low.
28 DVDD Digital Digital Power Supply: 2.7 V to 5.25 V
29 DGND Digital Digital Ground
30 VREFN Analog Input Reference Input Negative
31 VREFP Analog Input Reference Input Positive
32 AINCOM Analog Input Analog Input Common: Common input pin to all single-ended inputs.
33 AIN15 Analog Input Analog Input 15: Single-Ended Channel 15, Differential Channel 7 (–)
34 AIN14 Analog Input Analog Input 14: Single-Ended Channel 14, Differential Channel 7 (+)
35 AIN13 Analog Input Analog Input 13: Single-Ended Channel 13, Differential Channel 6 (–)
36 AIN12 Analog Input Analog Input 12: Single-Ended Channel 12, Differential Channel 6 (+)
37 AIN11 Analog Input Analog Input 11: Single-Ended Channel 11, Differential Channel 5 (–)
38 AIN10 Analog Input Analog Input 10: Single-Ended Channel 10, Differential Channel 5 (+)
39 AIN9 Analog Input Analog Input 9: Single-Ended Channel 9, Differential Channel 4 (–)
40 AIN8 Analog Input Analog Input 8: Single-Ended Channel 8, Differential Channel 4 (+)
41 ADCINN Analog Input ADC Differential Input (–)
42 ADCINP Analog Input ADC Differential Input (+)
43 MUXOUTN Analog Output Multiplexer Differential Output (–)
44 MUXOUTP Analog Output Multiplexer Differential Output (+)
45 AIN7 Analog Input Analog Input 7: Single-Ended Channel 7, Differential Channel 3 (–)
46 AIN6 Analog Input Analog Input 6 : Single-Ended Channel 6, Differential Channel 3 (+)
47 AIN5 Analog Input Analog Input 5: Single-Ended Channel 5, Differential Channel 2 (–)
48 AIN4 Analog Input Analog Input 4: Single-Ended Channel 4, Differential Channel 2 (+)
6Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
SCLK
CS(1)
DIN
DOUT
tSCLK
tCSSC tSPW
tDIST
tDIHD
tSPW
tCSDO
Hi-ZHi-Z
tCSPW
tDOPD
tDOHD
NOTE:(1) canbetiedlow.CS
DRDY
DOUT
tDRDY
tDDO
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
PARAMETER MEASUREMENT INFORMATION
Figure 1. Serial Interface Timing
SERIAL INTERFACE TIMING CHARACTERISTICS
At TA= –40°C to +105°C(1) and DVDD = 2.7 V to 5.25 V, unless otherwise noted.
SYMBOL DESCRIPTION MIN MAX UNITS
tSCLK SCLK Period 2 τCLK (2)
tSPW SCLK High or Low Pulse Width (exceeding max resets SPI interface) 0.8 4096(3) τCLK
tCSSC CS Low to First SCLK: Setup Time(4) 2.5 τCLK
tDIST Valid DIN to SCLK Rising Edge: Setup Time 10 ns
tDIHD Valid DIN to SCLK Rising Edge: Hold Time 5 ns
tDOPD SCLK Falling Edge to Valid New DOUT: Propagation Delay(5) 20 ns
tDOHD SCLK Falling Edge to Old DOUT Invalid: Hold Time 0 ns
tCSDO CS High to DOUT Invalid (tri-state) 5 τCLK
tCSPW CS Pulse Width High 2 τCLK
(1) Ensured by characterization only.
(2) τCLK = master clock period = 1/fCLK.
(3) Programmable to 256 τCLK.
(4) CS can be tied low.
(5) DOUT load = 20 pF || 100kΩto DGND.
Figure 2. DRDY Update Timing
DRDY UPDATE TIMING CHARACTERISTICS
SYMBOL DESCRIPTION TYP UNITS
tDRDY DRDY High Pulse Width Without Data Read 1 τCLK
tDDO Valid DOUT to DRDY Falling Edge (CS = 0) 0.5 τCLK
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): ADS1258-EP
1
1 0
1 0 0
1 0 0 0
8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0
Years of Estimaed Life
Continuous T (°C)
J
Electromigration Fail Mode
Wirebond Voiding Fail Mode
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
ADS1258 48/RTC Package Operating Life Derating Chart
Figure 3.
Notes:
1. See datasheet for absolute maximum and minimum recommended operating conditions.
2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package
interconnect life).
8Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
Number of Occurrences
Offset (µV)
3000
2500
2000
1500
1000
500
0
−50
−45
−40
−35
−30
−25
−20
−15
−10
5
0
5
10
15
20
25
30
35
40
45
50
DRATE[1:0] = 11
16384 Points
Number of Occurrences
Offset (µV)
3500
3000
2500
2000
1500
1000
500
0
−20
−16
−12
−8
−4
0
4
8
12
16
20
DRATE[1:0] = 01
16384 Points
Number of Occurrences
Offset (µV)
2500
2000
1500
1000
500
0
−12
−10
−8
−6
−4
−2
0
2
4
6
8
10
12
DRATE[1:0] = 00
16384 Points
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS
At TA= +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise
noted.
READING HISTOGRAM READING HISTOGRAM
Figure 4. Figure 5.
READING HISTOGRAM READING HISTOGRAM
Figure 6. Figure 7.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): ADS1258-EP
RMS Noise (µV)
Input Voltage (%FS)
20
15
10
5
0−100 −75 10075
−50 −25 50250
DRATE[1:0] = 11
DRATE[1:0] = 10
DRATE[1:0] = 01
DRATE[1:0] = 00
Number of Occurrences
RMS Noise (µV)
20
15
10
5
0
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
14.5
15.0
50 units from two production lots.
DRATE[1:0] = 11
RMS Noise (µV)
VREF (V)
16
14
12
10
8
6
4
2
00.5 1.5 5.52.5 3.5 4.5
DRATE[1:0] = 11
DRATE[1:0] = 10
DRATE[1:0] = 01
DRATE[1:0] = 00
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise
noted. NOISE HISTOGRAM NOISE vs INPUT VOLTAGE
Figure 8. Figure 9.
NOISE vs VREF NOISE vs SUPPLY VOLTAGE
Figure 10. Figure 11.
10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
RMS Noise (µV)
Temperature (_C)
20
18
16
14
12
10
8
6
4−40 −20 0 20 40 60 80 100
DRATE[1:0] = 11
RMS Noise (µV)
Common−Mode Input Voltage (V)
20
15
10
5
0
Offset (µV)
5
0
−5
−10
−15
−3−2 3
−1 0 1 2
OFFSET
CHOP = 1
OFFSET
CHOP = 0
NOISE
Number of Occurrences
Offset (µV)
200
180
160
140
120
100
80
60
40
20
0
−10
−8
−6
−4
−2
0
2
4
6
8
10
311 units from one production lot.
CHOP = 1
Number of Occurrences
Offset Drift (µV/_C)
80
60
40
20
0
−0.10
−0.09
−0.08
−0.07
−0.06
−0.05
−0.04
−0.03
−0.02
−0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
50 units from two
production lots.
Based on 20_C intervals
over the range of
−40_C to +105_C.
CHOP = 1
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise
noted. NOISE AND OFFSET vs
NOISE vs TEMPERATURE COMMON-MODE INPUT VOLTAGE
Figure 12. Figure 13.
OFFSET HISTOGRAM OFFSET DRIFT HISTOGRAM
Figure 14. Figure 15.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): ADS1258-EP
Normalized Offset (µV)
Temperature (_C)
20
0
−20
−40
−60−40 −20 1000 20 806040
CHOP = 1 CHOP = 1, No Buffer
CHOP = 0, No Buffer
50 units from two production lots.
Normalized Offset (µV)
VREF (V)
0.5 1.0
10
8
6
4
2
0
−2
−4
−6
−8
−10 5.51.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Number of Occurrences
Absolute Gain Error (ppm)
80
60
40
20
0
100
300
500
700
900
1100
1300
1500
1700
1900
320 units from one production lot.
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise
noted. OFFSET vs TEMPERATURE OFFSET vs VREF
Figure 16. Figure 17.
OFFSET POWER-ON WARMUP GAIN ERROR HISTOGRAM
Figure 18. Figure 19.
12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
Normalized Gain Error (ppm)
Temperature (_C)
30
20
10
0
−10−40 −20 100
0 20 806040
Number of Occurrences
Gain Drift (ppm/_C)
80
60
40
20
0
−1.8
−1.6
−1.4
−1.2
−1.0
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
50 units from two production lots.
Based on 20_C intervals over the
range of −40_C to +105_C.
Normalized Gain Error (ppm)
VREF (V)
20
15
10
5
0
−5
−10
−15
−20 0.5 1.0 5.01.5 2.0 2.5 3.0 3.5 4.0 4.5
Normalized Gain Error (ppm)
Time After Power−On (s)
10
8
6
4
2
0
−2
−4
−6
−8
−10 0 10 6020 30 40 50
Free−Air
Linearity Error (ppm)
VREF (V)
10
8
6
4
2
00.5 1.0 5.01.5 2.0 2.5 3.0 3.5 4.0 4.5
Linearity Error (ppm)
VIN (V)
−5−4
10
8
6
4
2
0
−2
−4
−6
−8
−10 5
−3−2−1 0 1 2 3 4
VREF = 5V
TA=−40_C, −10_C, +25_C, +55_C, +85_C, +105_C
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise
noted. GAIN DRIFT HISTOGRAM GAIN ERROR vs TEMPERATURE
Figure 20. Figure 21.
GAIN ERROR vs VREF GAIN ERROR POWER-ON WARMUP
Figure 22. Figure 23.
INTEGRAL NONLINEARITY vs VREF INTEGRAL NONLINEARITY vs INPUT LEVEL
Figure 24. Figure 25.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): ADS1258-EP
INL (ppm)
Temperature (_C)
8
6
4
2
0−40 −20 120100
0 20 806040
Level(dBFS)
Frequency(Hz)
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
1 10 100k100 1k 10k
f=1kHz, 0.5dBFS-
DRATE[1:0]=11
65536Points
Temperature Sensor Voltage (mV)
Temperature (_C)
210
200
190
180
170
160
150
140−40 −20 12040
0 20 60 80 100
Number of Occurrences
Temperature Reading (_C)
8
7
6
5
4
3
2
1
0
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
50 units from two production lots.
TA= +25_C
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise
noted. INTEGRAL NONLINEARITY vs TEMPERATURE OUTPUT SPECTRUM
Figure 26. Figure 27.
TEMPERATURE SENSOR VOLTAGE vs TEMPERATURE TEMPERATURE SENSOR READING HISTOGRAM
Figure 28. Figure 29.
14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
Ratio (µA/µA)
Temperature (_C)
18
17
16
15
14−40 −20 120100
0 20 806040
Number of Occurrences
Ratio (µA/µA)
25
20
15
10
5
0
14.0
14.5
15.0
15.5
16.0
16.5
17.0
17.5
18.0
18.5
19.0
50 units from two production lots.
AVDD, AVSS Current (mA)
Temperature (_C)
10
8
6
4
2
0
DVDD Current (mA)
1.0
0.8
0.6
0.4
0.2
0
−40 −20 120
0 20 40 60 80 100
AVDD, AVSS
DVDD
RMS Noise (µV)
Master Clock (MHz)
20
16
12
8
4
0
Linearity Error (ppm)
20
16
12
8
4
0
0.1 1 10010
DRATE[1:0] = 11
Noise
Linearity
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal
clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise
noted. SENSOR BIAS CURRENT SOURCE RATIO SENSOR BIAS CURRENT SOURCE RATIO
HISTOGRAM vs TEMPERATURE
Figure 30. Figure 31.
SUPPLY CURRENT vs TEMPERATURE NOISE AND INL vs MASTER CLOCK
Figure 32. Figure 33.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): ADS1258-EP
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AINCOM
Control
Logic
VREFPVREFN
AVSS
PLLCAP XTAL1XTAL2
DRDY
PWDN
RESET
START
SPI
Interface
CS
SCLK
DIN
DOUT
Digital Filter
Clock Control
16−Channel
MUX
AVDD
Sensor
Bias
MUXOUTP MUXOUTN ADCINP GND
ADCINN
ADC Channel Control
Supply Monitor
GPIO
GPIO[7:0]
DVDD
Temperature
Ext Ref Monitor
Internal Ref
ADC
CLKSELCLKIO
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
OVERVIEW
The ADS1258 is a flexible, 24-bit, low-noise ADC VIN = (ADCINP – ADCINN), against the differential
optimized for fast multi-channel, high-resolution reference input, VREF = (VREFP – VREFN). The
measurement systems. The converter provides a digital filter receives the modulator signal and
maximum channel scan rate of 23.7kSPS, providing a provides a low-noise digital output. The ADC channel
complete 16-channel scan in less than 700μs. block controls the multiplexer Auto-Scan feature.
Channel Auto-Scan occurs at a maximum rate of
Figure 34 shows the block diagram of the ADS1258. 23.7kSPS. Slower scan rates can be used with
The input multiplexer selects the analog input pins corresponding increases in resolution.
connected to the multiplexer output pins
(MUXOUTP/MUXOUTN). External signal conditioning Communication is handled over an SPI-compatible
can be used between the multiplexer output pins and serial interface with a set of simple commands
the ADC input pins (ADCINP/ADCINN) or the providing control of the ADS1258. Onboard registers
multiplexer output can be routed internally to the ADC store the various settings for the input multiplexer,
inputs without external circuitry. Selectable current sensor detect bias, data rate selection, etc. Either an
sources within the input multiplexer can be used to external 32.768kHz crystal, connected to pins XTAL1
bias sensors or detect for a failed sensor. On-chip and XTAL2, or an external clock applied to pin CLKIO
system function readings provide readback of can be used as the clock source. When using the
temperature, supply voltage, gain, offset, and external external crystal oscillator, the system clock is
reference. available as an output for driving other devices or
controllers. General-purpose digital I/Os (GPIO)
The ADS1258 converter comprises a fourth-order, provide input and output control of eight pins.
delta-sigma modulator followed by a programmable
digital filter. The modulator
measures the differential input signal,
Figure 34. ADS1258 Block Diagram
16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
ESD
Diodes
ESD
Diodes
3pF Reff = 40kΩ
(fCLK = 16MHz)
AVDD
AVSS
VREFP
VREFN
AVSS*100mV tǒVREFP or VREFNǓtAVDD)100mV
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
MULTIPLEXER INPUTS
A simplified diagram of the input multiplexer is
illustrated in Figure 36. The multiplexer connects one
of 16 single-ended external inputs, one of eight
differential external inputs, or one of the on-chip
internal variables to the ADC inputs. The output of the
channel multiplexer can be routed to external pins
and then to the input of the ADC. This flexibility
allows for use of external signal conditioning. See the
External Multiplexer Loop section.
ESD diodes protect the analog inputs. To keep these
diodes from turning on, make sure the voltages on
the input pins do not go below AVSS by more than
100 mV, and likewise do not exceed AVDD by more
than 100 mV:
AVSS – 100mV < (Analog Inputs) < AVDD + 100 mV.
Overdriving the multiplexer inputs may affect the
conversions of other channels. See the Input
Overload Protection description in the Hardware Figure 35. Simplified Reference Input Circuit
Considerations segment of the Applications section. ESD diodes protect the reference inputs. To keep
The converter supports two modes of channel access these diodes from turning on, make sure the voltages
through the multiplexer: the Auto-Scan mode and the on the reference pins do not go below AVSS by more
Fixed-Channel mode. These modes are selected by than 100mV, and likewise do not exceed AVDD by
the MUXMOD bit of register CONFIG0. The 100mV, as described in Equation 1:
Auto-Scan mode scans through the selected
channels automatically, with break-before-make (1)
switching. The Fixed-Channel mode requires the user A high-quality reference voltage is essential for
to set the channel address for each channel achieving the best performance from the ADS1258.
measured. Noise and drift on the reference degrade overall
system performance. It is especially critical that
VOLTAGE REFERENCE INPUTS special care be given to the circuitry that generates
(VREFP, VREFN) the reference voltages and the layout when operating
The voltage reference for the ADS1258 ADC is the in the low-noise settings (that is, with low data rates)
differential voltage between VREFP and VREFN: to prevent the voltage reference from limiting
VREF = VREFP – VREFN. The reference inputs use a performance. See the Reference Inputs description in
structure similar to that of the analog inputs with the the Hardware Considerations segment of the
circuitry on the reference inputs shown in Figure 35.Applications section.
The load presented by the switched capacitor can be
modeled with an effective resistance (Reff) of 40 kΩ
for fCLK = 16 MHz. Note that the effective impedance
of the reference inputs loads an external reference
with a non-zero source impedance.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): ADS1258-EP
ADC
AIN0
VREFN
VREFP
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AINCOM
Multiplexer Reference/Gain Monitor
NOTE: ESD diodes not shown.
Supply Monitor
AVDD
AVSS
AVDD
AVSS
Temperature Sensor Monitor
1x 2x
8x 1x
AVDD (AVDD −AVSS)/2
AVSS
Sensor Bias Offset Monitor
MUXOUTP
MUXOUTN
ADCINP
ADCINN
Internal
Reference
AVSS
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
Figure 36. Input Multiplexer
18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
tSAMPLE
ON
OFF
S1
S2OFF
ON
S1
S1
AVSS + 1.3V
RAIN = ReffB || 2ReffA
AVSS + 1.3V
ReffA = 190kΩ
ReffB = 78kΩ(fCLK = 16MHz)
ReffA = 190kΩ
ADCINN
ADCINP
CA1 = 0.65pF
CB= 1.6pF
CA2 = 0.65pF
ADCINN
S2
AVSS + 1.3V
S2
AVSS + 1.3V
ADCINP Equivalent
Circuit
Reff = tSAMPLE/CX
NOTE: ESD input diodes not shown.
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
ADC INPUTS As with the multiplexer and reference inputs, ESD
diodes protect the ADC inputs. To keep these diodes
The ADS1258 ADC inputs (ADCINP, ADCINN) from turning on, make sure the voltages on the input
measure the input signal using internal capacitors pins do not go below AVSS by more than 100 mV,
that are continuously charged and discharged. The and likewise do not exceed AVDD by more than 100
left side of Figure 38 shows a simplified schematic of mV.
the ADC input circuitry; the right side of Figure 38
shows the input circuitry with the capacitors and
switches replaced by an equivalent circuit. Figure 37
shows the ON/OFF timings of the switches shown in
Figure 38. S1switches close during the input
sampling phase. With S1closed, CA1 charges to
ADCINP, CA2 charges to ADCINN, and CBcharges to
(ADCINP – ADCINN). For the discharge phase, S1
opens first and then S2closes. CA1 and CA2 discharge
to approximately AVSS + 1.3 V and CBdischarges to
0V. This two-phase sample/discharge cycle repeats
with a period of tSAMPLE = 2/fCLK.Figure 37. S1and S2Switch Timing for Figure 38
The charging of the input capacitors draws a transient
current from the source driving the ADS1258 ADC
inputs. The average value of this current can be used
to calculate an effective impedance (Reff) where Reff =
VIN/IAVERAGE. These impedances scale inversely with
fCLK. For example, if fCLK is reduced by a factor of
two, the impedances double.
Figure 38. Simplified ADC Input Structure
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): ADS1258-EP
50Ω
32.768kHz(1)
4.7pF 4.7pF
22nF
CLKSEL XTAL1 XTAL2 PLLCAP
AVSS
CLKIO Clock Output
(15.729MHz)
0V to−2.5V
NOTE: (1) Parallel resonant type, CL= 12.5pF, ESR= 35kΩ(max).
Place the crystal and loadcapacitorsasclose as possible to thedevicepins.
Oscillator
andPLL
MUX
CLKENB
Bit
InternalMasterClock(f )
CLK
CLKSEL
CLKIO
XTAL1 XTAL2 PLL
50Ω
CLKSEL XTAL1 XTAL2 PLLCAP
DVDD
CLKIO Clock Input
(16MHz)
2.7V
to 5V
No Connection
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
MASTER CLOCK (fCLK)
The ADS1258 oversamples the analog input at a high
rate. This requires a high-frequency master clock to
be supplied to the converter. As shown in Figure 39,
the clock comes from either an internal oscillator (with
external crystal), or an external clock source.
Figure 40. Crystal Oscillator Connection
Table 1. System Clock Source
CLKSEL CLKENB
PIN CLOCK SOURCE BIT CLKIO FUNCTION
32.768 kHz Disabled
0 0
Crystal Oscillator (internally grounded)
Figure 39. Clock Generation Block Diagram 32.768 kHz
0 1 Output (15.729 MHz)
Crystal Oscillator
The CLKSEL pin determines the source of the 1 External Clock Input X Input (16 MHz)
system clock, as shown in Table 1. The CLKIO pin
functions as an input or as an output. When the Table 2. Approved Crystal Vendors
CLKSEL pin is set to '1', CLKIO is configured as an
input to receive the master clock. When the CLKSEL VENDOR CRYSTAL PRODUCT
pin is set to '0', the crystal oscillator generates the Epson C-001R
clock. The CLKIO pin can then be configured to
output the master clock. When the clock output is not External Clock Input
needed, it can be disabled to reduce device power
consumption. When using an external clock to operate the device,
apply the master clock to the CLKIO pin. For this
Crystal Oscillator mode, the CLKSEL pin is tied high. CLKIO then
becomes an input, as shown in Figure 41.
An on-chip oscillator and Phase-Locked Loop (PLL)
together with an external crystal can be used to
generate the system clock. For this mode, tie the
CLKSEL pin low. A 22nF PLL filter capacitor,
connected from the PLLCAP pin to the AVSS pin, is
required. The internal clock of the PLL can be output
to the CLKIO to drive other converters or controllers.
If not used, disable the clock output to reduce device
power consumption; see Table 1 for settings. The
clock output is enabled by a register bit setting
(default is ON). Figure 40 shows the oscillator
connections. Place these components as close to the Figure 41. External Clock Connection
pins as possible to avoid interference and coupling.
Do not connect XTAL1 or XTAL2 to any other logic.
The oscillator start-up time may vary, depending on Make sure to use a clock source clean from jitter or
the crystal and ambient temperature. The user should interference. Ringing or under/overshoot should be
verify the oscillator start-up time. avoided. A 50 Ωresistor in series with the CLKIO pin
(placed close to the source) can often help.
20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
fCLK
128(411b*DR )4.265625 )TD) 2CHOP
fCLK
128(411b*DR )CHOP(4.265625 )TD)) 2CHOP
Analog
Modulator sinc5
Filter Programmable
Averager
Data Rate = fCLK/128Modulator Rate = fCLK/2
Num_Ave
Data Rate(1) = fCLK/(128 ×Num_Ave)
NOTE: (1) Data rate for Fixed−Channel Mode, Chop = 0, Delay = 0.
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
ADC rate—filter more for higher resolution, filter less for
higher data rate. The filter is comprised of two
The ADC block of the ADS1258 is composed of two sections, a fixed filter followed by a programmable
blocks: a modulator and a digital filter. filter. Figure 42 shows the block diagram of the filter.
Data is supplied to the filter from the analog
Modulator modulator at a rate of fCLK/2. The fixed filter is a
fifth-order sinc filter with a decimation value of 64 that
The modulator converts the analog input voltage into outputs data at a rate of fCLK/128. The second stage
a Pulse Code Modulated (PCM) data stream. When of the filter is a programmable averager (first-order
the level of differential analog input (ADCINP – sinc filter) with the number of averages set by the
ADCINN) is near the level of the reference voltage, DRATE[1:0] bits.
the '1' density of the PCM data stream is at its
highest. When the level of the differential analog input The data rate depends upon the system clock
is near zero, the PCM '0' and '1' densities are nearly frequency (fCLK) and the converter configuration. The
equal. The fourth-order modulator shifts the data rate can be computed by Equation 2 or
quantization noise to a high frequency (out of the Equation 3:
passband) where the digital filter can easily remove it. Data Rate (Auto-Scan):
The modulator continuously chops the input, resulting
in excellent offset and offset drift performance. It is
important to note that offset or offset drift originating (2)
from the external circuitry is not removed by the Data Rate (Fixed-Channel Mode):
modulator chopping. These errors can be effectively
removed by using the external chopping feature of
the ADS1258 (see the External Chopping section). (3)
Where:
Digital Filter DR = DRATE[1:0] register bits (binary).
The programmable low-pass digital filter receives the CHOP = Chop register bit.
modulator output and produces a high-resolution TD = time delay value given in Table 5 from the
digital output. By adjusting the amount of filtering, DLY[2:0] register bits (128/fCLK periods).
tradeoffs can be made between resolution and data
Figure 42. Block Diagram of Digital Filter
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): ADS1258-EP
ŤHǒfǓŤ+ŤHsinc5ǒfǓŤ ŤHAveragerǒfǓŤ+
ȧ
ȧ
ȧ
ȧ
sinǒ128p f
fCLK Ǔ
64 sinǒ2p f
fCLK Ǔ
ȧ
ȧ
ȧ
ȧ
5
ȧ
ȧ
ȧ
ȧ
sinǒ128p Num_Ave f
fCLK Ǔ
Num_Ave sinǒ128p f
fCLK Ǔ
ȧ
ȧ
ȧ
ȧ
0
−20
−40
−60
−80
−100
−120
−140
Frequency (kHz)
Gain (dB)
125 2500 375 500 625
Data Rate
Auto−Scan Mode
(23.739kSPS)
Data Rate
Fixed−Channel Mode
(125kSPS)
0
−20
−40
−60
−80
−100
−120
−140
Frequency (kHz)
Gain (dB)
125 2500 375 500 625
Data Rate
Auto−Scan Mode
(15.123kSPS)
Data Rate
Fixed−Channel Mode
(31.25kSPS)
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
Table 3 shows a listing of the averaging and data Figure 44 shows the response with averaging set to 4
rates for each of the four DRATE[1:0] register (DRATE[1:0] = 10). 4-reading, post-averaging
settings for the Auto-Scan and Fixed-Channel modes, produces three equally-spaced notches between
with CHOP, DLY = 0. Note that the data rate scales each main notch of the sinc5filter. The frequency
directly with fCLK. For example, reducing fCLK by 2x response of DRATE[1:0] = 01 and 00 follows a similar
reduces the maximum data rate by 2x. pattern, but with 15 and 63 equally-spaced notches
between the main sinc5notches, respectively.
FREQUENCY RESPONSE
The low-pass digital filter sets the overall frequency
response for the ADS1258. The filter response is the
product of the responses of the fixed and
programmable filter sections and is given by
Equation 4:
(4)
The digital filter attenuates noise on the modulator
output including noise from within the ADS1258 and
external noise present within the ADS1258 input
signal. Adjusting the filtering by changing the number Figure 43. Frequency Response, DRATE[1:0] = 11
of averages used in the programmable filter changes
the filter bandwidth. With a higher number of
averages, the bandwidth is reduced and more noise
is attenuated.
The low-pass filter has notches (or zeros) at the data
output rate and multiples thereof. The sinc5part of
the filter produces wide notches at fCLK/128 and
multiples thereof. At these frequencies, the filter has
zero gain. Figure 43 shows the response with no post
averaging. Note that in Auto-Scan mode, the data
rate is reduced while retaining the same frequency
response as in Fixed-Channel mode.
With programmable averaging, the wide notches
produced by the sinc5filter remain, but a number of
narrow notches are superimposed in the response.
The number of the superimposed notches is
determined by the number of readings
averaged (minus one). Figure 44. Frequency Response, DRATE[1:0] = 10
Table 3. Data Rates(1)
DATA RATE AUTO-SCAN DATA RATE FIXED-CHANNEL –3dB BANDWIDTH
DRATE[1:0] Num_Ave(2) MODE (SPS)(3) MODE (SPS) (Hz)
11 1 23739 125000 25390
10 4 15123 31250 12402
01 16 6168 7813 3418
00 64 1831 1953 869
(1) fCLK = 16 MHz, Chop = 0, and Delay = 0.
(2) Num_Ave is the number of averages performed by the digital filter second stage.
(3) In Auto-Scan mode, the data rate listed is for a single channel; the effective data rate for multiple channels (on a per-channel basis) is
the value shown in Figure 43 and Figure 44 divided by the number of active channels in a scan loop.
22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
DRDY 1 2
Step Input
Data Not Settled Settled Data
DRDY 1 2 6
Step Input
Data Not Settled Settled Data
0
−20
−40
−60
−80
−100
−120
−140
Frequency (MHz)
Gain (dB)
4 80 12 16
DRATE[1:0] = 11
125kSPS
Fixed−Channel Mode
ENOB +lnǒFSRńRMS NoiseǓ
ln(2)
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
ALIASING input. For most modes of operation, the analog input
must be stable for one complete conversion cycle to
The digital filter low-pass characteristic repeats at provide settled data. In Fixed-Channel mode
multiples of the modulator rate of fCLK/2. Figure 45 (DRATE[1:0] = 11), the input must be stable for five
shows the response plotted out to 16MHz at the data complete conversion cycles.
rate of 125 kSPS (Fixed-Channel mode). Notice how
the responses near DC, 8 MHz, and 16 MHz are the
same. The digital filter attenuates high-frequency
noise on the ADS1258 inputs up to the frequency
where the response repeats. However, noise or
frequency components present on the analog input
where the response repeats alias into the passband.
For most applications, an anti-alias filter is
recommended to remove the noise. A simple
first-order input filter with a pole at 200kHz provides
–34dB rejection at the first image frequency. Figure 46. Asynchronous Step-Input Settling
Time (DRATE[1:0] = 10, 01, 00)
Figure 47. Asynchronous Step-Input Settling
Time (Fixed-Channel Mode, DRATE[1:0] = 11)
NOISE PERFORMANCE
Figure 45. Frequency Response Out to 16MHz The ADS1258 offers outstanding noise performance
that can be optimized by adjusting the data rate. As
the averaging is increased by reducing the data rate,
Referring to Figure 43 and Figure 44, frequencies noise drops correspondingly. See Table 4 for
present on the analog input above the Nyquist rate Input-Referred Noise, Noise-Free Resolution, and
(sample rate/2) are first attenuated by the digital filter Effective Number of Bits (ENOB). The noise
and then alias into the passband. performance of low-level signals can be improved
substantially by using external gain. Note that when
SETTLING TIME Chop = 1, the data rate is reduced by 2x and the
The design of the ADS1258 provides fully-settled noise is reduced by 1.4x.
data when scanning through the input channels in ENOB is defined in Equation 5:
Auto-Scan mode. The DRDY flag asserts low when
the data for each channel is ready. It may be
necessary to use the automatic switch time delay (5)
feature to provide time for settling of the external where FSR is the full-scale range.
buffer and associated components after channel
switching. When the converter is started (START pin The data for the Noise-Free Resolution (bits) is
transitions high or Start Command) with stable inputs, calculated in the same way as ENOB, except
the first converter output is fully settled. When peak-to-peak noise is used.
applying asynchronous step inputs, the settling time
is somewhat different. The step-input settling time As seen in the illustration of Noise vs VREF
diagrams (Figure 46 and Figure 47) show the (Figure 10), the converter noise is relatively constant
converter step response with an asynchronous step versus the reference voltage. Optimum
signal-to-noise ratio of the converter is achieved by
using higher reference voltages (VREF MAX = AVDD –
AVSS).
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): ADS1258-EP
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
Table 4. Noise Performance(1)
DATA RATE EFFECTIVE
DATA RATE FIXED-CHANNEL INPUT-REFERRED NOISE-FREE NUMBER
AUTO-SCAN MODE MODE NOISE RESOLUTION OF BITS
DRATE[1:0] (SPS) (SPS) (µVRMS) (Bits) (ENOB)
11 23739 125000 12 16.8 19.5
10 15123 31250 7.9 17.4 20.1
01 6168 7813 4.5 18.2 20.9
00 1831 1953 2.8 18.9 21.6
(1) VREF = 4.096V, fCLK = 16MHz, Chop = 0, Delay = 0, Inputs shorted, and 2048 sample size.
Table 5. Effective Data Rates with Switch-Time Delay (Auto-Scan Mode)(1)
TIME DELAY TIME DELAY
DLY[2:0] (128/fCLK periods) (μS) DRATE[1:0] = 11 DRATE[1:0] = 10 DRATE[1:0] = 01 DRATE[1:0] = 00
000 0 0 23739 15123 6168 1831
001 1 8 19950 13491 5878 1805
010 2 16 17204 12177 5614 1779
011 4 32 13491 10191 5151 1730
100 8 64 9423 7685 4422 1639
101 16 128 5878 5151 3447 1483
110 32 256 3354 3104 2392 1247
111 48 384 2347 2222 1831 1075
(1) Time delay and data rates scale with fCLK. If Chop = 1, the data rates are half those shown. fCLK = 16MHz, Auto-Scan Mode.
Use of the switch time delay register reduces the
EXTERNAL MULTIPLEXER LOOP effective channel data rate. Table 5 shows the actual
data rates derived from Equation 2, when using the
The external multiplexer loop consists of two switch time delay feature.
differential multiplexer output pins and two differential
ADC input pins. The user may use external When pulse converting, where one channel is
components (buffering/filtering, single-ended to converted with each START pin pulse or each pulse
differential conversion, etc.), forming a signal command, the application software may provide the
conditioning loop. For best performance, the ADC required time delay between pulses. However, with
input should be buffered and driven differentially. Chop = 1, the switch time delay feature may still be
necessary to allow for settling.
To bypass the external multiplexer loop, connect the
ADC input pins directly to the multiplexer output pins, In estimating the time delay that may be required,
or select internal bypass connection (BYPASS = 0 of Table 6 lists the time delay-to-time constant ratio (t/τ)
CONFIG0). Note that the multiplexer output pins are and the corresponding final settled data in % and
active regardless of the bypass setting. number of bits.
SWITCH TIME DELAY Table 6. Settling Time
When using the ADS1258 in the Auto-Scan mode, FINAL SETTLING FINAL SETTLING
where the converter automatically switches from one t/τ(1) (%) (Bits)
channel to the next, the settling time of the external 1 63 2
signal conditioning circuit becomes important. If the 3 95 5
channel does not fully settle after the multiplexer 5 99.3 7
channel is switched, the data may not be correct. The 7 99.9 10
ADS1258 provides a switch time delay feature which
automatically provides a delay after channel switching 10 99.995 14
to allow the channel to settle before taking a reading. 15 99.9999 20
The amount of time delay required depends primarily 17 99.999994 24
on the settling time of the external signal conditioning.
Additional consideration may be needed to account
for the settling of the input source arising from the
transient generated from channel switching.
(1) Multiple time constants can be approximated by:
(τ12+τ22+…).
24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
dV
dt +ISDC
C
80Ω
AVDD
RL
RS
ADCINP
80Ω
AVSS
ADCINN
MUXOUTP
MUXOUTN
ISDC
ISDC
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
SENSOR BIAS The current source is connected to the output of the
multiplexer. For unselected channels, the current
An integrated current source provides a means to source is not connected. This configuration means
bias an external sensor (for example, a diode that when a new channel is selected, the current
junction); or, it verifies the integrity of a sensor or source charges stray sensor capacitance, which may
sensor connection. When the sensor fails to an open slow the rise of the sensor voltage. The automatic
condition, the current sources drive the inputs of the switch time delay feature can be used to apply an
converter to positive full-scale. The biasing is in the appropriate time delay before a conversion is started
form of differential currents (programmable 1.5μA or to provide fully settled data (see the Switch Time
24μA), connected to the output of the multiplexer. Delay section).
Figure 48 shows a simplified diagram of ADS1258 The time to charge the external capacitance is given
input structure with the external sensor modeled as a in Equation 6:
resistance RSbetween two input pins. The two 80Ω
series resistors, RMUX, model the ADS1258 internal
resistances. RLrepresents the effective input (6)
resistance of the ADC input or external buffer. When It is also important to note that the low impedance
the sensor bias is enabled, they source ISDC to one (65kΩ) of the direct ADC inputs or the impedance of
selected input pin (connected to the MUXOUTP the external signal conditioning loads the current
channel) and sink ISDC from the other selected input sources. This low impedance limits the ability of the
pin (connected to the MUXOUTN channel). The current source to pull the inputs to positive full-scale
signal measured with the biasing enabled equals the for open-channel detection.
total IR drop: ISDC[(2RMUX + RS)׀׀ RL]. Note that when
the sensor is a direct short (that is, RS= 0), there is OPEN-SENSOR DETECTION
still a small signal measured by the ADS1258 when
the biasing is enabled: ISDC[2RMUX ׀׀ RL]. For open-sensor detection, set the biasing to either
1.5μA or 24μA. Then select the channel and read the
output code. When a sensor opens, the positive input
is pulled to AVDD and the negative input is pulled to
AVSS. Because of this configuration, the output code
trends toward positive full-scale. Note that the
interaction of the multiplexer resistance with the
current source may lead to degradation in converter
linearity. It is recommended to enable the current
source only periodically to check for open inputs and
discard the associated data.
EXTERNAL DIODE BIASING
The current source can be used to bias external
diodes for temperature sensing. Scan the appropriate
channels with the current source set to 24µA.
Re-scan the same channels with the current source
set to 1.5µA. The difference in diode voltage readings
resulting from the two bias currents is directly
proportional to temperature.
Note that errors in current ratio, diode and cable
Figure 48. Sensor Bias Structure resistance, or the non-ideality factor of the diode can
lead to errors in temperature readings. These effects
can be compensated by characterization or by
calibrating the diode at known temperatures.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): ADS1258-EP
ADC
Multiplexer
(chopping)
AINn
AINn
MUXOUTP
MUXOUTN
ADCINP
Optional
Signal
Conditioning
ADCINN
GPIO Pin
GPIO Data (read)
GPIO Data (write)
GPIO Control
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
EXTERNAL CHOPPING GPIO DIGITAL PORT (GPIOx)
The modulator of the ADS1258 incorporates a The ADS1258 has eight dedicated pins for
chopping front-end which removes offset errors, General-Purpose Digital I/O (GPIO). The digital I/O
providing excellent offset and offset drift performance. pins are individually configurable as either inputs or
However, offset and offset drift originating from as outputs through the GPIOC (GPIO-Configure)
external signal conditioning are not removed by the register. The GPIOD (GPIO-Data) register controls
modulator. The ADS1258 has an additional chopping the level of the pins. When reading the GPIOD
feature that removes external offset errors (CHOP = register, the data returned is the level of the pins,
1). whether they are programmed as inputs or outputs.
As inputs, a write to the GPIOD has no effect. As
With external chopping enabled, the converter takes outputs, a write to the GPIOD sets the output value.
two readings in succession on the same channel. The
first reading is taken with one polarity and the second During Standby and Power-Down modes, the GPIO
reading is taken with the opposite polarity. The remains active. If configured as inputs, they must be
converter averages the two readings, canceling the driven (do not float). If configured as outputs, they
offset, as shown in Figure 49. With chopping enabled, continue to drive the pins. The GPIO pins are set as
the effective reading is reduced to half of the nominal inputs after power-on or after a reset. Figure 50
reading rate. shows the GPIO port structure.
Figure 49. External Chopping
Figure 50. GPIO Port Pin
Note that since the inputs are reversed under control
of the ADS1258, a delay time may be necessary to
provide time for external signal conditioning to fully POWER-DOWN INPUT (PWDN)
settle before the second phase of the reading The PWDN pin is used to control the power-down
sequence starts (see the Switch time Delay section). mode of the converter. In power-down mode, all
External chopping can be used to significantly reduce internal circuitry is deactivated including the oscillator
total offset errors (to less than 10μV) and offset drift and the clock output. Hold PWDN low for at least two
over temperature (to less than 0.2μV/°C). Note that fCLK cycles to engage power-down. The register
chopping must be disabled (CHOP = 0) to take the settings are retained during power-down. When the
internal monitor readings. pin is returned high, the converter requires a wake-up
time before readings can be taken, as shown in the
Power-Up Timing section. Note that in power-down
mode, the inputs of the ADS1258 must still be driven
and the device continues to drive the outputs.
26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
CLKIO
Device Ready
tWAKE
3.2V, typical
CLKSEL
or
AVDD −AVSS(1)
or
PWDN
NOTE: (1) Shown with DVDD stable.
CLKIO
Device Ready
tWAKE
3.2V,typical
or
AVDD−AVSS(1)
PWDN,
CLKSEL
NOTE: (1) Shown with DVDD stable.
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
Table 7. Wake-Up Times
POWER-UP TIMING
tWAKE
When powering up the device or taking the PWDN INTERNAL tWAKE
pin high to wake the device, a wake-up time is CONDITION OSCILLATOR(1) EXTERNAL CLOCK
required before readings can be taken. When using PWDN or CLKSEL tOSC 2/fCLK
the internal oscillator, the wake-up time is composed AVDD – AVSS tOSC + 218/fCLK 218/fCLK
of the oscillator start-up time and the PLL lock time,
and if the supplies are also being powered, there is a
reset interval time of 218 fCLK cycles. Note that CLKIO POWER-UP SEQUENCE
is not valid during the wake-up period, as shown in The analog and digital supplies should be applied
Figure 51.before any analog or digital input is driven. The power
supplies may be sequenced in any order. The internal
master reset signal is generated from the analog
power supply (AVDD – AVSS), when the level
reaches approximately 3.2 V. The power-up master
reset signal is functionally the same as the Reset
Command and the RESET input pin.
Reset Input (RESET)
When RESET is held low for at least two fCLK cycles,
all registers are reset to their default values and the
digital filter is cleared. When RESET is released high,
the device is ready to convert data.
Clock Select Input (CLKSEL)
This pin selects the source of the system clock: the
crystal oscillator or an external clock. Tie CLKSEL
Figure 51. Device Wake Time with low to select the crystal oscillator. When using an
Internal Oscillator external clock (applied to the CLKIO pin), tie CLKSEL
high.
When using the device with an external clock, the
wake-up time is 2/fCLK periods when waking up with Clock Input/Output (CLKIO)
the PWDN pin and 218/fCLK periods when powering This pin serves either as a clock output or clock input,
the supplies, all after a valid CLKIO is applied, as depending on the state of the CLKSEL pin. When
shown in Figure 52.using an external clock, apply the clock to this pin
and set the CLKSEL pin high. When using the
internal oscillator, this pin has the option of providing
a clock output. The CLKENB bit of register CONFIG0
enables the clock output (default is enabled).
Start Input (START)
The START pin is an input that controls the ADC
process. When the START pin is taken high, the
converter starts converting the selected input
channels. When the START pin is taken low, the
conversion in progress runs to completion and the
converter is stopped. The device then enters one of
the two idle modes (see the Idle Modes section for
more details). See the Conversion Control section for
details of using the START pin.
Figure 52. Device Wake Time with External Clock
Table 7 summarizes the wake-up times using the
internal oscillator and the external clock operations. (1) Wake-up times for the internal oscillator operation are typical
and may vary depending on crystal characteristics and layout
capacitance. The user should verify the oscillator start-up
times (tOSC = oscillator start-up time).
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): ADS1258-EP
DRDY
DRDY
SCLK
SCLK
DRDY with SCLK
DRDY without SCLK
tDRDYPLS
tDRDYPLS =1
fCLK
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
Data Ready Output (DRDY) DRDY is usually connected to an interrupt of a
controller, DSP, or connected to a controller port pin
The DRDY pin is an output that asserts low to for polling in a software loop. Channel data can be
indicate when new channel data is available to read read without the use of DRDY. Read the data using
(the previous conversion data is lost). DRDY returns the register format read and check the Status Byte
high after the first falling edge of SCLK during a data when the NEW bit = 1, which indicates new channel
read operation. If the data is not read (no SCLK data.
pulses), DRDY remains low until new channel data is
available once again. DRDY then pulses high, then Output Data Scaling and Over-Range
low to indicate new data is available; see Figure 53.The ADS1258 is scaled such that the output data
code resulting from an input voltage equal to ±VREF
has a margin of 6.6% before clipping. This
architecture allows operation of applied input signals
at or near full-scale without overloading the converter.
Specifically, the device is calibrated so that:
1LSB = VREF/780000h,
and the output clips when:
|VIN|≥1.06 × VREF.
Table 8 summarizes the ideal output codes versus
input signals.
Figure 53. DRDY Timing
(See Figure 2 for the DRDY Pulse)
Table 8. Ideal Output Code vs Input Signal
INPUT SIGNAL VIN
(ADCINP – ADCINN) IDEAL OUTPUT CODE(1) DESCRIPTION
≥+1.06 VREF 7FFFFFh Maximum Positive Full-Scale Before Output Clipping
+VREF 780000h VIN = +VREF
+1.06 VREF/(223 – 1) 000001h +1LSB
0 000000h Bipolar Zero
–1.06 VREF/(223 – 1) FFFFFFh –1LSB
–VREF 87FFFFh VIN = –VREF
≤–1.06 VREF × (223/223 – 1) 800000h Maximum Negative Full-Scale Before Output Clipping
(1) Excludes effects of noise, linearity, offset, and gain errors.
28 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
External Reference (V)+Code
786432
Total Analog Supply Voltage (V)+Code
786432
Temperature(°C) +ƪTemp Reading(mV) *168,000mV
394mVń°Cƫ)25°C
Device Gain ǒVńVǓ+Code
7864320
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
INTERNAL SYSTEM READINGS The scale factor of Equation 9 converts the code
value to external reference voltage:
Analog Power-Supply Reading (VCC) (9)
The analog power-supply voltage of the ADS1258
can be monitored by reading the VCC register. The This readback function can be used to check for
supply voltage is routed internal to the ADS1258 and missing or an out-of-range reference. If the reference
is measured and scaled using an internal reference. input pins are floating (not connected), internal
The supply readback channel outputs the difference biasing pulls them to the AVSS supply. This causes
between AVDD and AVSS (AVDD – AVSS), for both the output code to tend toward '0'. Bypass capacitors
single and dual configurations. Note that it is required connected to the external reference pins may slow
to disable chopping (CHOP = 0) prior to taking this the response of the pins when open. When reading
reading. this register immediately after power-on, verify that
the reference has settled to ensure an accurate
The scale factor of Equation 7 converts the code reading. Note that it is required to disable chopping
value to volts: (CHOP = 0) prior to taking this reading.
(7) Temperature Reading (TEMP)
When the power supply falls below the minimum The ADS1258 contains an on-chip temperature
specified operating voltage, the full operation of the sensor. This sensor uses two internal diodes with one
ADS1258 cannot be ensured. Note that when the diode having a current density of 16x of the other.
total analog supply voltage falls to below The difference in current densities of the diodes
approximately 4.3 V the returned data is set to zero. yields a difference voltage that is proportional to
The SUPPLY bit in the status byte is then set. The bit absolute temperature.
is cleared when the total supply voltage rises
approximately 50 mV higher than the lower trip point. As a result of the low thermal resistance of the
package to the printed circuit board (PCB), the
The digital supply (DVDD) may be monitored by internal device temperature tracks the PCB
looping-back the supply voltage to an input channel. temperature closely. Note also that self-heating of the
A resistor divider may be required for bipolar supply ADS1258 causes a higher reading than the
operation to reduce the DVDD level to within the temperature of the surrounding PCB. Note that it is
range of the analog supply. required to disable chopping (CHOP = 0) prior to
taking this reading.
Gain Reading (GAIN) The scale factor of Equation 10 converts the
In this configuration, the external reference is temperature reading to °C. Before using the equation,
connected both to the analog input and to the the temperature reading code must first be scaled to
reference input of the ADC. The data from this μV.
register indicates the gain of the device.
The following scale factor (Equation 8) converts the
code value to device gain: (10)
(8) Offset Reading (OFFSET)
To correct the device gain error, the user software The differential output of the multiplexer is shorted
can divide each converter data value by the device together and set to a common-mode voltage of
gain. Note that this corrects only for gain errors (AVDD – AVSS)/2. Ideally, the code from this register
originating within the ADC; system gain errors function is 0h, but varies because of the noise of the
because of an external gain stage error or because of ADC and offsets stemming from the ADC and
reference errors are not compensated. Note that it is external signal conditioning. This register can be used
required to disable chopping (CHOP = 0) also prior to to calibrate or track the offset of the ADS1258 and
taking this reading. external signal conditioning. The chop feature of the
ADC can automatically remove offset and offset drift
Reference Reading (REF) from the external signal conditioning; see the External
Chopping section.
In this configuration, the external reference is
connected to the analog input and an internal
reference is connected to the reference of the ADC.
The data from this register indicates the magnitude of
the external reference voltage.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): ADS1258-EP
DRDY
START Pin
Pulse Convert
Command
Converting ConvertingIdle
Data Ready, Index to Next Channel
or
DRDY
STARTPin
tSDSU
tDRHD
SYMBOL DESCRIPTION MIN UNIT
tSDSU 8tCLK
8tCLK
tDRHD
STARTto SetupTime
DRDY
toHaltFurtherConversions
DRDY toSTARTHoldTime
toCompleteCurrentConversion
DRDY
START Pin
Data Ready, Index to Next Channel
IdleIdle Mode Converting
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
Pulse Convert Command
CONVERSION CONTROL Figure 55 also shows the start of conversions with the
The conversions of the ADS1258 are controlled by rising edge of the START pin. If the START pin is
the START pin. Conversions begin when the START taken high, and then low prior to completion of the
pin is taken high and conversions are stopped when conversion cycle (8 τCLK before DRDY asserts low),
the START pin is taken low. For continuous only the current channel is converted and the device
conversions, tie the START pin high. The START pin enters the standby or sleep modes waiting for a new
can also be tied low and the conversions controlled start condition. Figure 56 shows the START pin to
by the PULSE convert command. The PULSE DRDY timing. The same function of conversion
convert command converts one channel (only) for control is possible using the Pulse Convert command
each command sent. In this way, channel (with the START pin low). In this operation, the data
conversions can be stepped without the need to from one channel is converted with each Pulse
toggle the START pin. Convert command. The Pulse convert command
takes effect when the command byte is completely
START Pin shifted in (eighth falling edge of SCLK). After
As shown in Figure 54, when the START pin is taken conversion, if more than one channel is enabled
high, conversions start beginning with the current (Auto-Scan mode), the converter indexes to the next
channel. The device continues to convert all of the selected channel after completing the conversion.
programmed channels, in a continuous loop, until the
START pin is taken low. When this occurs, the
conversion in process completes, and the device
enters the standby or sleep mode waiting for a new
start condition. When DRDY asserts low, the
conversion data is ready. Figure 56 shows the
START pin to DRDY timing. The order in which
channel data is converted is described in Table 10.
When the last selected channel in the program list
has been converted, the device continues
conversions starting with the highest priority channel.
If there is only one channel selected in the Auto-Scan
mode, the converter remains fixed on one channel. A Figure 55. Pulse Conversion, Auto-Scan Mode
write operation to any of the multiplexer channel
select registers sets the channel pointer to the
highest priority channel (see Table 11). In
Fixed-Channel mode, the channel pointer remains
fixed.
Figure 56. START Pin and DRDY Timing
Figure 54. Conversion Control, Auto-Scan Mode
30 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
Initial Delay
Fully−Settled Data
DRDY
Start
Condition
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
GPIO Linked START Pin Control OPERATING MODES
The START pin can be contolled directly by software The operating modes of the ADS1258 are defined in
by connecting externally a GPIO port pin to the three basic states: Converting Mode, Idle Mode, and
START pin. (Note that an external pull-down resistor Power-Down mode. In Converting mode, the device
is recommended to keep the GPIO from floating until is actively converting channel data. The device power
the GPIO is configured as an output). For this mode dissipation is the highest in this mode. This mode is
of control, the START pin is effectively controlled by divided into two sub-modes: Auto-Scan and
writing to the GPIO Data Register (GPIOD), with the Fixed-Channel.
write operation setting or resetting the appropriate bit. The next mode is the Idle mode. In this mode, the
The data takes effect on the eighth falling edge of the device is not converting channel data. The device
data byte write. The START pin can then be remains active, waiting for input to start conversions.
controlled by the serial interface. The power consumption is reduced from that of the
Converting mode. This mode also has two
Initial Delay sub-modes: Standby and Sleep.
As seen in Figure 57, when a start convert condition The last mode is Power-Down mode. In this mode, all
occurs, the first reading from ADS1258 is delayed for functions of the converter are disabled to reduce
a number of clock cycles. This delay allows fully power consumption to a minimum.
settled data to occur at the first data read. Data reads
thereafter are available at the full data rate. The CONVERTING MODES
number of clock cycles delayed before the first
reading is valid depends on the data rate setting, and The ADS1258 has two converting modes: Auto-Scan
whether exiting the Standby or Sleep Mode. Table 9 and Fixed-Channel. In Auto-Scan mode, the channels
lists the delayed clock cycles versus data rate. to be measured are pre-selected in the address
register settings. When a convert condition is present,
the converter automatically measures and sequences
through the channels either in a continuous loop or
pulse-step fashion, depending on the trigger
condition.
In Fixed-Channel mode, the channel address is
selected in the address register settings prior to
acquiring channel data. When a convert condition is
present, the device converts a single channel, either
continuously or in pulse-step fashion, depending on
the trigger condition. The data rate in this mode is
higher than in Auto-Scan Mode since the input
Figure 57. Start Condition to First Data channels are not indexed for each reading.
The selection of converting modes is set with bit
MUXMOD of register CONFIG0.
Table 9. Start Condition to DRDY Delay, Chop = 0, DLY[2:0] = 000
INITIAL DELAY (Standby Mode) INITIAL DELAY (Sleep Mode)
(fCLK cycles) (fCLK cycles)
DRATE[1:0] Fixed-Channel Auto-Scan Fixed-Channel Auto-Scan
11 802 708 866 772
10 1186 1092 1250 1156
01 2722 2628 2786 2692
00 8866 8772 8930 8836
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): ADS1258-EP
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
Auto-Scan Mode register prior to converting a different channel. Note
that the AINCOM input and the internal system
The ADS1258 provides 16 analog inputs, which can registers cannot be referenced in this mode.
be configured in combinations of eight differential
inputs or 16 single-ended inputs, and provides an Idle Modes
additional five internal system measurements. Taken
together, the device allows a total of 29 possible When the START pin is taken low, the device
channel combinations. The converter automatically completes the conversion of the current channel and
scans and measures the selected channels, either in then enters one of the Idle modes, Standby or Sleep.
a continuous loop or pulse-step fashion, under the In the Standby mode, the internal biasing of the
control of the START pin or Start command software. converter is reduced. This state provides the fastest
The channels are selected for measurement in wake-up response when re-entering the run state. In
registers MUXDIF, MUXSG0, MUXSG1, and Sleep mode, the internal biasing is reduced further to
SYSRED. When any of these registers are written, provide lower power consumption than the Standby
the internal channel pointer is set to the channel mode. This mode has a slower wake-up response
address with the highest priority (see Table 11). when re-entering the Converting mode (see Table 9).
Selection of these modes is set under bit IDLMOD of
DRDY asserts low when the channel data is ready; register CONFIG1.
see Figure 55 and Figure 54. At the same time, the
converter indexes to the next selected channel and, if POWER-DOWN MODE
the START pin is high, starts a new channel
conversion. Otherwise, if pulse converting, the device In power-down mode, both the analog and digital
enters the Idle mode. circuitry are completely disabled.
For example, if channels 3, 4, 7, and 8 are selected SERIAL INTERFACE
for measurement in the list, the ADS1258 converts
the channels in that order, skipping all other The ADS1258 is operated via an SPI-compatible
channels. After channel 8 is converted, the device serial interface by writing data to the configuration
starts over, beginning at the top of the channel list, registers, using commands to control the converter
channel 3. and finally reading back the channel data. The
interface consists of four signals: CS, SCLK, DIN,
The following guidelines can be used when selecting and DOUT.
input channels for Auto-Scan measurement:
1. For differential measurements, adjacent input Chip Select (CS)
pins (AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, etc.) are
pre-set as differential pairs. Even number CS is an input that is used to select the device for
channels from each pair represent the positive serial communication. CS is active low. When CS is
input to the ADC and odd number channels within high, read or write commands in progress are aborted
a pair represent the negative input (for example, and the serial interface is reset. Additionally, DOUT
AIN0/AIN1: AIN0 is the positive channel, AIN1 is tri-states and inputs on DIN are ignored. DRDY
the negative channel.) indicates when data is ready, independent of CS.
2. For single-ended measurements use AIN0 The converter may be operated using CS to actively
through AIN15 as single-ended inputs and select and deselect the device, or with CS tied low
AINCOM is the shared common input among (always selected). CS must stay low for the entire
them. Note: AINCOM does not need to be at read or write operation. When operating with CS tied
ground potential. For example, AINCOM can be low, the number of SCLK pulses must be carefully
tied to VREFP or VREFN; or any potential controlled to avoid false command transmission.
between (AVSS – 100mV) and (AVDD + 100mV).
3. Combinations of differential, single-ended inputs, Serial Clock (SCLK) Operation
and internal system registers can be used in a The serial clock (SCLK) is an input which is used to
scan. clock data into (DIN) and out of (DOUT) the
ADS1258. This input is a Schmitt-trigger input that
Fixed-Channel Mode has a high degree of noise immunity. However, it is
In this mode, any of the 16 analog input channels recommended to keep SCLK as clean as possible to
(AIN0–AIN15) can be selected for the positive ADC prevent glitches from inadvertently shifting the data.
input and any analog input channels can be selected Data is shifted into DIN on the rising edge of SCLK
for the negative ADC input. New channel and data is shifted out of DOUT on the falling edge of
configurations must be selected by the MUXSCH SCLK. If SCLK is held inactive for 4096 or 256 fCLK
cycles (SPIRST bit of register CONFIG0), read or
32 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
NOTES: (1)OptionalforAuto-Scanmode,disabledforFixed-Channelmode.SeeTable13,StatusByte.
(2)Afterthechanneldatareadoperation, mustbetoggledoranSPItimeoutmustoccurbeforesendingcommands.
(3)NoSCLKactivity.
CS
(3)
DRDY
CS
SCLK
DOUT
DIN
(holdinactive)
StatusByte(1) DataByte1(MSB) DataByte3(MSB)
(2)
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
write operations in progress will terminate and the may be read at any time without concern to DRDY.
SPI interface resets. This timeout feature can be The NEW bit of the STATUS byte indicates that the
used to recover lost communication when a serial data register has been refreshed with new converter
interface transmission is interrupted or inadvertently data since the last read operation. The data is shifted
glitched. out MSB first after the STATUS byte.
It should be noted that on system power-up, if the
Data Input (DIN) and Data Output (DOUT) ADS1258 interface signals are floating or undefined,
Operation the interface could wake in an unknown state. This
The data input pin (DIN) is used to input data to the condition is remedied by resetting the interface in
ADS1258. The data output pin (DOUT) is used to three ways: toggle the RESET pin low then high;
output data from the ADS1258. Data on DIN is shifted toggle the CS pin high then low; or hold SCLK
into the converter on the rising edge of SCLK while inactive for 218 + 4096 fCLK cycles.
data is shifted out on DOUT on the falling edge of
SCLK. DOUT is tri-stated when CS is high to allow Channel Data Read Direct
multiple devices to share the line. Channel data can be accessed from the ADS1258 in
two ways: Direct data read or data read with register
SPI Bus Sharing format. With Direct read, the DIN input pin is held
The ADS1258 can be connected to a shared SPI bus. inactive (high or low) for at least the first three SCLK
DOUT tri-states when CS is deselected (high). When transitions. When the first three bits are 000 or 111,
the ADS1258 is connected to a shared bus, data can the device detects a direct data read and channel
be read only by the Channel Data Read command data is output. After the device defects this read
format. format, commands are ignored until either CS is
toggled, an SPI timeout occurs or the device is reset.
COMMUNICATION PROTOCOL The Channel Data Read command does not have
this requirement.
Communicating to the ADS1258 involves shifting data
into the device (via the DIN pin) or shifting data out of Concurrent with the first SCLK transition, channel
the device (via the DOUT pin) under control of the data is output on the DOUT output pin. A total of 24
SCLK input. or 32 SCLK transitions complete the data read
operation. The number of shifts depend on whether
Reading DATA the status byte is enabled. The data must be
completely shifted out before the next occurrence of
DRDY goes low to indicate that new conversion data DRDY or the remaining data will be corrupted. It is
is ready. The data may be read via a direct data read recommended to monitor DRDY to synchronize the
(Channel Data Read Direct) or the data may be read start of the read operation to avoid data corruption.
in a register format (Channel Data Read Register). A Before DRDY asserts low, the MSB of the Status byte
direct data read requires the data to be read before or the MSB of the data is output on DOUT (CS = '0'),
the next occurrence of DRDY or the data will be as shown in Figure 58. In this format, reading the
corrupted. This type of data read requires data a second time within the same DRDY frame
synchronization with DRDY to avoid this conflict. returns data = 0.
When reading data in the register format, the data
Figure 58. Channel Data Read Direct (No Command)
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): ADS1258-EP
CS
SCLK
DIN Command Byte 1 Don’t Care Don’t Care(1)
DOUT
(1) After the prescribed number of registers are read, then one or more additional commands can be issued in succession.
(2) Four bytes for channel data register read. See Table 13, Status Byte. One or more bytes for register data read, depending on MUL bit.
NOTE:
Don’t Care Data(2) Data(2)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
COMMAND DESCRIPTION SCLK falling edge (command byte completed), the
MSB of the channel data is restarted on DOUT. The
Commands may be sent to the ADS1258 with CS tied user clocks the data on the following rising edge of
low. However, after the Channel Data Read Direct SCLK. A total of 40 SCLK transitions complete the
operation, it is necessary to toggle CS or an SPI data read operation. Unlike the direct read mode, the
timeout must occur to reset the interface before channel data can be read during a DRDY transition
sending a command. without data corruption. This mode is recommended
when DRDY is not used and the data is polled to
Channel Data Read Command detect for the occurrence of new data or when CS is
tied low to avoid the necessity for an SPI timeout that
To read channel data in this mode (register format), otherwise occurs when reading data directly. This
the first three bits of the command byte to be shifted option avoids conflicts with DRDY, as shown in
into the device are 001. The MUL bit must be set Figure 59.
because this command is a multiple byte read. The
remaining bits are don’t care but still must be clocked
to the device. During this time, ignore any data that
appear on DOUT until the command completes. This
data should be ignored. Beginning with the eighth
Figure 59. Register and Channel Data (Register Format) Read
34 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
1234567812345678 12345678
CS
SCLK
DIN Command Byte Register Data(1) Register Data(1)(2)
(1) One or more bytes depending on MUL bit.
(2) After the prescribed number of registers are read, then one or more additional commands can be issued in succession.
NOTE:
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
CS
SCLK
DIN Command 1 Command 2(1) Command 3(1)
NOTE: (1) One or more commands can be issued in succession.
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
Register Read Command Beginning with the eighth SCLK rising edge
(command byte completed), the MSB of the data is
To read register data, the first three bits of the shifted in. The remaining seven SCLK rising edges
command byte to be shifted into the device are 010.complete the write to a single register. If MUL = '1',
These bits are followed by the multiple register read the data to the next register can be written by
bit (MUL). If MUL = '1', then multiple registers can be supplying additional SCLKs. The operation terminates
read in sequence beyond the desired register. If when the last register is accessed (address = 09h),
MUL = '0', only data from the addressed register can as shown in Figure 60.
be read. The last four bits of the command word are
the beginning register address bits. During this time, CONTROL COMMANDS
the invalid data may appear on DOUT until the
command is completed. This data should be ignored. Pulse Convert Command
Beginning with the eighth falling edge of SCLK
(command byte completed), the MSB of the register (See Conversion Control section)
data is output on DOUT. The remaining eight SCLK
transitions complete the read of a single register. If Reset Command
MUL = '1', the data from the next register can be read The Reset command resets the ADC. All registers
in sequence by supplying additional SCLKs. The are reset to their default values. A conversion in
operation terminates when the last register is process continues but is invalid when completed
accessed (address = 09h); see Figure 59.(DRDY low). This conversion data should be
discarded. Note that the SPI interface may require
Register Write Command reset for this command, or any command, to function.
To write register data, the first three bits of the To ensure device reset under a possible locked SPI
command byte to be shifted into the device are 011.interface condition, do one of the following: 1) toggle
These bits are followed by the multiple register read CS high then low and send the reset command; or 2)
bit (MUL). If MUL = '1', then multiple registers can be hold SCLK inactive for 256/fCLK or 4096/fCLK and send
written in sequence beyond the desired register. If the reset command. The control commands are
MUL = '0', only data to the addressed register can be illustrated in Figure 61.
written. The remaining four bits of the command word
are the beginning register address bits. During this
time, the invalid data may appear on DOUT until the
command is completed. This data should be ignored.
Figure 60. Register Write Operation
Figure 61. Control Command Operation
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s): ADS1258-EP
DRDY
NEW Bit
Data Reads
(register format)
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
CHANNEL DATA
The data read operation outputs either four bytes (one byte for status and three bytes for data), or three bytes for
data only. The selection of 4-byte or 3-byte data read is set by the bit STAT in register CONFIG0 (see Table 13,
Status Byte, for options). In the 4-byte read, the first byte is the status byte and the following three bytes are the
data bytes. The MSB (Data23) of the data is shifted out first.
Table 10. CHANNEL DATA FORMAT
BYTE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
1 STATUS NEW OVF SUPPLY CHID4 CHID3 CHID2 CHID1 CHID0
2 MSB Data23 Data22 Data21 Data20 Data19 Data18 Data17 Data16
3 MSB-1 Data15 Data14 Data13 Data12 Data11 Data10 Data9 Data8
4 LSB Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data0
STATUS BYTE
BIT STATUS.7, NEW
The NEW bit is set when the results of a Channel Data Read Command returns new channel data. The bit
remains set indefinitely until the channel data is read. When the channel data is read again before the converter
updates with new data, the previous data is output and the NEW bit is cleared. If the channel data is not read
before the next conversion update, the data from the previous conversion is lost. As shown in Figure 62, the
NEW bit emulates the operation of the DRDY output pin. To emulate the function of the DRDY output pin in
software, the user reads data at a rate faster than the converter's data rate. The user then polls the NEW bit to
detect for new channel data.
0 = Channel data has not been updated since the last read operation.
1 = Channel data has been updated since the last read operation.
Figure 62. NEW Bit Operation
BIT STATUS.6 OVF
When this bit is set, this indicates the differential voltage applied to the ADC inputs have exceeded the range of
the converter |VIN| > 1.06 VREF. During over-range, the output code of the converter clips to either positive FS
(VIN ≥1.06 × VREF) or negative FS (VIN ≤–1.06 × VREF). This bit, with the MSB of the data, can be used to
detect positive or negative over-range conditions. Note that because of averaging incorporated within the digital
filter, the absence of this bit does not assure that the modulator of the ADC has not saturated due to possible
transient input overload conditions.
BIT STATUS.5 SUPPLY
This bit indicates that the analog power-supply voltage (AVDD – AVSS) is below a preset limit. The SUPPLY bit
is set when the value falls below 4.3 V (typically) and is reset when the value rises 50mV higher (typically) than
the lower trip point. The output data of the ADC may not be valid under low power-supply conditions.
BITS CHID[4:0] CHANNEL ID BITS
The Channel ID bits indicate the measurement channel of the acquired data. Note that for Fixed-Channel mode,
the Channel ID bits are undefined. See Table 11 for the channel ID, the measurement priority, and the channel
description for Auto-Scan Mode.
36 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
BITS DATA[23:0] OF DATA BYTES
The ADC output data are 24 bits wide (DATA[23:0]). DATA23 is the most significant bit (MSB) and DATA0 is the
least significant bit (LSB). The data is coded in binary twos complement format.
Table 11. Channel ID and Measurement Order (Auto-Scan Mode)
BITS CHID[4:0] PRIORITY CHANNEL DESCRIPTION
00h 1 (Highest) DIFF0 (AIN0–AIN1) Differential 0
01h 2 DIFF1 (AIN2–AIN3) Differential 1
02h 3 DIFF2 (AIN4–AIN5) Differential 2
03h 4 DIFF3 (AIN6–AIN7) Differential 3
04h 5 DIFF4 (AIN8– AIN9) Differential 4
05h 6 DIFF5 (AIN10–AIN11) Differential 5
06h 7 DIFF6 (AIN12–AIN13) Differential 6
07h 8 DIFF7 (AIN14–AIN15) Differential 7
08h 9 AIN0 Single-Ended 0
09h 10 AIN1 Single-Ended 1
0Ah 11 AIN2 Single-Ended 2
0Bh 12 AIN3 Single-Ended 3
0Ch 13 AIN4 Single-Ended 4
0Dh 14 AIN5 Single-Ended 5
0Eh 15 AIN6 Single-Ended 6
0Fh 16 AIN7 Single-Ended 7
10h 17 AIN8 Single-Ended 8
11h 18 AIN9 Single-Ended 9
12h 19 AIN10 Single-Ended 10
13h 20 AIN11 Single-Ended 11
14h 21 AIN12 Single-Ended 12
15h 22 AIN13 Single-Ended 13
16h 23 AIN14 Single-Ended 14
17h 24 AIN15 Single-Ended 15
18h 25 OFFSET OFFSET
1Ah 26 VCC AVDD – AVSS Supplies
1Bh 27 TEMP Temperature
1Ch 28 GAIN Gain
1Dh 29 (Lowest) REF External Reference
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Link(s): ADS1258-EP
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
COMMAND AND REGISTER DEFINITIONS
Commands are used to read channel data, access the configuration registers, and control the conversion
process. If the command is a register read or write operation, one or more data bytes follow the command byte.
If bit MUL = 1 in the command byte, then multiple registers can be read or written in one command operation
(see the MUL bit). Commands can be sent back-to-back without toggling CS; however, after a channel Data
Read Direct operation, CS must be toggled or an SPI timeout must occur before sending a command. The data
read by command does not require CS to be toggled.
The command byte consists of three fields: the Command Bits(C[2:0]), multiple register access bit (MUL), and
the Register Address Bits (A[3:0]); see the Command Byte register.
Command Byte
76543210
C2 C1 C0 MUL A3 A2 A1 A0
Bits C[2:0] — Command Bits
These bits code the command within the command byte.
C[2:0] DESCRIPTION COMMENTS
000 Channel Data Read Direct (no command) Toggle CS or allow SPI timeout before sending command
001 Channel Data Read Command (register format) Set MUL = 1; status byte always included in data
010 Register Read Command
011 Register Write Command
100 Pulse Convert Command MUL, A[3:0] are don't care
101 Reserved
110 Reset Command MUL, A[3:0] don't care
111 Channel Data Read Direct (no command) Toggle CS or allow SPI timeout before sending command
Bit 4 MUL: Multiple Register Access
0 = Disable Multiple Register Access
1 = Enable Multiple Register Access
This bit enables the multiple register access. This option allows writing or reading more than one register in a
single command operation. If only one register is to be read or written, set MUL = '0'. For multiple register
access, set MUL = '1'. The read or write operation begins at the addressed register. The ADS1258 automatically
increments the register address for each register data byte subsequently read or written. The multiple register
read or write operations complete after register address = 09h (device ID register) has been accessed.
The multiple register access is terminated in one of three ways:
1. The user takes CS high. This action resets the SPI interface.
2. The user holds SCLK inactive for 4096 fCLK cycles. This action resets the SPI interface.
3. Register address = 09h has been accessed. This completes the command and the ADS1258 is then ready
for a new command. Note for the Channel Data Read command, this bit must be set to read the four data
bytes (one status byte and three data bytes).
A[3:0] Register Address Bits
These bits are the register addresses for a register read or write operation; see Table 12.
38 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
REGISTERS
Table 12. Register Map
ADDRESS REGISTER DEFAULT
Bits A[3:0] NAME VALUE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00h CONFIG0 0Ah 0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0
01h CONFIG1 83h IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0
02h MUXSCH 00h AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0
03h MUXDIF 00h DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0
04h MUXSG0 FFh AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0
05h MUXSG1 FFh AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8
06h SYSRED 00h 0 0 REF GAIN TEMP VCC 0 OFFSET
07h GPIOC FFh CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0
08h GPIOD 00h DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0
09h ID 8Bh ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
CONFIG0: CONFIGURATION REGISTER 0 (Address = 00h)
76543210
0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0
Default = 0Ah.
Bit 7 Must be 0 (default)
Bit 6 SPIRST SPI Interface Reset Timer
This bit sets the number of fCLK cycles in which SCLK is inactive the SPI interface will reset. This
places a lower limit on the frequency of SCLK in which to read or write data to the device. The SPI
interface only is reset and not the device itself. When the SPI interface is reset, it is ready for a new
command.
0 = Reset when SCLK inactive for 4096fCLK cycles (256µs, fCLK = 16MHz) (default).
1 = Reset when SCLK inactive for 256fCLK cycles (16µs, fCLK = 16MHz).
Bit 5 MUXMOD
This bit sets either the Auto-Scan or Fixed-Channel mode of operation.
0 = Auto-Scan Mode (default)
In Auto-Scan mode, the input channel selections are eight differential channels (DIFF0–DIFF7) and 16
single-ended channels (AIN0–AIN15). Additionally, five internal monitor readings can be selected.
These selections are made in registers MUXDIF, MUXSG0, MUXSG1, and SYSRED. In this mode,
settings in register MUXSCH have no effect. See the Auto-Scan Mode section for more details.
1 = Fixed-Channel Mode
In Fixed-Channel mode, any of the analog input channels may be selected for the positive
measurement and the negative measurement channels. The inputs are selected in register MUXSCH.
In this mode, registers MUXDIF, MUXSG0, MUXSG1, and SYSRED have no effect. Note that it is not
possible to select the internal monitor readings in this mode.
Bit 4 BYPAS
This bit selects either the internal or external connection from the multiplexer output to the ADC input.
0 = ADC inputs use internal multiplexer connection (default).
1 = ADC inputs use external ADC inputs (ADCINP and ADCINN).
Note that the Temperature, VCC, Gain, and Reference internal monitor readings automatically use the
internal connection, regardless of the BYPAS setting. The Offset reading uses the setting of BYPAS.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 39
Product Folder Link(s): ADS1258-EP
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
Bit 3 CLKENB
This bit enables the clock output on pin CLKIO. The clock output originates from the device crystal
oscillator and PLL circuit.
0 = Clock output on CLKIO disabled.
1 = Clock output on CLKIO enabled (default).
Note: If the CLKSEL pin is set to '1', the CLKIO pin is a clock input only. In this case, setting this bit
has no effect.
Bit 2 CHOP
This bit enables the chopping feature on the external multiplexer loop.
0 = Chopping Disabled (default)
1 = Chopping Enabled
The chopping feature corrects for offset originating from components used in the external multiplexer
loop; see the External Chopping section.
Note that for Internal System readings (Temperature, VCC, Gain, and Reference), the CHOP bit must
be 0.
Bit 1 STAT Status Byte Enable
When reading channel data from the ADS1258, a status byte is normally included with the conversion
data. However, in some ADS1258 operating modes, the status byte can be disabled. Table 13, Status
Byte, shows the modes of operation and the data read formats in which the status byte can be
disabled.
0 = Status Byte Disabled
1 = Status Byte Enabled (default)
Table 13. Status Byte
CHANNEL DATA CHANNEL DATA
MODE READ COMMAND READ DIRECT
Auto-Scan Always Enabled Enabled/Disabled by STAT Bit
Fixed-Channel Always Enabled (Byte is Undefined) Always Disabled
Bit 0 Must be 0
40 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
CONFIG1: CONFIGURATION REGISTER 1 (Address = 01h)
76543210
IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0
Default = 83h.
Bit 7 IDLMOD
This bit selects the Idle mode when the device is not converting, Standby or Sleep. The Sleep mode
offers lower power consumption but has a longer wake-up time to re-enter the run mode; see the Idle
Modes section.
0 = Select Standby Mode
1 = Select Sleep Mode (default)
Bits DLY[2:0]
6–4 These bits set the amount of time the converter will delay after indexing to a new channel but before
starting a new conversion. This value should be set large enough to allow for the full settling of
external filtering or buffering circuits used between the MUXOUTP, MUXOUTN, and ADCINP,
ADCINN pins; see the Switch Time Delay section. (default = 000)
Bits SBCS[1:0]
3–2 These bits set the sensor bias current source.
0 = Sensor Bias Current Source Off (default)
1 = 1.5µA Source
3 = 24µA Source
Bits DRATE[1:0]
1–0 These bits set the data rate of the converter. Slower reading rates yield increased resolution; see
Table 4. The actual data rates shown in the table can be slower, depending on the use of Switch Time
Delay or the Chop feature. See the Switch Time Delay section. The reading rate scales with the
master clock frequency.
DATA RATE DATA RATE
AUTO-SCAN MODE FIXED-CHANNEL MODE
DRATE[1:0] (SPS) (SPS)
11 23739 125000
10 15123 31250
01 6168 7813
00 1831 1953
fCLK = 16MHz, Chop = 0, Delay = 0.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 41
Product Folder Link(s): ADS1258-EP
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
MUXSCH: MULTIPLEXER FIXED-CHANNEL REGISTER (Address = 02h)
76543210
AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0
Default = 00h.
This register selects the input channels of the multiplexer to be used for the Fixed-Channel mode. The MUXMOD
bit in register CONFIG0 must be set to '1'. In this mode, bits AINN[3:0] select the analog input channel for the
negative ADC input, and bits AINP[3:0] select the analog input channel for the positive ADC input. See the
Fixed-Channel Mode section.
MUXDIF: MULTIPLEXER DIFFERENTIAL INPUT SELECT REGISTER (Address = 03h)
76543210
DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0
Default = 00h.
MUXSG0: MULTIPLEXER SINGLE-ENDED INPUT SELECT REGISTER 0 (Address = 04h)
76543210
AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0
Default = FFh.
MUXSG1: MULTIPLEXER SINGLE-ENDED INPUT SELECT REGISTER 1 (Address = 05h)
76543210
AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8
Default = FFh.
SYSRED: SYSTEM READING SELECT REGISTER (Address = 06h)
76543210
0 0 REF GAIN TEMP VCC 0 OFFSET
Default = 00h.
These four registers select the input channels and the internal readings for measurement in Auto-Scan mode.
For differential channel selections (DIFF0…DIFF7), adjacent input pins (AIN0/AIN1, AIN2/AIN3, etc.) are pre-set
as differential inputs. All single-ended inputs are measured with respect to the AINCOM input. AINCOM may be
set to any level within ±100 mV of the analog supply range. Channels not selected are skipped in the
measurement sequence. Writing to any of these four registers resets the internal channel pointer to the channel
with the highest priority (see Table 11). Note that the bits indicated as '0' must be set to 0.
0 = Channel not selected within a reading sequence.
1 = Channel selected within a reading sequence.
42 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
GPIOC: GPIO CONFIGURATION REGISTER (Address = 07h)
76543210
CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0
Default = FFh.
This register configures the GPIO pins as inputs or as outputs. Note that the default configurations of the port
pins are inputs and as such they should not be left floating. See the GPIO Digital Port section.
0 = GPIO is an output; 1 = GPIO is an input (default).
CIO[7:0] GPIO Configuration
bit 7 CIO7, Digital I/O Configuration Bit for Pin GPIO7
bit 6 CIO6, Digital I/O Configuration Bit for Pin GPIO6
bit 5 CIO5, Digital I/O Configuration Bit for Pin GPIO5
bit 4 CIO4, Digital I/O Configuration Bit for Pin GPIO4
bit 3 CIO3, Digital I/O Configuration Bit for Pin GPIO3
bit 2 CIO2, Digital I/O Configuration Bit for Pin GPIO2
bit 1 CIO1, Digital I/O Configuration Bit for Pin GPIO1
bit 0 CIO0, Digital I/O Configuration Bit for Pin GPIO0
GPIOD: GPIO DATA REGISTER (Address = 08h)
76543210
DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0
Default = 00h.
This register is used to read and write data to the GPIO port pins. When reading this register, the data returned
corresponds to the state of the GPIO external pins, whether they are programmed as inputs or as outputs. As
outputs, a write to the GPIOD sets the output value. As inputs, a write to the GPIOD has no effect. See the
GPIO Digital Port section.
0 = GPIO is logic low (default); 1 = GPIO is logic high.
DIO[7:0] GPIO Data
bit 7 DIO7, Digital I/O Data bit for Pin GPIO7
bit 6 DIO6, Digital I/O Data bit for Pin GPIO6
bit 5 DIO5, Digital I/O Data bit for Pin GPIO5
bit 4 DIO4, Digital I/O Data bit for Pin GPIO4
bit 3 DIO3, Digital I/O Data bit for Pin GPIO3
bit 2 DIO2, Digital I/O Data bit for Pin GPIO2
bit 1 DIO1, Digital I/O Data bit for Pin GPIO1
bit 0 DIO0, Digital I/O Data bit for Pin GPIO0
ID: DEVICE ID REGISTER (Address = 09h)
76543210
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Default = 8Bh.
ID[7:0] ID Bits
Factory-programmed ID bits. Read-only.
APPLICATIONS
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 43
Product Folder Link(s): ADS1258-EP
Input AINx
AVDD
BAT54SWTI
AVSS
10kΩ
typ.
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
HARDWARE CONSIDERATIONS
The following summarizes the design and layout
considerations when using the ADS1258:
a. Power Supplies: The converter accepts a single
+5V supply (AVDD = 5 V and AVSS = AGND) or
dual, bipolar supplies (typically AVDD = 2.5 V,
AVSS = –2.5 V). Dual supply operation
accommodates true bipolar input signals, within a
±2.5-V range. Note that the maximum negative
input voltage to the multiplexer is limited to AVSS
– 100 mV, and the maximum positive input
voltage is limited to AVDD + 100 mV. The range Figure 63. Input Overload Protection
for the digital power supply (DVDD) is 2.7 V to d. ADC Inputs: The external multiplexer loop of the
5.25 V. For all supplies, use a 10-μF tantalum ADS1258 allows for the inclusion of signal
capacitor, bypassed with a 0.1-μF ceramic conditioning between the output of the multiplexer
capacitor, placed close to the device pins. and the input of the ADC. Typically, an amplifier
Alternatively, a single 10-μF ceramic capacitor is used to provide gain, buffering, and/or filtering
can be used. The supplies should be relatively to the input signal. For best performance, the
free from noise and should not be shared with ADC inputs should be driven differentially. A
devices that produce voltage spikes (such as differential in/differential out or a
relays, LED display drivers, etc.). If a switching single-ended-to-differential driver is recom-
power supply is used, the voltage ripple should mended. If the driver uses higher supply voltages
be low (< 2 mV). The analog and digital power than the device itself (for example, ±15V),
supplies may be sequenced in any order. attention should be paid to power-supply
b. Analog (Multiplexer) Inputs: The 16-channel sequencing and potential over-voltage fault
analog input multiplexer can accommodate 16 conditions. Protection resistors and/or external
single-ended inputs, eight differential input pairs, clamp diodes may be used to protect the ADC
or combinations of either. These options permit inputs. A 1-nF or higher capacitor should be used
freedom in choosing the input channels. The directly across the ADC inputs.
channels do not have to be used consecutively. e. Reference Inputs: It is recommended to use a
Unassigned channels are skipped by the device. 10-μF tantalum with a 0.1-μF ceramic capacitor
In the Fixed-Channel mode, any of the analog directly across the reference pins, VREFP and
inputs (AIN0 to AIN15) can be addressed for the VREFN. The reference inputs should be driven
positive input and for the negative input. The by a low-impedance source. For rated
full-scale range of the device is 2.13 VREF, but the performance, the reference should have less than
absolute analog input voltage is limited to 100 mV 3μVRMS broadband noise. For references with
beyond the analog supply rails. Input signals higher noise, external filtering may be necessary.
exceeding the analog supply rails (for example, Note that when exiting the sleep mode, the
±10 V) must be divided prior to the multiplexer device begins to draw a small current through the
inputs. reference pins. Under this condition, the transient
c. Input Overload Protection: Overdriving the response of the reference driver should be fast
multiplexer inputs may affect the conversions of enough to settle completely before the first
other channels. In the case of input overload, reading is taken, or simply discard the first
external Schottky diode clamps and series several readings.
resistor are recommended, as shown in Figure
61.
44 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
f. Clock Source: The ADS1258 requires a clock for more details. The SPI interface can be
signal for operation. The clock can originate from operated in a minimum configuration without the
either the crystal oscillator or from an external use of CS (tie CS low; see the Serial Interface
clock source. The internal oscillator uses a PLL and Communication Protocol sections).
circuit and an external 32.768-kHz crystal to j. GPIO: The ADS1258 has eight, user-
generate a 15.7-MHz master clock. The PLL programmable digital I/O pins. These pins are
requires a 22-nF capacitor from the PLLCAP pin controlled by register settings. The register
to AVSS. The crystal and load capacitors should setting is default to inputs. If these pins are not
be placed close to the pins as possible and kept used, tie them high or low (do not float input pins)
away from other traces with AC components. A or configure them as outputs.
buffered output of the 15.7-MHz clock can be k. QFN Package: See Application Report SLUA271,
used to drive other converters or controllers. An QFN/SON PCB Attachment for PCB layout
external clock source can be used up to 16 MHz. recommendations, available for download at
For best performance, the clock of the SPI www.ti.com. The exposed thermal pad of the
interface controller and the converter itself should ADS1258 should be connected electrically to
be on the same domain. This configuration AVSS.
requires that the ratio of the SCLK to device clock
must be limited to 1,1/2,1/4, 1/8, etc. CONFIGURATION GUIDE
g. Digital Inputs: It is recommended to source Configuration of the ADS1258 involves setting the
terminate the digital inputs and outputs of the configuration registers via the SPI interface. After the
device with a 50-Ω(typical) series resistor. The device is configured for operation, channel data is
resistors should be placed close to the driving read from the device through the same SPI interface.
end of the source (output pins, oscillator, logic The following is a suggested procedure for
gates, DSP, etc). This placement helps to reduce configuring the device:
the ringing and overshoot on the digital lines. 1. Reset the SPI Interface: Before using the SPI
h. Hardware Pins: START, DRDY, RESET, and interface, it may be necessary to recover the SPI
PWDN. These pins allow direct pin control of the interface. To reset the interface, set CS high or
ADS1258. The equivalent of the START and disable SCLK for 4096 (256) fCLK cycles.
DRDY pins is provided via commands through
the SPI interface; these pins may be left unused. 2. Stop the Converter: Set the START pin low to
The device also has a RESET command. The stop the converter. Although not necessary for
PWDN pin places the ADC into very low-power configuration, this command stops the channel
state where the device is inactive. scanning sequence which then points to the first
channel after configuration.
i. SPI Interface: The ADS1258 has an
SPI-compatible interface. This interface consists 3. Reset the Converter: The reset pin can be
of four signal lines: SCLK, DIN, DOUT, and CS. pulsed low or a Reset command can be sent.
When CS is high, the DIN input is ignored and Although not necessary for configuration, reset
the DOUT output tri-states. See Chip Select (CS )re-initializes the device into a known state.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 45
Product Folder Link(s): ADS1258-EP
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
4. Configure the Registers: The registers are Convert command sent through the interface.
configured by writing to them either sequentially 7. Read Channel Data: The DRDY asserts low
or as a group. The user may configure the when data is ready. The channel data can be
software in either mode. Any write to the read at that time. If DRDY is not used, the
Auto-Scan channel-select registers resets the updated channel data can be checked by reading
channel pointer to the channel of highest priority. the NEW bit in the status byte. The status byte
5. Verify Register Data: The register data may be also indicates the origin of the channel data. If
read back for verification of device the data for a given channel is not read before
communications. DRDY asserts low again, the data for that
channel is lost and replaced with new channel
6. Start the Converter: The converter can be data.
started with the START pin or with a Pulse
46 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
DIN
DOUT
DRDY
SCLK
CS(1)
ADS1258
SPISIMO
SPISOMI
XINT1
SPICLK
SPISTA
TMS320R2811
(1) CS may be tied low.
DIN
DOUT
DRDY
SCLK
CS(1)
ADS1258
(1) CS may be tied low.
P1.3
P1.2
P1.0
P1.6
P1.4
MSP430
GPIOx
(Input)
GPIOx
(Output)
ADS1258
4.7kΩ
10kΩ
Key Pad
3.3V
3.3V
470
LED Indicator
DIN
DOUT
DRDY
SCLK
CS(1)
ADS1258
(1) CS may be tied low.
MOSI
MISO
INT
SCK
IO
MSC12xx or
68HC11
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
DIGITAL INTERFACE CONNECTIONS
The ADS1258 SPI-compatible interface easily
connects to a wide variety of microcontrollers and
DSPs. Figure 64 shows the basic connection to TI's
MSP430 family of low-power microcontrollers.
Figure 65 shows the connection to microcontrollers
with an SPI interface such as the 68HC11 family, or
TI's MSC12xx family. Note that the MSC12xx
includes a high-resolution ADC; the ADS1258 can be
used to provide additional channels of measurement
or add higher-speed connections. Finally, Figure 66
shows how to connect the ADS1258 to a TMS320x
DSP.
Figure 66. Connection to a TMS320R2811 DSP
GPIO Connections
The ADS1258 has eight general purpose input/output
(GPIO) pins. Each pin can be configured as an input
or an output. Note that pins configured as inputs
should not float. The pins can be used to read key
pads, drive LED indicator, etc., by reading and writing
the GPIO data register (GPIOD). See Figure 67.
Figure 64. Connection to MSP430 Microcontroller
Figure 67. GPIO Connections
Figure 65. Connection to Microcontrollers with an
SPI Interface
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 47
Product Folder Link(s): ADS1258-EP
100Ω10kΩ
9.09kΩ
10kΩ
OPA350
OPA365
OPA365
ADS1258
47Ω
10kΩ
2.2nF
+2.5V
+2.5V
MUXOUTN
MUXOUTP
ADCINP
ADCINN
−2.5V
+2.5V
−2.5V
+2.5V
−2.5V
AIN15
AINCOM
REFP
REFN
AIN0
AVSS AVDD
±10V
9.09kΩ
±10V
50Ω
AINx
20mA Input
1kΩ
1kΩ
+2.5V
−2.5V
0.1µF100µF 0.1µF0.47µF
+10µF+REF3125
0.1µF
+10µF
−2.5V
0.1µF
+
10µF
…
…
NOTE: 0.1µF capacitors not shown.
47Ω
ADS1258-EP
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
www.ti.com
ANALOG INPUT CONNECTIONS When using Auto-Scan mode to sequence through
the channels, the switch time delay feature
Figure 68 shows the ADS1258 interfacing to (programmable by registers) can be used to provide
high-level ±10V inputs, commonly used in industrial additional settling time of the external components.
environments. In this case, bipolar power supplies are
used, avoiding the need for input signal level-shifting Figure 69 illustrates the ADS1258 interfacing to
otherwise required when a single supply is used. The multiple pressure sensors having a resistor bridge
input resistors serve both to reduce the level of the output. Each sensor is excited by the 5-V single
10V input signal to within the ADC range and also supply that also powers the ADS1258 and likewise is
protect the inputs from inadvertent signal over-voltage used as the ADS1258 reference input; the 6% input
up to 30V. The external amplifiers convert the overrange capability accommodates input levels at or
single-ended inputs to a fully differential output to above VREF. The ratiometric connection provides
drive the ADC inputs. Driving the inputs differentially cancellation of excitation voltage drift and noise. For
maintains good linearity performance. The 2.2-nF best performance, the 5-V supply should be free from
capacitor at the ADC inputs is required to bypass the glitches or transients. The 5-V supply input amplifiers
ADC sampling currents. The 2.5-V reference, (two OPA365s) form a differential input/differential
REF3125, is filtered and buffered to provide a output buffer with the gain set to 10. The chop feature
low-noise reference input to the ADC. The chop of the ADS1258 is used to reduce offset and offset
feature of the ADC can be used to reduce offset and drift to very low levels. The 2.2-nF capacitor at the
offset drift of the amplifiers. ADC inputs is required to bypass the ADC sampling
currents. The 47-Ωresistors isolate the op-amp
For ±1V input signals, the input resistor divider can outputs from the filter capacitor.
be removed and replaced with a series protection
resistor. For 20-mA input signals, the input resistor
divider is replaced by a 50-Ωresistor, connected from
each input to AINCOM.
Figure 68. Multichannel, ±10V Single-Ended Input, Bipolar Supply Operation
48 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS1258-EP
2kW
47W
R
10kW
2
ADS1258
2.2nF
+5V
+5V
47W
AIN0
AINCOM
MUXOUTN
MUXOUTP
ADCINP
ADCINN
2kW
AIN1
2kW
AIN14
2kW
AIN15
REFP
REFN
AVSS AVDD
R
2.2kW
1
10 Fm
+0.1 Fm
0.1 Fm
+
10 Fm
OPA365
OPA365
RFI
RFI
RFI
RFI
RFI
RFI
NOTE:G=1+2R /R .
2 1
0.1 Fsupplybypasscapacitornotshown.m
¼
¼
¼
R
10kW
2
ADS1258-EP
www.ti.com
SBAS445C –MARCH 2009–REVISED DECEMBER 2009
Figure 69. Bridge Input, Single-Supply Operation
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 49
Product Folder Link(s): ADS1258-EP
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS1258IPHPREP ACTIVE HTQFP PHP 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS1258IPHPREPG4 ACTIVE HTQFP PHP 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS1258MPHPTEP ACTIVE HTQFP PHP 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS1258MPHPTEPG4 ACTIVE HTQFP PHP 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS1258MRTCTEP ACTIVE VQFN RTC 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
V62/09626-01XE ACTIVE VQFN RTC 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
V62/09626-01YE ACTIVE HTQFP PHP 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
V62/09626-02XE ACTIVE HTQFP PHP 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
V62/09626-02YE ACTIVE HTQFP PHP 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS1258-EP :
•Catalog: ADS1258
PACKAGE OPTION ADDENDUM
www.ti.com 7-Jan-2010
Addendum-Page 1
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 7-Jan-2010
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS1258IPHPREP HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1258IPHPREP HTQFP PHP 48 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated