18
S and Noise Parameter Measurements
The position of the reference
planes used for the measurement
of both S and Noise Parameter
measurements is shown in Figure
36. The reference plane can be
described as being at the center
of both the gate and drain pads.
S and noise parameters are
measured with a 50 ohm
microstrip test fixture made with
a 0.010" thickness aluminum
substrate. Both source pads are
connected directly to ground via
a 0.010" thickness metal rib
which provides a very low
inductance path to ground for
both source pads. The inductance
associated with the addition of
printed circuit board plated
through holes and source bypass
capacitors must be added to the
computer circuit simulation to
properly model the effect of
grounding the source leads in a
typical amplifier design.
Gate
Pin 2
Source
Pin 3
Drain
Pin 4
Source
Pin 1
Reference
Plane
Microstrip
Transmission Lines
Vx
Figure 36. Position of the Reference Planes.
Noise Parameter Applications
Information
The Fmin values are based on a
set of 16 noise figure measure-
ments made at 16 different
impedances using an ATN NP5
test system. From these measure-
ments, a true Fmin is calculated.
Fmin represents the true mini-
mum noise figure of the device
when the device is presented
with an impedance matching
network that transforms the
source impedance, typically 50Ω,
to an impedance represented by
the reflection coefficient Γo. The
designer must design a matching
network that will present Γo to
the device with minimal associ-
ated circuit losses. The noise
figure of the completed amplifier
is equal to the noise figure of the
device plus the losses of the
matching network preceding the
device. The noise figure of the
device is equal to Fmin only
when the device is presented
with Γo. If the reflection coeffi-
cient of the matching network is
other than Γo, then the noise
figure of the device will be
greater than Fmin based on the
following equation.
NF = F
min
+ 4 R
n
|Γ
s
– Γ
o
| 2
Zo (|1 + Γ
o
|2)(1 - |Γ
s
|2)
Where Rn/Zo is the normalized
noise resistance, Γo is the opti-
mum reflection coefficient
required to produce Fmin and
Γ
s
is the reflection coefficient of the
source impedance actually
presented to the device.
The losses of the matching
networks are non-zero and they
will also add to the noise figure
of the device creating a higher
amplifier noise figure. The losses
of the matching networks are
related to the Q of the compo-
nents and associated printed
circuit board loss. Γo is typically
fairly low at higher frequencies
and increases as frequency is
lowered. Larger gate width
devices will typically have a
lower Γo as compared to nar-
rower gate width devices. Typi-
cally for FETs , the higher Γo
usually infers that an impedance
much higher than 50Ω is re-
quired for the device to produce
Fmin. At VHF frequencies and
even lower L Band frequencies,
the required impedance can be in
the vicinity of several thousand
ohms. Matching to such a high
impedance requires very hi-Q
components in order to minimize
circuit losses. As an example at
900 MHz, when air wound coils
(Q>100)are used for matching
networks, the loss can still be up
to 0.25 dB which will add di-
rectly to the noise figure of the
device. Using muiltilayer molded
inductors with Qs in the 30 to 50
range results in additional loss
over the air wound coil. Losses as
high as 0.5 dB or greater add to
the typical 0.15 dB Fmin of the
device creating an amplifier
noise figure of nearly 0.65 dB.
SMT Assembly
The package can be soldered
using either lead-bearing or lead-
free alloys (higher peak tempera-
tures). Reliable assembly of
surface mount components is a
complex process that involves
many material, process, and
equipment factors, including:
method of heating (e.g. IR or
vapor phase reflow, wave solder-
ing, etc) circuit board material,
conductor thickness and pattern,
type of solder alloy, and the
thermal conductivity and ther-
mal mass of components. Compo-
nents with a low mass, such as
the Minipak 1412 package, will
reach solder reflow temperatures
faster than those with a greater
mass.
The recommended leaded solder
time-temperature profile is
shown in Figure 37. This profile
is representative of an IR reflow
type of surface mount assembly
process. After ramping up from
room temperature, the circuit
board with components attached
to it (held in place with solder
paste) passes through one or
more preheat zones. The preheat
zones increase the temperature
of the board and components to
prevent thermal shock and begin
evaporating solvents from the
solder paste. The reflow zone