AD7920BKS-REEL7 - Analog Devices

250 kSPS,

10-/12-Bit ADCs in 6-Lead SC70

AD7910/AD7920

Rev. C

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

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FEATURES

Throughput rate: 250 kSPS

Specified for VDD of 2.35 V to 5.25 V

Low power

3.6 mW typ at 250 kSPS with 3 V supplies

12.5 mW typ at 250 kSPS with 5 V supplies

Wide input bandwidth

71 dB SNR at 100 kHz input frequency

Flexible power/serial clock speed management

No pipeline delays

High speed serial interface

SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible

Standby mode: 1 μA max

6-lead SC70 package

8-lead MSOP package

APPLICATIONS

Battery-powered systems

Personal digital assistants

Medical instruments

Mobile communications

Instrumentation and control systems

Data acquisition systems

High speed modems

Optical sensors

FUNCTIONAL BLOCK DIAGRAM

T/H

CONTROL LOGIC

10-/12-BIT

SUCCESSIVE

APPROXIMATION

ADC

GND

AD7910/AD7920

SDATA

SCLK

02976-001

Figure 1.

GENERAL DESCRIPTION

The AD7910/AD79201 are, respectively, 10-bit and 12-bit, high

speed, low power, successive approximation ADCs. The parts

operate from a single 2.35 V to 5.25 V power supply and feature

throughput rates up to 250 kSPS. The parts contain a low noise,

wide bandwidth track-and-hold amplifier that can handle input

frequencies in excess of 13 MHz.

The conversion process and data acquisition are controlled

using CS and the serial clock, allowing the devices to interface

with microprocessors or DSPs. The input signal is sampled on

the falling edge of CS and the conversion is initiated at this

point. There are no pipeline delays associated with the part.

The AD7910/AD7920 use advanced design techniques to

achieve very low power dissipation at high throughput rates.

The reference for the part is taken internally from VDD. This

allows the widest dynamic input range to the ADC. Thus, the

analog input range for the part is 0 to VDD. The conversion rate

is determined by the SCLK.

PRODUCT HIGHLIGHTS

1. 10-/12-bit ADCs in SC70 and MSOP packages.

2. Low power consumption.

3. Flexible power/serial clock speed management. The

conversion rate is determined by the serial clock, allowing

the conversion time to be reduced through the serial clock

speed increase. This allows the average power consumption

to be reduced when power-down mode is used while not

converting. The part also features a power-down mode to

maximize power efficiency at lower throughput rates.

Current consumption is 1 μA maximum and 50 nA typically

when in power-down mode.

4. Reference derived from the power supply.

5. No pipeline delay. The parts feature a standard successive

approximation ADC with accurate control of the sampling

instant via a CS input and once-off conversion control.

1 Protected by U.S. Patent No. 6,681,332.

AD7910/AD7920

Rev. C | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Specifications..................................................................................... 3

AD7910.......................................................................................... 3

AD7920.......................................................................................... 4

Timing Specifications .................................................................. 6

Timing Examples .............................................................................. 7

Timing Example 1 ........................................................................ 7

Timing Example 2 ........................................................................ 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 10

Term i nol og y .................................................................................... 12

Circuit Information........................................................................ 13

Converter Operation...................................................................... 14

ADC Transfer Function............................................................. 14

Typical Connection Diagram ................................................... 14

Analog Input ............................................................................... 15

Digital Inputs .............................................................................. 15

Modes of Operation ....................................................................... 16

Normal Mode.............................................................................. 16

Power-Down Mode .................................................................... 16

Power-Up Time .......................................................................... 16

Power vs. Throughput Rate........................................................... 18

Serial Interface ................................................................................ 19

Microprocessor Interfacing........................................................... 20

AD7910/AD7920 to TMS320C541 Interface ......................... 20

AD7910/AD7920 to ADSP-218x.............................................. 20

AD7910/AD7920 to DSP563xx Interface ............................... 21

Application Hints ........................................................................... 22

Grounding and Layout .............................................................. 22

Evaluating Performance ............................................................ 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 24

REVISION HISTORY

9/05—Rev. B to Rev. C

Updated Formatting ..........................................................Universal

Updated Outline Dimensions....................................................... 23

Changes to Ordering Guide.......................................................... 24

3/04—Rev. A to Rev. B

Added U.S. Patent Number ............................................................ 1

Changes to Note 5 ............................................................................ 2

Changes to Note 6 of AD7920 Specifications............................... 4

Changes to Note 1 of Timing Specifications ................................ 4

Changes to Absolute Maximum Ratings ...................................... 6

Changes to Ordering Guide............................................................ 6

8/03—Rev. 0 to Rev. A

Changes to Ordering Guide.............................................................6

Changes to Evaluating the AD7910/AD7920 Performance

Section.............................................................................................. 18

Updated Outline Dimensions ...................................................... 19

AD7910/AD7920

Rev. C | Page 3 of 24

SPECIFICATIONS

AD7910

VDD = 2.35 V to 5.25 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted.

Table 1.

Parameter1 A Grade1, 2Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 100 kHz sine wave

Signal-to-Noise + Distortion (SINAD)3 61 dB min

Total Harmonic Distortion (THD)3 −72 dB max

Peak Harmonic or Spurious Noise (SFDR)3 −73 dB max

Intermodulation Distortion (IMD)3

Second-Order Terms −82 dB typ fa = 100.73 kHz, fb = 90.7 kHz

Third-Order Terms −82 dB typ fa = 100.73 kHz, fb = 90.7 kHz

Aperture Delay 10 ns typ

Aperture Jitter 30 ps typ

Full Power Bandwidth 13.5 MHz typ @ 3 dB

2 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity ±0.5 LSB max

Differential Nonlinearity ±0.5 LSB max Guaranteed no missed codes to 10 bits

Offset Error3, 4 ±1 LSB max

Gain Error3, 4±1 LSB max

Total Unadjusted Error (TUE)3, 4±1.2 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to VDD V

DC Leakage Current ±0.5 A max

Input Capacitance 20 pF typ Track-and-hold in track, 6 pF typ when in hold

LOGIC INPUTS

Input High Voltage, VINH 2.4 V min

Input Low Voltage, VINL 0.8 V max VDD = 5 V

0.4 V max VDD = 3 V

Input Current, IIN, SCLK Pin ± 0.5 A max Typically 10 nA, VIN = 0 V or VDD

Input Current, IIN, CS Pin ± 10 nA typ

Input Capacitance, CIN5 5 pF max

LOGIC OUTPUTS

Output High Voltage, VOH VDD − 0.2 V min ISOURCE = 200 A, VDD = 2.35 V to 5.25 V

Output Low Voltage, VOL 0.4 V max ISINK = 200 A

Floating-State Leakage Current ±1 A max

Floating-State Output Capacitance5 5 pF max

Output Coding Straight (natural) binary

CONVERSION RATE

Conversion Time 2.8 s max 14 SCLK cycles with SCLK at 5 MHz

Track-and-Hold Acquisition Time3 250 ns max

Throughput Rate 250 kSPS max

POWER REQUIREMENTS

VDD 2.35/5.25 V min/max

IDD Digital I/Ps = 0 V or VDD

Normal Mode (Static) 2.5 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off

1.2 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off

Normal Mode (Operational) 3 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = 250 kSPS

1.4 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 250 kSPS

Full Power-Down Mode 1 A max Typically 50 nA

AD7910/AD7920

Rev. C | Page 4 of 24

Parameter1 A Grade1, 2Unit Test Conditions/Comments

Power Dissipation6

Normal Mode (Operational) 15 mW max VDD = 5 V, fSAMPLE = 250 kSPS

4.2 mW max VDD = 3 V, fSAMPLE = 250 kSPS

Full Power-Down 5 W max VDD = 5 V

3 W max VDD = 3 V

1 Temperature range from −40°C to +85°C.

2 Operational from VDD = 2.0 V, with input high voltage (VINH) 1.8 V min.

3 See the Terminology section.

4 SC70 values guaranteed by characterization.

5 Guaranteed by characterization.

6 See the Power vs. Throughput Rate section.

AD7920

VDD = 2.35 V to 5.25 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted.

Table 2.

Parameter1 A Grade , 1 2 B Grade1, 2Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 100 kHz sine wave

Signal-to-Noise + Distortion (SINAD)3 70 70 dB min VDD = 2.35 V to 3.6 V, TA = 25°C

69 69 dB min VDD = 2.4 V to 3.6 V

71.5 71.5 dB typ VDD = 2.35 V to 3.6 V

69 69 dB min VDD = 4.75 V to 5.25 V, TA = 25°C

68 68 dB min VDD = 4.75 V to 5.25 V

Signal-to-Noise Ratio (SNR)3 71 71 dB min VDD = 2.35 V to 3.6 V, TA = 25°C

70 70 dB min VDD = 2.4 V to 3.6 V

70 70 dB min VDD = 4.75 V to 5.25 V, TA = 25°C

69 69 dB min VDD = 4.75 V to 5.25 V

Total Harmonic Distortion (THD)3 −80 −80 dB typ

Peak Harmonic or Spurious Noise (SFDR)3 −82 −82 dB typ

Intermodulation Distortion (IMD)3

Second-Order Terms −84 −84 dB typ fa = 100.73 kHz, fb = 90.72 kHz

Third-Order Terms −84 −84 dB typ fa = 100.73 kHz, fb = 90.72 kHz

Aperture Delay 10 10 ns typ

Aperture Jitter 30 30 ps typ

Full Power Bandwidth 13.5 13.5 MHz typ @ 3 dB

2 2 MHz typ @ 0.1 dB

DC ACCURACY B Grade4

Resolution 12 12 Bits

Integral Nonlinearity3 ±1.5 LSB max

± 0.75 LSB typ

Differential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits

±0.75 LSB typ

Offset Error3, 5 ±1.5 LSB max

±1.5 ±0.2 LSB typ

Gain Error3, 5 ±1.5 LSB max

±1.5 ±0.5 LSB typ

Total Unadjusted Error (TUE)3, 5 ±2 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to VDD 0 to VDD V

DC Leakage Current ±0.5 ±0.5 A max

Input Capacitance 20 20 pF typ Track-and-hold in track, 6 pF typ when in hold

AD7910/AD7920

Rev. C | Page 5 of 24

Parameter1 A Grade , 1 2 B Grade1, 2Unit Test Conditions/Comments

LOGIC INPUTS

Input High Voltage, VINH 2.4 2.4 V min

1.8 1.8 V min VDD = 2.35 V

Input Low Voltage, VINL 0.8 0.8 V max VDD = 3.6 V to 5.25 V

0.4 0.4 V max VDD = 2.35 V to 3.6 V

Input Current, IIN, SCLK Pin ±0.5 ±0.5 A max Typically 10 nA, VIN = 0 V or VDD

Input Current, IIN, CS Pin ±10 ±10 nA typ

Input Capacitance, CIN6 5 5 pF max

LOGIC OUTPUTS

Output High Voltage, VOH VDD − 0.2 VDD − 0.2 V min ISOURCE = 200 µA, VDD = 2.35 V to 5.25 V

Output Low Voltage, VOL 0.4 0.4 V max ISINK = 200 µA

Floating-State Leakage Current ±1 ±1 A max

Floating-State Output Capacitance6 5 5 pF max

Output Coding Straight (natural) binary

CONVERSION RATE

Conversion Time 3.2 3.2 s max 16 SCLK cycles with SCLK at 5 MHz

Track-and-Hold Acquisition Time3 250 250 ns max

Throughput Rate 250 250 kSPS max See the Serial Interface section

POWER REQUIREMENTS

VDD 2.35/5.25 2.35/5.25 V min/max

IDD Digital I/Ps = 0 V or VDD

Normal Mode (Static) 2.5 2.5 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off

1.2 1.2 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off

Normal Mode (Operational) 3 3 mA max VDD = 4.75 V to 5.25 V, fSAMPLE = 250 kSPS

1.4 1.4 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 250 kSPS

Full Power-Down Mode 1 1 A max Typically 50 nA

Power Dissipation7

Normal Mode (Operational) 15 15 mW max VDD = 5 V, fSAMPLE = 250 kSPS

4.2 4.2 mW max VDD = 3 V, fSAMPLE = 250 kSPS

Full Power-Down 5 5 W max VDD = 5 V

3 3 W max VDD = 3 V

1 Temperature range from −40°C to +85°C.

2 Operational from VDD = 2.0 V, with input low voltage (VINL) 0.35 V max.

3 See the Terminology section.

4 B Grade, maximum specifications apply as typical figures when VDD = 4.75 V to 5.25 V.

5 SC70 values guaranteed by characterization.

6 Guaranteed by characterization.

7 See the Power vs. Throughput Rate section.

AD7910/AD7920

Rev. C | Page 6 of 24

TIMING SPECIFICATIONS

VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter1

AD7910/AD7920

Limit at TMIN, TMAX Unit Description

fSCLK2 10 kHz min3

5 MHz max

tCONVERT 14 × tSCLK AD7910

16 × tSCLK AD7920

tQUIET 50 ns min Minimum quiet time required between bus relinquish and start of next

conversion

t1 10 ns min Minimum CS pulse width

t2 10 ns min CS to SCLK setup time

t34 22 ns max Delay from CS until SDATA three-state disabled

t4 40 ns max Data access time after SCLK falling edge

t5 0.4 × tSCLK ns min SCLK low pulse width

t6 0.4 × tSCLK ns min SCLK high pulse width

t75, 6 SCLK to data valid hold time

10 ns min VDD ≤ 3.3 V

9.5 ns min 3.3 V < VDD ≤ 3.6 V

7 ns min VDD > 3.6 V

t86, 736 ns max SCLK falling edge to SDATA three-state

See Note 7 ns min SCLK falling edge to SDATA three-state

tPOWER-UP81 s max Power-up time from full power-down

1 Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2 Mark/Space ratio for the SCLK input is 40/60 to 60/40.

3 Minimum fSCLK at which specifications are guaranteed.

4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 1.8 V when VDD = 2.35 V and 0.8 V or 2.0 V for VDD > 2.35 V.

5 Measured with a 50 pF load capacitor.

6 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, shown in the Timing Specifications is the true bus relinquish

time of the part and is independent of the bus loading.

7 T7 values apply to t8 minimum values also.

8 See Power-Up Time section.

200μAI

1.6V

TO OUTPUT

PIN C

50pF

02976-002

Figure 2. Load Circuit for Digital Output Timing Specifications

AD7910/AD7920

Rev. C | Page 7 of 24

TIMING EXAMPLES

Figure 3 and Figure 4 show some of the timing parameters from

Table 3 .

TIMING EXAMPLE 1

From Figure 4, having fSCLK = 5 MHz and a throughput rate of

250 kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 4 μs.

With t2 = 10 ns min, this leaves tACQ to be 1.49 μs. This 1.49 μs

satisfies the requirement of 250 ns for tACQ. From Figure 4, tACQ

comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 36 ns max. This

allows a value of 954 ns for tQUIET, satisfying the minimum

requirement of 50 ns.

TIMING EXAMPLE 2

The AD7920 can also operate with slower clock frequencies.

From Figure 4, having fSCLK = 3.4 MHz and a throughput rate of

150 kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 6.66 μs.

With t2 = 10 ns min, this leaves tACQ to be 2.97 μs. This 2.97 μs

satisfies the requirement of 250 ns for tACQ. From Figure 4, tACQ

comprises 2.5(1/fSCLK) + t8 + tQUIET, t8 = 36 ns max. This allows a

value of 2.19 μs for tQUIET, satisfying the minimum requirement

of 50 ns. As in this example and with other slower clock values,

the signal may already be acquired before the conversion is

complete, but it is still necessary to leave 50 ns minimum tQUIET

between conversions. In this example, the signal should be fully

acquired at approximately Point C in Figure 4.

SCLK

SDATA

CONVERT

QUIET

ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0

THREE-STATETHREE-

STATE

4 LEADING ZEROS

12345 13141516

02976-003

Figure 3. AD7920 Serial Interface Timing Diagram

CLK

CONVERT

12345 13141516

QUIET

ACQ

12.5(1/f

SCLK

)

1/THROUGHPUT

02976-004

Figure 4. Serial Interface Timing Example

AD7910/AD7920

Rev. C | Page 8 of 24

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7 V

Analog Input Voltage to GND −0.3 V to VDD + 0.3 V

Digital Input Voltage to GND −0.3 V to +7 V

Digital Output Voltage to GND −0.3 V to VDD + 0.3 V

Input Current to Any Pin Except Supplies1± 10 mA

Operating Temperature Range

Commercial (A, B Grade) −40°C to +85°C

Storage Temperature Range −65°C to +150°C

Junction Temperature 150°C

MSOP Package

θJA Thermal Impedance 205.9°C/W

θJC Thermal Impedance 43.74°C/W

SC70 Package

θJA Thermal Impedance 340.2°C/W

θJC Thermal Impedance 228.9°C/W

Lead Temperature, Soldering

Reflow (10 sec to 30 sec) 235 (0/+5)°C

ESD 3.5 kV

1 Transient currents of up to 100 mA will not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

AD7910/AD7920

Rev. C | Page 9 of 24

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DD 1

GND

IN 3

SDATA

SCLK

AD7910/

AD7920

TOP VIEW

(Not to Scale)

02976-005

Figure 5. 6-Lead SC70 Pin Configuration

VDD 1

SDATA 2

CS 3

NC 4

VIN

GND7

SCLK

NC5

NC = NO CONNECT

AD7910/

AD7920

TOP VIEW

(Not to Scale)

02976-006

Figure 6. 8-Lead MSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

6-Lead

SC70

Pin No.

8-Lead

MSOP Mnemonic Description

6 3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the

AD7910/AD7920 and framing the serial data transfer.

1 1 VDD Power Supply Input. The VDD range for the AD7910/AD7920 is from 2.35 V to 5.25 V.

2 7 GND

Analog Ground. Ground reference point for all circuitry on the AD7910/AD7920. All analog input signals

should be referred to this GND voltage.

3 8 VIN Analog Input. Single-ended analog input channel. The input range is 0 to VDD.

5 2 SDATA

Data Out. Logic output. The conversion result from the AD7910/AD7920 is provided on this output as a

serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from

the AD7920 consists of four leading zeros followed by the 12 bits of conversion data, which is provided

MSB first. The data stream from the AD7910 consists of four leading zeros followed by the 10 bits of

conversion data followed by two trailing zeros, which is also provided MSB first.

4 6 SCLK

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input

is also used as the clock source for the AD7910/AD7920 conversion process.

N/A 4, 5 NC No Connect.

AD7910/AD7920

Rev. C | Page 10 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7 and Figure 8 show a typical FFT plot for the AD7920 and

AD7910, respectively, at a 250 kSPS sampling rate and a 100 kHz

input frequency.

Figure 9 shows the signal-to-(noise + distortion) ratio performance

vs. input frequency for various supply voltages while sampling at

250 kSPS with an SCLK frequency of 5 MHz for the AD7920.

Figure 10 and Figure 11 show typical INL and DNL performance

for the AD7920.

Figure 12 shows a graph of the total harmonic distortion vs. analog

input frequency for different source impedances when using a

supply voltage of 3.6 V and sampling at a rate of 250 kSPS. See the

Analog Input section.

Figure 13 shows a graph of the total harmonic distortion vs.

analog input signal frequency for various supply voltages while

sampling at 250 kSPS with an SCLK frequency of 5 MHz.

FREQUENCY (kHz)

–5

–55

–115 0 12525

SNR (dB)

50 75 100

–15

–35

–75

–95

8192 POINT FFT

= 2.7V

SAMPLE

= 250kSPS

= 100kHz

SINAD = 72.05dB

THD = –82.87dB

SFDR = –87.24dB

02976-007

Figure 7. AD7920 Dynamic Performance at 250 kSPS

FREQUENCY (kHz)

–45

–105

SNR (dB)

–5

–25

–65

–85

0 12525 50 75 100

02976-008

8192 POINT FFT

= 2.35V

SAMPLE

= 250kSPS

= 100kHz

SINAD = 61.67dB

THD = –79.59dB

SFDR = –82.93dB

Figure 8. AD7910 Dynamic Performance at 250 kSPS

FREQUENCY (kHz)

–72.0

10 1000

SINAD (dB)

100

–73.0

–73.5

= 5.25V

= 2.35V

= 2.7V

= 4.75V V

= 3.6V

–72.5

–71.0

–71.5

02976-009

Figure 9. AD7920 SINAD vs. Input Frequency at 250 kSPS

CODE

1.0

0.4

–0.2

0 1024

INL ERROR (LSB)

512

0.8

0.6

0.2

–0.4

–0.6

–0.8

–1.0 1536 2048 2560 3072 3584 4096

= 2.35V

TEMP = 25°C

SAMPLE

= 250kSPS

02976-010

Figure 10. AD7920 INL Performance

AD7910/AD7920

Rev. C | Page 11 of 24

CODE

1.0

0.4

–0.2

0 1024

DNL ERROR (LSB)

512

0.8

0.6

0.2

–0.4

–0.6

–0.8

–1.0 1536 2048 2560 3072 3584 4096

= 2.35V

TEMP = 25°C

SAMPLE

= 250kSPS

02976-011

Figure 11. AD7920 DNL Performance

INPUT FREQUENCY (kHz)

–30

–60

10 1000

THD (dB)

100

–10

–20

–40

–50

–70

–80

–90

= 3.6V

= 10kΩ

= 1kΩ

= 130ΩR

= 13Ω

= 0Ω

02976-012

Figure 12. THD vs. Analog Input Frequency for Various Source Impedances

INPUT FREQUENCY (kHz)

–75

–9010 1000

THD (dB)

100

–65

–70

–80

–85

= 5.25V

= 2.35V

= 2.7V

= 4.75V

= 3.6V

02976-013

Figure 13. THD vs. Analog Input Frequency for Various Supply Voltages

AD7910/AD7920

Rev. C | Page 12 of 24

TERMINOLOGY

Integral Nonlinearity

The maximum deviation from a straight line passing through

the endpoints of the ADC transfer function. For the AD7920

and AD7910, the endpoints of the transfer function are zero

scale, a point 1 LSB below the first code transition, and full

scale, a point 1 LSB above the last code transition.

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Offset Error

The deviation of the first code transition (00 . . . 000) to (00 . . . 001)

from the ideal, that is, GND + 1 LSB.

Gain Error

The deviation of the last code transition (111 . . . 110) to

(111 . . . 111) from the ideal, that is, VREF − 1 LSB after the offset

error has been adjusted out.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode at the end

of conversion. Track-and-hold acquisition time is the time

required for the output of the track-and-hold amplifier to reach

its final value, within ±0.5 LSB, after the end of conversion. See

the Serial Interface section for more details.

Signal-to-(Noise + Distortion) Ratio

The measured ratio of signal-to-(noise + distortion) at the output

of the A/D converter. The signal is the rms amplitude of the

fundamental. Noise is the sum of all nonfundamental signals up

to half the sampling frequency (fS/2), excluding dc. The ratio is

dependent on the number of quantization levels in the digiti-

zation process. The more levels, the smaller the quantization

noise. The theoretical signal-to-(noise + distortion) ratio for an

ideal N-bit converter with a sine wave input is given by:

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Thus, for a 12-bit converter this is 74 dB, and for a 10-bit

converter this is 62 dB.

Tota l Una djuste d Error

A comprehensive specification that includes gain error, linearity

error, and offset error.

Total Harmonic Distortion (THD)

Total harmonic distortion is the ratio of the rms sum of

harmonics to the fundamental. It is defined as:

log20)( V

VVVVV

dBTHD ++++

where:

V1 is the rms amplitude of the fundamental.

V2, V3, V4, V5, and V6 are the rms amplitudes of the second

through the sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is the ratio of the rms value of

the next largest component in the ADC output spectrum (up to

fS/2 and excluding dc) to the rms value of the fundamental.

Normally, the value of this specification is determined by the

largest harmonic in the spectrum, but for ADCs whose

harmonics are buried in the noise floor, it is a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb,

any active device with nonlinearities creates distortion products

at sum and difference frequencies of mfa ± nfb where m, n = 0, 1,

2, 3, and so on. Intermodulation distortion terms are those for

which neither m nor n are equal to zero. For example, the second-

order terms include (fa + fb) and (fa − fb), while the third-order

terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The AD7910/AD7920 are tested using the CCIF standard, where

two input frequencies are used (see fa and fb in the Specifications

page). In this case, the second-order terms are usually distanced in

frequency from the original sine waves, while the third-order terms

are usually at a frequency close to the input frequencies. As a result,

the second- and third-order terms are specified separately. The

calculation of the intermodulation distortion is as per the THD

specification, the ratio of the rms sum of the individual distortion

products to the rms amplitude of the sum of the fundamentals,

expressed in dB.

AD7910/AD7920

Rev. C | Page 13 of 24

CIRCUIT INFORMATION

The AD7910/AD7920 are fast, micropower, 10-bit/12-bit,

single-supply A/D converters, respectively. The parts can be

operated from a 2.35 V to 5.25 V supply. When operated from

either a 5 V supply or a 3 V supply, the AD7910/AD7920 are

capable of throughput rates of 250 kSPS when provided with a

5 MHz clock.

The AD7910/AD7920 provide the user with an on-chip track-

and-hold, A/D converter, and a serial interface housed in a tiny

6-lead SC70 package or 8-lead MSOP package, which offers the

user considerable space saving advantages over alternative

solutions.

The serial clock input accesses data from the part but also

provides the clock source for the successive approximation A/D

converter. The analog input range is 0 V to VDD. An external

reference is not required for the ADC and there is no reference

on-chip. The reference for the AD7910/AD7920 is derived from

the power supply and thus gives the widest dynamic input

range.

The AD7910/AD7920 also feature a power-down option to

allow power saving between conversions. The power-down

feature is implemented across the standard serial interface, as

described in the Modes of Operation section.

AD7910/AD7920

Rev. C | Page 14 of 24

CONVERTER OPERATION

The AD7910/AD7920 are successive approximation analog-to-

digital converters based around a charge redistribution DAC.

Figure 14 and Figure 15 show simplified schematics of the

ADC. Figure 14 shows the ADC during its acquisition phase.

When SW2 is closed and SW1 is in Position A, the comparator

is held in a balanced condition, and the sampling capacitor

acquires the signal on VIN.

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

COMPARATOR

SW2

SAMPLING

CAPACITOR

ACQUISITION

PHASE

SW1

AGND V

02976-014

Figure 14. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 15), SW2 opens

and SW1 moves to Position B, causing the comparator to become

unbalanced. The control logic and charge redistribution DAC are

used to add and subtract fixed amounts of charge from the

sampling capacitor to bring the comparator back into a balanced

condition. When the comparator is rebalanced, the conversion is

complete. The control logic generates the ADC output code.

Figure 16 shows the ADC transfer function.

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

COMPARATOR

SW2

SAMPLING

CAPACITOR

CONVERSION

PHASE

SW1

AGND V

02976-015

Figure 15. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding of the AD7910/AD7920 is straight binary.

The designed code transitions occur at the successive integer

LSB values, that is, 1 LSB, 2 LSBs, and so on. The LSB size is

VDD/4096 for the AD7920 and VDD/1024 for the AD7910. The

ideal transfer characteristic for the AD7910/AD7920 is shown

in Figure 16.

000...000

ADC CODE

ANALOG INPUT

111...111

000...001

000...010

111...110

111...000

011...111

1LSB +V

– 1LSB

1LSB = V

/1024 (AD7910)

1LSB = V

/4096 (AD7920)

02976-016

Figure 16. Transfer Characteristic

TYPICAL CONNECTION DIAGRAM

Figure 17 shows a typical connection diagram for the AD7910/

AD7920. VREF is taken internally from VDD and, as such, VDD

should be well decoupled. This provides an analog input range of

0 V to VDD. The conversion result is output in a 16-bit word with

four leading zeros followed by the MSB of the 12-bit or 10-bit

result. Two trailing zeros follow the 10-bit result from the

AD7910.

Alternatively, because the supply current required by the

AD7910/AD7920 is so low, a precision reference can be used as

the supply source to the AD7910/AD7920. An REF19x voltage

reference (REF195 for 5 V or REF193 for 3 V) can be used to

supply the required voltage to the ADC (see Figure 17). This

configuration is especially useful if the power supply is quite

noisy or if the system supply voltages are at a value other than

5 V or 3 V (for example, 15 V). The REF19x outputs a steady

voltage to the AD7910/AD7920. If the low dropout REF193 is

used, the current it needs to supply to the AD7910/AD7920 is

typically 1.2 mA. When the ADC is converting at a rate of

250 kSPS, the REF193 needs to supply a maximum of 1.4 mA to

the AD7910/AD7920. The load regulation of the REF193 is

typically 10 ppm/mA (REF193, VS = 5 V), which results in an

error of 14 ppm (42 μV) for the 1.4 mA drawn from it. This

corresponds to a 0.057 LSB error for the AD7920 with VDD =

3 V from the REF193 and a 0.014 LSB error for the AD7910.

For applications where power consumption is of concern, the

power-down mode of the ADC and the sleep mode of the

REF19x reference should be used to improve power

performance. See the Modes of Operation section.

AD7910/AD7920

Rev. C | Page 15 of 24

AD7910/

AD7920

SERIAL

INTERFACE

0V TO V

INPUT

GND

SCLK

SDATA

0.1

F10

TANT

0.1

680nF

3V 5V

SUPPLY

1.2mA REF193

02976-017

Figure 17. REF193 as Power Supply

Table 6 provides typical performance data with various

references used as a VDD source for a 100 kHz input tone at

room temperature, under the same setup conditions.

Table 6. AD7920 Typical Performance for Various Voltage

References IC

Reference Tied to VDD AD7920 SNR Performance (dB)

AD780 @ 3 V 72.65

REF193 72.35

AD780 @ 2.5 V 72.5

REF192 72.2

REF43 72.6

ANALOG INPUT

Figure 18 shows an equivalent circuit of the analog input

structure of the AD7910/AD7920. The two diodes, D1 and D2,

provide ESD protection for the analog input. Care must be

taken to ensure that the analog input signal never exceeds the

supply rails by more than 300 mV. This causes these diodes to

become forward biased and start conducting current into the

substrate. The maximum current these diodes can conduct

without causing irreversible damage to the parties is 10 mA.

Capacitor C1 in Figure 18 is typically about 6 pF and can be

attributed primarily to pin capacitance. Resistor R1 is a lumped

component made up of the on resistance of a switch. This

resistor is typically about 100 Ω. Capacitor C2 is the ADC

sampling capacitor and has a capacitance of 20 pF typically. For

ac applications, removing high frequency components from the

analog input signal is recommended by use of a band-pass filter

on the relevant analog input pin. In applications where

harmonic distortion and signal-to-noise ratio are critical, the

analog input should be driven from a low impedance source.

Large source impedances significantly affect the ac performance

of the ADC. This can necessitate the use of an input buffer

amplifier. The choice of the op amp is a function of the

particular application.

6pF

20pF

CONVERSION PHASE—SWITCH OPEN

TRACK PHASE—SWITCH CLOSED

VDD

02976-018

Figure 18. Equivalent Analog Input Circuit

Table 7 provides some typical performance data with various op

amps used as the input buffer for a 100 kHz input tone at room

temperature, under the same setup conditions.

Table 7. AD7920 Typical Performance for Various Input

Buffers, VDD = 3 V

Op Amp in the Input Buffer AD7920 SNR Performance (dB)

AD711 72.3

AD797 72.5

AD845 71.4

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance depends on the amount of total harmonic

distortion (THD) that can be tolerated. The THD increases as

the source impedance increases, and performance degrades (see

Figure 12).

DIGITAL INPUTS

The digital inputs applied to the AD7910/AD7920 are not limited

by the maximum ratings that limit the analog input. Instead, the

digital inputs applied can go to 7 V and are not restricted by the

VDD + 0.3 V limit as on the analog input. For example, if the

AD7910/AD7920 were operated with a VDD of 3 V, then 5 V logic

levels could be used on the digital inputs. However, it is important

to note that the data output on SDATA still have 3 V logic levels

when VDD = 3 V. Another advantage of SCLK and CS not being

restricted by the VDD + 0.3 V limit is that power supply

sequencing issues are avoided. If CS or SCLK is applied before

VDD, there is no risk of latch-up as there would be on the analog

inputs if a signal greater than 0.3 V were applied prior to VDD.

AD7910/AD7920

Rev. C | Page 16 of 24

MODES OF OPERATION

The mode of operation of the AD7910/AD7920 is selected by

controlling the logic state of the CS signal during a conversion.

There are two possible modes of operation, normal mode and

power-down mode. The point at which CS is pulled high after

the conversion is initiated determines whether the

AD7910/AD7920 enters power-down mode. Similarly, if the

device is already in power-down mode, CS can control whether

it returns to normal operation or remains in power-down

mode. These modes of operation are designed to provide

flexible power management options. These options can be

chosen to optimize the power dissipation/throughput rate ratio

for different application requirements.

NORMAL MODE

This mode is intended for fastest throughput rate performance

because the user does not have to worry about any power-up

times; the AD7910/AD7920 remains fully powered all the time.

Figure 19 shows the general diagram of the operation of the

AD7910/AD7920 in this mode.

The conversion is initiated on the falling edge of CS as

described in the Serial Interface section. To ensure that the part

remains fully powered up at all times, CS must remain low until

at least 10 SCLK falling edges have elapsed after the falling edge

of CS. If CS is brought high any time after the tenth SCLK

falling edge but before the end of the tCONVERT, then the part

remains powered up but the conversion is terminated and

SDATA goes back into three-state.

For the AD7920, 16 serial clock cycles are required to complete

the conversion and access the complete conversion result. For

the AD7910, a minimum of 14 serial clock cycles is required to

complete the conversion and access the complete conversion

result.

CS can idle high until the next conversion or can idle low until

CS returns high sometime prior to the next conversion,

effectively idling CS low.

Once a data transfer is complete (SDATA has returned to three-

state), another conversion can be initiated after the quiet time,

tQUIET, has elapsed by bringing CS low again.

POWER-DOWN MODE

This mode is intended for use in applications where slower

throughput rates are required; either the ADC is powered down

between conversions, or a series of conversions can be

performed at a high throughput rate and the ADC is powered

down for a relatively long duration between these bursts of

several conversions. When the AD7910/AD7920 is in power-

down mode, all analog circuitry is powered down.

To enter power-down mode, the conversion process must be

interrupted by bringing CS high anywhere after the second

falling edge of SCLK, and before the tenth falling edge of SCLK,

as shown in Figure 20. Once CS is brought high in this window

of SCLKs, the part enters power-down mode, the conversion

that was initiated by the falling edge of CS is terminated, and

SDATA goes back into three-state. If CS is brought high before

the second SCLK falling edge, the part remains in normal mode

and does not power down. This avoids accidental power-down

due to glitches on the CS line.

To exit this mode of operation and power up the AD7910/

AD7920 again, a dummy conversion is performed. On the falling

edge of CS, the device begins to power up, and continues to

power up as long as CS is held low until after the falling edge of

the tenth SCLK. The device is fully powered up once 16 SCLKs

have elapsed and valid data results from the next conversion, as

shown in Figure 21. If CS is brought high before the tenth SCLK

falling edge, the AD7910/AD7920 goes back into power-down

mode again. This avoids accidental power-up due to glitches on

the CS line or an inadvertent burst of eight SCLK cycles while CS

is low. Although the device can begin to power up on the falling

edge of CS, it powers down again on the rising edge of CS as long

as it occurs before the tenth SCLK falling edge.

POWER-UP TIME

The power-up time of the AD7910/AD7920 is 1 μs, which

means that one dummy cycle is always sufficient to allow the

device to power up. Once the dummy cycle is complete, the

ADC fully powered up and the input signal acquired properly.

The quiet time, tQUIET, must still be allowed from the point

where the bus goes back into three-state after the dummy

conversion, to the next falling edge of CS.

When powering up from the power-down mode with a dummy

cycle, as in Figure 21, the track-and-hold that was in hold mode

while the part was powered down returns to track mode after

the first SCLK edge the part receives after the falling edge of CS.

This is shown as Point A in Figure 21. Although at any SCLK

frequency one dummy cycle is sufficient to power up the device

and acquire VIN, it does not necessarily mean that a full dummy

cycle of 16 SCLKs must always elapse to power up the device

and fully acquire VIN; 1 μs is sufficient to power the device up

and acquire the input signal. Therefore, if a 5 MHz SCLK

frequency is applied to the ADC, the cycle time is 3.2 μs. In one

dummy cycle, 3.2 μs, the part powers up and VIN is fully

acquired. However, after 1 μs with a 5 MHz SCLK, only five

SCLK cycles have elapsed. At this stage, the ADC is fully

powered up and the signal is acquired. In this case, the CS can

be brought high after the tenth SCLK falling edge and brought

low again after a time, tQUIET, to initiate the conversion.

AD7910/AD7920

Rev. C | Page 17 of 24

VALID DATA

SCLK

DAT

110121416

AD7910/AD7920

02976-019

Figure 19. Normal Mode Operation

THREE-STATE

SDATA

SCLK

110121416

02976-020

Figure 20. Entering Power-Down Mode

SCLK

SDAT

THE PART

BEGINS TO

POWER UP

THE PART IS FULLY

POWERED UP WITH

FULLY ACQUIRED

A10 12 14 16 116

VALID DATA

INVALID DATA

02976-021

Figure 21. Exiting Power-Down Mode

When power supplies are first applied to the AD7910/AD7920, the

ADC can power up in either power-down mode or in normal

mode. Because of this, it is best to allow a dummy cycle to elapse to

ensure the part is fully powered up before attempting a valid

conversion. Likewise, if the intention is to keep the part in power-

down mode while not in use and the user wishes the part to power

up in power-down mode, the dummy cycle can be used to ensure

the device is in power-down mode by executing a cycle such as that

shown in Figure 20. Once supplies are applied to the

AD7910/AD7920, the power-up time is the same as that when

powering up from power-down mode. It takes approximately 1 μs

to power up fully if the part powers up in normal mode. It is not

necessary to wait 1 μs before executing a dummy cycle to ensure

the desired mode of operation.

Instead, the dummy cycle can occur directly after power is

supplied to the ADC. If the first valid conversion is performed

directly after the dummy conversion, care must be taken to

ensure that adequate acquisition time is allowed. As mentioned

earlier, when powering up from the power-down mode, the part

returns to track upon the first SCLK edge applied after the

falling edge of CS. However, when the ADC powers up initially

after supplies are applied, the track-and-hold is in track. This

means, assuming the user has the facility to monitor the ADC

supply current, if the ADC powers up in the desired mode of

operation and thus a dummy cycle is not required to change

mode then a dummy cycle is required to place the track-and-

hold into track.

AD7910/AD7920

Rev. C | Page 18 of 24

POWER VS. THROUGHPUT RATE

By using the power-down mode on the AD7910/AD7920 when

not converting, the average power consumption of the ADC

decreases at lower throughput rates. Figure 22 shows how, as the

throughput rate is reduced, the device remains in its power-

down state longer and the average power consumption over

time drops accordingly.

For example, if the AD7910/AD7920 is operated in a

continuous sampling mode with a throughput rate of 100 kSPS

and an SCLK of 5 MHz (VDD = 5 V), and the device is placed in

the power-down mode between conversions, the power

consumption is calculated as follows.

The power dissipation during normal mode is 15 mW (VDD = 5 V).

The power dissipation includes the power dissipated while the part

is entering power-down mode, the power dissipated during the

dummy conversion (when the part is exiting power-down mode

and powering up), and the power dissipated during conversion.

As mentioned in the power-down mode section, to enter

power-down mode, CS has to be brought high anywhere

between the second and tenth SCLK falling edge. Therefore, the

power consumption when entering power-down mode varies

depending on the number of SCLK cycles used. In this example,

five SCLK cycles are used to enter power-down mode. This

gives a time period of 5 × (1/fSCLK) = 1 μs.

The power-up time is 1 μs, which implies that only five SCLK

cycles are required to power up the part. However, CS has to

remain low until at least the tenth SCLK falling edge when

exiting power-down mode. This means that a minimum of nine

SCLK cycles have to be used to exit power-down mode and

power up the part.

So, if nine SCLK cycles are used, the time to power up the part

and exit power-down mode is 9 × (1/fSCLK) = 1.8 μs.

Finally, the conversion time is 16 × (1/fSCLK) = 3.2 μs.

Therefore, the AD7910/AD7920 can be said to dissipate 15 mW

for 3.2 μs + 1.8 μs + 1 μs = 6 μs during each conversion cycle. If

the throughput rate is 100 kSPS, the cycle time is 10 μs and the

average power dissipated during each cycle is (6/10) × (15 mW)

= 9 mW. The power dissipation when the part is in power-down

has not been taken into account because the shutdown current

is so low and it does not have any effect on the overall power

dissipation value.

If VDD = 3 V, SCLK = 5 MHz, and the device is again in power-

down mode between conversions, the power dissipation during

normal operation is 4.2 mW. Assuming the same timing

conditions as before, the AD7910/AD7920 can now be said to

dissipate 4.2 mW for 6 μs during each conversion cycle. With a

throughput rate of 100 kSPS, the average power dissipated

during each cycle is (6/10) × (4.2 mW) = 2.52 mW. Figure 22

shows the power vs. throughput rate when using the power-

down mode between conversions with both 5 V and 3 V

supplies.

Power-down mode is intended for use with throughput rates of

approximately 160 kSPS and under because at higher sampling

rates there is no power saving made by using the power-down

mode.

THROUGHPUT RATE (kSPS)

100

0.1

POWER (mW)

0.01 20

= 5V, SCLK = 5MHz

= 3V, SCLK = 5MHz

40 60 80 100 120 140 160 180

02976-022

Figure 22. Power vs. Throughput Rate

AD7910/AD7920

Rev. C | Page 19 of 24

SERIAL INTERFACE

Figure 23 and Figure 24 show the detailed timing diagram for

serial interfacing to the AD7920 and AD7910, respectively. The

serial clock provides the conversion clock and also controls the

transfer of information from the AD7910/AD7920 during

conversion.

The CS signal initiates the data transfer and conversion process.

The falling edge of CS puts the track-and-hold into hold mode

and takes the bus out of three-state; the analog input is sampled

at that point. The conversion is also initiated at this point.

For the AD7920, the conversion requires 16 SCLK cycles to

complete. Once 13 SCLK falling edges have elapsed, track-and-

hold goes back into track on the next SCLK rising edge, as

shown in Figure 23 at Point B. On the 16th SCLK falling edge,

the SDATA line goes back into three-state. If the rising edge of

CS occurs before 16 SCLKs have elapsed then the conversion is

terminated and the SDATA line goes back into three-state;

otherwise, SDATA returns to three-state on the 16th SCLK

falling edge, as shown in Figure 23. Sixteen serial clock cycles

are required to perform the conversion process and to access

data from the AD7920.

For the AD7910, the conversion requires 14 SCLK cycles to

complete. Once 13 SCLK falling edges have elapsed, track-and-

hold goes back into track on the next SCLK rising edge, as

shown in Figure 24 at Point B.

If the rising edge of CS occurs before 14 SCLKs have elapsed, the

conversion is terminated and the SDATA line goes back into

three-state. If 16 SCLKs are used in the cycle, SDATA returns to

three-state on the 16th SCLK falling edge, as shown in Figure 24.

CS going low clocks out the first leading zero to be read in by

the microcontroller or DSP. The remaining data is then clocked

out by subsequent SCLK falling edges beginning with the

second leading zero. Thus, the first falling clock edge on the

serial clock has the first leading zero provided and also clocks

out the second leading zero. The final bit in the data transfer is

valid on the 16th falling edge, having been clocked out on the

previous (15th) falling edge.

In applications with a slower SCLK, it is possible to read in data on

each SCLK rising edge. In this case, the first falling edge of SCLK

clocks out the second leading zero, which could be read in the first

rising edge. However, the first leading zero that was clocked out

when CS went low is missed unless it was not read in the first

falling edge. The 15th falling edge of SCLK clocks out the last bit

and it could be read in the 15th rising SCLK edge.

If CS goes low just after the SCLK falling edge has elapsed, CS

clocks out the first leading zero as before, and it can be read on the

SCLK rising edge. The next SCLK falling edge clocks out the sec-

ond leading zero and it could be read on the following rising edge.

SCLK

DAT

CONVERT

QUIET

ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0

THREE-STATETHREE-

STATE

4 LEADING ZEROS

15141354321 16

1/THROUGHPUT

02976-023

Figure 23. AD7920 Serial Interface Timing Diagram

SCLK

DAT

CONVERT

QUIET

ZERO ZERO ZERO DB9 DB8 DB0 ZERO ZERO

THREE-STATETHREE-

STATE

4 LEADING ZEROS 2 TRAILING ZEROS

15141354321 16

1/THROUGHPUT

02976-024

Figure 24. AD7910 Serial Interface Timing Diagram

AD7910/AD7920

Rev. C | Page 20 of 24

MICROPROCESSOR INTERFACING

The serial interface on the AD7910/AD7920 allows the parts to

be directly connected to a range of different microprocessors.

This section explains how to interface the AD7910/AD7920

with some of the more common microcontroller and DSP serial

interface protocols.

AD7910/AD7920 TO TMS320C541 INTERFACE

The serial interface on the TMS320C541 uses a continuous serial

clock and frame synchronization signals to synchronize the data

transfer operations with peripheral devices like the

AD7910/AD7920. The CS input allows easy interfacing between

the TMS320C541 and the AD7910/AD7920 without any glue logic

required. The serial port of the TMS320C541 is set up to operate in

burst mode (FSM = 1 in the serial port control register, SPC) with

internal serial clock CLKX (MCM = 1 in SPC register) and internal

frame signal (TXM = 1 in the SPC), so both pins are configured as

outputs. For the AD7920, the word length should be set to 16 bits

(FO = 0 in the SPC register). This DSP allows frames with a word

length of 16 bits or 8 bits. Therefore, in the case of the AD7910

where just 14 bits could be required, the FO bit would be set up to

16 bits also. This means that to obtain the conversion result, 16

SCLKs are needed and two trailing zeros are clocked out in the two

last clock cycles.

To summarize, the values in the SPC register are:

FO = 0

FSM = 1

MCM = 1

TXM = 1

The format bit, FO, can be set to 1 to set the word length to

eight bits to implement the power-down mode on the

AD7910/AD7920.

Figure 25 shows the connection diagram. It should be noted

that for signal processing applications, it is imperative that the

frame synchronization signal from the TMS320C541 provides

equidistant sampling.

AD7910/AD7920*

SCLK

SDATA

CLKX

CLKR

FSX

FSR

TMS320C541*

*ADDITIONAL PINS OMITTED FOR CLARITY

02976-025

Figure 25. Interfacing to the TMS320C541

AD7910/AD7920 TO ADSP-218x

The ADSP-218x family of DSPs is interfaced directly to the

AD7910/AD7920 without any glue logic required. The SPORT

control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

ISCLK = 1, Internal Serial Clock

TFSR = RFSR = 1, Frame Every Word

IRFS = 0, Sets up RFS as an Input

ITFS = 1, Sets up TFS as an Output

SLEN = 1111, 16 Bits for the AD7920

SLEN = 1101, 14 Bits for the AD7910

To implement power-down mode, SLEN should be set to 0111

to issue an 8-bit SCLK burst. The connection diagram is shown

in Figure 26. The ADSP-218x has the TFS and RFS of the

SPORT tied together, with TFS set as an output and RFS set as

an input. The DSP operates in alternate framing mode and the

SPORT control register is set up as described. The frame

synchronization signal generated on the TFS is tied to CS and,

as with all signal processing applications, equidistant sampling

is necessary. However, in this example, the timer interrupt is

used to control the sampling rate of the ADC and, under certain

conditions, equidistant sampling can not be achieved.

AD7910/AD7920

SCLK

SDATA

SCLK

RFS

TFS

ADSP-218x*

02976-026

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 26. Interfacing to the ADSP-218x

The timer registers are loaded with a value that provides an

interrupt at the required sample interval. When an interrupt is

received, a value is transmitted with TFS/DT (ADC control

word). The TFS is used to control the RFS and thus the reading

of data. The frequency of the serial clock is set in the SCLKDIV

that is, TX0 = AX0, the state of the SCLK is checked. The DSP

waits until the SCLK has gone high, low, and high before

transmission starts. If the timer and SCLK values are chosen

such that the instruction to transmit occurs on or near the

rising edge of SCLK, the data can be transmitted or it can wait

until the next clock edge.

AD7910/AD7920

Rev. C | Page 21 of 24

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3, an

SCLK of 2 MHz is obtained and eight master clock periods

elapse for every one SCLK period. If the timer registers are

loaded with the value 803, 100.5 SCLKs occur between

interrupts and subsequently between transmit instructions. This

situation results in nonequidistant sampling as the transmit

instruction is occurring on an SCLK edge. If the number of

SCLKs between interrupts is a whole integer figure of N,

equidistant sampling is implemented by the DSP.

AD7910/AD7920 TO DSP563xx INTERFACE

The diagram in Figure 27 shows how the AD7910/AD7920 can

be connected to the synchronous serial interface (SSI)

(synchronous serial interface) of the DSP563xx family of DSPs

from Motorola. The SSI is operated in synchronous and normal

mode (SYN = 1 and MOD = 0 in Control Register B, CRB) with

internally generated word frame sync for both Tx and Rx (Bit

FSL1 = 0 and Bit FSL0 = 0 in the CRB). Set the word length in

the Control Register A (CRA) to 16 by setting Bits WL2 = 0,

WL1 = 1, and WL0 = 0 for the AD7920. This DSP does not

offer the option for a 14-bit word length, so the AD7910 word

length is set to 16 bits like the AD7920. For the AD7910, the

conversion process uses 16 SCLK cycles, with the last two clock

periods clocking out two trailing zeros to fill the 16-bit word.

To implement the power-down mode on the AD7910/AD7920,

the word length can be changed to eight bits by setting Bits

WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in the

CRB register can be set to 1, which means the frame goes low

and a conversion starts. Likewise, by means of Bits SCD2,

SCKD, and SHFD in the CRB register, it is established that Pin

SC2 (the frame sync signal) and SCK in the serial port is

configured as outputs and the MSB is shifted first.

To summarize:

MOD = 0

SYN = 1

WL2, WL1, WL0 Depend on the Word Length

FSL1 = 0, FSL0 = 0

FSP = 1, Negative Frame Sync

SCD2 = 1

SCKD = 1

SHFD = 0

It should be noted that for signal processing applications, it is

imperative that the frame synchronization signal from the

DSP563xx provides equidistant sampling.

AD7910/AD7920*

SDATA

SCLK

DSP563xx*

SCK

SRD

SC2

*ADDITIONAL PINS OMITTED FOR CLARITY

02976-027

Figure 27. Interfacing to the DSP563xx

AD7910/AD7920

Rev. C | Page 22 of 24

APPLICATION HINTS

GROUNDING AND LAYOUT

The printed circuit board that houses the AD7910/AD7920

should be designed such that the analog and digital sections are

separated and confined to certain areas of the board. This

facilitates the use of ground planes that can be easily separated.

A minimum etch technique is generally best for ground planes

as it gives the best shielding. Digital and analog ground planes

should be joined at only one place. If the AD7910/AD7920 is in

a system where multiple devices require an AGND to DGND

connection then the connection should still be made at one

point only, a star ground point that should be established as

close to the AD7910/AD7920 as possible.

Avoid running digital lines under the device as these couple

noise onto the die. The analog ground plane should be allowed

to run under the AD7910/AD7920 to avoid noise coupling. The

power supply lines to the AD7910/AD7920 should use as large a

trace as possible to provide low impedance paths and reduce the

effects of glitches on the power supply line. Fast switching

signals like clocks should be shielded with digital ground to

avoid radiating noise to other sections of the board, and clock

signals should never be run near the analog inputs. Avoid

crossover of digital and analog signals. Traces on opposite sides

of the board should run at right angles to each other. This

reduces the effects of feedthrough through the board. A micro-

strip technique is by far the best but is not always possible with

a double-sided board. In this technique, the component side of

the board is dedicated to ground planes while signals are placed

on the solder side.

Good decoupling is also very important. The supply should be

decoupled with, for example, a 680 nF 0805 to GND. When

using the SC70 package in applications where the size of the

components is of concern, a 220 nF 0603 capacitor, for example,

could be used instead. However, in that case, the decoupling can

not be as effective and can result in an approximate SINAD

degradation of 0.3 dB. To achieve the best performance from

these decoupling components, the user should endeavor to keep

the distance between the decoupling capacitor and the VDD and

GND pins to a minimum with short track lengths connecting

the respective pins. Figure 28 and Figure 29 show the

recommended positions of the decoupling capacitor for the

MSOP and SC70 packages, respectively.

As can be seen in Figure 28, for the MSOP package, the

decoupling capacitor is placed as close as possible to the IC,

with short track lengths to VDD and GND pins. The decoupling

capacitor could also be placed on the underside of the PCB

directly underneath the IC, between the VDD and GND pins

attached by vias. This method would not be recommended on

PCBs above a standard 1.6 mm thickness. The best performance

is seen with the decoupling capacitor on the top of the PCB next

to the IC.

02976-028

Figure 28. Recommended Supply Decoupling Scheme for the

AD7910/AD7920 MSOP Package

Similarly, for the SC70 package, the decoupling capacitor should

be located as close as possible to the VDD and GND pins.

Because of its pinout, that is, VDD being next to GND, the

decoupling capacitor can be placed extremely close to the IC.

The decoupling capacitor could be placed on the underside of

the PCB directly under the VDD and GND pins, but, as before,

the best performance is seen with the decoupling capacitor on

the same side as the IC.

02976-029

Figure 29. Recommended Supply Decoupling Scheme for the

AD7910/AD7920 SC70 Package

EVALUATING PERFORMANCE

The evaluation board package includes a fully assembled and

tested evaluation board, documentation, and software for

controlling the board from the PC via the Eval-Board

Controller. To demonstrate/evaluate the ac and dc performance

of the AD7910/AD7920, the evaluation board controller can be

used in conjunction with the AD7910/AD7920CB evaluation

boards as well as many other Analog Devices’ evaluation boards

ending in the CB designator.

The software allows the user to perform ac (fast Fourier

transform) and dc (histogram of codes) tests on the

AD7910/AD7920. See the evaluation board technical note for

more information.

AD7910/AD7920

Rev. C | Page 23 of 24

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-203-AB

0.22

0.08

0.30

0.15

1.00

0.90

0.70

SEATING

PLANE

4 5 6

3 2 1

PIN 1 0.65 BSC

1.30 BSC

0.10 MAX

0.10 COPLANARITY

0.40

0.10

1.10

0.80

2.20

2.00

1.80

2.40

2.10

1.80

1.35

1.25

1.15

0.46

0.36

0.26

Figure 30. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-6)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MO-187-AA

0.80

0.60

0.40

8°

0°

PIN 1 0.65 BSC

SEATING

PLANE

0.38

0.22

1.10 MAX

3.20

3.00

2.80

COPLANARITY

0.10

0.23

0.08

3.20

3.00

2.80

5.15

4.90

4.65

0.15

0.00

0.95

0.85

0.75

Figure 31. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

AD7910/AD7920

Rev. C | Page 24 of 24

registered trademarks are the property of their respective owners.

C02976-0-9/05(C)

ORDERING GUIDE

Model Temperature Range Linearity Error (LSB)1 Package Description Package Option Branding

AD7910AKS-500RL7 −40°C to +85°C ±0.5 max 6-Lead SC70 KS-6 CVA

AD7910AKS-REEL −40°C to +85°C ±0.5 max 6-Lead SC70 KS-6 CVA

AD7910AKS-REEL7 −40°C to +85°C ±0.5 max 6-Lead SC70 KS-6 CVA

AD7910AKSZ-500RL72−40°C to +85°C ±0.5 max 6-Lead SC70 KS-6 C49

AD7910AKSZ-REEL2−40°C to +85°C ±0.5 max 6-Lead SC70 KS-6 C49

AD7910AKSZ-REEL72−40°C to +85°C ±0.5 max 6-Lead SC70 KS-6 C49

AD7910ARM −40°C to +85°C ±0.5 max 8-Lead MSOP RM-8 CVA

AD7910ARM-REEL −40°C to +85°C ±0.5 max 8-Lead MSOP RM-8 CVA

AD7910ARM-REEL7 −40°C to +85°C ±0.5 max 8-Lead MSOP RM-8 CVA

AD7910ARMZ2 −40°C to +85°C ±0.5 max 8-Lead MSOP RM-8 C49

AD7920AKS-500RL7 −40°C to +85°C ±0.75 typ 6-Lead SC70 KS-6 CUA

AD7920AKS-REEL −40°C to +85°C ±0.75 typ 6-Lead SC70 KS-6 CUA

AD7920AKS-REEL7 −40°C to +85°C ±0.75 typ 6-Lead SC70 KS-6 CUA

AD7920AKSZ-500RL72−40°C to +85°C ±0.75 typ 6-Lead SC70 KS-6 C47

AD7920AKSZ-REEL72−40°C to +85°C ±0.75 typ 6-Lead SC70 KS-6 C47

AD7920BKS-500RL7 −40°C to +85°C ±1.5 max 6-Lead SC70 KS-6 CUB

AD7920BKS-REEL −40°C to +85°C ±1.5 max 6-Lead SC70 KS-6 CUB

AD7920BKS-REEL7 −40°C to +85°C ±1.5 max 6-Lead SC70 KS-6 CUB

AD7920BKSZ-500RL72−40°C to +85°C ±1.5 max 6-Lead SC70 KS-6 C4B

AD7920BKSZ-REEL2−40°C to +85°C ±1.5 max 6-Lead SC70 KS-6 C4B

AD7920BKSZ-REEL72−40°C to +85°C ±1.5 max 6-Lead SC70 KS-6 C4B

AD7920BRM −40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CUB

AD7920BRM-REEL −40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CUB

AD7920BRM-REEL7 −40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CUB

AD7920BRMZ2−40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 C4B

AD7920BRMZ-REEL2−40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 C4B

AD7920BRMZ-REEL72−40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 C4B

EVAL-AD7910CB3 Evaluation Board

EVAL-AD7920CB3 Evaluation Board

EVAL-CONTROL BRD24 Controller Board

1 Linearity error refers to integral nonlinearity.

2 Z = Pb-free part.

3 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.

4 This board is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a

complete evaluation kit, a particular ADC evaluation board must be ordered, for example., EVAL-AD7920CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See

relevant evaluation board technical note for more information.