TC58NVG2S0FTAI0
2012-09-01
1
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
4 GBIT (512M × 8 BIT) CMOS NAND E2PROM
DESCRIPTION
The TC58NVG2S0F is a single 3.3V 4 Gbit (4,529,848,320 bits) NAND Electrically Erasable and Progr ammabl e
Read-Only Memory (NAND E2PROM) organized as (4096 + 224) bytes × 64 pages × 2048blocks.
The device has two 4320-byte static registers whic h allow program and read data to be transferred between the
register and the memory cell ar ray in 4320-byte increments. The Erase operation is implemented in a single block
unit (256 Kbytes + 14 Kbytes: 4320 bytes × 64 page s).
The TC58NVG2S0F is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other sy stems which requir e hig h-density non-volatile memory data stor age.
FEATURES
• Organization
x8
Memory cell array 4320 × 128K × 8
Register 4320 × 8
Page size 4320 bytes
Block size (256K + 14K) bytes
• Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
• Mode control
Serial input/output
Command control
• Number of valid blocks
Min 2008 blocks
Max 2048 blocks
• Power supply
VCC = 2.7V to 3.6V
• Access time
Cell array to register 30 µs max
Serial Read Cycle 25 ns min (CL=100pF)
• Program/Erase time
Auto Page Program 300 µs/page typ.
Auto Block Erase 3 ms/block typ.
• Operating current
Read (25 ns cycle) 30 mA max.
Program (avg.) 30 mA max
Erase (avg.) 30 mA max
Standby 50 µA max
• Package
TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.)
• 4bit ECC for each 512Byte is required.
TC58NVG2S0FTAI0
2012-09-01
2
PIN ASSIGNMENT (TOP VIEW)
PINNAMES
I/O1 to I/O8 I/O port
CE Chip enable
WE Write enable
RE Read enable
CLE Command latch enable
ALE Address latch enable
WP Write protect
BY/RY Ready/Busy
VCC Power supply
VSS Ground
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
NC
NC
VCC
VSS
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
NC
NC
NC
NC
NC
NC
BY/RY
RE
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
×8×8
TC58NVG2S0FTAI0
TC58NVG2S0FTAI0
2012-09-01
3
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VCC Power Supply Voltage −0.6 to 4.6 V
VIN Input Voltage −0.6 to 4.6 V
VI/O Input /Output Voltage −0.6 to VCC + 0.3 (≤ 4.6 V) V
PD Power Dissipation 0.3 W
TSOLDER Soldering Temperature (10 s) 260 °C
TSTG Storage Temperature −55 to 150 °C
TOPR Operating Temperature -40 to 85 °C
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMB0L PARAMETER CONDITION MIN MAX UNIT
CIN Input VIN = 0 V ⎯ 10 pF
COUT Output VOUT = 0 V ⎯ 10 pF
* This parameter is periodically sampled and is not tested for every device.
I/O
Control circuit
Status register
Command register
Column buffer
Column decoder
Data register
Sense amp
Memory cell array
Control circuit
HV generator
Row address decoder
Logic control
BY/RY
VCC
I/O1
VSS
I/O8
CE
CLE
ALE
WE
RE
BY/RY
Row address buffer
decoder
to
WP
Address register
TC58NVG2S0FTAI0
2012-09-01
4
VALID BLOCKS
SYMBOL PARAMETER MIN TYP. MAX UNIT
NVB Number of Valid Blocks 2008 ⎯ 2048 Blocks
NOTE: The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime
The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane
operations.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL PARAMETER MIN TYP. MAX UNIT
VCC Power Supply Voltage 2.7 ⎯ 3.6 V
VIH High Level input Voltage 2.7 V ≤ VCC ≤ 3.6 V Vcc x 0.8 ⎯ V
CC + 0.3 V
VIL Low Level Input Voltage 2.7 V ≤ VCC ≤ 3.6 V −0.3* ⎯ Vcc x 0.2 V
* −2 V (pulse width lower than 20 ns)
DC CHARACTERISTICS (Ta = -40 to 85℃, VCC = 2.7 to 3.6V)
SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT
IIL Input Leakage Current VIN = 0 V to VCC ⎯ ⎯ ±10 µA
ILO Output Leakage Current VOUT = 0 V to VCC ⎯ ⎯ ±10 µA
ICCO1 Serial Read Current CE = VIL, IOUT = 0 mA, tcycle = 25 ns ⎯ ⎯ 30 mA
ICCO2 Programming Current ⎯ ⎯ ⎯ 30 mA
ICCO3 Erasing Current ⎯ ⎯ ⎯ 30 mA
ICCS Standby Current CE = VCC − 0.2 V, WP = 0 V/VCC ⎯ ⎯ 50 µA
VOH High Level Output Voltage IOH = −0.4 mA Vcc – 0.2 ⎯ ⎯ V
VOL Low Level Output Voltage IOL = 2.1 mA ⎯ ⎯ 0.2 V
IOL
(BY/RY ) Output current of BY/RY
pin VOL = 0.4 V ⎯ 4 ⎯ mA
TC58NVG2S0FTAI0
2012-09-01
5
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = -40 to 85℃, VCC = 2.7 to 3.6V)
SYMBOL PARAMETER MIN MAX UNIT
tCLS CLE Setup Time 12 ⎯ ns
tCLH CLE Hold Time 5 ⎯ ns
tCS CE Setup Time 20 ⎯ ns
tCH CE Hold Time 5 ⎯ ns
tWP Write Pulse Width 12 ⎯ ns
tALS ALE Setup Time 12 ⎯ ns
tALH ALE Hold Time 5 ⎯ ns
tDS Data Setup Time 12 ⎯ ns
tDH Data Hold Time 5 ⎯ ns
tWC Write Cycle Time 25 ⎯ ns
tWH WE High Hold Time 10 ⎯ ns
tWW WP High to WE Low 100 ⎯ ns
tRR Ready to RE Falling Edge 20 ⎯ ns
tRW Ready to WE Falling Edge 20 ⎯ ns
tRP Read Pulse Width 12 ⎯ ns
tRC Read Cycle Time 25 ⎯ ns
tREA RE Access Time ⎯ 20 ns
tCEA CE Access Time ⎯ 25 ns
tCLR CLE Low to RE Low 10 ⎯ ns
tAR ALE Low to RE Low 10 ⎯ ns
tRHOH RE High to Output Hold Time 25 ⎯ ns
tRLOH RE Low to Output Hold Time 5 ⎯ ns
tRHZ RE High to Output High Impedance ⎯ 60 ns
tCHZ CE High to Output High Impedance ⎯ 20 ns
tCSD CE High to ALE or CLE Don’t Care 0 ⎯ ns
tREH RE High Hold Time 10 ⎯ ns
tIR Output-High-impedance-to-RE Falling Edge 0 ⎯ ns
tRHW RE High to WE Low 60 ⎯ ns
tWHC WE High to CE Low 30 ⎯ ns
tWHR WE High to RE Low 60 ⎯ ns
tR Memory Cell Array to Starting Address ⎯ 30 µs
tDCBSYR1 Data Cache Busy in Read Cache (following 31h and 3Fh) ⎯ 30 µs
tDCBSYR2 Data Cache Busy in Page Copy (following 3Ah) ⎯ 35 µs
tWB WE High to Busy ⎯ 100 ns
tRST Device Reset Time (Ready/Read/Program/Erase) ⎯ 10/10/30/500 µs
*1: tCLS and tALS can not be shorter than tW P
*2: tCS should be longer than tWP + 8ns.
TC58NVG2S0FTAI0
2012-09-01
6
AC TEST CONDITIONS
CONDITION
PARAMETER VCC: 2.7 to 3.6V
Input level 0V to Vcc
Input pulse rise and fall time 3 ns
Input comparison level Vcc / 2
Output data comparison level Vcc / 2
Output load CL (100 pF) + 1 TTL
Note: Busy to ready time depends on the pull-up resistor tied to the BY/RY pin.
(Refer to Application Note (9) toward the end of this document.)
PROGRAMMING AND ERASING CHARACTE RISTICS
(Ta = -40 to 85℃, VCC = 2.7 to 3.6V)
SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES
tPROG Average Programming Time ⎯ 300 700 µs
tDCBSYW1 Data Cache Busy Time in Write Cache (following 11h) ⎯ 0.5 1 µs
tDCBSYW2 Data Cache Busy Time in Write Cache (following 15h) ⎯ ⎯ 700 µs (2)
N Number of Partial Program Cycles in the Same Page ⎯ ⎯ 4 (1)
tBERASE Block Erasing Time ⎯ 3 10 ms
(1) Refer to Application Note (12) toward the end of this document.
(2) tDCBSYW2 depends on the timing between internal programming time and data in time.
Data Output
When tREH is long, output buffer s are disabled by /RE=High, and the hold time of da ta output depend on tRHOH
(25ns MIN). On this condition, waveforms look like normal serial read mode.
When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend on
tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE,ALE,/CE or falling
edge of /WE, and waveforms look like Extended Data Output Mode.
TC58NVG2S0FTAI0
2012-09-01
7
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address/Data
Command Input Cycle Timing Diagram
CLE
ALE
CE
RE
WE
Hold T ime
tDH
Setup T ime
tDS
I/O
: VIH or VIL
tCS
tDH
tDS
tALS tALH
tWP
tCLS tCH
tCLH
: VIH or VIL
CE
CLE
WE
ALE
I/O
TC58NVG2S0FTAI0
2012-09-01
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Address Input Cycle Timing Diagram
Data Input Cycle Timing Diagram
WE
tWP
tWP
tWH
tWP
tALS
tWC
tDH
tDS
DIN0 DIN1
tCLH
tCH
ALE
CLE
CE
I/O DIN4319*
tDH
tDS tDH
tDS
tCS
tCLS
tCH tCS
tALH
PA16
PA8 to 15
CA8 to 12
: VIH or VIL
tDH
tDS
tCLS
CLE
tALS tALH
tWP
tWH
tWP
CA0 to 7
tDH
tDS
tCS tCS
CE
WE
ALE
I/O
tDH
tDS
tWP
tWH
tDH
tDS
tWP
tWH
tWC
tDH
tDS
tWP
tWH
tWC
PA0 to 7
tCLH
tCH
tCH
TC58NVG2S0FTAI0
2012-09-01
9
Serial Read Cycle Timing Diagram
Status Read Cycle Timing Diagram
tREH tCHZ
CE
tRHZ
tREA
tRC
tRR
tRHZ
tREA
tRHZ
tREA
RE
BY/RY
I/O
tRHOH tRHOH tRHOH
tRP
tRP tRP
: VIH or VIL
tCEA tCEA
: VIH or VIL
*: 70h represents the hexadecimal number
tWHR
WE
tDH
tDS
tCLS
tCLR
tCS
tCLH
tCH
tWP
Status
output
70h*
tWHC
tIR
tREA tRHZ
tCHZ
CE
CLE
RE
BY/RY
I/O
tRHOH
tCEA
TC58NVG2S0FTAI0
2012-09-01
10
Read Cycle Timing Diagram
Read Cycle Timing Diagram: When Interrupted by
CE
30h
PA16
PA8
to 15
PA0
to 7
CA8
to 12
CA0
to 7
I/O
tCS
tCLS tCLH
tCH
tDH
tDS
tWC
tALS
tALH
WE
CLE
CE
ALE
RE
tDH
tDS
tDH
tDS
tDH
tDS tDH
tDS
tALH
tCLR
tR
tDH
tDS
tWB
tCS
tCLS tCLH
tCH
tALS
tRC
tRR
tREA
Col. Add. N Data out from
Col. Add. N
tDH
tDS
00h DOUT
N DOUT
N + 1
BY/RY
tCEA
30h
PA16
PA8
to 15
PA0
to 7
CA8
to 12
CA0
to 7
I/O
tCS
tCLS tCLH
tCH
tDH
tDS
tWC
tALS
tALH
WE
CLE
CE
ALE
RE
tDH
tDS
tDH
tDS
tDH
tDS tDH
tDS
tALH
tCLR
tR
tDH
tDS
tWB
tCS
tCLS tCLH
tCH
tALS
tRC
tRR
tREA
Col. Add. N
tDH
tDS
00h DOUT
N DOUT
N + 1
BY/RY
tCHZ
tRHZ
tRHOH
Col. Add. N
tCSD
tCEA
TC58NVG2S0FTAI0
2012-09-01
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Read Cycle with Data Cache Timing Diagram (1/2)
30h
PA16
PA8
to 15
PA0
to 7
CA8
to 12
CA0
to 7
I/O
tDH
tDS
tWC
tALS
tALH
WE
CLE
CE
ALE
RE
tDH
tDS
tDH
tDS
tDH
tDS tDH
tDS
tALH
tR
tDH
tDS
tWB
tALS
tRC
tRR tREA
Column address
N *
tDH
tDS
00h DOUT
0 DOUT
1
BY/RY
tCEA
Page address M
DOUT
31h
tDH
tDS
tWB
tDCBSYR1
31h
tDH
tDS
tWB
DOUT
0
tRR tREA
tDCBSYR1
tCLR tCLR
tCEA
Page address
M
Col. Add. 0 Col. Add. 0
Page address
M + 1
tRW
tCS
tCLS tCLH
tCH
1
Continues to of next page
1
* The column address will be reset to 0 by the 31h command input.
tCS
tCLS tCLH
tCH tCS
tCLS tCLH
tCH tCS
tCLS tCLH
tCH
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Read Cycle with Data Cache Timing Diagram (2/2)
Continues from of last page
1
I/O
WE
CLE
CE
ALE
RE
BY/RY
DOUT
tCLR
tWB
31h
tDH
tDS
tWB
31h
tDH
tDS
tRC
tRR tREA
Page address M + 1 Page address M + x
tCLR
tWB
tRC
tRR tREA
tCEA
3Fh
tDH
tDS
DOUT
0 DOUT
1 DOUT
tRC
tRR tREA
tCEA
Page address
M + 2
tDCBSYR1 tDCBSYR1 tDCBSYR1
tCLR
Col. Add. 0 Col. Add. 0 Col. Add. 0
tCEA
DOUT
0 DOUT
1 DOUT
DOUT
0 DOUT
1 DOUT
1
tCS
tCLS tCLH
tCH tCS
tCLS tCLH
tCH tCS
tCLS tCLH
tCH
Make sure to terminate the operation with 3Fh command.
TC58NVG2S0FTAI0
2012-09-01
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Column Address Change in Read Cycle Timing Diagram (1/2)
tCLR
I/O
tCS
tCLS tCLH
tCH
tWC
tALS
tALH
tR
CLE
CE
ALE
RE
tDH
tDS
tDH
tDS
tALH
tWB
tCS
tCLS tCLH
tCH
tALS
tRC
tREA
tCEA
tRR
Page address
P Page address
P
Column address
A
00h CA0
to 7
tDH
tDS
CA8
to 12
tDH
tDS
PA0
to 7
tDH
tDS
PA8
to 15
tDH
tDS
PA16
tDH
tDS
30h DOUT
A DOUT
A + 1 DOUT
A + N
WE
1
Continues from of next page
1
BY/RY
TC58NVG2S0FTAI0
2012-09-01
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Column Address Change in Read Cycle Timing Diagram (2/2)
I/O
tCS
tCLS tCLH
tCH
05h CA0
to 7 CA8
to 12
tWC
tALS
tALH
CLE
CE
ALE
RE
tDH
tDS
tDH
tDS
tDH
tDS
Column address
B
E0h
tDH
tDS
tALH
tCS
tCLS tCLH
tCH
tALS
tREA
DOUT
A + N
tRHW
Page address
P
Column address
B
tRC
tCLR
tCEA
tIR DOUT
B + N’
DOUT
B + 1
DOUT
B
1
Continues from of last page
1
WE
BY/RY
tWHR
TC58NVG2S0FTAI0
2012-09-01
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Data Output Timing Diagram
CommandI/O
tRC
tDH
tRP
tRP
WE
CLE
CE
ALE
RE
tRLOH
tREH
tREA
tRHZ
tREA
tCS
tCLS tCLH
tCH
tRP
tRR
tREA tRLOH tDS
BY/RY
tCHZ
tRHOH
tRHOH
tCEA
DoutDout
tALH
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Auto-Program Operation Timing Diagram
CA0
to 7
tCLS
tCLS
tALS
tDS tDH
WE
CLE
CE
ALE
RE
BY/RY
: VIH or VIL
tCLH
tCH
tCS
tDS tDH
tALH
I/O
: Do not input data while data is being output.
tCS
tDH
tDS
tDH
tPROG
tWB
tDS
tALH
tALS
*) M: up to 4319 (byte input data for ×8 device).
Column address
N
CA8
to 12 DINNDINM10h 70h Status
output
PA0
to 7 PA8
to 15 PA16
80h DIN
N+1
TC58NVG2S0FTAI0
2012-09-01
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Auto-Program Operation with Data Cache Timing Diagram (1/3)
tCLS
tALS
tDS tDH
80h
WE
CLE
CE
ALE
RE
BY/RY
: VIH or VIL
tCLH
tCH
tCS
tCLS
tDS tDH
tALH
I/O
: Do not input data while data is being output.
tCS
tDH
tDS tDH
tDCBSYW2
DINNDIN
N+1
tWB
80h
tDS
15h
tALH
tALS
DIN4319
1
Continues to 1 of next page
PA16
CA0 to CA12 is 0 in this diagram.
CA0
to 7
CA0
to 7 CA8
to 12 PA0
to 7 PA8
to 15
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2012-09-01
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Auto-Program Operation with Data Cache Timing Diagram (2/3)
tCLS
tALS
tDS tDH
CA0
to 7
80h
WE
CLE
CE
ALE
RE
BY/RY
tCLH
tCH
tCS
tCLS
tDS tDH
tALH
I/O
: VIH or VIL
: Do not input data while data is being output.
PA0
to 7
CA8
to 12
tCS
1
Continued from 1 of last page
tDH
tDStDH
tDCBSYW2
DINNDIN
N+1
tWB
80h
tDS
15h
tALH tALS
DIN4319
PA16
2
PA8
to 15
CA0
to 7
Repeat a max of 62 times (in order to program pages 1 to 62 of a block).
TC58NVG2S0FTAI0
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Auto-Program Operation with Data Cache Timing Diagram (3/3)
(Note) Make sure to terminate the operation with 80h-10h - command sequence.
If the operation is terminated by 80h-15h command sequenc e, monitor I/O 6 (Ready / Busy) by
issuing Status Read c o mman d (70h) and make sure the previous page program operation is
completed. If the page program operation i s c ompleted issue FFh reset before next operation.
70h
tCLS
tALS
tDS tDH
WE
CLE
CE
ALE
RE
BY/RY
: VIH or VIL
tCLH
tCH
tCS
tCLS
tDS tDH
tALH
I/O
: Do not input data while data is being output.
tCS
2
tDH
tDS tDH
tPROG (*1)
tWB
tDS
tALHtALS
DIN4319
Continued from 2 of last page
(*1) tPROG: Since the last page programming by 10h command is initiated after the previous cache
program, the tPROG during cache programming is given by the following equation.
tPROG = tPROG of the last page + tPROG of the previous page − A
A
= (command input cycle + address input cycle + data input cycle time of the last page)
If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.
80h CA0
to 7 CA8
to 12 PA0
to 7 PA8
to 15 PA16 DINNDIN
N
+
1
10h Status
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Multi-Page Program Operation with Data Cache Timing Diagram (1/4)
Continues to 1 of next page
tCLS
tALS
tDS tDH
80h
WE
CLE
CE
ALE
RE
BY/RY
: VIH or VIL
tCLH
tCH
tCS
tCLS
tDS tDH
tALH
I/O
: Do not input data while data is being output.
tCS
tDH
tDS tDH
tDCBSYW1
DINNDIN
N+1
tWB
81h
tDS
11h
tALHtALS
DIN4319
1
PA16 CA0
to 7
CA0
to 7 CA8
to 12 PA0
to 7 PA8
to 15
Page Address M
District-0
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Multi-Page Program Operation with Data Cache Timing Diagram (2/4)
: VIH or VIL
: Do not input data while data is being output.
tCLS
tALS
tDS tDH
CA0
to 7
81h
WE
CLE
CE
ALE
RE
BY/RY
tCLH
tCH
tCS
tCLS
tDS tDH
tALH
I/O PA0
to 7
CA8
to 12
tCS
1
Continued from 1 of last page
tDH
tDStDH
tDCBSYW2
DINNDIN
N+1
tWB
80h
tDS
15h
tALH
tALS
DIN4319
PA16
2
PA8
to 15 CA0
to 7
Repeat a max of 63 times (in order to program pages 0 to 62 of a block).
Page Address M
District-1
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Multi-Page Program Operation with Data Cache Timing Diagram (3/4)
I/O
tCLS
tALS
tDS tDH
80h
WE
CLE
CE
ALE
RE
BY/RY
: VIH or VIL
tCLH
tCH
tCS
tCLS
tDS tDH
tALH
: Do not input data while data is being output.
tCS
tDH
tDS tDH
tDCBSYW1
DINNDIN
N+1
tWB
81h
tDS
11h
tALH tALS
DIN4319
3
Continues to 3 of next page
PA16 CA0
to 7
CA0
to 7 CA8
to 12 PA0
to 7 PA8
to 15
Page Address M+n
District-0
2
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Multi-Page Program Operation with Data Cache Timing Diagram (4/4)
(Note) Make sure to terminate the operation with 80h-10h- command sequence.
If the operation is terminated by 81h-15h command sequence, monitor I/O 6 (Ready / Busy) by issuing Status
Read command (70h) and make sure the previous page program operatio n is completed. If the page program
operation is completed issue F Fh reset before next operation.
(*1) tPROG: Since the last page programming by 10h command is initiated after the previous cache
program, the tPROG during cache programming is given by the following equation.
tPROG = tPROG of the last page + tPROG of the previous page − A
A
= (command input cycle + address input cycle + data input cycle time of the last page)
If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.
71h
tCLS
tALS
tDS tDH
WE
CLE
CE
ALE
RE
BY/RY
: VIH or VIL
tCLH
tCH
tCS
tCLS
tDS tDH
tALH
I/O
: Do not input data while data is being output.
tCS
3
tDH
tDS tDH
tPROG (*1)
tWB
tDS
tALHtALS
DIN4319
Continued from 3 of last page
81h CA0
to 7 CA8
to 12 PA0
to 7 PA8
to 15 PA16 DIN
N
+
1
10h StatusDINN
Page Address M+n
District-1
TC58NVG2S0FTAI0
2012-09-01
24
Auto Block Erase Timing Diagram
tCS
60h PA8
to 15
WE
CLE
CE
ALE
RE
BY/RY
: VIH or VIL
tCLS tCLH
tCLS
PA0
to 7
tDS tDH
tALS
: Do not input data while data is being output.
Auto Block
Erase Setup
command
I/O D0h 70h
tWB tBERASE
Busy Status Read
command
Erase Start
command
Status
output
tALH
PA16
TC58NVG2S0FTAI0
2012-09-01
25
Multi Block Erase Timing Diagram
60h PA8
to 15
WE
CLE
CE
ALE
RE
BY/RY
: VIH or VIL
tCS
tCLS tCLH
tCLS
PA0
to 7
tDS tDH
tALS
: Do not input data while data is being output.
D0h 71h
tWB tBERASE
Busy Status Read
command
Auto Block
Erase Setup
command
I/O1
to Status
output
tALH
Repeat 2 times (District-0,1)
PA16
TC58NVG2S0FTAI0
2012-09-01
26
Copy Back Program with Random Data Input
WE
CLE
RE
I/Ox
ALE
CE
tWC
tWB
R/B
Col
Add1
00h 35h 85h
Col
Add2 Row
Add1 Row
Add2 Row
Add3 Col
Add1 Col
Add2 Row
Add1 Data1 DataN 10h 70h I/O
Row
Add2 Row
Add3
tR
Busy Busy
tWB
tPROG
tWHR
Copy Back Program Data
Input Command I/O1=0 Successful Program
I/O1=1 Error in Program
Read Status command
Column Addre ss Row Address Column Addre ss Row Address
TC58NVG2S0FTAI0
2012-09-01
27
ID Read Operation Timing Diagram
: VIH or VIL
WE
CLE
RE
tCEA
CE
ALE
I/O
tAR
ID Read
command Address
00 Maker code Device code
tREA
tCLS
tCS
tDS
tCH
tALH tALS
tCLS
tCS tCH
tALH
tDH
90h 00h 98h
tREA
DCh
tREA tREA
See
Table 5 See
Table 5
tREA
See
Table 5
TC58NVG2S0FTAI0
2012-09-01
28
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the operation mode command into the internal command
register. The command is latched into the command register from the I/O port on the rising edge of the WE
signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading address information into the internal address register. Address
information is latched into the address register from the I/O port on the rising edge of WE while ALE is High.
Chip Enable:
The device goes into a low-power Standby mode when CE goes High during the device is in Ready state. The
CE signal is ignored when device is in Busy state ( BY/RY = L), such as during a Program or Erase or Read
operation, and will not enter Standby mode even if the CE input goes High.
Write Enable:
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable:
The RE signal controls serial data output. Data is available tREA after the falling edge of RE .
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
the device.
Write Protect:
TheWP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy:
The BY/RY output signal is used to indicate the operating condition of the device. The BY/RY signal is
in Busy state ( BY/RY = L) during the Program, Erase and Read operations and will return to Ready state
(BY/RY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be
pulled-up to Vccq with an appropriate resister.
CE
WE
RE
WP
BY/RY
TC58NVG2S0FTAI0
2012-09-01
29
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
A page consists of 4320 bytes in which 4096 bytes are
used for main memory storage and 224 by tes ar e for
redundancy or for other uses.
1 page = 4320bytes
1 block = 4320 bytes × 64 pages = (256K + 14K) bytes
Capacity = 4320 bytes × 64pages × 2048 blocks
An address is read in via the I/O port over five
consecutive clock cycles, as shown in Table 1.
Table 1. Addressing
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
First cycle CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
Second cycle L L L CA12 CA11 CA10 CA9 CA8
Third cycle PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
CA0 to CA12: Column address
PA0 to PA16: Page address
PA6 to PA16: Block address
PA0 to PA5: NAND address in block
Fourth cycle PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8
Fifth cycle L L L L L L L PA16
4320
131072
pages
2048 blocks
4096
4096
224
224 Page Buffe
r
Data Cache I/O8
I/O1
64 Pages=1 block
8I/O
TC58NVG2S0FTAI0
2012-09-01
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Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by command operations shown
in Table 3. Address inpu t, command input and data input/output are controlled by the CLE, ALE, CE, WE ,
RE and WP signals, as shown in Table 2.
Table 2. Logic Table
CLE ALE
CE WE RE WP *1
Command Input H L L H *
Data Input L L L H H
Address input L H L H *
Serial Data Output L L L H *
During Program (Busy) * * * * * H
During Erase (Busy) * * * * * H
* * H * * *
During Read (Busy) * * L H (*2) H (*2) *
Program, Erase Inhibit * * * * * L
Standby * * H * * 0 V/VCC
H: VIH, L: VIL, *: VIH or VIL
*1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit
*2: If CE is low during read busy, WE and RE must be held High to avoid unintended command/address input to the device or
read to device. Reset or Status Read command can be input during Read Busy.
TC58NVG2S0FTAI0
2012-09-01
31
Table 3. Command table (HEX)
First Set Second Set Acceptable while Busy
Serial Data Input 80 ⎯
Read 00 30
Column Address Change in Serial Data Output 05 E0
Read with Data Cache 31 ⎯
Read Start for Last Page in Read Cycle with Data Cache 3F ⎯
Auto Page Program 80 10
Column Address Change in Serial Data Input 85 ⎯
Auto Program with Data Cache 80 15
80 11
81 15
Multi Page Program
81 10
Read for Page Copy (2) with Data Out 00 3A
Read for Copy-Back without Data Out 00 35
Copy-Back Program without Data Out 85 10
Auto Program with Data Cache during Page Copy (2) 8C 15
Auto Program for last page during Page Copy (2) 8C 10
Auto Block Erase 60 D0
Page Program with 2KB Data 80 – 11 80 - 10
Copy-Back Program with 2KB Data 85 - 11 85 - 10
ID Read 90 ⎯
Status Read 70 ⎯ {
Status Read for Multi-Page Program or Multi Block Erase 71 ⎯ {
Reset FF ⎯ {
Table 4. Read mode operation states
CLE ALE
CE WE RE I/O1 to I/O8 Power
Output select L L L H L Data output Active
Output Deselect L L L H H High impedance Active
H: VIH, L: VIL
HEX data bit assignment
(Example)
10000000
8765432I/O1
Serial Data Input: 80h
TC58NVG2S0FTAI0
2012-09-01
32
DEVICE OPERATION
Read Mode
Read mode is set when the "00h" and “30h” commands are issued to th e Command register. Between the two
commands, a start address for the Read mode needs to be issued. After initial power on sequence, “00h”
command is latched into the internal command register. Therefore read operation after power on sequence is
excuted by the setting of only five address cycles and “30h” command. Refer to the figures below for the
sequence and the block diagram (Refer to the detailed timing chart.).
Random Column Address Change in Read Cycle
BY/RY
WE
CLE
RE
00h
CE
ALE
I/O
Busy
30h
Page Address N
Column Address M
M M+1 M+2
Page Address N
tR
Start-address input A data transfer operation from the cell array to the Data
Cache via Page Buffer starts on the rising edge of WE in the
30h command input cycle (after the address information has
been latched). The device will be in the Busy state during this
transfer period.
After the transfer period, the device returns to Ready state.
Serial data can be output synchronously with the RE clock
from the start address designated in the address input cycle.
Cell array
Select page
N
M m
Data Cache
Page Buffer
I/O1 to 8: m = 4319
Start-address input
Select page
N
M
BY/RY
WE
CLE
00h
CE
ALE
I/O
Col. M Page N
M’
Busy
Page N
30h 05h E0h
Col. M’
MM+1M’ M’+1 M’+2M’+3M’+4
Page N
Col. M
Start from Col. M Start from Col. M’
During the serial data output from the Data Cache, the column
address can be changed by inputting a new column address
using the 05h and E0h commands. The data is read out in serial
starting at the new column address. Random Column Address
Change operation can be done multiple times within the same
page.
tR
M+2M+3
RE
TC58NVG2S0FTAI0
2012-09-01
33
Read Operation with Read Cache
The device has a Read operation with Data Cache that enables the high speed read operation shown below. When the block address changes, this sequence has to be
started from the beginning.
Page N + 2
If the 31h command is issued to the device, the data content of the next page is transferred to the Page Buffer during serial data out from the Data Cache, and therefore the tR (Data transfer from memory
cell to data register) will be reduced.
1 Normal read. Data is transferred from Page N to Data Cache through Page Buffer. During this time period, the device outputs Busy state for tR max.
2 After the Ready/Busy returns to Ready, 31h command is issued and data is transferred to Data Cache from Page Buffer again. This data transfer takes tDCBSYR1 max and the completion of this time
period can be detected by Ready/Busy signal.
3 Data of Page N + 1 is transferred to Page Buffer from cell while the data of Page N in Data cache can be read out by /RE clock simultaneously.
4 The 31h command makes data of Page N + 1 transfer to Data Cache from Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max..
This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time.
5 Data of Page N + 2 is transferred to Page Buffer from cell while the data of Page N + 1 in Data cache can be read out by /RE clock simultaneously
6 The 3Fh command makes the data of Page N + 2 transfer to the Data Cache from the Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for
tDCBSYR1 max.. This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time.
7 Data of Page N + 2 in Data Cache can be read out, but since the 3Fh command does not transfer the data from the memory cell to Page Buffer, the device can accept new command input immediately
after the completion of serial data out.
BY/RY
WE
CLE
00h
CE
ALE
I/O
tR
30h
Col. M Page N
0123
31h 31h 0 123
Page Address N
Column 0
4319
Page Address N + 1
4319 0 123
Page Address N + 2
4319
3Fh
Data Cache
Page Buffer
Cell Array 1
2
3
34
5
5
1
67
Page N
Page N
Page N + 1
Page N
30h 31h & RE clock
Page N + 1
Page N + 2
Page N + 1
31h & RE clock
Page N + 2
3Fh & RE clock
1 24
3 5 67
tDCBSYR1 t
DCBSYR1 t
DCBSYR1
RE
TC58NVG2S0FTAI0
2012-09-01
34
Multi Page Read Operation
The device has a Multi Page Read operation and Multi Page Read with Data Cache operation..
(1) Multi Page Read without Data Cache
The sequence of command and address input is shown below.
Same page address (PA0 to PA5) within each district has to be selected.
The data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising
edge of WE in the 30h command input cycle (after the 2 Districts address information has been
latched). The device will be in the Busy state during this transfer period.
After the transfer period, the device returns to Ready state. Serial data can be output synchronously
with the RE clock from the start address designated in the address input cycle.
Selected
page
Reading
District 0 District 1
Selected
page
BY/RY
60
Command
input
Page Address
PA0 to PA16
(District 0) tR
Address input 60
Page Address
PA0 to PA16
(District 1)
Address input 30 A
A
BY/RY
00
Command
input
Column + Page Address
CA0 to CA12, PA0 to PA16
(District 0)
Address input 05
Column Address
CA0 to CA12
(District 0)
Address input E0 B
B
A
A
Data output
BY/RY
00
Command
input
Column + Page Address
CA0 to CA12, PA0 to PA16
(District 1)
Address input 05
Column Address
CA0 to CA12
(District 1)
Address input E0
B
B
Data output
(District 0)
(District 1)
(3 cycle) (3 cycle)
(5 cycle)
(5 cycle)
(2 cycle)
TC58NVG2S0FTAI0
2012-09-01
35
(2) Multi Page Read with Data Cache
When the block address chan ges (increments) this seque nced has to be started from the beginning.
The sequence of command and address input is shown below.
Same page address (PA0 to PA5) within each district has to be selected.
BY/RY
60
Command
input
Page Address
PA0 to PA16
(Page m0 ; District 0) tR
Address input 60
Page Address
PA0 to PA16
(Page n0 ; District 1)
Address input 30 A
A
BY/RY
00
Command
input
Column + Page Address
CA0 to CA12, PA0 to PA16
(Page m0 ; District 0)
Address input 05
Column Address
CA0 to CA12
(District 0)
Address input E0 B
A
A
Data output
BY/RY
00
Command
input
Column + Page Address
CA0 to CA12, PA0 to PA16
(Page n0 ; District 1)
Address input 05
Column Address
CA0 to CA12
(District 1)
Address input E0
B
B
Data output
(District 0)
(District 1)
31
C
C
BY/RY
00
Command
input
Column + Page Address
CA0 to CA12, PA0 to PA16
(Page m63 ; District 0)
Address input 05
Column Address
CA0 to CA12
(District 0)
Address input E0 D
C
C
Data output
BY/RY
00
Command
input
Column + Page Address
CA0 to CA12, PA0 to PA16
(Page n63 ; District 1)
Address input 05
Column Address
CA0 to CA12
(District 1)
Address input E0
D
D
Data output
(District 0)
(District 1)
3F
B
Return to A
Re
p
eat a max of 63 times
tDCBSYR1
tDCBSYR1 D
TC58NVG2S0FTAI0
2012-09-01
36
(3) Notes
(a) Internal addr essing in relation with the Districts
To use Multi Page Read operation, the internal addressing should be considered in relation with the District.
• The device consists from 2 Districts.
• Each District consists from 1024 erase blocks.
• The allocation rule is follows.
District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046
District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047
(b) Address input restriction for the Multi Page Read opera t ion
There are following restrictions in using Multi Page Read;
(Restriction)
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two distric ts h as to be selected.
For example;
(60) [District 0, Page Address 0x00000] (60) [District 1, Page Address 0x00040] (30)
(60) [District 0, Page Address 0x00001] (60) [District 1, Page Address 0x00041] (30)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 0] (60) [Distr ict 1] (30)
(60) [District 1] (60) [Distr ict 0] (30)
It requires no mutual addres s r e lation between the selected blocks from each District.
(c)WP signal
Make sureWP is held to High level when Multi Page Read operation is performed
TC58NVG2S0FTAI0
2012-09-01
37
Auto Page Program Operation
The device carries out an Automatic Page Program operation when it receives a "10h" Program command
after the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)
Random Column Address Change in Auto Page Program Operation
The column address can be changed by the 85h command during the data input sequence of the Auto Page Program
operation.
Two address input cycles after the 85h command are recognized as a new column address for the data input. After
the new data is input to the new column address, the 10h command initiates the actual data program into the
selected page automatically. The Random Column Address Change operation can be repeated multiple times within
the same page.
80h
Page N Col. M
85h Din Din 10h Status Din Din Din Din
Col. M’
Din Din 70h
Busy
Data input
Selected
page
Readin
g
& verification
Program
Col. M Col. M’
The data is transferred (programmed) from the Data Cache via
the Page Buffer to the selected page on the rising edge of WE
following input of the “10h” command. After programming, the
programmed data is transferred back to the Page Buffer to be
automatically verified by the device. If the programming does not
succeed, the Program/Verify operation is repeated by the device
until success is achieved or until the maximum loop number set in
the device is reached.
Selected
page
Program
Data input
Read& verification
CLE
80h
ALE
I/O
Page P
CE
WE
Col. M
Din 10h 70h
Din Din Din
Data
Status
Out
RE
BYRY/
TC58NVG2S0FTAI0
2012-09-01
38
Multi Page Program
The device has a Multi Page Program, which enables even higher speed program operation compared to Auto
Page Program. The sequence of command, address and data input is shown bellow. (Refer to the detailed timing
chart.)
Although two planes are programmed simultaneously, pass/fail is not available for each page when the program
operation completes. Status bit of I/O 1 is set to “1” when any of the pages fails. Limitation in addressing with
Multi Page Program is shown below.
Multi Page Program
NOTE: Any command between 11h and 81h is prohibited except 70h and FFh.
Data
Input
80h 11h
Plane 0
(1024 Block)
Block 0
Block 2
Block 2044
Block 2046
81h 10h
Plane 1
(1024 Block)
Block 1
Block 3
Block 2045
Block 2047
I/O0~7
R/B
I/O1 Pass
Fail
”1”
”0”
tDCBSYW1 tPROG
CA0~CA12 : Valid
PA 0 ~ PA 5 : Va l i d ’
PA6 : District0’
PA7~PA16 : Valid’
80h Address & Data Input 11h
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6 : District1
PA7~PA16 : Valid
81h Address & Data Input 10h 70h
Note
TC58NVG2S0FTAI0
2012-09-01
39
Auto Page Program Operation with Data Cache
The device has an Auto Page Program with Data Cache operation enabling the high speed program operation shown below. When the block address changes this
sequenced has to be started f r om the beginning.
BY/RY
CLE
ALE
I/O
CE
WE
Page N
80h
A
dd
A
dd
A
dd
A
dd
Status Output
Din 15h 70h
Din Din
Page N + 1
80h
A
dd
A
dd
A
dd
A
dd
1 Status Output
Din 15h 70h
Din Din
Page N + P
80h
A
dd
A
dd
A
dd
A
dd
3 4 Status Output
Din 10h 70h
Din Din
56
Data Cache
Page Buffer
Cell Array
Page N + P
1
234
5
5
6
Page N
Page N + 1
Data for Page N + P
3
A
dd
A
dd
A
dd
Data for Page N
Data for Page N
Data for Page N + 1
Data for Page N + 1
Page N + P − 1
tDCBSYW2 t
DCBSYW2 tPROG (NOTE)
Issuing the 15h command to the device after serial data input initiates the program operation with Data Cache
1 Data for Page N is input to Data Cache.
2 Data is transferred to the Page Buffer by the 15h command. During the transfer the Ready/Busy outputs Busy State (tDCBSYW2).
3 Data is programmed to the selected page while the data for page N + 1 is input to the Data Cache.
4 By the 15h command, the data in the Data Cache is transferred to the Page Buffer after the p rogramming of page N is completed. The device output busy state from the 15h command
until the Data Cache becomes empty. The duration of this period depends on timing between the internal programming of page N and serial data input for Page N + 1 (tDCBSYW2).
5 Data for Page N + P is input to the Data Cache while the data of the Page N + P − 1 is being programmed.
6 The programming with Data Cache is terminated by the 10h command. When the device becomes Ready, it shows that the internal programming of the Page N + P is completed.
NOTE: Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG during cache programming is given by the following;
tPROG = tPROG for the last page + tPROG of the previous page − ( command input cycle + address input cycle + data input cycle time of the previous page)
RE
2
TC58NVG2S0FTAI0
2012-09-01
40
Pass/fail status for each page programmed by the Auto Page Programming with Data Cache operation can be detected by the Status Read operation.
z I/O1 : Pass/fail of the current page program operation.
z I/O2 : Pass/fail of the previous page program operation.
The Pass/Fail status on I/O1 and I/O2 are valid under the following conditions.
z Status on I/O1: Page Buffer Ready/Busy is Ready State.
The Page Buffer Ready/Busy is output on I/O6 by Status Read operation or BY/RY pin after the 10h command
z Status on I/O2: Data Cache Read/Busy is Ready State.
The Data Cache Ready/Busy is output on I/O7 by Status Read operation or BY/RY pin after the 15h command.
80h…15h 70h Status
Out
Page 1
Data Cache Busy
Page Buffer Busy Page 1 Page 2
70h 70h
Page 2
70h
80h…15h
Page N − 1
80h…10h
Page N
Page N − 1 Page N
70h
80h…15h
I/O2 =>
I/O1 => Invalid
Invalid Page 1
Invalid Page N − 2
Invalid invalid
invalid Page N − 1
Page N
Page 1
Page 2
70h
If the Page Buffer Busy returns to Ready before the next 80h command input, and if Status Read is done during
this Ready period, the Status Read provides pass/fail for Page 2 on I/O1 and pass/fail result for Page1 on I/O2
Status
Out Status
Out Status
Out Status
Out Status
Out
Example)
BYRY/ pin
TC58NVG2S0FTAI0
2012-09-01
41
Multi Page Program with Data Cache
The device has a Multi Page Program with Data Cache operation, which enables even higher speed program
operation compared to Auto Page Progr am with Data Cache as shown below. When the block address changes
(increments) this sequen ced has to be started from the beginning.
The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.)
After “15h” or “10h” Program c ommand is input to device, physical programing starts as follows. For details
of Auto Program with Data Cache, refer to “Auto Page Program with Data Cache”.
The data is transferred (programmed) from the page buffer to the selected page on the rising edge of
/WE following input of the “15h” or “10h” command. After programming, the programmed data is
transferred back to the register to be automatically verified by the device. If the programming does not
succeed, the Program/Verify operation is repeated by the device until success is achieved or until the
maximum loop number set in the device is reached.
Selected
page
Reading & verificationProgram
District 0 District 1
BY/RY
Data input
command
for multi-page
program
Data input
0 to 4319
1581 80 11 1081 80 11
Data input
command
Address
input
(District 0)
Data input
0 to 4319
Dummy
Program
command Data input
command
Data input
0 to 4319
Address
input
(District 1)
Program with
Data Cache
command
Address
input
(District 0)
Dummy
Program
command
Auto Page
Program
command
Data input
0 to 4319
Address
input
(District1)
Data input
command
for multi-page
program
TC58NVG2S0FTAI0
2012-09-01
42
Starting the above operation from 1st page of the selected erase blocks, and then repeating the operation
total 64 times with incrementing the page address in the blocks, and then input the last page data of the
blocks, “10h” command executes final programming. Make sure to terminate with 81h-10h- command
sequence.
In this full sequence, the command sequence is following.
After the “15h” or “10h” command, the results of the above operation is shown through the “71h”Status Read
command.
The 71h command Status desc ription is as below.
STATUS OUTPUT
I/O1 Chip Status1 : Pass/Fail Pass: 0 Fail: 1
I/O2 District 0 Chip Status1 : Pass/Fail Pass: 0 Fail: 1
I/O3 District 1 Chip Status1 : Pass/Fail Pass: 0 Fail: 1
I/O4 District 0 Chip Status2 : Pass/Fail Pass: 0 Fail: 1
I/O5 District 1 Chip Status2 : Pass/Fail Pass: 0 Fail: 1
I/O6 Ready/Busy Ready: 1 Busy: 0
I/O7 Data Cache Ready/Busy Ready: 1 Busy: 0
I/O8 Write Protect Protect: 0 Not Protect: 1
I/O1 describes Pass/Fail condition of
district 0 and 1(OR data of I/O2 and I/O3).
If one of the districts fails during multi
page program operation, it shows “Fail”.
I/O2 to 5 shows the Pass/Fail condition of
each district. For details on “Chip Status1”
and “Chip Status2”, refer to section
“Status Read”.
10 or15 71 Pass
I/O
Status Read
command Fail
BY/RY
15
15
10
15
81
81
81
81
11
11
11
11
80
80
80
80
1st
63th
64th
TC58NVG2S0FTAI0
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43
Internal addressing in relation with the Districts
To use Multi Page Program operation, the internal addressing should be considered in relation with the
District.
• The device consists from 2 Districts.
• Each District consists from 1024 erase blocks.
• The allocation rule is follows.
District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046
District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047
Address input restriction for the Multi Page Program with Data Cache operation
There are following restrictions in using Multi Page Program with Data Cache;
(Restriction)
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two distric ts h as to be selected.
For example;
(80) [District 0, Page Address 0x00000] (11) (81) [District 1, Page Address 0x 00040] (15 or 10)
(80) [District 0, Page Address 0x00001] (11) (81) [District 1, Page Address 0x 00041] (15 or 10)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(80) [District 0] (11) (81) [District 1] (15 or 10)
(80) [District 1] (11) (81) [District 0] (15 or 10)
It requires no mutual addres s r e lation between the selected blocks from each District.
Operating restriction during the Multi Page Program with Data Cache operation
(Restriction)
The operation has to be terminated with “10h” command.
Once the operation is started, no commands other than the commands shown in the timing diagr am is allowed
to be input except for Status Read command and reset command.
TC58NVG2S0FTAI0
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44
Page Copy (2)
By using Page Copy (2), data in a page can be copied to another page after the data has been read out.
When the block address chan ges (increments) this seque nced has to be started from the beginning.
Page Copy (2) operation is as following.
1 Data for Page N is transferred to the Data Cache.
2 Data for Page N is read out.
3 Copy Page address M is input and if the data needs to be changed, changed data is input.
4 Data Cache for Page M is transferred to the Page Buffer.
5 After the Ready state, Data for Page N + P1 is output from the Data Cache while the data of Page M is being programmed.
When changing data,
changed data is input.
1
3
4 5
2
tR tDCBSYW2 t
DCBSYR2
BYRY/
00
Command
input
Address
CA0 to CA12, PA0 to PA16
(Page N)
Address input 30 Address input
8C A
Data input 15 00 Address input 3A Data output
Address
CA0 to CA12, PA0 to PA16
(Page M)
Address
CA0 to CA12, PA0 to PA16
(Page N+P1)
A
Data output
Col = 0 start Col = 0 start
Data Cache
Page Buffer
Cell Array
1 2 3 4 5
Page N
Data for Page N Data for Page N
Page M
Page N + P1
Data for Page N + P1
Data for Page M
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45
6 Copy Page address (M + R1) is input and if the data needs to be changed, changed data is input.
7 After programming of page M is completed, Data Cache for Page M + R1 is transferred to the Page Buffer.
8 By the 15h command, the data in the Page Buffer is programmed to Page M + R1. Data for Page N + P2 is transferred to the Data cache.
9 The data in the Page Buffer is programmed to Page M + Rn − 1. Data for Page N + Pn is transferred to the Data Cache.
BY/RY
89
6
7
tDCBSYW2 t
DCBSYR2 t
DCBSYR2
When changing data,
changed data is input.
Command
input
Address
CA0 to CA12, PA0 to PA16
(Page M+R1)
B
00 Address input 3A Data output
Address input
8C Data input 15 00 Address input 3A Data output
Address
CA0 to CA12, PA0 to PA16
(Page N+P2)
Address
CA0 to CA12, PA0 to PA16
(Page N+Pn)
A
B A
Col = 0 start Col = 0 start
Data Cache
Page Buffer
Cell Array
6
7
8
Page M
Data for Page M + R1 Data for Page M + R1 Data for Page N + P2 Data for Page N + Pn
Page M + R1
Page N + P2
Page N + P1
Page M + Rn − 1
Page N + Pn
Page M + Rn − 1
9
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10 Copy Page address (M + Rn) is input and if the data needs to be changed, changed data is input.
11 By issuing the 10h command, the data in the Page Buffer is programmed to Page M + Rn.
(*1) Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG here will be expected as the following,
tPROG = tPROG of the last page + tPROG of the previous page − ( command input cycle + address input cycle + data output/input cycle time of the last page)
NOTE) This operation needs to be executed within District-0 or District-1.
Data input is required only if previous data output needs to be altered.
If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command, and change only the data that needs be changed.
If the data does not have to be changed, data input cycles are not required.
Make sure WP is held to High level when Page Copy (2) operation is performed.
Also make sure the Page Copy operation is terminated with 8Ch-10h command sequence
Data Cache
Page Buffer
Cell Array
Page M + Rn − 1
Data for Page M + Rn Data for Page M + Rn
Page N + Pn
10 11
BY/RY
10
11
tPROG (*1)
Command
input
Address
CA0 to CA12, PA0 to PA16
(Page M+Rn)
Address input
8C Data input 10 70 Status output
B
B
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47
Multi Page Copy (2)
By using Multi Page Copy (2), data in two pages can be copied to another pages after the data has been read out.
When the each block address changes (increments) this sequenced has to be started from the beginning .
Same page address (PA0 to PA5) within two distric ts h as to be selected.
tR
BYRY/
60
Command
input
Address
PA0 to PA16
(Page m0 ; District 0)
Address input 30 A
00 Address input E0 Data output
Address
CA0 to CA12, PA0 to PA16
(Page m0)
A
60 Address input
Address
PA0 to PA16
(Page n0 ; District 1)
05 Address input
Address
CA0 to CA12
(Col = 0)
tDCBSYW1
00 Address input 05 Address input E0 B
B
Data output
Address
CA0 to CA12, PA0 to PA16
(Page n0)
Address
CA0 to CA12
(Col = 0)
8C Address input 11
Data input
Address
CA0 to CA12, PA0 to PA16
(Page M0 ; District 0)
BYRY/
A
A
00 Address input 05 Address input E0 Data output
Address
CA0 to CA12, PA0 to PA16
(Page m1)
Address
CA0 to CA12
(Col = 0)
BYRY/
00 Address input 05 Address input E0 Data output
Address
CA0 to CA12, PA0 to PA16
(Page n1)
Address
CA0 to CA12
(Col = 0)
D
D
C
C
tDCBSYW2
8C Address input 15
Data input
Address
CA0 to CA12, PA0 to PA16
(Page N0 ; District 1)
BYRY/
60
Address
PA0 to PA16
(Page m1 ; District 0)
Address input 3A60 Address input
Address
PA0 to PA16
(Page n1 ; District 1)
C
C
B
B tDCBSYR2
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tDCBSYW1
00 Address input 05 Address input E0 G
G
Data output
Address
CA0 to CA12, PA0 to PA16
(Page n63)
Address
CA0 to CA12
(Col = 0)
8C Address input 11
Data input
Address
CA0 to CA12, PA0 to PA16
(Page M63 ; District 0)
BYRY/
F
F
tDCBSYR2
BYRY/
60
Address
PA0 to PA16
(Page m63 ; District 0)
Address input 3A F
00 Address input E0 Data output
Address
CA0 to CA12, PA0 to PA16
(Page m63)
F
60 Address input
Address
PA0 to PA16
(Page n63 ; District 1)
05 Address input
Address
CA0 to CA12
(Col = 0)
E
E
tDCBSYW1
8C Address input 11
Data input
Address
CA0 to CA12, PA0 to PA16
(Page M1 ; District 0)
BYRY/
E
E
D
D
8C Address input 15
Data input
Address
CA0 to CA12, PA0 to PA16
(Page N1 ; District 1)
tDCBSYW2
BYRY/
G
G
8C Address input 10
Data input
Address
CA0 to CA12, PA0 to PA16
(Page N63 ; District 1)
tPROG
(
*1
)
Note)
This operation needs to be executed within each District.
Data input is required only if previous data output needs to be altered.
If the data has to be changed, locate the desired address with the column and page address input after
the 8Ch command, and change only the data that needs be changed.
If the data does not have to be changed, data input cycles are not required.
Make sure WP is held to High level when Multi Page Copy (2) operation is performed.
Also make sure the Multi Page Copy operation is terminated with 8Ch-10h command sequence
(
*1) tPROG: Since the last page programming by 10h command is initiated after the previous cache
program, the tPROG* during cache programming is given by the following equation.
tPROG = tPROG of the last page + tPROG of the previous page-A
A = (command input cycle + address input cycle + data output/input cycle time of the last page)
If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.
TC58NVG2S0FTAI0
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Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which
follows the Erase Setup command “60h ”. Th is two-cycle process for Erase operations acts as an extra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.
Multi Block Erase
The Multi Block Erase operation st arts by selecting two block addresses before D0h command as in below
diagram. The device automatically executes the Erase and Verify operations and the result can be monitored by
checking the status by 71h status read c omman d. For details on 71h status read command, refer to section
“Multi Page Program with Data Cache”.
Internal addressing in relation with the Districts
To use Multi Block Erase operation, the internal addressing should be considered in relation with the District.
• The device consists from 2 Districts.
• Each District consists from 1024 erase blocks.
• The allocation rule is follows.
District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046
District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047
Address input restriction for the Multi Block Erase
There are following restrictions in using Multi Block Erase
(Restriction)
Maximum one block should be selected from each District.
For example;
(60) [District 0] (60) [District 1] (D0)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 1] (60) [District 0] (D0)
It requires no mutual addres s r e lation between the selected blocks from each District.
Make sure to terminate the operation with D0h command. If the operation needs to be terminated before D0h
command input, input the FFh reset command to terminate the operation.
Pass
I/O
Fail
BY/RY
60 D0 70
Block Address
input: 3 cycles Status Read
command
Busy
Erase Start
command
Pass
I/O
Fail
BY/RY
60 D0 71
Block Address
input: 3 cycles
District 0
Status Read
command
Busy
Erase Start
command
60
Block Address
input: 3 cycles
District 1
TC58NVG2S0FTAI0
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50
READ FOR COPY-BACK WITH DATA OUTPUT TIMING GUIDE
Copy-Back operation is a sequ en ce execution of Read for Copy-Back and of copy -back program with the
destination page address. A read operation with “35h” command and the address of source page moves the
whole 4320byte data into the internal data buffer. Bit errors are checked by sequential reading the data. In the
case where there is no bit error, the data don’t need to be reloaded. Therefore Copy-Back program operation is
initiated by issuing Page-Copy Data-Input command (85h) with destination page address. Acutual programming
operation begins after Program Confirm command (10h) i s issued. Once the program process starts, the Read
Status Register command (70h) may be enterd to read the status register. The system contoller can detect the
completion of a program cycle by monitoring the BY/RY output, or the Status Bit (I/O7) of the Status Register.
When the Copy-Back Program is complete, the Write Status Bit (I/O1) may be checked. The command register
remains in Read Status command mode until another valid command is written to the command register.
During copy-Back program, data modification is possible using randam data input command (85h) as shown
below.
Page Copy-Back Program Operation
NOTE: 1. Copy-Back Program operation is allowed only within the same district.
Page Copy-Back Program Operation with Random Data Input
Col. Add.1,2 & Page Add.1,2,3
Source Address
I/Ox 00h
R/B
Add.(5Cycles) I/O1 Pass
Fail
”1”
”0”
Col. Add.1,2 & Page Add.1,2,3
Destination Address
tR tPROG
35h Data Output 85h Add.(5Cycles) 10h 70h
Col. Add.1,2 & Page Add.1,2,3
Source Address
I/Ox 00h
R/B
Add.(5Cycles)
Col. Add.1,2 & Page Add.1,2,3
Destination Address
tR tPROG
Data Output35h 85h Add.(5Cycles) Data 85h Add.(2Cycles) Data 10h 70h
Col. Add.1
,
2
There is no limitation for the number of re
p
etition
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51
Two-Plane Copy-Back Program Operation
Multi Page Copy-Back Program is an extension of Copy-Back Program, for a single plane with 4320 byte data
registers. Since the device is equipped with two memory planes, activating the two sets of 4320 byte data
registers enable a simultaneous programming of two pages. Same page address (PA0 to PA5) within two
districts has to be selec ted.
NOTE: 1. Copy-Back Program operation is allowed only within the same district.
2. Any command between 11h and 81h is prohibited except 70h and FFh.
I/Ox 60h
R/B
Address(3Cycle) 60h 35h
tR
Address(3Cycle)
Row Add.1,2,3
PA0~PA5 : Valid
PA6 : Fixed ‘Low’
PA7~PA16 : Valid
Row Add.1,2,3
PA0~PA5 : Valid
PA6 : Fixed ‘High’
PA7~PA16 : Valid
1
I/Ox 00h
R/B
Address(5Cycle) 05h E0hAddress(2Cycle)
Col. Add.1,2 & Row Add.1,2,3
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6 : Fixed ‘Low’
PA7~PA16 : Valid
Col. Add.1,2
CA0~CA12 : Valid 2
Data Output
1
I/Ox 00h
R/B
Address(5Cycle) 05h E0hAddress(2Cycle)
Col. Add.1,2 & Row Add.1,2,3
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6 : Fixed ‘High’
PA7~PA16 : Valid
Col. Add.1,2
CA0~CA12 : Valid
Data Output
2
I/Ox 85h
R/B
Add.(5Cycles) 11h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6 : Fixed ‘Low’
PA7~PA16 : Valid
3
81h Add.(5Cycles) 10h 70h
tDCBSYW1 tPROG
Note
*2
Col. Add.1,2 & Row Add.1,2,3
Destination Address
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6 : Fixed ‘High’
PA7~PA16 : Valid
3
Plane0
Source page
Target page
(1) (3)
(2) Data field Spare field
Plane1
Source page
Target page
(1) (3)
(2) Data field Spare field
(1) : Multi Page Read for Copy Back
(2) : Multi Page Random Data Out
(3) : Multi Page Copy-Back Program
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52
Two-Plane Copy-Back Program Operation with Random Data Input
NOTE: 1. Copy-Back Program operation is allowed only within the same district.
2. Any command between 11h and 81h is prohibited except 70h and FFh.
I/Ox 60h
R/B
Address(3Cycle) 60h 35h
tR
Address(3Cycle)
Page Add.1,2,3
PA0~PA5 : Valid
PA6 : Fixed ‘Low’
PA7~PA16 : Valid
Page Add.1,2,3
PA0~PA5 : Valid
PA6 : Fixed ‘High’
PA7~PA16 : Valid
1
I/Ox 00h
R/B
Address(5Cycle) 05h E0hAddress(2Cycle)
Col. Add.1,2 & Page Add.1,2,3
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6 : Fixed ‘Low’
PA7~PA16 : Valid
Col. Add.1,2
CA0~CA12 : Valid 2
Data Output
1
I/Ox 00h
R/B
Address(5Cycle) 05h E0hAddress(2Cycle)
Col. Add.1,2 & Page Add.1,2,3
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6 : Fixed ‘High’
PA7~PA16 : Valid
Col. Add.1,2
CA0~CA12 : Valid
Data Output
2 3
I/Ox 85h
R/B
Add.(5Cycles) Data
Col. Add.1,2 & Page Add.1,2,3
Destination Address
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6 : Fixed ‘Low’
PA7~PA16 : Valid
3
Add.(2Cycles)
tDBS
Y
Col. Add.1,2
85h Data 11h
4
Note
*2
I/Ox 81h
R/B
Add.(5Cycles) Data
Col. Add.1,2 & Page Add.1,2,3
Destination Address
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6 : Fixed ‘High’
PA7~PA16 : Valid
4
Add.(2Cycles)
tPROG
Col. Add.1,2
85h Data 10h
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53
2KB Program Operation Timing Guide
The device is designed also to support the program operation with 2KByte data to offer the backward
compatibility to the controller which uses the NAND Flash with 2KByte page. The sequence of command,
address and data input is shown below.
(2KBx2) Program Operation
NOTE: 1. Any command between 11h and 81h is prohibited except 70h and FFh
(2KBx2) Copy-Back
NOTE: 1. Copy-Back is allowed only within the same memory district.
2. Any command between 11h and 81h is prohibited except 70h and FFh.
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6 : Valid
PA7~PA16 : Valid
I/O0~7
R/B
tDCBSYW1 tPROG
80h Address & Data Input 11h 80h Address & Data Input 10h 70h
Note
Col. Add.1,2 & Row Add.1,2,3
2112 B
y
te Data
CA0~CA12 : Valid
PA0~PA5 : Must be same with the previous
PA6 : Must be same with the previous
PA7~PA16 : Must be same with the previous
Col. Add.1,2 & Row Add.1,2,3
2112 B
y
te Data
tR
I/Ox
R/B
Col. Add.1,2 & Row Add.1,2,3
Source Address
00h Add.(5Cycles) 35h Data Output
1
tDCBSYW1
I/Ox
R/B
85h Add.(5Cycles) Data
1
11h 85h Add.(5Cycles) Data 10h
tPROG
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6 : Valid
PA7~PA16 : Valid
Col. Add.1,2 & Row Add.1,2,3
Destination Address
CA0~CA12 : Valid
PA0~PA5 : Must be same with the previous
PA6 : Must be same with the previous
PA7~PA16 : Must be same with the previous
Col. Add.1,2 & Row Add.1,2,3
Destination Address
TC58NVG2S0FTAI0
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54
(2KBx2) Copy-Back with Random Data Input
NOTE: 1. Copy-Back is allowed only within the same memory district.
2. Any command between 11h and 81h is prohibited except 70h and FFh.
tR
I/Ox
R/B
Col. Add.1,2 & Row Add.1,2,3
Source Address
00h Add.(5Cycles) 35h Data Output
1
I/Ox 85h
R/B
Add.(5Cycles) Data
Col. Add.1,2 & Row Add.1,2,3
Destination Address
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6 : Valid
PA7~PA16 : Valid
1
Add.(2Cycles)
tDCBSYW1
Col. Add.1,2
85h Data 11h
2
Note
*2
I/Ox 85h
R/B
Add.(5Cycles) Data
Col. Add.1,2 & Row Add.1,2,3
Destination Address
CA0~CA12 : Valid
PA0~PA5 : Must be same with the previous
PA6 : Must be same with the previous
PA7~PA16 : Must be same with the previous
2
Add.(2Cycles)
tPROG
Col. Add.1,2
85h Data 10h
TC58NVG2S0FTAI0
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55
Multi Page Copy-Back using 4KB Buffer RAM
The deveice consists of 4KB pages and can support Multi Plane program operation. The internal RAM
requirement for a controller is 8KB, but for those controllers which support less than 8KB RAM, the sequence of
command, address and data input is shown below for Multi Plane program operation.
Multi Page Copy-Back with Random Data Inp u t
NOTE: 1. Copy-Back is allowed only within the same memory district.
District0
Target page
(1) (6)
(2) Data field Spare field
District1
4KByte 4KByte
Source page Source page
Target page
(1) (6)
Data field Spare field
(1) : Two-Plane Read for Copy-Back
(2) : Random Data Out On Plane 0(Up to 4320Byte)
(3) : Random Data In On Plane 0(Up to 4320Byte)
(4) : Random Data Out On Plane 1(Up to 4320Byte)
(5) : Random Data In On Plane 1(Up to 4320Byte)
(6) : Two-Plane Program for Copy-Back
(3) (4) (5)
Row Add.1,2,3
tR
I/Ox
R/B
Add.(3Cycle) Add.(3Cycle)
1
PA0~PA5 : Valid
PA6 : Fixed ‘Low’
PA7~PA16 : Valid
Row Add.1,2,3
PA0~PA5 : Valid
PA6 : Fixed ‘High’
PA7~PA16 : Valid
CA0~CA12 : Fixed ‘Low’
PA0~PA5 : Fixed ‘Low’
PA6 : Fixed ‘Low’
PA7~PA16 : Fixed ‘Low’
Col. Add.1,2 & Row Add.1,2,3
Destination Address
tDCBSYW1
I/Ox 85h
R/B
Add.(5Cycle)
Col. Add.1,2 Up to 4320Byte
DOUT
2
Col. Add.1,2, CA0~CA12 : Valid
Col. Add.1,2 & Row Add.1,2,3
CA0~CA12 : Fixed ‘Low’
PA0~PA5 : Fixed ‘Low’
PA6 : Fixed ‘High’
PA7~PA16 : Fixed ‘Low’
1
Add.(2Cycle)DIN 85h DIN Add.(2Cycle) 05h E0h Add.(5Cycle)00h11h
Col. Add.1,2 Up to 4320Byte
DOUT
CA0~CA12 : Valid
Col. Add.1,2 & Row Add.1,2,3
Add.(2Cycle) 05h E0h Add.(5Cycle)00h60h 60h 35h
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6 : Fixed ‘Low’
PA7~PA16 : Valid
Col. Add.1,2 & Row Add.1,2,3
Destination Address
tPROG
I/Ox 81h
R/B
Add.(5Cycle) 70h
Col. Add.1,2,
2
Add.(2Cycle)DIN 85h DIN 10h
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6 : Fixed ‘High’
PA 7~ PA1 6 : Va l id
TC58NVG2S0FTAI0
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56
ID Read
The device contains ID codes which can be used to identify the device type, the manufacturer, and features of
the device. The ID codes can be read out under the following timing conditions:
Table 5. Code table
Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Hex Data
1st Data Maker Code 1 0 0 1 1 0 0 0 98h
2nd Data Device Code 1 1 0 1 1 1 0 0 DCh
3rd Data Chip Number, Cell Type ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ See table
4th Data Page Size, Block Size ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ See table
5th Data Plane Number ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ See table
3rd Data
Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
Internal Chip Number
1
2
4
8
0
0
1
1
0
1
0
1
Cell Type
2 level cell
4 level cell
8 level cell
16 level cell
0
0
1
1
0
1
0
1
90h 00h 98h DCh See
table 5 See
table 5
WE
CLE
RE
tCEA
CE
ALE
I/O
tAR
tRE
A
ID Read
command Address 00 Maker code Device code
See
table 5
TC58NVG2S0FTAI0
2012-09-01
57
4th Data
Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
Page Size
(without redundant area)
1 KB
2 KB
4 KB
8 KB
0
0
1
1
0
1
0
1
Block Size
(without redundant area)
64 KB
126 KB
256 KB
512 KB
0
0
1
1
0
1
0
1
5th Data
Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
Plane Number
1 Plane
2 Plane
4 Plane
8 Plane
0
0
1
1
0
1
0
1
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Status Read
The device automatically implements the execution and verification of the Program and Erase operations.
The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass
/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is
output via the I/O port using RE or CE after a “70h” command input. This two signal control allows the
system to poll the progress of each device in multiple memory connections even when Ready/Busy pins are
common-wired. The Status Read can also be used during a Read operation to fin d ou t the Ready / Busy status.
The resulting information is outlined in Table 6.
Table 6. Status output table
Definition
Page Program
Block Erase Cache Program Read
Cache Read
I/O1 Chip Status1
Pass: 0 Fail: 1 Pass/Fail Pass/Fail Invalid
I/O2 Chip Status 2
Pass: 0 Fail: 1 Invalid Pass/Fail Invalid
I/O3 Not Used 0 0 0
I/O4 Not Used 0 0 0
I/O5 Not Used 0 0 0
I/O6 Page Buffer Ready/Busy
Ready: 1 Busy: 0 Ready/Busy Ready/Busy Ready/Busy
I/O7 Data Cache Ready/Busy
Ready: 1 Busy: 0 Ready/Busy Ready/Busy Ready/Busy
I/O8 Write Protect
Not Protected :1 Protected: 0 Write Protect Write Protect Write Protect
The Pass/Fail status on I/O1 and I/O2 is only valid during a Program/Erase operation when the device is in the Ready state.
Chip Status 1:
During a Auto Page Program or Auto Block Erase operation this bit indicates the pass/fail result.
During a Auto Page Programming with Data Cache operation, this bit shows the pass/fail resu lts of the
current page program operation, and therefore this bit is only valid when I/O6 shows the Ready state.
Chip Status 2:
This bit shows the pass/fail result of the previous page program operation during Auto Page Programming
with Data Cache. This status is valid when I/O7 shows the Ready State.
The status output on the I/O6 is the same as that of I/O7 if the command input just before the 70h is not
15h or 31h.
Reset
The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally
generated voltage is discharged to 0 volt and the device enters the Wait state.
Reset during a Cache Program/Page Copy may not just stop the most re cent page program but it may also
stop the previous program to a page depending on when the FF reset is input.
The response to a “FFh” Reset command input during the various device operations is as follows:
When a Reset (FFh) command is in put during programming
Internal VPP
80 10 FF 00
BY/RY
tRST (max 30 µs)
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When a Reset (FFh) comm and is input during erasing
When a Reset (FFh) comm and is input during Read operation
When a Reset (FFh) comm and is input during Ready
When a Status Re ad command (70h) is input af ter a Reset
When two or more Reset commands are input in succession
10
BY/RY
FF FF
(3)(2)(1)
The second command is invalid, but the third command is valid.
FF FF
FF
I/O status : Pass/Fail → Pass
: Ready/Busy
→ Ready
FF 70
BY/RY
00 FF 00
BY/RY
tRST (max 10 µs)
30
Internal erase
voltage
D0 FF 00
BY/RY
tRST (max 500 µs)
00
BY/RY
tRST (max 10 µs)
FF
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APPLICATION NOTES AND COMMENTS
(1) Power-on/off sequence:
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power on
sequence. During the initialization the device Ready/Busy sig nal indicates the Busy state as sh own in the
figure below. In this time period, the acceptable commands are FFh or 70h/71h.
The WP signal is useful for protecting against data corruption at power-on/off.
(2) Power-on Reset
The following sequence is necessary because some input signals may not be stable at power-on.
(3) Prohibition of unspecified commands
The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
(4) Restriction of commands w h ile in the Busy state
During the Busy state, do not in pu t any command except 70h(71h) an d FFh.
FF
Reset
Power on
VIL
Operation
0 V VCC
2.7 V
2.5 V
VIL
Don’t
care Don’t
care
VIH
CE , WE , RE
WP
CLE, ALE
Invalid Don’t
care
Ready/Busy
2 ms max
100 µs max
Don’t
care
Invalid
2 ms max
100 µs max
≥ 1ms
2.7 V
2.5 V
0.5 V 0.5 V
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(5) Acceptable commands after Serial Input command “80h”
Once the Serial Input command “80h” has been input, do not input any command other than the Column
Address Change in Serial Data Input command “85h”, Auto Program command “10h”, M ulti Page Program
command “11h”, Auto Program with Data Cache Command “15h”, or the Reset command “FFh”.
If a command other than “85h” , “10h” , “11h” , “15h” or “FFh” is input, the Program operation is not
performed and the device operation is set to the mode which the input command specifies.
(6) Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.
DATA IN: Data (1)
Page 0
Data register
Page 2
Page 1
Page 31
Page 63
(1)
(2)
(3)
(32)
(64)
Data (64)
From the LSB page to MSB page
DATA IN: Data (1)
Page 0
Data register
Page 2
Page 1
Page 31
Page 63
(2)
(32)
(3)
(1)
(64)
Data (64)
Ex.) Random page program (Prohibition)
Command other than
“85h”, “10h”, “11h”, “15h” or “FFh”
80 Programming cannot be executed.
10XX Mode specified by the command.
WE
BY/RY
80 FF
Address input
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(7) Status Read during a Read operation
The device status can be read out by in putting the Status Read command “70h” in Read mode. Once the
device has been set to Status Read mode by a “70h” command, the device will not return to Read mode
unless the Read command “00h” is inputted during [A]. If the Read command “00h” is inputted during [A],
Status Read mode is reset, and the device returns to Read mode. In this case, data output starts
automatically from address N and address input is unnecessary
(8) Auto programming failure
(9) BY/RY : termination for the Ready/Busy pin ( BY/RY )
A pull-up resistor needs to be used for termination because the BY/RY buffer consists of an open drain
circuit.
Fail
80 108010
Address
M Data
input
70 I/O Address
N Data
input
If the programming result for page address M is Fail, do not try to program the
page to address N in another block without the data input sequence.
Because the previous input data has been lost, the same input sequence of 80h
command, address and data is necessary.
10
80
M
N
This data may vary from device to device.
We recommend that you use this data as a
reference when selecting a resistor value.
VCC
VCC
Device
VSS
R
BY/RY
CL
1.5 µs
1.0 µs
0.5 µs
01 KΩ4 KΩ3 KΩ2 KΩ
15 ns
10 ns
5 ns
tf
tr
R
tr
tf
VCC = 3.3 V
Ta = 25°C
CL = 100 pF
tf
Ready VCC
tr
Busy
00
Address N
Command
CE
WE
BY/RY
RE
[A]
Status Read
command input Status Read Status output
.
70
00
30
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(10) Note regarding the WP signal
The Erase and Program operations are automatically reset when WP goes Low. The operations are
enabled and disabled as follo ws:
Enable Programming
Disable Programming
Enable Erasing
Disable Erasing
WP
tWW (100 ns MIN)
80 10
WE
BY/RY
DIN
WP
tWW (100 ns MIN)
60 D0
WE
BY/RY
DIN
WP
tWW (100 ns MIN)
80 10
WE
BY/RY
DIN
WP
tWW (100 ns MIN)
60 D0
WE
BY/RY
DIN
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(11) When six address cycles are input
Although the device may read in a sixth address, it is ignored inside the chip.
Read operation
Program operation
CLE
Address input
00h
CE
WE
ALE
I/O
BY/RY
Ignored
30h
CLE
CE
WE
ALE
I/O
Address input Ignored
80h
Data input
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(12) Several programming cy c les on the same page (Partial Page Program)
Each segment can be programmed individually as follows:
Data Pattern 4
Data Pattern 1 All 1 s
All 1 s All 1 s
All 1 s
1st programming
2nd programming
4th programming
Result Data Pattern 1 Data Pattern 2
Data Pattern 4
Data Pattern 2
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(13) Invalid blocks (bad blocks)
The device occasionally contains unusable blocks. Therefore, the following issues must be recognized:
Please do not perform an erase operation to bad blocks. It may be
impossible to recover the bad block information if the information is
erased.
Check if the device has any bad blocks after installation into the system.
Refer to the test flow for bad block detection. Bad blocks which are
detected by the test flow must be managed as unusable blocks by the
system.
A bad block does not affect the performance of good blocks because it is
isolated from the bit lines by select gates.
The number of valid blocks over the device lifetime is as follows:
MIN TYP. MAX UNIT
Valid (Good) Block Number 2008 ⎯ 2048 Block
Bad Block Test Flow
Regarding invalid blocks, bad block mark is in either the 1st or the 2nd page.
*1: No erase operation is allowed to detected bad blocks
Bad Block
Bad Block
Pass
Read Check
Start
Bad Block *1
Last Block
End
Yes
Fail
Block No = 1
No
Block No. = Block No. + 1
Read Check :
Read either column 0 or 4096 of the 1st page or the
2nd page of each block. If the data of the column is not
FF (Hex), define the block as a bad block.
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(14) Failure phenomena for Program and Erase operations
The device may fail during a Program or Erase operation.
The following possible failure modes should be considered when implementing a highly reliable system.
FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE
Block Erase Failure Status Read after Erase → Block Replacement
Page Programming Failure Status Read after Program → Block Replacement
Random
Bit Programming Failure
“1 to 0” ECC
• ECC: Er ror Correction Code. 4 bit correction per 512Bytes is ne cessary.
• Block Replacement
Program
Erase
When an error occ ur s during an Erase operation, prevent future accesses to this bad bloc k
(again by creating a table with in the system or by using another appr opriate scheme).
(15) Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery
is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data
and/or damage to data.
(16) The number of valid blocks is on the basis of single plane operations, and this may be decreased with two
plane operations.
When an error happens in Block A, try to reprogram the
data into another Block (Block B) by loading from an
external buffer. Then, prevent further system accesses
to Block A ( by creating a bad block table or by using
another appropriate scheme).
Block A
Block B
Error occurs
Buffer
memory
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(17) Reliability Guidance
This reliability guidance is intended to notify some guidance related to using NAND flash with
4 bit ECC for each 512 bytes. For detailed reliability data, please refer to TOSHIBA’s reliability note.
Although random bit errors may occur during use, it does not necessarily mean that a block is bad.
Generally, a block should be marked as bad when a program status failure or erase status failure is detected.
The other failure modes may be recovered by a block erase.
ECC treatment for read data is mandatory due to the following Data Retention and Read Disturb failures.
• Write/Erase Endurance
Write/Erase endur ance failures may occur in a ce ll, page, or block, and are detected by doing a status read
after either an auto program or auto block erase operation. The cumulative bad block count will increase
along with the number of write/erase cycles.
• Data Retention
The data in memory may change after a certain amount of storage time. This is due to charge loss or charge
gain. After block er asure and reprogramming, th e block may become usable again.
Here is the combined characteristics image of Write/Erase Endurance and Data Retention.
• Read Disturb
A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit
errors occur on other pages in the block, not the page being read. After a large number of read cycles
(between block erases), a tiny char g e may bu ild u p and can cause a cell to be soft programmed to another
state. After block erasu re and reprogramming, the bloc k may bec ome usable again.
Wr ite /Erase Endurance [Cycles]
Data
Retention
[Years]
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Package Dimensions
Weight: 0.53g (typ.)
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Revision History
Date Rev. Description
2010-08-18 1.00 Original version
2010-10-22 1.10 Editorial correction
2011-04-07 1.20 Deleted PSL description
Corrected typo.
2011-05-18 1.30 Editorial correction
2011-09-01 1.40 Deleted TENTATIVE notaion
2012-09-01 1.50 Changed “RESTRICTIONS ON PRODUCT USE”.
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RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively "Product") without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts,
diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating
parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR
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• PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
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OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.
