Description
The L6219DS motor driver is designed to drive both windings
of a bipolar stepper motor or bidirectionally control two DC
motors. Both bridges are capable of sustaining 45 V and include
internal pulse-width modulation (PWM) control of the output
current to 750 mA. The outputs have been optimized for a low
output saturation voltage drop (less than 1.8 V total source
plus sink at 500 mA).
For PWM current control, the maximum output current is
determined by user selection of a reference voltage and sensing
resistor. Two logic-level inputs select output current limits of
0, 33, 67, or 100% of the maximum level. A PHASE input to
each bridge determines load current direction.
The bridges include both ground clamp and flyback diodes for
protection against inductive transients. Internally generated
delays prevent crossover currents when switching current
direction. Special power-up sequencing is not required. Thermal
protection circuitry disables the outputs if the chip temperature
exceeds safe operating limits.
The L6219DS is supplied in a 24-pin surface-mountable SOIC,
with 4 internally-fused leads for maximum package power
dissipation in the smallest possible construction. It is lead (Pb)
free with 100% matte tin leadframe plating.
29319.43I
Features and Benefits
▪ Interchangeable with SGS L6219DS
▪ 750 mA Continuous Output Current
▪ 45 V Output Sustaining Voltage
▪ Internal Clamp Diodes
▪ Internal PWM Current Control
▪ Low Output Saturation Voltage
▪ Internal Thermal Shutdown Circuitry
▪ Similar to Dual PBL3717, UC3770
Dual Full-Bridge PWM Motor Driver
Package: 24 pin SOICW (suffix LB)
Typical Application
Not to scale
L6219DS
FROM
μP
V
REF
Dwg. EP-008B1
V
BB
FROM
μP
1
2
3
4
5
6
7
8
9
24
23
22
21
20
17
16
15
14
1312
11
10
9
Q
2
V
CC
2
V
BB
1
V
REF
+5 V
STEPPER
MOTOR
R
S
R
S
R
C
R
C
R
T
C
T
C
C
C
C
+
PWM 1
PWM 2
Q
1
820 pF 56 k7
C
T
820 pF
56 k7
R
T
19
18
Dual Full-Bridge PWM Motor Driver
L6219DS
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Motor Supply Voltage VBB 45 V
Logic Supply Voltage VCC 7.0 V
Logic Input Voltage Range VIN –0.3 to VCC+0.3 V
Output Emitter Voltage VSENSE 1.5 V
Output Current, Peak IOUT(pk) 1.0 A
Output Current, Continuous IOUT
Output current rating may be limited by duty
cycle, ambient temperature, and heat sinking.
Under any set of conditions, do not exceed
the specifi ed peak current rating or a junction
temperature of +150°C.
750 mA
Operating Ambient Temperature TARange S –20 to 85 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
Selection Guide
Part Number Packing Operating Ambient Temperature Range
TA (°C)
L6219DSTR-T 1000 pieces per reel –20 to 85
Thermal Characteristics
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance
RθJA
1-layer PCB with copper limited to solder pads 77 ºC/W
1-layer PCB with 3.57 in.2 of copper area 49 ºC/W
RθJT 6 ºC/W
*Additional thermal information available on the Allegro website.
50 75 100 125
150
2.5
1.5
1.0
0.5
0
TEMPERATURE in °C
2.0
25
Dwg. GP-019C
R = 6°C/W
θJT
R = 77°C/W
θJA
R = 49°C/W
θJA
Dual Full-Bridge PWM Motor Driver
L6219DS
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright © 1998, 2003 Allegro MicroSystems, Inc.
PWM Current-Control Circuitry
V
REF
Dwg. EP-007-5
V
BB
COMP IN ONE
SHOT
SOURCE
DISABLE
RC
–
+
I
0
I
1
w10
SENSE
OUT A
OUTB
CHANNEL 1
TERMINAL NUMBERS
SHOWN.
RC
RSRT
CC
CT
24
20 k7
40 k7
10 k7
211
23
22
14
20
17
15
Pin-Out Diagram
1
2
3
4
5
6
7
8
24
23
22
21
20
17
16
15
14
13
12
11
10
9
Q
2
Q
1
VCC
PWM 2
PWM 1
2
VBB
1
GROUND
GROUND GROUND
GROUND
02
I
12
I
PHASE 2
VREF 2
2
RC
1
RC
VREF 1
PHASE 1
11
I
2B
OUT
SENSE 2
2
COMP IN
2A
OUT
1A
OUT
1
COMP IN
SENSE 1
1B
OUT
01
I
LOAD
SUPPLY
LOGIC
SUPPLY
Dwg. PP-005-3
19
18
Phase Truth Table
PHASE OUTA OUTB
HHL
LLH
Dual Full-Bridge PWM Motor Driver
L6219DS
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Drivers (OUTA or OUTB)
Motor Supply Range VBB 10 — 45 V
Output Leakage Current ICEX V
OUT = VBB — < 1.0 50 μA
V
OUT = 0 — <-1.0 -50 μA
Output Sustaining Voltage VCE(sus) I
OUT = ±750 mA, L = 3.0 mH 45 — — V
Output Saturation Voltage VCE(SAT) Sink Driver, IOUT = +500 mA — 0.4 0.6 V
Sink Driver, IOUT = +750 mA — 1.0 1.2 V
Source Driver, IOUT = -500 mA — 1.0 1.2 V
Source Driver, IOUT = -750 mA — 1.3 1.5 V
Clamp Diode Leakage Current IR V
R = 45 V — < 1.0 50 μA
Clamp Diode Forward Voltage VF I
F = 750 mA — 1.6 2.0 V
Driver Supply Current IBB(ON) Both Bridges On, No Load — 20 25 mA
I
BB(OFF) Both Bridges Off — 5.0 10 mA
Control Logic
Input Voltage VIN(1) All inputs 2.4 — — V
V
IN(0) All inputs — — 0.8 V
Input Current IIN(1) VIN = 2.4 V — <1.0 20 μA
VIN = 0.8 V — - 3.0 -200 μA
Reference Voltage Range VREF Operating 1.5 — 7.5 V
Current Limit Threshold VREF/V
COMPIN I
0 = I1 = 0.8 V 9.5 10 10.5 —
I
0 = 2.4 V, I1 = 0.8 V 13.5 15 16.5 —
I
0 = 0.8 V, I1 = 2.4 V 25.5 30 34.5 —
Thermal Shutdown Temperature TJ — 170 — °C
Total Logic Supply Current ICC(ON) I0 = I1 = 0.8 V, No Load — 40 50 mA
I
CC(OFF) I
0 = I1 = 2.4 V, No Load — 10 14 mA
Fixed Off-Time toff R
T = 56 k, CT = 820 pF — 46 — μs
(at trip point)
ELECTRICAL CHARACTERISTICS at TA = +25°C, TJ 150°C, VBB = 45 V, VCC = 4.75 V to 5.25 V,
VREF = 5.0 V (unless otherwise noted).
Dual Full-Bridge PWM Motor Driver
L6219DS
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Applications Information
PWM Current Control
The L6219DS dual bridge is designed to drive both windings of
a bipolar stepper motor. Output current is sensed and controlled
independently in each bridge by an external sense resistor (RS),
internal comparator, and monostable multivibrator.
When the bridge is turned on, current increases in the motor
winding and it is sensed by the external sense resistor until
the sense voltage (VCOMPIN) reaches the level set at the
comparator’s input:
ITRIP = VREF/10 RS
The comparator then triggers the monostable which turns off
the source driver of the bridge. The actual load current peak
will be slightly higher than the trip point (especially for low-
inductance loads) because of the internal logic and switching
delays. This delay (td) is typically 2 μs. After turn-off, the
motor current decays, circulating through the ground-clamp
diode and sink transistor. The source driver’s off time (and
therefore the magnitude of the current decrease) is determined
by the monostable’s external RC timing components, where
toff = RTCT within the range of 20 kΩ to 100 kΩ and 100 pF to
1000 pF.
The fi xed-off time should be short enough to keep the current
chopping above the audible range (< 46 μs) and long enough to
properly regulate the current. Because only slow-decay current
control is available, short off times (< 10 μs) require additional
efforts to ensure proper current regulation. Factors that can
negatively affect the ability to properly regulate the current
when using short off times include: higher motor-supply
voltage, light load, and longer than necessary blank time.
When the source driver is re-enabled, the winding current (the
sense voltage) is again allowed to rise to the comparator’s
threshold. This cycle repeats itself, maintaining the average
motor winding current at the desired level.
Loads with high distributed capacitances may result in high
turn-on current peaks. This peak (appearing across RS) will
attempt to trip the comparator, resulting in erroneous current
control or high-frequency oscillations. An external RCCC
time delay should be used to further delay the action of the
comparator. Depending on load type, many applications will
not require these external components (SENSE connected to
COMP IN).
+
–
0
Dwg. WM-003-1A
VPHASE
IOUT
tdto
I
TRIP
Dwg. E P -006-1
RS
BB
V
BRIDGE ON
SOURCE OFF
ALL OFF
PWM Output Current Wave Form
Load Current Paths
Dual Full-Bridge PWM Motor Driver
L6219DS
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Logic Control of Output Current
Two logic level inputs (I0 and I1) allow digital selection of
the motor winding current at 100%, 67%, 33%, or 0% of the
maximum level per the table below. The 0% output current
condition turns off all drivers in the bridge and can be used as an
OUTPUT ENABLE function.
These logic level inputs greatly enhance the implementation of
μP-controlled drive formats.
During half-step operations, the I0 and I1 allow the μP to control
the motor at a constant torque between all positions in an eight-
step sequence. This is accomplished by digitally selecting 100%
drive current when only one phase is on and 67% drive current
when two phases are on. Logic highs on both I0 and I1 turn off all
drivers to allow rapid current decay when switching phases. This
helps to ensure proper motor operation at high step rates.
The logic control inputs can also be used to select a reduced
current level (and reduced power dissipation) for ‘hold’
conditions and/or increased current (and available torque) for
start-up conditions.
General
The PHASE input to each bridge determines the direction
motor winding current fl ows. An internally generated dead time
(approximately 2 μs) prevents crossover currents that can occur
when switching the PHASE input.
All four drivers in the bridge output can be turned off between
steps (I0 = I1 ≥ 2.4 V) resulting in a fast current decay through the
internal output clamp and fl yback diodes. The fast current decay
is desirable in half-step and high-speed applications. The PHASE,
I0,and I1 inputs fl oat high.
Varying the reference voltage (VREF) provides continuous control
of the peak load current for microstepping applications.
Thermal protection circuitry turns off all drivers when the
junction temperature reaches 170°C. It is only intended to protect
the device from failures due to excessive junction temperature
and should not imply that output short circuits are permitted. The
output drivers are re-enabled when the junction temperature cools
to 145°C.
The L6219DS output drivers are optimized for low output
saturation voltages—less than 1.8 V total (source plus sink) at
500 mA. Under normal operating conditions, when combined
with the excellent thermal properties of the fused internal lead
package design, this allows continuous operation of both bridges
simultaneously at 500 mA.
Current-Control Truth Table
l0I1Output Current
LL
VREF/10 RS = ITRIP
HL
VREF/15 RS = 2/3 ITRIP
LH
VREF/30 RS = 1/3 ITRIP
HH 0
Dual Full-Bridge PWM Motor Driver
L6219DS
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Current Sensing
To minimize current sensing inaccuracies caused by ground trace
IR drops, each current-sensing resistor should have a separate
return to the ground terminal of the device. For low-value sense
resistors, the IR drops in the PCB can be signifi cant and should be
taken into account. The use of sockets should be avoided as their
contact resistance can cause variations in the effective value of RS.
Generally, larger values of RS reduce the aforementioned effects
but can result in excessive heating and power loss in the sense
resistor. The selected value of RS should not cause the absolute
maximum voltage rating of 1.5 V, for the SENSE terminal, to be
exceeded. The recommended value of RS is in the range of:
RS = 0.75 / ITRIP(max) ± 50% .
If desired, the reference input voltage can be fi ltered by placing
a capacitor from REFIN to ground. The ground return for this
capacitor as well as the bottom of any resistor divider used should
be independent of the high-current power-ground trace to avoid
changes in REFIN due to IR drops.
Thermal Considerations
For reliable operation, it is recommended that the maximum
junction temperature be kept below 110°C to 125°C. The junction
temperature can be measured best by attaching a thermocouple
to the power pins (6, 7, 18 and 19) of the device and measuring
the pin temperature, TTAB. The junction temperature can then be
approximated by using the formula:
TJ = TTAB + (2 ILOAD VF RJT) ,
where VF can be chosen from the electrical specifi cation table
for the given level of ILOAD. The value for RJT is approximately
6°C/W.
The power dissipation can be improved 20% to 30% by adding a
section of printed circuit board copper (typically 6 to 18 square
centimeters) connected to the power pins of the device.
The thermal performance in applications that run at high load
currents, high duty cycles, or both can be improved by adding
external diodes from each output to ground in parallel with the
internal diodes. Fast-recovery (200 ns) diodes should be used to
minimize switching losses.
Load Supply Terminal
The load supply terminal, VBB, should be decoupled with an
electrolytic capacitor (47μF is recommended), placed as close
to the device as is physically practical. To minimize the effect of
system ground IR drops on the logic and reference input signals,
the system ground should have a low-resistance return to the load
supply voltage.
Fixed Off-Time Selection
With increasing values of tOFF, switching losses decrease, low-
level load current regulation improves, EMI reduces, PWM
frequency decreases, and ripple current increases. The value of
tOFF can be chosen for optimization of these parameters. For
applications where audible noise is a concern, typical values of
tOFF should be chosen in the range of 15 to 35 μs.
Application Information
Dual Full-Bridge PWM Motor Driver
L6219DS
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©1998-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
1.27
BReference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
B
0.20 ±0.10
0.41 ±0.10
2.20
0.65
9.60
1.27
21
24
A
15.40±0.20
2.65 MAX
10.30±0.33
7.50±0.10
C
SEATING
PLANE
C0.10
24X
For Reference Only
Pins 6 and 7, and 18 and 19 internally fused
Dimensions in millimeters
(Reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
0.25
GAUGE PLANE
SEATING PLANE PCB Layout Reference View
4° ±4
0.27 +0.07
–0.06
0.84 +0.44
–0.43
Package LB, 24-Pin SOICW
