LITE-ON ELECTRONICS, INC.
Property
of
Lite-On
Only
BNS-OD-C131/A4
ELECTRICAL/OPTICAL CHARACTERISTICS AT Ta=25℃
Average Luminous Intensity
Luminous Intensity Matching Ratio
FUNCTIONAL DESCRIPTION
Serial data transfer from the data source to the display driver is accomplished with 2
signals serial data and clock. Using a format of a leading “1” followed by the 35 data bits
allow data transfer without an additional load signal. The 35 data bits are latched after the
36th bit is completed, thus providing non multiplexed, direct drive to the display. Outputs
change only if the serial data bits differ from the previous time.
Brightness of display is determined by control the output current of LED display. A 1nF
capacitor should be connected to brightness control, Pin 7 to prevent possible oscillations.
The output current is typically 25 times greater than the current into Pin 7 which is set by
an external variable resistor. There is an internal limiting resistor of 400 Ω nominal
value.
Figure 1 shows the input data format. A start bit of logical “1” proceed the 35 bits of data.
At the 36th clock, a LOAD signal is generated synchronously with the high state of the
clock, which loads the 35 bits of the shift registers into the latches. At the low state of the
clock a RESET signal is generated which clears all the shift registers for the next set of
data. The shift registers are static master-slave configuration. There is no clear for master
portion of the first register, thus allowing continuous operation.
There must be a complete set of 36 clocks or the shift registers won’t clear. When power is
first applied to the chip, an internal power ON, a reset signal is generated which reset all
registers and all latches. The START bit and first clock return the chip on its normal
operation. Bit 1 is the first following the start bit and it will appear on the segment A of the
digit 1. A logical “1” at the input will turn on the appropriate LED. Figure 2 shows the
timing relationship between data, clock, and DATA ENABLE. A max. clock frequency of
0.5 MHz is assumed.