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Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. FAN2365AMPX 15 A Synchronous Buck Regulator Features Description The FAN2365A is a highly efficient synchronous buck regulator. The regulator is capable of operating with an input range from 4.5 V to 24 V and supporting up to 15 A continuous load currents. VIN Range: 4.5 V to 24 V High Efficiency: Over to 96% Peak Continuous Output Current: 15 A PFM Mode for Light-Load Efficiency Excellent Line and Load Transient Response Precision Reference: 1% Over-Temperature Output Voltage Range: 0.6 to 5.5 V Programmable Frequency: 200 kHz to 1 MHz Programmable Soft-Start Low Shutdown Current Adjustable Sourcing Current Limit Internal Boot Diode Thermal Shutdown Halogen and Lead Free, RoHS Compliant The FAN2365A utilizes Fairchild's constant on-time control architecture to provide excellent transient response and to maintain a relatively constant switching frequency. This device utilizes Pulse Frequency Modulation (PFM) mode to maximize light-load efficiency by reducing switching frequency when the inductor is operating in discontinuous conduction mode at light loads, while clamping the minimum frequency above the audible range with ultrasonic mode. Switching frequency and over-current protection can be programmed to provide a flexible solution for various applications. Output over-voltage, undervoltage, over-current, and thermal shutdown protections help prevent damage to the device during fault conditions. After thermal shutdown is activated, a hysteresis feature restarts the device when normal operating temperature is reached. Applications Mainstream Notebooks Servers and Desktop Computers Game Consoles Telecommunications Storage Base Stations Ordering Information Part Number Configuration Operating Temperature Range Output Current (A) FAN2365AMPX PFM with Ultrasonic Mode -40 to 125C 15 (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 Package 34-Lead, PQFN, 5.5 mm x 5.0 mm www.fairchildsemi.com FAN2365AMPX -- 6 A Synchronous Buck Regulator September 2015 VBIAS = 5V R11 10 C9 0.1F C10 2.2F PVCC VCC Ext EN VIN = 12V CIN 0.1F VIN CIN 2x10F PVIN C3 0.1F EN VOUT = 1.2V IOUT=0-6A BOOT L1 1.2H FAN2365A SW PGOOD ILIM SOFT START R5 1.5k C7 15nF R2 1.5k C4 0.1F R3 10k C5 100pF FREQ COUT 4x47F FB R9 54.9k AGND R6 4.99k PGND Figure 1. R4 10k Typical Application Functional Block Diagram VIN BOOT PVIN FAN2365AMPX -- 15 A Synchronous Buck Regulator Typical Application Diagram PVCC PVCC VCC VCC VCC UVLO 0.8V/ 2.0V PVCC EN ENABLE VCC VCC 10A Modulator HS Gate Driver SS FB FB Comparator VREF SW FREQ Control Logic x1.2 2nd Level Over Voltage Comparator x1.1 1st Level Over Voltage Comparator x0.9 Under Voltage Comparator PFM Comparator PVCC LS Gate Driver VCC PGOOD Thermal Shutdown 10A Current Limit Comparator AGND ILIM Figure 2. (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 PGND Block Diagram www.fairchildsemi.com 2 9 VIN PVIN 9 SW PVIN 8 BOOT PVIN 7 AGND PVIN 6 PVIN PVIN 5 PVIN AGND 4 PVIN BOOT 3 PVIN SW 2 PVIN VIN 1 8 7 6 5 4 3 2 1 10 PVIN PVIN 10 34 NC 11 PVIN PVIN 11 33 NC 12 SW SW 12 32 FREQ 13 SW SW 13 31 SS 14 SW SW 30 PGOOD 29 15 SW SW 15 29 EN NC 28 16 SW SW 16 28 NC FB 27 17 SW SW 17 27 FB 24 23 22 21 20 PVCC ILIM AGND SW PGND PGND 19 18 Figure 3. Pin Assignments, Bottom View 18 19 20 21 22 23 24 25 26 VCC 26 25 VCC EN 14 PVCC SW (P3) PGOOD 30 ILIM AGND (P1) AGND 31 SW SS PGND 32 PGND FREQ PGND 33 PGND NC PVIN (P2) PGND 34 PGND NC Figure 4. Pin Assignments, Top View Pin Definitions Name Pad / Pin PVIN P2, 5-11 Description Power input for the power stage. VIN 1 Input to the modulator for input voltage feed-forward. PVCC 25 Power supply input for the low-side gate driver and boot diode. VCC 26 Power supply input for the controller. PGND 18-21 AGND P1, 4, 23 SW Power ground for the low-side power MOSFET and for the low-side gate driver. Analog ground for the analog portions of the IC and substrate. P3, 2, 12-17, 22 Switching node; junction between high-and low-side MOSFETs. BOOT 3 Supply for high-side MOSFET gate driver. A capacitor from BOOT to SW supplies the charge to turn on the N-channel high-side MOSFET. During the freewheeling interval (low-side MOSFET on), the high-side capacitor is recharged by an internal diode connected to PVCC. ILIM 24 Current limit. A resistor between ILIM and SW sets the current limit threshold. FB 27 Output voltage feedback to the modulator. EN 29 Enable input to the IC. Pin must be driven logic high to enable, or logic low to disable. SS 31 Soft-start input to the modulator. FREQ 32 On-time and frequency programming pin. Connect a resistor between FREQ and AGND to program on-time and switching frequency. PGOOD 30 Power good; open-drain output indicating VOUT is within set limits. NC 28, 33-34 Leave pin open or connect to AGND. (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 www.fairchildsemi.com 3 FAN2365AMPX -- 15 A Synchronous Buck Regulator Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VPVIN VIN VBOOT VSW VBOOT Parameter Conditions Min. Max. Unit Power Input Referenced to PGND -0.3 30.0 V Modulator Input Referenced to AGND -0.3 30.0 V Referenced to PVCC -0.3 30.0 V Referenced to PVCC, <20 ns -0.3 33.0 V Referenced to PGND, AGND -1 30 V Referenced to PGND, AGND < 20 ns -5 30 V 6.0 V Boot Voltage SW Voltage to GND Boot to SW Voltage Referenced to SW -0.3 Boot to PGND Referenced to PGND -0.3 30 V VPVCC Gate Drive Supply Input Referenced to PGND, AGND -0.3 6.0 V VVCC Controller Supply Input Referenced to PGND, AGND -0.3 6.0 V VILIM Current Limit Input Referenced to AGND -0.3 6.0 V VFB Output Voltage Feedback Referenced to AGND -0.3 6.0 V VEN Enable Input Referenced to AGND -0.3 6.0 V VSS Soft Start Input Referenced to AGND -0.3 6.0 V VFREQ Frequency Input Referenced to AGND -0.3 6.0 V Power Good Output Referenced to AGND -0.3 6.0 V 1000 V VPGOOD ESD Electrostatic Discharge TJ Junction Temperature TSTG Storage Temperature Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101 -55 2500 V +150 C +150 C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VPVIN Parameter Conditions Min Max. Unit Power Input Referenced to PGND 4.5 24.0 V VIN Modulator Input Referenced to AGND 4.5 24.0 V TJ Junction Temperature -40 +125 C 20 A 5.5 V ILOAD PVCC Load Current TA=25C, No Airflow Gate Drive Supply Input Referenced to PGND, AGND 4.5 Thermal Characteristics The thermal characteristics were evaluated on a 4-layer pcb structure (1 oz/1 oz/1 oz/1 oz) measuring 7 cm x 7 cm). Symbol Parameter Typ. Unit JA Thermal Resistance, Junction-to-Ambient 35 C/W JC Thermal Characterization Parameter, Junction-to-Top of case 2.7 C/W JPB Thermal Characterization Parameter, Junction-to-PCB 2.3 C/W (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 www.fairchildsemi.com 4 FAN2365AMPX -- 15 A Synchronous Buck Regulator Absolute Maximum Ratings Unless otherwise noted; VIN=12 V, VOUT=1.2 V, and TA=TJ = -40 to +125C. Symbol Parameter (1) Condition Min. Typ. Max. Unit 10 A 1.8 mA Supply Current IVCC,SD Shutdown Current EN=0 V IVCC,Q Quiescent Current EN=5 V, Not Switching IVCC,GateCharge Gate Charge Current EN=5 V, fSW=500 kHz 22 mA Reference, Feedback Comparator VFB FB Voltage Trip Point 592 596 602 mV IFB FB Pin Bias Current -100 0 100 nA 20 % Modulator tON On-Time Accuracy RFREQ=56.2 k, VIN=10 V, tON=250 ns, No Load -20 tON,PFM PFM On-Time Multiplier 150 tOFF,MIN Minimum SW Off-Time 320 tON,MIN Minimum SW On-Time DMIN Minimum Duty Cycle fMINF Minimum Frequency Clamp FB=1 V % 374 ns 45 ns 0 % 18.2 25.4 32.7 kHz 10 13 A 100 % Soft-Start ISS tON,SSMOD Soft-Start Current SS=0.5 V 7 SS On-Time Modulation SS<0.6 V 25 VSSCLAMP,NOM Nominal Soft-Start Voltage Clamp VSSCLAMP,OVL Soft-Start Voltage Clamp in Overload Condition VFB=0.6 V 400 mV VFB=0.3 V, OC Condition 40 mV PFM Zero-Crossing Detection Comparator VOFF ZCD Offset Voltage TA=TJ=25C -6 0 mV TA=TJ=25C, IVALLEY=18 A -10 10 % -1 1 mV Current Limit ILIM VILIM,OFFSET Valley Current Limit Accuracy Comparator Offset KILIM ILIM Set-Point Scale Factor ILIMTC Temperature Coefficient 85 4000 ppm/C Continued on the following page... (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 www.fairchildsemi.com 5 FAN2365AMPX -- 15 A Synchronous Buck Regulator Electrical Characteristics Unless otherwise noted; VIN=12 V, VOUT=1.2 V, and TA=TJ = -40 to +125C. Symbol Parameter (1) Condition Min. Typ. Max. Unit 2.0 V Enable VTH+ Rising Threshold VTH- Falling Threshold IENLK Enable Pin Leakage EN=1.2 V 0.8 100 nA V IENLK Enable Pin Leakage EN=5 V 76 A UVLO VON VCC Good Threshold Rising VHYS Hysteresis Voltage 4.4 160 V mV Fault Protection VUVP PGOOD UV Trip Point On FB Falling 86 89 92 % VVOP1 PGOOD OV Trip Point On FB Rising 108 111 115 % VOVP2 Second OV Trip Point On FB Rising; LS=On 118 122 125 % PGOOD Pull-Down Resistance IPGOOD=2 mA 125 2.03 ms 1 A RPGOOD tPG,SSDELAY PGOOD Soft-Start Delay IPG,LEAK PGOOD Leakage Current 0.82 1.42 Thermal Shutdown TOFF THYS Thermal Shutdown Trip Point Hysteresis (2) (2) 155 C 15 C Internal Bootstrap Diode VFBOOT Forward Voltage IF=10 mA 0.6 V IR Reverse Leakage VR=24 V 1000 A Notes: 1. Device is 100% production tested at TA=25C. Limits over that temperature are guaranteed by design. 2. Guaranteed by design; not production tested. (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 www.fairchildsemi.com 6 FAN2365AMPX -- 15 A Synchronous Buck Regulator Electrical Characteristics (Continued) 100 100 90 90 80 80 Efficiency (%) Efficiency (%) Tested using evaluation board circuit shown in Figure 1 with VIN=19 V, VOUT=1.2 V, fSW=500 kHz, TA=25C, and no airflow; unless otherwise specified. 70 60 50 19VIN_1.05VOUT_500KHZ_0.4UH 19VIN_1.2VOUT_500KHZ_0.56UH 19VIN_3.3VOUT_500KHZ_1.2UH 19VIN_5VOUT_500KHZ_1.2UH 40 30 20 0.01 0.1 1 Load Current (A) 60 50 30 20 0.01 10 20 90 90 80 80 Efficiency (%) 100 70 60 50 70 60 50 12VIN_1.2VOUT_300KHZ_0.72UH 12VIN_1.2VOUT_500KHZ_0.56UH 12VIN_1.2VOUT_1MHZ_0.3UH 40 19VIN_1.2VOUT_300KHZ_0.72UH 19VIN_1.2VOUT_500KHZ_0.56UH 19VIN_1.2VOUT_1MHZ_0.3UH 30 10 20 0.1 1 Load Current (A) Figure 6. Efficiency vs. Load Current with VIN=12 V and fSW=500 kHz 100 40 30 20 20 0.01 0.1 1 Load Current (A) 0.01 10 20 Figure 7. Efficiency vs. Load Current with VIN=19 V and VOUT=1.2 V Figure 8. 100 100 95 95 90 10 20 0.1 1 Load Current (A) Efficiency vs. Load Current with VIN=12 V and VOUT=1.2 V 90 Efficiency (%) Efficiency (%) 12VIN_1.05VOUT_500KHZ_0.4UH 12VIN_1.2VOUT_500KHZ_0.56UH 12VIN_3.3VOUT_500KHZ_1.2UH 12VIN_5VOUT_500KHZ_1.2UH 40 Figure 5. Efficiency vs. Load Current with VIN=19 V and fSW=500 kHz Efficiency (%) 70 85 19VIN_5VOUT_500KHZ_1.2UH 80 19VIN_3.3VOUT_500KHZ_1.2UH 75 19VIN_1.2VOUT_300KHZ_0.72UH 85 12VIN_5VOUT_500KHZ_1.2UH 12VIN_3.3VOUT_500KHZ_1.2UH 12VIN_1.2VOUT_300KHZ_0.72UH 12VIN_1.2VOUT_500KHZ_0.56UH 12VIN_1.05VOUT_500KHZ_0.4UH 12VIN_1.2VOUT_1MHZ_0.3UH 80 19VIN_1.2VOUT_500KHZ_0.56UH 70 75 19VIN_1.05VOUT_500KHZ_0.4UH 19VIN_1.2VOUT_1MHZ_0.3UH 65 70 0 5 10 15 20 0 Load Current (A) Figure 9. Efficiency vs. Load Current with VIN=19 V (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 Figure 10. 5 10 Load Current (A) 15 20 Efficiency vs. Load Current with VIN=12 V www.fairchildsemi.com 7 FAN2365AMPX -- 15 A Synchronous Buck Regulator Typical Performance Characteristics Tested using evaluation board circuit shown in Figure 1 with VIN=19 V, VOUT=1.2 V, fSW=500 kHz, TA=25C, and no airflow; unless otherwise specified. Efficiency (%) 100 90 80 70 60 5VIN_1.2VOUT_500KHZ_0.56UH 50 8VIN_1.2VOUT_500KHZ_0.56UH 40 12VIN_1.2VOUT_500KHZ_0.56UH 19VIN_1.2VOUT_500KHZ_0.56UH 30 20 0.01 0.1 Figure 11. 1 Load Current (A) 10 20 Efficiency vs. Load Current with VOUT=1.2 V and fSW=500 kHz 80 12VIN_1.2VOUT_1MHz_0.23uH 12VIN_1.2VOUT_500kHz_0.56uH 12VIN_1.2VOUT_300kHz_0.72uH 80 70 Case Temperature Rise (C) Case Temperature Rise (C) 90 60 50 40 30 20 10 19VIN_1.2VOUT_1MHz_0.23uH 70 19VIN_1.2VOUT_500kHz_0.56uH 60 19VIN_1.2VOUT_300kHz_0.72uH 50 40 30 20 10 0 0 0 5 10 15 Load Current (A) 0 20 5 10 15 Load Current (A) 20 Figure 12. Case Temperature Rise vs. Load Current on Figure 13. Case Temperature Rise vs. Load Current on 4 Layer PCB, 1 oz Copper, 7 cm x 7 cm 4 Layer PCB, 1 oz Copper, 7 cm x 7 cm 1.21 1.212 1.208 1.206 12VIN_1.2VOUT 1.208 Output Voltage (V) Output Voltage (V) 1.21 19VIN_1.2VOUT 1.206 1.204 1.202 1.204 1.202 1.2 0A_VOUT[V] 1.198 15A_VOUT[V] 1.196 1.194 1.2 1.192 1.198 1.19 0 2 4 6 8 10 12 14 16 18 20 7 Load Current (A) 11 13 15 17 19 21 23 25 Input Voltage (V) Figure 15. Line Regulation Figure 14. Load Regulation (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 9 www.fairchildsemi.com 8 FAN2365AMPX -- 15 A Synchronous Buck Regulator Typical Performance Characteristics Tested using evaluation board circuit shown in Figure 1 with VIN=19 V, VOUT=1.2 V, fSW=500 kHz, TA=25C, and no airflow; unless otherwise specified. EN (5V/div) VIN=19V IOUT=0A EN (5V/div) VIN=19V IOUT=15A Soft Start (0.5V/div) Soft Start (0.5V/div) VOUT (0.5V/div) VOUT (0.5V/div) PGOOD (5V/div) PGOOD (5V/div) Time (500s/div) Time (500s/div) Figure 16. Startup Waveforms with 0 A Load Current Figure 17. Startup Waveforms with 15 A Load Current EN (5V/div) EN (5V/div) VIN=19V IOUT=0A Soft Start (0.5V/div) Soft Start (0.5V/div) VOUT (0.5V/div) VIN=19V IOUT=15A Vout Prebias VOUT (0.5V/div) PGOOD (5V/div) PGOOD (5V/div) Time (500s/div) Time (200s/div) Figure 18. Shutdown Waveforms with 15 A Load Current Figure 19. Startup Waveforms with Prebias Voltage on Output VOUT (20mV/div) VOUT (20mV/div) VIN=19V IOUT=0A VIN=19V IOUT=15A VSW (10V/div) VSW (10V/div) Time (20s/div) Figure 20. Time (1s/div) Static Load Ripple at No Load (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 Figure 21. Static Load Ripple at Full Load www.fairchildsemi.com 9 FAN2365AMPX -- 15 A Synchronous Buck Regulator Typical Performance Characteristics Tested using evaluation board circuit shown in Figure 1 with VIN=19 V, VOUT=1.2 V, fSW=500 kHz, TA=25C, and no airflow; unless otherwise specified. VOUT (20mV/div) VOUT (20mV/div) VIN=19V VOUT=1.2V VIN=19V VOUT=1.2V IOUT (1A/div) IOUT (1A/div) Time (50s/div) Time (50s/div) Figure 22. Operation as Load Changes from 0 A to 3 A Figure 23. Operation as Load Changes from 3 A to 0 A VOUT (20mV/div) VOUT (20mV/div) VIN=19V, VOUT=1.2V IOUT from 0A to 7.5A, 2.5A/s IOUT (5A/div) IOUT (5A/div) VIN=19V, VOUT=1.2V IOUT from 7.5A to 15A, 2.5A/us Time (100s/div) Time (100s/div) Figure 24. Load Transient from 0% to 50% Load Current Figure 25. Load Transient from 50% to 100% Load Current PGOOD indicates UVP With VOUT falling in OCP PGOOD (5V/div) Level 2 VOUT (1V/div) VFB (0.5V/div) Pull VOUT to 3.8V through 3 resistor Level 1 VOUT (1V/div) Soft Start (1V/div) PGOOD (5V/div) IL (10A/div) IOUT=0A then short output VSW (10V/div) Time (20s/div) Figure 26. Over-Current Protection with Heavy Load Figure 27. Over-Voltage Protection Level 1 and Level 2 Applied (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 www.fairchildsemi.com 10 FAN2365AMPX -- 15 A Synchronous Buck Regulator Typical Performance Characteristics The FAN2365A uses a constant on-time modulation architecture with a VIN feed-forward input to accommodate a wide VIN range. This method provides fixed switching frequency (fSW ) operation when the inductor operates in Continuous Conduction Mode (CCM) and variable frequency when operating in Pulse Frequency Mode (PFM) at light loads. Additional benefits include excellent line and load transient response, cycle-by-cycle current limiting, and no loop compensation is required. At the beginning of each cycle, FAN2365A turns on the high-side MOSFET (HS) for a fixed duration (tON). At the end of tON, HS turns off for a duration (tOFF) determined by the operating conditions. Once the FB voltage (VFB) falls below the reference voltage (VREF), a new switching cycle begins. The modulator provides a minimum off-time (tOFF-MIN) of 320 ns to provide a guaranteed interval for low-side MOSFET (LS) current sensing and PFM operation. tOFFMIN is also used to provide stability against multiple pulsing and limits maximum switching frequency during transient events. (3) where RFREQ is the frequency-setting resistor described in the Setting Switching Frequency section; CtON is the internal 2.2 pF capacitor; and ItON is the VIN feed-forward current that generates the on-time. The FAN2365A implements open-circuit detection on the FREQ pin to protect the output from an infinitely long on-time. In the event the FREQ pin is left floating, switching of the regulator is disabled. The FAN2365A is designed for VIN input range 4.5 to 24 V, fSW 200 kHz to 1 MHz, resulting in an ItON ratio exceeding 1 to 25. As the ratio of VOUT to VIN increases, tOFF,min introduces a limit on the maximum switching frequency as calculated in the following equation, where the factor 1.2 is included in the denominator to add some headroom for transient operation: (4) Soft-Start (SS) Enable A conventional soft-start ramp is implemented to provide a controlled startup sequence of the output voltage. A current is generated on the SS pin to charge an external capacitor. The lesser of the voltage on the SS pin and the reference voltage is used for output regulation. To reduce VOUT ripple and achieve a smoother ramp of the output voltage, tON is modulated during soft-start. tON starts at 50% of the steady-state on-time (PWM Mode) and ramps up to 100% gradually. During normal operation, the SS voltage is clamped to 400 mV above the FB voltage. The clamp voltage drops to 40 mV during an overload condition to allow the converter to recover using the soft-start ramp once the overload condition is removed. On-time modulation during SS is disabled when an overload condition exists. To maintain a monotonic soft-start ramp, the regulator is forced into PFM Mode during soft-start. The minimum frequency clamp is disabled during soft-start. The nominal startup time is programmable through an internal current source charging the external soft-start capacitor CSS: The enable pin is TTL compatible, which supports lowshutdown-current applications, such as notebooks. VCC should be applied after VIN / PVIN is applied to the circuit. The EN pin can be directly driven by logic voltages of 5 V, 3.3 V, 2.5 V, etc. If the EN pin is driven by 5 V logic, a small current flows into the pin when the EN pin voltage exceeds the internal clamp voltage of 4.3 V. To eliminate clamp current flowing into the EN pin use a voltage divider to limit the EN pin voltage to < 4 V. Constant On-Time Modulation The FAN2365A uses a constant on-time modulation technique, in which the HS MOSFET is turned on for a fixed time, set by the modulator, in response to the input voltage and the frequency setting resistor. This on-time is proportional to the desired output voltage, divided by the input voltage. With this proportionality, the frequency is essentially constant over the load range where inductor current is continuous. For buck converter in Continuous-Conduction Mode (CCM), the switching frequency fSW is expressed as: (5) (1) where: The on-time generator sets the on-time (tON) for the high-side MOSFET, which results in the switching frequency of the regulator during steady-state operation. To maintain a relatively constant switching frequency over a wide range of input conditions, the input voltage information is fed into the on-time generator. tON is determined by: CSS ISS tSS VREF For example; for 1 ms startup time, CSS=15 nF. The soft-start option can be used for ratiometric tracking. When EN is LOW, the soft-start capacitor is discharged. (2) where ItON is: (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 = External soft-start programming capacitor; = Internal soft-start charging current source, 10 A; = Soft-start time; and = 600 mV www.fairchildsemi.com 11 FAN2365AMPX -- 15 A Synchronous Buck Regulator Circuit Operation a minimum value of 18 kHz. The LS MOSFET is turned on to discharge the output and trigger a new PWM cycle. FAN2365A allows the regulator to start on a pre-bias output, VOUT, and ensures VOUT is not discharged during the soft-start operation. Protection Features The converter output is monitored and protected against over-current, over-voltage, under-voltage, and hightemperature conditions. To guarantee no glitches on VOUT at the beginning of the soft-start ramp, the LS is disabled until the first positivegoing edge of the PWM signal. The regulator is also forced into PFM Mode during soft-start to ensure the inductor current remains positive, reducing the possibility of discharging the output voltage. Over-Current Protection (OCP) The FAN2365A uses current information through the LS to implement valley-current limiting. While an OC event is detected, the HS is prevented from turning on and the LS is kept on until the current falls below the userdefined set point. Once the current is below the set point, the HS is allowed to turn on. PVCC The FAN2365A requires an external source connected to the PVCC to supply power to the internal gate drivers. The PVCC pin should be bypassed with a 2.2 F ceramic capacitor. During an OC event, the output voltage may droop if the load current is greater than the current the converter is providing. If the output voltage drops below the UV threshold, an overload condition is triggered. During an overload condition, the SS clamp voltage is reduced to 40 mV and the on-time is fixed at the steady-state duration. By nature of the control method; as VOUT drops, the switching frequency is lower due to the reduced rate of inductor current decay during the off-time. VCC Bias Supply and UVLO The VCC rail supplies power to the controller. It is generally connected to the PVCC rail through a lowpass filter of a 10 resistor and 0.1 F capacitor to minimize any noise sources from the driver supply. An Under-Voltage Lockout (UVLO) circuit monitors the VCC voltage to ensure proper operation. Once the VCC voltage is above the UVLO threshold, the part begins operation after an initialization routine of 50 s. There is no UVLO circuitry on either the PVCC or VIN rails. The ILIM pin has an open-detection circuit to provide protection against operation without a current limit. Under-Voltage Protection (UVP) If VFB is below the under-voltage threshold of -11% VREF (534 mV), the part enters UVP and PGOOD pulls LOW. Pulse Frequency Modulation (PFM) Over-Voltage Protection (OVP) There are two levels of OV protection: +11% and +22%. During an over-voltage event, PGOOD pulls LOW. One of the key benefits of using a constant on-time modulation scheme is the seamless transitions in and out of Pulse Frequency Modulation (PFM) Mode. The PWM signal is not slave to a fixed oscillator and, therefore, can operate at any frequency below the target steady-state frequency. By reducing the frequency during light-load conditions, the efficiency can be significantly improved. When VFB is > +11% of VREF (666 mV), both HS and LS turn off. By turning off the LS during an OV event, V OUT overshoot can be reduced when there is positive inductor current by increasing the rate of discharge. Once the VFB voltage falls below VREF, the latched OV signal is cleared and operation returns to normal. The FAN2365A provides a Zero-Crossing Detector (ZCD) circuit to identify when the current in the inductor reverses direction. To improve efficiency at light load, the LS MOSFET is turned off around the zero crossing to eliminate negative current in the inductor. For predictable operation entering PFM mode the controller waits for nine consecutive zero crossings before allowing the LS MOSFET to turn off. A second over-voltage detection is implemented to protect the load from more serious failure. When VFB rises +22% above the VREF (732 mV), the HS latches off until a power cycle on VCC and the LS is forced on until 530 mV of VFB. Over-Temperature Protection (OTP) The FAN2365A incorporates an over-temperature protection circuit that disables the converter when the die temperature reaches 155C. The IC restarts when the die temperature falls below 140C. In PFM Mode, fSW varies or modulates proportionally to the load; as load decreases, fSW also decreases. The switching frequency, while the regulator is operating in PFM, can be expressed as: Power Good (PGOOD) The PGOOD pin serves as an indication to the system that the output voltage of the regulator is stable and within regulation. Whenever VOUT is outside the regulation window or the regulator is at overtemperature (UV, OV, and OT), the PGOOD pin is pulled LOW. (6) where L is inductance and IOUT is output load current. Minimum Frequency Clamp To maintain a switching frequency above the audible range, the FAN2365A clamps the switching frequency to (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 PGOOD is an open-drain output that asserts LOW when VOUT is out of regulation or when OT is detected. www.fairchildsemi.com 12 FAN2365AMPX -- 15 A Synchronous Buck Regulator Startup on Pre-Bias Stability Setting the Output Voltage (VOUT) Constant on-time stability consists of two parameters: stability criterion and sufficient signal at VFB. The output voltage VOUT is regulated by initiating a highside MOSFET on-time interval when the valley of the divided output voltage appearing at the FB pin reaches VREF. Since this method regulates at the valley of the output ripple voltage, the actual DC output voltage on VOUT is offset from the programmed output voltage by the average value of the output ripple voltage. The initial VOUT setting of the regulator can be programmed from 0.6 V to 5.5 V by an external resistor divider (R3 and R4): Stability criterion is given by: (7) Sufficient signal requirement is given by: (8) where IIND is the inductor current ripple and VFB is the ripple voltage on VFB, which should be 12 mV. In certain applications, especially designs utilizing only ceramic output capacitors, there may not be sufficient ripple magnitude available on the feedback pin for stable operation. In this case, an external circuit consisting of 2 resistors (R2 and R6) and 2 capacitors (C4 and C5) can be added to inject ripple voltage into the FB pin (See Figure 1). There are some specific considerations when selecting the RCC ripple injector circuit. For typical applications, use 4.99 k for R6; the value of C4 can be selected as 0.1 F and approximate values for R2 and C5 can be determined using the following equations. (13) where VREF is 600 mV. For example; for 1.2 V VOUT and 10 k R3, then R4 is 10 k. For 600 mV VOUT, R4 is left open. VFB is trimmed to a value of 596 mV when VREF=600 mV, so the final output voltage, including the effect of the output ripple voltage, can be approximated by the equation: (14) Setting the Switching Frequency (fSW) fSW is programmed through external RFREQ as follows: R2 must be small enough to develop 12 mV of ripple: (15) (9) R2 must be selected such that the R2C4 time constant enables stable operation: where CtON=2.2 pF internal capacitor that generates tON. For example; for fSW=500 kHz and VOUT=1.2 V, select a standard value for RFREQ=54.9 k. Inductor Selection (10) The minimum value of C5 can be selected to minimize the capacitive component of ripple appearing on the feedback pin: (11) Using the minimum value of C5 generally offers the best transient response, and 100pF is a good initial value in many applications. However, under some operating conditions excessive pulse jitter may be observed. To reduce jitter and improve stability, the value of C5 can be increased: (12) 5 V PVCC The PVCC is supplied from an external source to provide power to the drivers and VCC. It is crucial to keep this pin decoupled to PGND with a 1 F X5R or X7R ceramic capacitor. Because VCC powers internal analog circuit, it is filtered from PVCC with a 10 resistor and 0.1 F X7R decoupling ceramic capacitor to AGND. The inductor is typically selected based on the ripple current (IL), which is approximately 25% to 45% of the maximum DC load. The inductor current rating should be selected such that the saturation and heating current ratings exceed the intended currents encountered in the application over the expected temperature range of operation. Regulators that require fast transient response use smaller inductance and higher current ripple; while regulators that require higher efficiency keep ripple current on the low side. The inductor value is given by: (16) For example: for 19 V VIN, 1.2 V VOUT, 15 A load, 25% IL, and 500 kHz fSW; L is 576 nH, and a standard value of 560 nH is selected. Input Capacitor Selection Input capacitor CIN is selected based on voltage rating, RMS current ICIN(RMS) rating, and capacitance. For capacitors having DC voltage bias derating, such as ceramic capacitors, higher rating is strongly recommended. RMS current rating is given by: (17) (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 www.fairchildsemi.com 13 FAN2365AMPX --- 15 A Synchronous Buck Regulator Application Information The capacitance is given by: onto the ILIM pin, which creates a voltage across the resistor. When the voltage on ILIM goes negative, an over-current condition is detected. RILIM is calculated by: (18) where VIN is the input voltage ripple, normally 1% of VIN. For example; for VIN=19 V, VIN=120 mV, VOUT=1.2 V, 15 A load, and fSW=500 kHz; CIN is 14.8 F and ICIN(RMS) is 3.64 ARMS. Select a minimum of three 10 F 25 Vrated ceramic capacitors with X7R or similar dielectric, recognizing that the capacitor DC bias characteristic indicates that the capacitance value falls approximately 60% at VIN=19 V, with a resultant small increase in VIN ripple voltage above 120 mV used in the calculation. Also, each 10 F can carry over 3 ARMS in the frequency range from 100 kHz to 1 MHz, exceeding the input capacitor current rating requirements. An additional 0.1 F capacitor may be needed to suppress noise generated by high frequency switching transitions. Output Capacitor Selection Output capacitor COUT is selected based on voltage rating, RMS current ICOUT(RMS) rating, and capacitance. For capacitors having DC voltage bias derating, such as ceramic capacitors, higher rating is highly recommended. When calculating COUT, usually the dominant requirement is the current load step transient. If the unloading transient requirement (IOUT transitioning from HIGH to LOW), is satisfied, then the load transient (IOUT transitioning LOW to HIGH), is also usually satisfied. The unloading COUT calculation, assuming COUT has negligible parasitic resistance and inductance in the circuit path, is given by: (19) where IMAX and IMIN are maximum and minimum load steps, respectively and VOUT is the voltage overshoot, usually specified at 3 to 5%. For example: for VI=19 V, VOUT=1.2 V, 10 A IMAX, 5 A IMIN, fSW=500 kHz, LOUT=560 nH, and 3% VOUT ripple of 36 mV; the COUT value is calculated to be 360 F. This capacitor requirement can be satisfied using eight 47 F, 6.3 V-rated X5R ceramic capacitors. This calculation applies for load current slew rates that are faster than the inductor current slew rate, which can be defined as VOUT/L during the load current removal. Setting the Current Limit (20) where KILIM is the current source scale factor, and IVALLEY is the inductor valley current when the current limit threshold is reached. The factor 1.08 accounts for the temperature offset of the LS MOSFET compared to the control circuit. With the constant on-time architecture, HS is always turned on for a fixed on-time; this determines the peakto-peak inductor current. Current ripple I is given by: (21) From the equation above, the worst-case ripple occurs during an output short circuit (where VOUT is 0 V). This should be taken into account when selecting the current limit set point. The FAN2365A uses valley-current sensing, the current limit (IILIM) set point is the valley (IVALLEY). The valley current level for calculating RILIM is given by: (22) where ILOAD (CL) is the DC load current when the current limit threshold is reached.. For example: In a converter designed for 15 A steadystate operation and 4.5 A current ripple, the current-limit threshold could be selected at 120% of ILOAD,(MAX) to accommodate transient operation and inductor value decrease under loading. As a result, ILOAD,(MAX) is 18 A, IVALLEY=15.75 A, and RILIM is selected as the standard value of 1.47 k Boot Resistor In some applications, especially with higher input voltage, the VSW ring voltage may exceed derating guidelines of 80% to 90% of absolute rating for VSW. In this situation a resistor can be connected in series with boot capacitor (C3 in Figure 1) to reduce the turn-on speed of the high side MOSFET to reduce the amplitude of the VSW ring voltage. If necessary, a resistor and capacitor snubber can be added from VSW to PGND to reduce the magnitude of the ringing voltage. Please contact Fairchild Customer Support for assistance selecting a boot resistor or snubber circuit in applications that operate above a 21 V typical input voltage. Current limit is implemented by sensing the inductor valley current across the LS MOSFET VDS during the LS on-time. The current limit comparator prevents a new on-time from being started until the valley current is less than the current limit. The set point is configured by connecting a resistor from the ILIM pin to the SW pin. A trimmed current is output (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 www.fairchildsemi.com 14 FAN2365AMPX --- 15 A Synchronous Buck Regulator where ILOAD-MAX is the maximum load current and D is the duty cycle VOUT/VIN. The maximum ICIN(RMS) occurs at 50% duty cycle. The following points should be considered before beginning a PCB layout using the FAN2365A. A sample PCB layout from the evaluation board is shown in Figure 28-Figure 31 following the layout guidelines. The current return path from PGND at the low-side MOSFET source to the negative terminal of the input capacitor can be routed under the inductor and also through vias that connect the input capacitor and lowside MOSFET source to the PGND region under the power portion of the IC. Power components consisting of the input capacitors, output capacitors, inductor, and device should be placed on a common side of the pcb in close proximity to each other and connected using surface copper. The SW node trace which connects the source of the high-side MOSFET and the drain of the low-side MOSFET to the inductor should be short and wide. Sensitive analog components including SS, FB, ILIM, FREQ, and EN should be placed away from the highvoltage switching circuits such as SW and BOOT, and connected to their respective pins with short traces. To control the voltage across the output capacitor, the output voltage divider should be located close to the FB pin, with the upper FB voltage divider resistor connected to the positive side of the output capacitor, and the bottom resistor should be connected to the AGND portion of the device. The inner PCB layer closest to the device should have Power Ground (PGND) under the power processing portion of the device (PVIN, SW, and PGND). This inner PCB layer should have a separate Analog Ground (AGND) under the P1 pad and the associated analog components. AGND and PGND should be connected together near the IC between PGND pins 18-21 and AGND pin 23 which connects to P1 thermal pad. When using ceramic capacitor solutions with external ramp injection circuitry (R2, C4, C5 in Figure 1), R2 and C4 should be connected near the inductor, and coupling capacitor C5 should be placed near FB pin to minimize FB pin trace length. The AGND thermal pad (P1) should be connected to AGND plane on inner layer using four 0.25 mm vias spread under the pad. No vias are included under PVIN (P2) and SW (P3) to maintain the PGND plane under the power circuitry intact. Decoupling capacitors for PVCC and VCC should be located close to their respective device pins. SW node connections to BOOT, ILIM, and ripple injection resistor R2 should be made through separate traces. Power circuit loops that carry high currents should be arranged to minimize the loop area. Primary focus should be directed to minimize the loop for current flow (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 www.fairchildsemi.com 15 FAN2365AMPX -- 15 A Synchronous Buck Regulator from the input capacitor to PVIN, through the internal MOSFETs, and returning to the input capacitor. The input capacitor should be placed as close to the PVIN terminals as possible. Printed Circuit Board (PCB) Layout Guidelines FAN2365AMPX -- 15 A Synchronous Buck Regulator Figure 28. Figure 29. (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 Evaluation Board Top Layer Copper Evaluation Board Inner Layer 1 Copper www.fairchildsemi.com 16 FAN2365AMPX -- 15 A Synchronous Buck Regulator (c) 2015 Fairchild Semiconductor Corporation FAN2365AMPX * Rev. 1.0 Figure 30. Evaluation Board Inner Layer 2 Copper Figure 31. Evaluation Board Bottom Layer Copper www.fairchildsemi.com 17 5.500.10 26 18 1.050.10 17 27 0.250.05 (30X) 5.000.10 34 0.250.05 0.0250.025 10 1 9 SEATING PLANE PIN#1 INDICATOR SEE DETAIL 'A' 1.580.01 (0.35) SCALE: 2:1 2.180.01 (0.43) 0.500.01 9 1 (0.25) 0.400.01 (30X) (0.35) 34 10 0.680.01 (0.35) 3.500.01 2.580.01 (1.75) 17 (0.75) (0.33) (0.35) 27 0.430.01 18 26 (0.35) NOTES: UNLESS OTHERWISE SPECIFIED A) NO INDUSTRY REGISTRATION APPLIES. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009. E) DRAWING FILE NAME: MKT-PQFN34AREV2 F) FAIRCHILD SEMICONDUCTOR (0.25) (0.28) (3X) (0.24) 1.750.01 5.70 2.18 1.58 0.55 (30X) 2.10 (0.35) 1.80 26 18 0.55 17 27 (1.75) 2.58 4.10 3.50 3.60 (1.85) 0.68 34 10 0.75 1 (0.30) 9 (0.35) 0.500.05 0.43 (0.08) 4.10 LAND PATTERN RECOMMENDATION 0.20 0.30 (30X) 5.20 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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