This is information on a product in full production.
December 2015 DocID10518 Rev 13 1/32
STM706T/S/R, STM706P,
STM708T/S/R
3 V supervisor
Datasheet - production data
Features
•Precision VCC monitor
– T: 3.00 V
≤
VRST
≤
3.15 V
–S: 2.88 V
≤
VRST
≤
3.00 V
– R: STM706P: 2.59 V
≤
VRST
≤
2.70 V
•RST and RST outputs
•200 ms (typ.) trec
•Watchdog timer - 1.6 s (typ.)
•Manual reset input (MR)
•Power-fail comparator (PFI/PFO)
•Low supply current - 40 µA (typ.)
•Guaranteed RST (RST) assertion down to
VCC = 1.0 V
•Operating temperature: –40 °C to 85 °C
(industrial grade)
•RoHS compliance
– Lead-free components are compliant with
the RoHS directive
Applications
•Computers
•Controllers
•Intelligent instruments
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Table 1. Device summary
Watchdog
input
Watchdog
output(1)
Active low
RST (1)
1. Push-pull output.
Active high
RST(1)
Manual
reset input
Power-fail
comparator
STM706T/S/R ✓✓ ✓ ✓ ✓
STM706P(2)
2. The STM706P device is identical to the STM706R device, except its reset output is active high.
✓✓ ✓ ✓ ✓
STM708T/S/R ✓✓✓✓
www.st.com
Contents STM706T/S/R, STM706P, STM708T/S/R
2/32 DocID10518 Rev 13
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 WDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 WDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.7 PFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Push-button reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.3 Watchdog input (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . .11
3.4 Watchdog output (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . .11
3.5 Power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 Ensuring a valid reset output down to VCC = 0 V . . . . . . . . . . . . . . . . . . . 12
3.7 Interfacing to microprocessors with bi-directional reset pins . . . . . . . . . . 13
4 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1 SO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2 TSSOP8 3x3 (DS) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DocID10518 Rev 13 3/32
STM706T/S/R, STM706P, STM708T/S/R List of tables
3
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. SO8 - 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . . . 27
Table 8. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size,
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 9. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
List of figures STM706T/S/R, STM706P, STM708T/S/R
4/32 DocID10518 Rev 13
List of figures
Figure 1. Logic diagram (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic diagram (STM708T/S/R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. STM706T/S/R and STM706P SO8 connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. STM706T/S/R and STM706P TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. STM708T/S/R SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. STM708T/S/R TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. Block diagram (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Block diagram (STM708T/S/R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10. Reset output valid to ground circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Interfacing to microprocessors with bi-directional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13. VPFI threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14. Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. Power-up trec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. Watchdog timeout period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 18. PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 19. Output voltage vs. load current (VCC = 5 V; TA = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 20. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26. Power-fail comparator waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 28. Watchdog timing (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 29. SO8 - 8-lead plastic small outline, 150 mils body width, package outline. . . . . . . . . . . . . . 27
Figure 30. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, package outline. . . . . . . 28
DocID10518 Rev 13 5/32
STM706T/S/R, STM706P, STM708T/S/R Description
31
1 Description
The STM70x supervisors are self-contained devices which provide microprocessor
supervisory functions. A precision voltage reference and comparator monitors the VCC input
for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset output
(RST) is forced low (or high in the case of RST).
These devices also offer a watchdog timer (except for STM708T/S/R) as well as a power-fail
comparator to provide the system with an early warning of impending power failure.
The STM706P device is identical to the STM706R device, except its reset output is active
high. These devices are available in a standard 8-pin SOIC package or a space-saving 8-
pin TSSOP package.
Figure 1. Logic diagram (STM706T/S/R and STM706P)
1. For STM706P only.
Figure 2. Logic diagram (STM708T/S/R)
AI08841
VCC
STM706T/S/R,
STM706P
VSS
WDO
RST (RST)(1)
WDI
PFI
MR
PFO
AI08842
VCC
STM708T/S/R
VSS
RST
RST
MR
PFI
PFO
Description STM706T/S/R, STM706P, STM708T/S/R
6/32 DocID10518 Rev 13
Figure 3. STM706T/S/R and STM706P SO8 connections
1. For STM706P reset output is active high.
Figure 4. STM706T/S/R and STM706P TSSOP8 connections
1. For STM706P reset output is active high.
Figure 5. STM708T/S/R SO8 connections
Table 2. Signal names
Symbol Name
MR Push-button reset input
WDI Watchdog input
WDO Watchdog output
RST Active low reset output
RST(1)
1. For STM706P and STM708T/S/R only.
Active high reset output
VCC Supply voltage
PFI Power-fail input
PFO Power-fail output
VSS Ground
NC No connect
1
PFO
PFI
WDI
RST(RST)(1)
VCC
MR WDO
VSS
AI08837
SO8
2
3
4
8
7
6
5
1
PFO
PFI
WDI
RST(RST)(1)
VCC
MR
WDO
VSS
AI08838
TSSOP8
2
3
4
8
7
6
5
1
PFO
PFI
NC
RST
VCC
MR RST
VSS
AI08839
SO8
2
3
4
8
7
6
5
DocID10518 Rev 13 7/32
STM706T/S/R, STM706P, STM708T/S/R Description
31
Figure 6. STM708T/S/R TSSOP8 connections
1
PFO
PFI
NC
RST
VCC
MR
RST
VSS
AI08840
TSSOP8
2
3
4
8
7
6
5
Pin descriptions STM706T/S/R, STM706P, STM708T/S/R
8/32 DocID10518 Rev 13
2 Pin descriptions
2.1 MR
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for trec after MR returns high. This active low input has an internal pull-up. It can be
driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
2.2 WDI
If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset (or
WDO) is triggered. The internal watchdog timer clears while reset is asserted or when WDI
sees a rising or falling edge.
The watchdog function can be disabled by allowing the WDI pin to float. This feature is
available for the “D” version only (see Section 8: Part numbering).
2.3 WDO
WDO goes low when a transition does not occur on WDI within 1.6 s, and remains low until
a transition occurs on WDI (indicating the watchdog interrupt has been serviced) or MR
input is asserted (goes low). WDO also goes low when VCC falls below the reset threshold;
however, unlike the reset output, WDO goes high as soon as VCC exceeds the reset
threshold. Output type is push-pull.
Note: For those devices with a WDO output, a watchdog timeout will not trigger reset unless WDO
is connected to MR.
2.4 RST
Pulses low for trec when triggered, and stays low whenever VCC is below the reset
threshold or when MR is a logic low. It remains low for trec after either VCC rises above the
reset threshold, the watchdog triggers a reset, or MR goes from low to high.
2.5 RST
Pulses high for trec when triggered, and stays high whenever VCC is above the reset
threshold or when MR is a logic high. It remains high for trec after either VCC falls below the
reset threshold, the watchdog triggers a reset, or MR goes from high to low.
2.6 PFI
When PFI is less than VPFI, PFO goes low; otherwise, PFO remains high. Connect to
ground if unused.
DocID10518 Rev 13 9/32
STM706T/S/R, STM706P, STM708T/S/R Pin descriptions
31
2.7 PFO
When PFI is less than VPFI, PFO goes low; otherwise, PFO remains high. Output type is
push-pull. PFO pin is not supposed to be forced low by a processor. MR input is gated off
during the period PFO is forced low. Leave open if unused.
Figure 7. Block diagram (STM706T/S/R and STM706P)
1. For STM706P only
Table 3. Pin description
Pin
Name Function STM706P STM706T/S/R STM708T/S/R
SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8
1 3 1 3 1 3 MR Push-button reset input
6 8 6 8 — — WDI Watchdog input
8 2 8 2 — — WDO Watchdog output (push-pull)
— — 7 1 7 1 RST Active low reset output
7 1 — — 8 2 RST Active high reset output
2 4 2 4 2 4 VCC Supply voltage
4 6 4 6 4 6 PFI Power-fail input
5 7 5 7 5 7 PFO Power-fail output (push-pull)
3 5 3 5 3 5 VSS Ground
— — — — 6 8 NC No connect
AI08829
WATCHDOG
TIMER
VRST
WDI
transitional
detector
COMPARE
COMPARE
trec
generator
VPFI
VCC
VCC
PFI
MR
WDI
RST (RST)(1)
PFO
WDO
Pin descriptions STM706T/S/R, STM706P, STM708T/S/R
10/32 DocID10518 Rev 13
Figure 8. Block diagram (STM708T/S/R)
Figure 9. Hardware hookup
1. For STM706T/S/R and STM706P devices
2. For STM706P and STM708T/S/R devices
AI08830
VRST
RST
COMPARE
COMPARE
trec
generator
VPFI
VCC
PFI
MR RST
PFO
VCC
AI08843
VCC
MR
PFI
0.1 μF
STM706T/S/R;
STM706P;
STM708T/S/R
WDI(1)
PFO
WDO(1)
RST(2)
RST To microprocessor reset
Unregulated
voltage
Regulator
VCC
VIN
R1
R2
From microprocessor
Push-button
To microprocessor NMI
To microprocessor IRQ
DocID10518 Rev 13 11/32
STM706T/S/R, STM706P, STM708T/S/R Operation
31
3 Operation
3.1 Reset output
The STM70x supervisor asserts a reset signal to the MCU whenever V
CC
goes below the
reset threshold (V
RST
), a watchdog timeout occurs (if WDO is connected to MR), or when the
push-button reset input (MR) is taken low. RST is guaranteed to be a logic low (logic high for
STM706P and STM708T/S/R) for V
CC
< V
RST
down to V
CC
=1 V for T
A
= 0 °C to 85 °C.
During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for
the reset timeout period, trec. After this interval RST returns high.
If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
low for at least the reset timeout period (trec). Any time VCC goes below the reset threshold
the internal timer clears. The reset timer starts when VCC returns above the reset threshold.
3.2 Push-button reset input
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see
Figure 27) after it returns high. The MR input has an internal 40 kΩ pull-up resistor, allowing
it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with
open-drain / collector outputs. Connect a normally open momentary switch from MR to GND
to create a manual reset function; external debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor
from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when
not used.
3.3 Watchdog input (STM706T/S/R and STM706P)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the watchdog input (WDI) within tWD (1.6 s), the watchdog output pin (WDO) is
asserted. The internal 1.6s timer is cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.
See Figure 28 for STM706T/S/R and STM706P.
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting.
Note: The watchdog function may be disabled by floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and
the maximum allowable load capacitance is 200 pF.
3.4 Watchdog output (STM706T/S/R and STM706P)
When VCC drops below the reset threshold, WDO will go low even if the watchdog timer has
not yet timed out. However, unlike the reset output, WDO goes high as soon as VCC
exceeds the reset threshold. WDO may be used to generate a reset pulse by connecting it
to the MR input.
Operation STM706T/S/R, STM706P, STM708T/S/R
12/32 DocID10518 Rev 13
3.5 Power-fail input/output
The power-fail input (PFI) is compared to an internal reference voltage (independent from
the VRST comparator). If PFI is less than the power-fail threshold (VPFI), the power-fail
output (PFO) will go low. This function is intended for use as an undervoltage detector to
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 9) to either the unregulated DC input (if it is available) or the regulated output of
the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below
VPFI several milliseconds before the regulated VCC input to the STM70x or the micro-
processor drops below the minimum operating voltage.
If the comparator is unused, PFI should be connected to VSS and PFO left unconnected.
PFO may be connected to MR on the STM70x so that a low voltage on PFI will generate
a reset output.
3.6 Ensuring a valid reset output down to VCC = 0 V
When VCC falls below 1 V, the state of the RST output can no longer be guaranteed, and
becomes essentially an open circuit. If a high value pulldown resistor is added to the RST
pin, the output will be held low during this condition. A resistor value of approximately
100 kΩ will be large enough to not load the output under operating conditions, but still
sufficient to pull RST to ground during this low voltage condition (see Figure 10).
Figure 10. Reset output valid to ground circuit
AI08844
STM70x
RST
R1
DocID10518 Rev 13 13/32
STM706T/S/R, STM706P, STM708T/S/R Operation
31
3.7 Interfacing to microprocessors with bi-directional reset pins
Microprocessors with bi-directional reset pins can contend with the STM70x reset output.
For example, if the reset output is driven high and the micro wants to pull it low, signal
contention will result. To prevent this from occurring, connect a 4.7kΩ resistor between the
reset output and the micro's reset I/O as in Figure 11.
Figure 11. Interfacing to microprocessors with bi-directional reset I/O
AI08845
STM70x
RST
GND
4.7 kΩ
VCC
Microprocessor
RST
Buffered reset to other
system components
GND
VCC
Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R
14/32 DocID10518 Rev 13
4 Typical operating characteristics
Typical values are at TA = 25 °C.
Figure 12. Supply current vs. temperature (no load)
Temperature (°C)
Supply current (µA)
AI09141b
0
5
10
15
20
25
30
–40 –20 0 20 40 60 80 100 120
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
VCC = 4.5 V
VCC = 5.5 V
DocID10518 Rev 13 15/32
STM706T/S/R, STM706P, STM708T/S/R Typical operating characteristics
31
Figure 13. VPFI threshold vs. temperature
Figure 14. Reset comparator propagation delay vs. temperature
Temperature (°C)
VPFI threshold (V)
1.225
1.230
1.235
1.240
1.245
1.250
1.255
1.260
1.265
1.270
–40 –20 0 20 40 60 80 100 120
VCC
= 2.5 V
VCC
= 3.0 V
VCC
= 3.3 V
VCC
= 3.6 V
AI09142b
Temperature (°C)
Propagation delay (µs)
AI09143b
10
12
14
16
18
20
22
24
26
28
30
–40 –20 0 20 40 60 80 100 120
Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R
16/32 DocID10518 Rev 13
Figure 15. Power-up trec vs. temperature
Figure 16. Normalized reset threshold vs. temperature
AI09144b
Temperature (°C)
trec (ms)
210
215
220
225
230
235
240
–40 –20 0 20 40 60 80 100 120
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
Temperature (°C)
Normalized threshold
AI09145b
0.996
0.998
1.000
1.002
1.004
–40 –20 0 20 40 60 80 100 120
reset
DocID10518 Rev 13 17/32
STM706T/S/R, STM706P, STM708T/S/R Typical operating characteristics
31
Figure 17. Watchdog timeout period vs. temperature
Figure 18. PFI to PFO propagation delay vs. temperature
Temperature (˚C)
Watchdog timeout period (s)
AI09146b
1.60
1.65
1.70
1.75
1.80
1.85
1.90
–40 –20 0 20 40 60 80 100 120
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
Temperature (˚C) AI09148b
PFI to PFO propagation dela
0.0
1.0
2.0
3.0
4.0
–40 –20 0 20 40 60 80 100 120
VCC = 3.0 V
VCC = 3.6 V
VCC = 4.5 V
VCC = 5.5 V
Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R
18/32 DocID10518 Rev 13
Figure 19. Output voltage vs. load current (VCC = 5 V; TA = 25 °C)
Figure 20. RST output voltage vs. supply voltage
4.94
4.96
4.98
5.00
0 1020304050
IOUT (mA)
VOUT (V)
AI10496
VRST (V)
VCC (V)
AI09149b
500 ms / div
VRST
VCC
0
1
2
3
4
5
0
1
2
3
4
5
DocID10518 Rev 13 19/32
STM706T/S/R, STM706P, STM708T/S/R Typical operating characteristics
31
Figure 21. RST output voltage vs. supply voltage
Figure 22. Power-fail comparator response time (assertion)
VRST (V)
VCC (V)
AI09150b
0
1
2
3
4
5
0
1
2
3
4
5
VRST
VCC
500 ms / div
9
 9
3),
9 GLY
9
 P9 GLY
9
 QV GLY
3)2
Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R
20/32 DocID10518 Rev 13
Figure 23. Power-fail comparator response time (de-assertion)
Figure 24. Maximum transient duration vs. reset threshold overdrive
9
 9
3),
9 GLY
9
 P9 GLY
9
 QV GLY
3)2
Reset comparator overdrive, VRST
– VCC (V)
Reset occurs
above the curve
Transient duration (µs)
AI09156b
0
1000
2000
3000
4000
5000
6000
0111.010.0100.0
DocID10518 Rev 13 21/32
STM706T/S/R, STM706P, STM708T/S/R Maximum ratings
31
5 Maximum ratings
Stressing the device above the rating listed in the Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in Table 5: Operating and AC
measurement conditions of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
TSTG Storage temperature (VCC off) –55 to 150 °C
TSLD(1)
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
Lead solder temperature for 10 seconds 260 °C
VIO(2)
2. Negative undershoot of –1.5 V for up to 10 ns or positive overshoot of VCC + 1.5 V for up to 10 ns is
allowable on the WDI and MR input pins.
Input or output voltage –0.3 to VCC +0.3 V
VCC Supply voltage –0.3 to 7.0 V
IOOutput current 20 mA
PD Power dissipation 320 mW
DC and AC parameters STM706T/S/R, STM706P, STM708T/S/R
22/32 DocID10518 Rev 13
6 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in Table 6: DC and AC characteristics are
derived from tests performed under the measurement conditions summarized in Table 5:
Operating and AC measurement conditions. Designers should check that the operating
conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Figure 25. AC testing input/output waveforms
Figure 26. Power-fail comparator waveform
Table 5. Operating and AC measurement conditions
Parameter STM70x Unit
VCC supply voltage 1.0 to 5.5 V
Ambient operating temperature (TA) –40 to 85 °C
Input rise and fall times ≤
5 ns
Input pulse voltages 0.2 to 0.8 VCC V
Input and output timing ref. voltages 0.3 to 0.7 VCC V
AI02568
0.8 V CC
0.2 V CC
0.7 V CC
0.3 V CC
DocID10518 Rev 13 23/32
STM706T/S/R, STM706P, STM708T/S/R DC and AC parameters
31
Figure 27. MR timing waveform
1. RST for STM706P and STM708T/S/R.
Figure 28. Watchdog timing (STM706T/S/R and STM706P)
AI07837a
RST (1)
MR
tMLRL
trec
tMLMH
AI08833
RST
WDO
WDI
VCC
trec
tWD
DC and AC parameters STM706T/S/R, STM706P, STM708T/S/R
24/32 DocID10518 Rev 13
Table 6. DC and AC characteristics
Symbol Description Test condition(1) Min. Typ. Max. Unit
VCC Operating voltage 1.2(2) 5.5 V
ICC V
CC supply current
VCC < 3.6 V 35 50 µA
VCC < 5.5 V 40 60 µA
ILI
Input leakage current
(WDI) 0 V < VIN < VCC –1 +1 µA
Input leakage current
(WDI) with watchdog
disable feature (“D”
version)
0 V < VIN < VCC -110 110 µA
Input leakage current
(PFI) 0 V < VIN < VCC –25 2 +25 nA
Input leakage current
(MR)
VRST (max.) < VCC < 3.6 V 25 80 250 µA
4.5 V < VCC < 5.5 V 75 125 300 µA
VIH Input high voltage (MR)
4.5 V < VCC < 5.5 V 2.0 V
VRST (max.) < VCC < 3.6 V 0.7 VCC V
VIH Input high voltage (WDI) VRST (max.) < VCC < 5.5 V 0.7 VCC V
VIL Input low voltage (MR)
4.5 V < VCC < 5.5 V 0.8 V
VRST (max.) < VCC < 3.6 V 0.6 V
VIL Input low voltage (WDI) VRST (max.) < VCC < 5.5 V 0.3 VCC V
VOL Output low voltage (PFO,
RST, RST, WDO)
VCC = VRST (max.),
ISINK = 3.2 mA 0.3 V
VOL Output low voltage (RST)
ISINK = 50 µA, VCC = 1.0 V,
TA = 0 °C to 85 °C 0.3 V
ISINK = 100 µA,
VCC = 1.2 V 0.3 V
VOH Output high voltage (RST,
RST, WDO)
ISOURCE = 1 mA,
VCC = VRST (max.) 2.4 V
Output high voltage
(PFO)
ISOURCE = 75 µA,
VCC = VRST (max.) 0.8 VCC V
Power-fail comparator
VPFI PFI input threshold
PFI falling
(STM70xP/R, VCC = 3.0 V;
STM70xS/T, VCC = 3.3 V)
1.20 1.25 1.30 V
tPFD PFI to PFO propagation
delay 2 µs
DocID10518 Rev 13 25/32
STM706T/S/R, STM706P, STM708T/S/R DC and AC parameters
31
Reset thresholds
VRST Reset threshold(3)
STM706P/70xR 2.55 2.63 2.70 V
STM70xS 2.85 2.93 3.00 V
STM70xT 3.00 3.08 3.15 V
Reset threshold
hysteresis 20 mV
trec RST pulse width
Blank (see Table 9) 140 200 280
ms
A(4) (see Table 9) 160 200 280
Push-button reset input
tMLMH
(or tMR)MR pulse width
VRST (max.) < VCC < 3.6 V 500 ns
4.5 V < VCC < 5.5 V 150 ns
tMLRL
(or tMRD)MR to RST output delay
VRST (max.) < VCC < 3.6 V 750 ns
4.5 V < VCC < 5.5 V 250 ns
Watchdog timer (STM706T/S/R and STM706P)
tWD Watchdog timeout period
STM706P/70xR,
VCC = 3.0 V 1.12 1.60 2.24 s
STM70xS/70XT,
VCC = 3.3 V
WDI pulse width
4.5 V < VCC < 5.5 V 50 ns
VRST (max.) < VCC < 3.6 V 100 ns
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = VRST (max.) to 5.5 V (except where noted).
2. VCC (min) = 1.0 V for TA = 0 °C to +85 °C.
3. For VCC falling.
4. STM706P/STM70xR device, VCC = 3 V; STM706xS/STM70xT device, VCC = 3.3 V.
Table 6. DC and AC characteristics (continued)
Symbol Description Test condition(1) Min. Typ. Max. Unit
Package information STM706T/S/R, STM706P, STM708T/S/R
26/32 DocID10518 Rev 13
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID10518 Rev 13 27/32
STM706T/S/R, STM706P, STM708T/S/R Package information
31
7.1 SO8 package information
Figure 29. SO8 - 8-lead plastic small outline, 150 mils body width, package outline
Note: Drawing is not to scale.
SO-A
E
8
ddd
B
e
A
D
C
LA1
1
H
A2
Table 7. SO8 - 8-lead plastic small outline, 150 mils body width, mechanical data
Symbol
Dimensions
mm inches
Typ. Min. Max. Typ. Min. Max.
A — 1.35 1.75 — 0.053 0.069
A1 — 0.10 0.25 — 0.004 0.010
B — 0.33 0.51 — 0.013 0.020
C — 0.19 0.25 — 0.007 0.010
D — 4.80 5.00 — 0.189 0.197
ddd — — 0.10 — — 0.004
E — 3.80 4.00 — 0.150 0.157
e 1.27 — — 0.050 — —
H — 5.80 6.20 — 0.228 0.244
h — 0.25 0.50 — 0.010 0.020
L — 0.40 0.90 — 0.016 0.035
α— 0° 8° — 0° 8°
N 8 8
Package information STM706T/S/R, STM706P, STM708T/S/R
28/32 DocID10518 Rev 13
7.2 TSSOP8 3x3 (DS) package information
Figure 30. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size,
package outline
Note: Drawing is not to scale.
TSSO P8 BM
1
8
CP
c
L
EE1
D
A2A
eb
4
5
A1
L1
Table 8. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size,
mechanical data
Symbol
Dimensions
mm inches
Typ. Min. Max. Typ. Min. Max.
A — — 1.10 — — 0.043
A1 — 0.05 0.15 — 0.002 0.006
A2 0.85 0.75 0.95 0.034 0.030 0.037
b — 0.25 0.40 — 0.010 0.016
c — 0.13 0.23 — 0.005 0.009
CP — — 0.10 — — 0.004
D 3.00 2.90 3.10 0.118 0.114 0.122
e 0.65 — — 0.026 — —
E 4.90 4.65 5.15 0.193 0.183 0.203
E1 3.00 2.90 3.10 0.118 0.114 0.122
L 0.55 0.40 0.70 0.022 0.016 0.030
L1 0.95 — — 0.037 — —
α— 0° 6° — 0° 6°
N 8 8
DocID10518 Rev 13 29/32
STM706T/S/R, STM706P, STM708T/S/R Part numbering
31
8 Part numbering
For other options, or for more information on any aspect of this device, please contact the ST sales office
nearest you.
Table 9. Ordering information scheme
Example: STM706 T D M 6 F
Device type
STM706
STM708
Reset threshold voltage
T: 3.00 V
≤
VRST
≤
3.15 V
S: 2.88 V
≤
VRST
≤
3.00 V
R: STM706P: 2.59 V ≤
VRST
≤
2.70 V
Watchdog disable
Blank = not activated
D = activated
RST pulse width
Blank = 140 to 280 ms
A(1) = 160 to 280 ms
Package
M = SO8
DS(2) = TSSOP8
Temperature range
6 = –40 to 85 °C
Shipping method
F = ECOPACK® packages, tape and reel
1. Available in SO8 (M) package only
2. Contact local ST sales office for availability
Part numbering STM706T/S/R, STM706P, STM708T/S/R
30/32 DocID10518 Rev 13
Table 10. Marking description
Part number Reset threshold Package Topside marking
STM706P 2.63 V
SO8
706P
TSSOP8
STM706T 3.08 V
SO8
706T
TSSOP8
STM706S 2.93 V
SO8
706S
TSSOP8
STM706R 2.63 V
SO8
706R
TSSOP8
STM706RD 2.63 V
SO8
706RD
TSSOP8
STM708T 3.08 V
SO8
708T
TSSOP8
STM708S 2.93 V
SO8
708S
TSSOP8
STM708R 2.63 V
SO8
708R
TSSOP8
DocID10518 Rev 13 31/32
STM706T/S/R, STM706P, STM708T/S/R Revision history
31
9 Revision history
Table 11. Document revision history
Date Revision Changes
Oct-2003 1 Initial release.
12-Dec-2003 2 Reformatted; update characteristics (Figure 2, 3, 8 to 10, 27 to 29;
Table 6 to 9).
16-Jan-2004 2.1 Add Typical operating characteristics (Figure 13, to 19, 21, to 25).
09-Apr-2004 3 Reformatted; update characteristics (Figure 15, 19, 21, 22, 25; Ta ble 8 ).
25-May-2004 4 Update characteristics (Table 3, Table 6).
02-Jul-2004 5 Datasheet promoted; waveform corrected (Table 27).
21-Sep-2004 6 Clarify root part numbers; (Figure 2, to 10, 29; Table 1, 3, 6, 9).
25-Feb-2005 7 Update typical characteristics (Figure 13 to 25).
02-Nov-2009 8 Updated Table 1 , Table 3 , Table 4, Tabl e 6, Table 9, Section 2.3,
Section 2.7, text in Section 7; reformatted document.
30-Apr-2010 9 Updated Table 4 , corrected typo in Table 2, Section 2.3, Section 3,
Section 5 and Section 6, Figure 17, Table 7 and Table 8.
06-Aug-2010 10 Updated Features, Section 4: Typical operating characteristics; Table 9.
06-Sep-2011 11 Updated Section 2.7, Section 5 and Disclaimer, minor typo
modifications throughout the document.
21-Aug-2012 12
Added Applications, updated Section 2.2 and Section 2.3, added note
to Section 3.3, added cross-references in Section 5 and Section 6,
minor text corrections throughout document.
15-Dec-2015 13
Updated layout of cover page and Section 7: Package information.
Added information about the watchdog disable function to Section 2.2:
WDI, Table 6, Table 9, and Table 10.
Table 9: removed the “E” option (tubes) from shipping method
STM706T/S/R, STM706P, STM708T/S/R
32/32 DocID10518 Rev 13
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