Product Folder Order Now Support & Community Tools & Software Technical Documents Reference Design LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 LM5022 60-V Low-Side Controller for Boost and SEPIC 1 Features 3 Description * * * The LM5022 device is a high-voltage, low-side, Nchannel MOSFET controller ideal for use in boost and SEPIC regulators. It contains all of the features required to implement single-ended primary topologies. Output voltage regulation is based on current-mode control, which eases the design of loop compensation while providing inherent input voltage feedforward. The LM5022 includes a start-up regulator that operates over a wide input range of 6 V to 60 V. The PWM controller is designed for highspeed capability including an oscillator frequency range up to 2.2 MHz and total propagation delays less than 100 ns. Additional features include an error amplifier, precision reference, line undervoltage lockout, cycle-by-cycle current limit, slope compensation, soft start, external synchronization capability, and thermal shutdown. The LM5022 is available in the 10-pin VSSOP package. 1 * * * * * * * * Internal 60-V start-up regulator 1-A Peak MOSFET gate driver VIN Range: 6 V to 60 V (operates down to 3 V after start-up) Duty cycle limit of 90% Programmable UVLO with hysteresis Cycle-by-cycle current limit External synchronizable (AC-coupled) Single resistor oscillator frequency set Slope compensation Adjustable soft start 10-Pin VSSOP package 2 Applications * * Boost converters SEPIC converters Device Information(1) PART NUMBER LM5022 PACKAGE VSSOP (10) BODY SIZE (NOM) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application VIN L1 CIN RS1 VIN VO D1 CO Q1 OUT RT RUV2 RT RUV1 LM5022 UVLO CSS RSNS CS SS CCS GND CF VCC COMP FB R1 C2 RFB2 RFB1 C1 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 7 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 7.2 7.3 7.4 Overview ................................................................... 9 Functional Block Diagram ......................................... 9 Feature Description................................................. 10 Device Functional Modes........................................ 12 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Application .................................................. 14 9 Power Supply Recommendations...................... 29 10 Layout................................................................... 30 10.1 Layout Guidelines ................................................. 30 10.2 Layout Examples................................................... 31 11 Device and Documentation Support ................. 33 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Device Support...................................................... Documentation Support ........................................ Receiving Notification of Documentation Updates Support Resources ............................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 33 33 33 33 33 33 33 12 Mechanical, Packaging, and Orderable Information ........................................................... 33 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (December 2017) to Revision J Page * Changed Figure 14 to correct Gnd trace between device-Gnd pin and Rsns........................................................................ 14 * Corrected Equation 3 ........................................................................................................................................................... 16 Changes from Revision H (December 2016) to Revision I * Page Changed numerator From: 1 To: C2 in Equation 55 ............................................................................................................ 24 Changes from Revision G (December 2013) to Revision H Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 * Deleted soldering temperature (215C Vapor phase maximum and 220C Infrared maximum) ........................................... 4 * Changed Junction to Ambient Thermal Resistance, RJA, value From: 200 To: 161.5 .......................................................... 4 * Changed slope compensation amplitude, VSLOPE, values From: 80 To: 83 (Minimum), From: 105 To: 110 (Typical), and From: 130 To: 137 (Maximum)........................................................................................................................................ 5 Changes from Revision F (March 2013) to Revision G * Changed timing resistor equation. Incorrect change when converting to TI format ............................................................. 12 Changes from Revision E (March 2013) to Revision F * 2 Page Page Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1 Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 5 Pin Configuration and Functions DGS Package 10-Pin VSSOP Top View VIN 1 10 SS FB 2 9 RT/SYNC COMP 3 8 CS VCC 4 7 UVLO OUT 5 6 GND Not to scale Pin Functions PIN NO. NAME I/O DESCRIPTION 1 VIN I Source input voltage: Input to the start-up regulator. Operates from 6 V to 60 V. 2 FB I Feedback pin: Inverting input to the internal voltage error amplifier. The non-inverting input of the error amplifier connects to a 1.25-V reference. 3 COMP I/O Error amplifier output and PWM comparator input: The control loop compensation components connect between this pin and the FB pin. 4 VCC O Output of the internal, high-voltage linear regulator: This pin must be bypassed to the GND pin with a ceramic capacitor. 5 OUT O Output of MOSFET gate driver: Connect this pin to the gate of the external MOSFET. The gate driver has a 1-A peak current capability. 6 GND -- System ground 7 UVLO I Input undervoltage lockout: Set the start-up and shutdown levels by connecting this pin to the input voltage through a resistor divider. A 20-A current source provides hysteresis. 8 CS I Current sense input: Input for the switch current used for current mode control and for current limiting. 9 RT/SYNC I Oscillator frequency adjust pin and synchronization input: An external resistor connected from this pin to GND sets the oscillator frequency. This pin can also accept an AC-coupled input for synchronization from an external clock. 10 SS I Soft-start pin: An external capacitor placed from this pin to ground is charged by a 10-A current source, creating a ramp voltage to control the regulator start-up. Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 3 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT VIN to GND -0.3 65 V VCC to GND -0.3 16 V RT/SYNC to GND -0.3 5.5 V -1.5 for < 100 ns V OUT to GND All other pins to GND -0.3 Power dissipation 7 Junction temperature, TJ (3) Storage temperature, Tstg (1) (2) (3) V Internally limited -65 150 C 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications. High junction temperatures degrade operating lifetimes. Operating lifetime is derated for junction temperatures greater than 125C. 6.2 ESD Ratings VALUE V(ESD) (1) (2) (3) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2) 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (3) 750 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. The human-body model is a 100-pF capacitor discharged through a 1.5-k resistor into each pin. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) Supply voltage MIN MAX 6 60 UNIT V External voltage at VCC 7.5 14 V Junction temperature -40 125 C (1) Device thermal limitations may limit usable range 6.4 Thermal Information LM5022 THERMAL METRIC (1) DGS (VSSOP) UNIT 10 PINS RJA Junction-to-ambient thermal resistance RJC(top) Junction-to-case (top) thermal resistance 161.5 C/W 56 C/W RJB JT Junction-to-board thermal resistance 81.3 C/W Junction-to-top characterization parameter 5.7 C/W JB Junction-to-board characterization parameter 80 C/W RJC(bot) Junction-to-case (bottom) thermal resistance -- C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 6.5 Electrical Characteristics Typical limits apply for TJ=25C and are provided for reference purposes only; minimum and maximum limits apply over the junction temperature (TJ) range of -40C to 125C. VIN = 24 V and RT = 27.4 k (unless otherwise noted). (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.225 1.25 1.275 V 6.6 7 7.4 SYSTEM PARAMETERS VFB FB pin voltage STARTUP REGULATOR 10 V VIN 60 V, ICC = 1 mA VCC VCC regulation (2) ICC Supply current OUT Pin Capacitance = 0, VCC = 10 V ICC-LIM VCC current limit VCC = 0 V (2) (3) 35 mA VIN - VCC Dropout voltage across bypass switch ICC = 0 mA, SW < 200 kHz, 6 V VIN 8.5 V 200 mV VBYP-HI Bypass switch turnoff threshold VIN increasing 8.7 V VBYP-HYS Bypass switch threshold hysteresis VIN Decreasing 260 mV 6 V VIN < 10V, VCC Pin Open Circuit V 5 3.5 15 VIN = 6 V 58 VIN = 8 V 53 VIN = 24 V 1.6 4 mA ZVCC VCC pin output impedance 0 mA ICC 5 mA VCC-HI VCC pin UVLO rising threshold VCC-HYS VCC pin UVLO falling hysteresis IVIN Startup regulator leakage VIN = 60 V 150 500 A IIN-SD Shutdown current VUVLO = 0 V, VCC = Open Circuit 350 450 A 5 V 300 mV ERROR AMPLIFIER GBW Gain bandwidth ADC DC gain ICOMP COMP pin current sink capability 4 VFB = 1.5 V, VCOMP = 1 V MHz 75 dB 5 17 mA 1.22 1.25 1.28 V 16 20 24 A UVLO VSD Shutdown threshold ISD-HYS Shutdown hysteresis current source CURRENT LIMIT tLIM-DLY Delay from ILIM to output VCS Current limit threshold voltage tBLK Leading edge blanking time RCS CS pin sink impedance CS steps from 0 V to 0.6 V, OUT transitions to 90% of VCC 30 0.45 0.5 ns 0.55 65 Blanking active V ns 40 75 7 10 13 A 0.35 0.55 0.75 V SOFT START ISS Soft-start current source VSS-OFF Soft start to COMP offset (1) (2) (3) All Minimum and Maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. The junction temperature (TJ in C) is calculated from the ambient temperature (TA in C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD x RJA) where RJA (in C/W) is the package thermal impedance provided in Thermal Information. VCC provides bias for the internal gate drive and control circuits. Device thermal limitations may limit usable range. Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 5 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com Electrical Characteristics (continued) Typical limits apply for TJ=25C and are provided for reference purposes only; minimum and maximum limits apply over the junction temperature (TJ) range of -40C to 125C. VIN = 24 V and RT = 27.4 k (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OSCILLATOR 170 (4) 200 230 kHz RT to GND = 27.4 k See (4) 525 600 675 kHz RT to GND = 16.2 k See (4) 865 990 1115 kHz RT to GND = 84.5 k fSW VSYNC-HI Synchronization rising threshold 3.8 V PWM COMPARATOR tCOMP-DLY Delay from COMP to OUT transition VCOMP = 2 V, CS stepped from 0 V to 0.4 V DMIN Minimum duty cycle VCOMP = 0 V DMAX Maximum duty cycle APWM COMP to PWM comparator gain VCOMP-OC COMP pin open circuit voltage VFB = 0 V 4.3 5.2 6.1 V ICOMP-SC COMP pin short circuit current VCOMP = 0 V, VFB = 1.5 V 0.6 1.1 1.5 mA 83 110 137 mV 25 ns 0% 90% 95% 0.33 V/V SLOPE COMPENSATION VSLOPE Slope compensation amplitude MOSFET DRIVER VSAT-HI Output high saturation voltage (VCC - VOUT) IOUT = 50 mA 0.25 0.75 V VSAT-LO Output low saturation voltage (VOUT) IOUT = 100 mA 0.25 0.75 V tRISE OUT pin rise time OUT Pin load = 1 nF 18 ns tFALL OUT pin fall time OUT Pin load = 1 nF 15 ns THERMAL CHARACTERISTICS TSD Thermal shutdown threshold 165 C TSD-HYS Thermal shutdown hysteresis 25 C (4) 6 Specification applies to the oscillator frequency. Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 6.6 Typical Characteristics VO = 40 V VIN = 24 V Figure 1. Efficiency, Example Circuit BOM TA = 25C Figure 2. VFB vs Temperature TA = 25C Figure 3. VFB vs VIN Figure 4. VCC vs VIN TA = 25C RT = 16.2 K Figure 5. Maximum Duty Cycle vs SW Figure 6. SW vs Temperature Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 7 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com Typical Characteristics (continued) TA = 25C 8 Figure 7. RT vs SW Figure 8. SS vs Temperature Figure 9. OUT Pin TRISE vs Gate Capacitance Figure 10. OUT Pin TFALL vs Gate Capacitance Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 7 Detailed Description 7.1 Overview The LM5022 is a low-side, N-channel MOSFET controller that contains all of the features required to implement single-ended power converter topologies. The LM5022 includes a high-voltage start-up regulator that operates over a wide input range of 6 V to 60 V. The PWM controller is designed for high-speed capability including an oscillator frequency range up to 2.2 MHz and total propagation delays less than 100 ns. Additional features include an error amplifier, precision reference, input undervoltage lockout, cycle-by-cycle current limit, slope compensation, soft start, oscillator sync capability, and thermal shutdown. The LM5022 is designed for current-mode control power converters that require a single drive output, such as boost and SEPIC topologies. The LM5022 provides all of the advantages of current-mode control including input voltage feedforward, cycle-by-cycle current limiting, and simplified loop compensation. 7.2 Functional Block Diagram BYPASS SWITCH (6 V to 8.7 V) VCC VIN 7-V SERIES REGULATOR REFERENCE ENABLE UVLO 1.25 V + - 5V 1.25 V LOGIC UVLO HYSTERESIS (20 A) RT/SYNC CLK OSC DRIVER 45 A Max Duty Limit 0 S Q R Q OUT 5V COMP GND 5k 1.25 V PWM + - 100 NY FB 1.4 V 50 NY SS CS 0.5 V 2 NY LOGIC SS 10 A SS + - CLK + LEB Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 9 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com 7.3 Feature Description 7.3.1 High-Voltage Start-Up Regulator The LM5022 contains an internal high-voltage start-up regulator that allows the VIN pin to be connected directly to line voltages as high as 60 V. The regulator output is internally current limited to 35 mA (typical). When power is applied, the regulator is enabled and sources current into an external capacitor, CF, connected to the VCC pin. The recommended capacitance range for CF is 0.1 F to 100 F. When the voltage on the VCC pin reaches the rising threshold of 5 V, the controller output is enabled. The controller remains enabled until VCC falls below 4.7 V. In applications using a transformer, an auxiliary winding can be connected through a diode to the VCC pin. This winding must raise the VCC pin voltage to above 7.5 V to shut off the internal start-up regulator. Powering VCC from an auxiliary winding improves conversion efficiency while reducing the power dissipated in the controller. The capacitance of CF must be high enough that it maintains the VCC voltage greater than the VCC UVLO falling threshold (4.7 V) during the initial start-up. During a fault condition when the converter auxiliary winding is inactive, external current draw on the VCC line must be limited such that the power dissipated in the start-up regulator does not exceed the maximum power dissipation capability of the controller. An external start-up or other bias rail can be used instead of the internal start-up regulator by connecting the VCC and the VIN pins together and feeding the external bias voltage (7.5 V to 14 V) to the two pins. 7.3.2 Input Undervoltage Detector The LM5022 contains an input undervoltage lockout (UVLO) circuit. UVLO is programmed by connecting the UVLO pin to the center point of an external voltage divider from VIN to GND. The resistor divider must be designed such that the voltage at the UVLO pin is greater than 1.25 V when VIN is in the desired operating range. If the undervoltage threshold is not met, all functions of the controller are disabled and the controller remains in a low power standby state. UVLO hysteresis is accomplished with an internal 20-A current source that is switched on or off into the impedance of the setpoint divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25-V threshold the current source is turned off, causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to implement a remote enable or disable function. If an external transistor pulls the UVLO pin below the 1.25-V threshold, the converter is disabled. This external shutdown method is shown in Figure 11. VIN VIN RUV2 LM5022 UVLO RUV1 ON/OFF 2N7000 or Equivalent GND Figure 11. Enable or Disable Using UVLO 10 Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 Feature Description (continued) 7.3.3 Error Amplifier An internal high gain error amplifier is provided within the LM5022. The noninverting input of the amplifier is internally set to a fixed reference voltage of 1.25 V. The inverting input is connected to the FB pin. In nonisolated applications such as the boost converter the output voltage, VO, is connected to the FB pin through a resistor divider. The control loop compensation components are connected between the COMP and FB pins. For most isolated applications, the error amplifier function is implemented on the secondary side of the converter and the internal error amplifier is not used. The internal error amplifier is configured as an open-drain output and can be disabled by connecting the FB pin to ground. An internal 5-k pullup resistor between a 5-V reference and COMP can be used as the pullup for an opto-coupler in isolated applications. 7.3.4 Current Sensing and Current Limiting The LM5022 provides a cycle-by-cycle over current protection function. Current limit is accomplished by an internal current sense comparator. If the voltage at the current sense comparator input exceeds 0.5 V, the MOSFET gate drive is immediately terminated. A small RC filter, placed near the controller, is recommended to filter noise from the current sense signal. The CS input has an internal MOSFET which discharges the CS pin capacitance at the conclusion of every cycle. The discharge device remains on an additional 65 ns after the beginning of the new cycle to attenuate leading edge ringing on the current sense signal. The LM5022 current sense and PWM comparators are very fast, and may respond to short duration noise pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS filter must be placed very close to the device and connected directly to the pins of the controller (CS and GND). If a current sense transformer is used, both leads of the transformer secondary must be routed to the sense resistor and the current sense filter network. The current sense resistor can be placed between the source of the primary power MOSFET and power ground, but it must be a low inductance type. When designing with a current sense resistor all of the noise sensitive low-power ground connections must be connected together locally to the controller and a single connection must be made to the high current power ground (sense resistor ground point). 7.3.5 PWM Comparator and Slope Compensation The PWM comparator compares the current ramp signal with the error voltage derived from the error amplifier output. The error amplifier output voltage at the COMP pin is offset by 1.4 V and then further attenuated by a 3:1 resistor divider. The PWM comparator polarity is such that 0 V on the COMP pin results in a zero duty cycle at the controller output. For duty cycles greater than 50%, current mode control circuits can experience subharmonic oscillation. By adding an additional fixed-slope voltage ramp signal (slope compensation), this oscillation can be avoided. Proper slope compensation damps the double pole associated with current mode control (see the Control Loop Compensation section) and eases the design of the control loop compensator. The LM5022 generates the slope compensation with a sawtooth-waveform current source with a slope of 45 A x SW, generated by the clock (see Figure 12). This current flows through an internal 2-k resistor to create a minimum compensation ramp with a slope of 100 mV x SW (typical). The slope of the compensation ramp increases when external resistance is added for filtering the current sense (RS1) or in the position RS2. As shown in Figure 12 and the Functional Block Diagram, the sensed current slope and the compensation slope add together to create the signal used for current limiting and for the control loop itself. ISW LM5022 45 A 0 RS1 RS2 CS 2 NY 0.5V RSNS CSNS + Current Limit VCL Figure 12. Slope Compensation Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 11 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com Feature Description (continued) In peak current mode control, the optimal slope compensation is proportional to the slope of the inductor current during the power switch off-time. For boost converters, the inductor current slope while the MOSFET is off is (VO - VIN) / L. This relationship is combined with the requirements to set the peak current limit and is used to select RSNS and RS2 in the Application and Implementation section. 7.3.6 Soft Start The soft start feature allows the power converter output to gradually reach the initial steady-state output voltage, thereby reducing start-up stresses and current surges. At power on, after the VCC and input undervoltage lockout thresholds are satisfied, an internal 10-A current source charges an external capacitor connected to the SS pin. The capacitor voltage ramps up slowly and limits the COMP pin voltage and the switch current. 7.3.7 MOSFET Gate Driver The LM5022 provides an internal gate driver through the OUT pin that can source and sink a peak current of 1 A to control external, ground-referenced N-channel MOSFETs. 7.3.8 Thermal Shutdown Internal thermal shutdown circuitry is provided to protect the LM5022 in the event that the maximum junction temperature is exceeded. When activated, typically at 165C, the controller is forced into a low power standby state, disabling the output driver and the VCC regulator. After the temperature is reduced (typical hysteresis is 25C) the VCC regulator is re-enabled and the LM5022 performs a soft start. 7.4 Device Functional Modes 7.4.1 Oscillator, Shutdown, and SYNC A single external resistor, RT, connected between the RT/SYNC and GND pins sets the LM5022 oscillator frequency. To set the switching frequency (SW), RT can be calculated with Equation 1. RT (1 - 8 10 = -8 fSW fSW 5.77 10 ) -11 where * * fSW is in Hz RT is in (1) The LM5022 can also be synchronized to an external clock. The external clock must have a higher frequency than the free-running oscillator frequency set by the RT resistor. The clock signal must be capacitively coupled into the RT/SYNC pin with a 100-pF capacitor as shown in Figure 13. A peak voltage level greater than 3.8 V at the RT/SYNC pin is required for detection of the sync pulse. The sync pulse width must be set between 15 ns to 150 ns by the external components. The RT resistor is always required, whether the oscillator is free-running or externally synchronized. The voltage at the RT/SYNC pin is internally regulated to 2 V, and the typical delay from a logic high at the RT/SYNC pin to the rise of the OUT pin voltage is 120 ns. RT must be placed very close to the device and connected directly to the pins of the controller (RT/SYNC and GND). 12 Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 Device Functional Modes (continued) EXTERNAL CLOCK LM5022 CSS RT/SYNC 100 pF RT 15 ns to 150 ns EXTERNAL CLOCK 120 ns (Typical) OUT PIN Figure 13. SYNC Operation Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 13 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The most common circuit controlled by the LM5022 is a non-isolated boost regulator. The boost regulator steps up the input voltage and has a duty ratio D in Equation 2. D V O - V IN + V D V O + VD where * VD is the forward voltage drop of the output diode (2) The following is a design procedure for selecting all the components for the boost converter circuit shown in Figure 14. The application is in-cabin automotive, meaning that the operating ambient temperature ranges from -20C to 85C. This circuit operates in continuous conduction mode (CCM), where inductor current stays above 0 A at all times, and delivers an output voltage of 40 V 2% at a maximum output current of 0.5 A. Additionally, the regulator must be able to handle a load transient of up to 0.5 A while keeping VO within 4%. The voltage input comes from the battery or alternator system of an automobile, where the standard range of 9 V to 16 V and transients of up to 32 V must not cause any malfunction. 8.2 Typical Application L1 VIN = 9 V to 16 V CIN1,2 D1 VO = 40 V CINX Q1 RS1 VIN RS2 UVLO CSS LM5022 RT RUV1 COX OUT RT RUV2 CO1,2 SS RSNS CS CCS GND CF VCC COMP RFB2 FB R1 C2 RFB1 C1 Figure 14. LM5022 Typical Application 14 Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 Typical Application (continued) 8.2.1 Design Requirements For typical low-side controller applications, use the parameters listed in Table 1. Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 9 V to 16 V Output voltage 40 V Maximum output current 500 mA Switching frequency 500 kHz 8.2.2 Detailed Design Procedure Table 2 lists the bill of materials for this design example. Table 2. BOM for Example Circuit ID PART NUMBER TYPE SIZE PARAMETERS QTY VENDOR U1 LM5022 Low-Side Controller 10-pin VSSOP 60 V 1 TI Q1 Si4850EY MOSFET SO-8 60 V, 31 m, 27 nC 1 Vishay D1 CMSH2-60M Schottky Diode SMA 60 V, 2 A 1 Central Semi L1 SLF12575T-M3R2 Inductor 12.5 x 12.5 x 7.5 mm 33 H, 3.2 A, 40 m 1 TDK Cin1, Cin2 C4532X7R1H475M Capacitor 1812 4.7 F, 50 V, 3 m 2 TDK Co1, Co2 C5750X7R2A475M Capacitor 2220 4.7 F,100 V, 3 m 2 TDK Cf C2012X7R1E105K Capacitor 0805 1 F, 25 V 1 TDK Cinx Cox C2012X7R2A104M Capacitor 0805 100 nF, 100 V 2 TDK C1 VJ0805A561KXXAT Capacitor 0805 560 pF 10% 1 Vishay C2 VJ0805Y124KXXAT Capacitor 0805 120 nF 10% 1 Vishay Css VJ0805Y103KXXAT Capacitor 0805 10 nF 10% 1 Vishay Ccs VJ0805Y102KXXAT Capacitor 0805 1 nF 10% 1 Vishay R1 CRCW08053011F Resistor 0805 3.01 k 1% 1 Vishay Rfb1 CRCW08056490F Resistor 0805 649 1% 1 Vishay Rfb2 CRCW08052002F Resistor 0805 20 k 1% 1 Vishay Rs1 CRCW0805101J Resistor 0805 100 5% 1 Vishay Rs2 CRCW08053571F Resistor 0805 3.57 k 1% 1 Vishay Rsns ERJL14KF10C Resistor 1210 100 m, 1%, 0.5 W 1 Panasonic Rt CRCW08053322F Resistor 0805 33.2 k 1% 1 Vishay Ruv1 CRCW08052611F Resistor 0805 2.61 k 1% 1 Vishay Ruv2 CRCW08051002F Resistor 0805 10 k 1% 1 Vishay 8.2.2.1 Switching Frequency The selection of switching frequency is based on the tradeoffs between size, cost, and efficiency. In general, a lower frequency means larger, more expensive inductors and capacitors is required. A higher switching frequency generally results in a smaller but less efficient solution, as the power MOSFET gate capacitances must be charged and discharged more often in a given amount of time. For this application, a frequency of 500 kHz was selected as a good compromise between the size of the inductor and efficiency. PCB area and component height are restricted in this application. Following Equation 1, a 33.2-k 1% resistor must be used to switch at 500 kHz. Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 15 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com 8.2.2.2 MOSFET Selection of the power MOSFET is governed by tradeoffs between cost, size, and efficiency. Breaking down the losses in the MOSFET is one way to determine relative efficiencies between different devices. For this example, the SO 8-pin package provides a balance of a small footprint with good efficiency (see Q1 in Table 2). Losses in the MOSFET can be broken down into conduction loss, gate charging loss, and switching loss. Conduction, or I2R loss (PC) is approximately Equation 3. 2 I O * Pc D u u R DSON u 1.3 1 D (c) 1/4 (3) The factor 1.3 accounts for the increase in MOSFET on-resistance due to heating. Alternatively, the factor of 1.3 can be ignored and the maximum on-resistance of the MOSFET can be used. Gate charging loss, PG, results from the current required to charge and discharge the gate capacitance of the power MOSFET and is approximated with Equation 4. PG = VCC x QG x fSW (4) QG is the total gate charge of the MOSFET. Gate charge loss differs from conduction and switching losses because the actual dissipation occurs in the LM5022 and not in the MOSFET itself. If no external bias is applied to the VCC pin, additional loss in the LM5022 IC occurs as the MOSFET driving current flows through the VCC regulator. This loss (PVCC) is estimated with Equation 5. PVCC = (VIN - VCC) x QG x fSW (5) Switching loss (PSW) occurs during the brief transition period as the MOSFET turns on and off. During the transition period both current and voltage are present in the channel of the MOSFET. The loss can be approximated with Equation 6. PSW = 0.5 x VIN x [IO / (1 - D)] x (tR + tF) x SW where * * tR is the rise time of the MOSFET tF is the fall time of the MOSFET (6) For this example, the maximum drain-to-source voltage applied across the MOSFET is VO plus the ringing due to parasitic inductance and capacitance. The maximum drive voltage at the gate of the high-side MOSFET is VCC, or 7 V typical. The MOSFET selected must be able to withstand 40 V plus any ringing from drain to source, and be able to handle at least 7 V plus ringing from gate to source. A minimum voltage rating of 50-VD-S and 10-VG-S MOSFET is used. Comparing the losses in a spreadsheet leads to a 60 VD-S rated MOSFET in SO-8 with an RDSON of 22 m (the maximum value is 31 m), a gate charge of 27 nC, and rise and falls times of 10 ns and 12 ns, respectively. 8.2.2.3 Output Diode The boost regulator requires an output diode D1 (see Figure 14) to carrying the inductor current during the MOSFET off-time. The most efficient choice for D1 is a Schottky diode due to low forward drop and near-zero reverse recovery time. D1 must be rated to handle the maximum output voltage plus any switching node ringing when the MOSFET is on. In practice, all switching converters have some ringing at the switching node due to the diode parasitic capacitance and the lead inductance. D1 must also be rated to handle the average output current, IO. The overall converter efficiency becomes more dependent on the selection of D1 at low duty cycles, where the boost diode carries the load current for an increasing percentage of the time. This power dissipation can be calculating by checking the typical diode forward voltage, VD, from the I-V curve on the data sheet of the diode and then multiplying it by IO. Diode data sheets also provides a typical junction-to-ambient thermal resistance, RJA, which can be used to estimate the operating die temperature of the Schottky. Multiplying the power dissipation (PD = IO x VD) by RJA gives the temperature rise. The diode case size can then be selected to maintain the Schottky diode temperature below the operational maximum. 16 Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 In this example, a Schottky diode rated to 60 V and 1 A is suitable, as the maximum diode current is 0.5 A. A small case such as SOD-123 can be used if a small footprint is critical. Larger case sizes generally have lower RJA and lower forward voltage drop, so for better efficiency the larger SMA case size is used. 8.2.2.4 Boost Inductor The first criterion for selecting an inductor is the inductance itself. In fixed-frequency boost converters, this value is based on the desired peak-to-peak ripple current, iL, which flows in the inductor along with the average inductor current, IL. For a boost converter in CCM, IL is greater than the average output current, IO. The two currents are related by Equation 7. IL = IO / (1 - D) (7) As with switching frequency, the inductance used is a tradeoff between size and cost. Larger inductance means lower input ripple current, however because the inductor is connected to the output during the off-time only, there is a limit to the reduction in output ripple voltage. Lower inductance results in smaller, less expensive magnetics. An inductance that gives a ripple current of 30% to 50% of IL is a good starting point for a CCM boost converter. Minimum inductance must be calculated with Equation 8 at the extremes of input voltage to find the operating condition with the highest requirement. L1 V IN u D f SW u 'i L (8) By calculating in terms of amperes, volts, and megahertz, the inductance value comes out in micro henries. To ensure that the boost regulator operates in CCM, a second equation is required, and must also be evaluated with Equation 9 at the corners of input voltage to find the minimum inductance required. L2 D(1 D) u V IN I O u f SW (9) By calculating in terms of volts, amps, and megahertz, the inductance value comes out in H. For this design, iL is set to 40% of the maximum IL. Duty cycle is evaluated first at VIN(MIN) and at VIN(MAX). Second, the average inductor current is evaluated at the two input voltages. Third, the inductor ripple current is determined. Finally, the inductance can be calculated, and a standard inductor value selected that meets all the criteria. 1. Inductance for Minimum Input Voltage (Equation 10, Equation 11, and Equation 12) DVIN(MIN) = (40 - 9 + 0.5) / (40 + 0.5) = 78% IL-VIN(MIN) = 0.5 / (1 - 0.78) = 2.3 A iL = 0.4 x 2.3 A = 0.92 A L1 L2 VIN (MIN) VIN (MIN) 9 u 0.78 0.5 u 0.92 (10) 15.3 PH (11) 0.78 u 0.22 u 9 0.5 u 0.5 6.2 PH (12) 2. Inductance for Maximum Input Voltage (Equation 13, Equation 14, and Equation 15) DVIN(MAX) = (40 - 16 + 0.5) / (40 + 0.5) = 60% IL-VIN(MIAX) = 0.5 / (1 - 0.6) = 1.25 A iL = 0.4 x 1.25 A = 0.5 A L1 L2 VIN ( MIN ) VIN (MIN) 16 u 0.6 0.5 u 0.5 (13) 38.4 PH 0.6 u 0.4 u 16 0.5 u 0.5 (14) 15.4 PH (15) Maximum average inductor current occurs at VIN(MIN), and the corresponding inductor ripple current is 0.92 AP-P. Selecting an inductance that exceeds the ripple current requirement at VIN(MIN) and the requirement to stay in CCM for VIN(MAX) provides a tradeoff that allows smaller magnetics at the cost of higher ripple current at maximum input voltage. For this example, a 33-H inductor satisfies these requirements. Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 17 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com The second criterion for selecting an inductor is the peak current carrying capability. This is the level above which the inductor saturates. In saturation, the inductance can drop off severely, resulting in higher peak current that can overheat the inductor or push the converter into current limit. In a boost converter, peak current, IPK, is equal to the maximum average inductor current plus one half of the ripple current. First, the current ripple must be determined under the conditions that give maximum average inductor current with Equation 16. 'i L V IN x D f SW u L (16) Maximum average inductor current occurs at VIN(MIN). Using the selected inductance of 33 H yields Equation 17. iL = (9 x 0.78) / (0.5 x 33) = 425 mAP-P (17) The highest peak inductor current over all operating conditions is therefore Equation 18. IPK = IL + 0.5 x iL = 2.3 + 0.213 = 2.51 A (18) Hence, an inductor must be selected that has a peak current rating greater than 2.5 A and an average current rating greater than 2.3 A. One possibility is an off-the-shelf 33 H 20% inductor that can handle a peak current of 3.2 A and an average current of 3.4 A. Finally, the inductor current ripple is recalculated with Equation 19 at the maximum input voltage. iL-VIN(MAX) = (16 x 0.6) / (0.5 x 33) = 0.58 AP-P (19) 8.2.2.5 Output Capacitor The output capacitor in a boost regulator supplies current to the load during the MOSFET on-time and also filters the AC portion of the load current during the off-time. This capacitor determines the steady-state output voltage ripple, VO, a critical parameter for all voltage regulators. Output capacitors are selected based on their capacitance, CO, their equivalent series resistance (ESR), and their RMS or AC current rating. The magnitude of VO is comprised of three parts, and in steady-state, the ripple voltage during the on-time is equal to the ripple voltage during the off-time. For simplicity, the analysis is performed for the MOSFET turning off (off-time) only. The first part of the ripple voltage is the surge created as the output diode D1 turns on. At this point, inductor and diode current are at peak value, and the ripple voltage increase can be calculated with Equation 20. VO1 = IPK x ESR (20) The second portion of the ripple voltage is the increase due to the charging of CO through the output diode. This portion can be approximated with Equation 21. VO2 = (IO / CO) x (D / SW) (21) The final portion of the ripple voltage is a decrease due to the flow of the diode and inductor current through the ESR of the output capacitor. This decrease can be calculated with Equation 22. VO3 = iL x ESR (22) The total change in output voltage is Equation 23. VO = VO1 + VO2 - VO3 (23) The combination of two positive terms and one negative term may yield an output voltage ripple with a net rise or a net fall during the converter off-time. The ESR of the output capacitor or capacitors has a strong influence on the slope and direction of VO. Capacitors with high ESR such as tantalum and aluminum electrolytic create an output voltage ripple that is dominated by VO1 and VO3, with a shape shown in Figure 15. Ceramic capacitors, in contrast, have very low ESR and lower capacitance. The shape of the output ripple voltage is dominated by VO2, with a shape shown in Figure 16. 18 Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 AvO VO AvO VO ID ID Figure 15. VO Using High-ESR Capacitors Figure 16. VO Using Low-ESR Capacitors For this example, the small size and high temperature rating of ceramic capacitors make them a good choice. The output ripple voltage waveform of Figure 16 is assumed, and the capacitance is selected first. The desired VO is 2% of 40 V, or 0.8 VP-P. Beginning with the calculation for VO2, the required minimum capacitance is in Equation 24. CO-MIN = (IO / VO) x (DMAX / fSW) CO-MIN = (0.5 / 0.8) x (0.77 / 5 x 105) = 0.96 F (24) The next higher standard 20% capacitor value is 1 F, however, to provide margin for component tolerance and load transients, two capacitors rated 4.7 F each (CO= 9.4 F) are used. Ceramic capacitors rated 4.7 F 20% are available from many manufacturers. The minimum quality dielectric that is suitable for switching power supply output capacitors is X5R, while X7R (or better) is preferred. Pay careful attention to the DC voltage rating and case size, as ceramic capacitors can lose 60% or more of their rated capacitance at the maximum DC voltage. This is the reason that ceramic capacitors are often de-rated to 50% of their capacitance at their working voltage. The output capacitors for this example has a 100-V rating in a 2220 case size. The typical ESR of the selected capacitors is 3 m each, and in parallel is approximately 1.5 m. The worstcase value for VO1 occurs during the peak current at minimum input voltage in Equation 25. VO1 = 2.5 x 0.0015 = 4 mV (25) The worst-case capacitor charging ripple occurs at maximum duty cycle in Equation 26. VO2 = (0.5 / 9.4 x 10-6) x (0.77 / 5 x 105) = 82 mV (26) Finally, the worst-case value for VO3 occurs when inductor ripple current is highest, at maximum input voltage in Equation 27. VO3 = 0.58 x 0.0015 = 1 mV (negligible) (27) The output voltage ripple can be estimated by summing the three terms in Equation 28. VO = 4 mV + 82 mV - 1 mV = 85 mV (28) The RMS current through the output capacitor or capacitors can be estimated using the following, worst-case equation in Equation 29. IO RMS 1.13 u I L u D u (1 D ) (29) The highest RMS current occurs at minimum input voltage. For this example, the maximum output capacitor RMS current is calculated with Equation 30. IO-RMS(MAX) = 1.13 x 2.3 x (0.78 x 0.22)0.5 = 1.08 ARMS (30) These 2220 case size devices are capable of sustaining RMS currents of over 3 A each, making them more than adequate for this application. Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 19 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com 8.2.2.6 VCC Decoupling Capacitor The VCC pin must be decoupled with a ceramic capacitor placed as close as possible to the VCC and GND pins of the LM5022. The decoupling capacitor must have a minimum X5R or X7R type dielectric to ensure that the capacitance remains stable over voltage and temperature, and be rated to a minimum of 470 nF. One good choice is a 1-F device with X7R dielectric and 1206 case size rated to 25 V. 8.2.2.7 Input Capacitor The input capacitors to a boost regulator control the input voltage ripple (VIN) hold up the input voltage during load transients and prevent impedance mismatch (also called power supply interaction) between the LM5022 and the inductance of the input leads. Selection of input capacitors is based on their capacitance, ESR, and RMS current rating. The minimum value of ESR can be selected based on the maximum output current transient, ISTEP, using Equation 31. ESR MIN 1 D u 'V IN 2 x I STEP (31) For this example, the maximum load step is equal to the load current or 0.5 A. The maximum permissable VIN during load transients is 4%P-P. VIN and duty cycle are taken at minimum input voltage to give the worst-case value in Equation 32. ESRMIN = [(1 - 0.77) x 0.36] / (2 x 0.5) = 83 m (32) The minimum input capacitance can be selected based on VIN, based on the drop in VIN during a load transient, or based on prevention of power supply interaction. In general, the requirement for greatest capacitance comes from the power supply interaction. The inductance and resistance of the input source must be estimated, and if this information is not available, they can be assumed to be 1 H and 0.1 , respectively. Minimum capacitance is then estimated with Equation 33. C MIN 2 u L S u VO u I O VIN 2 u RS (33) As with ESR, the worst-case, highest minimum capacitance calculation comes at the minimum input voltage. Using the default estimates for LS and RS, minimum capacitance is calculated with Equation 34. C MIN 2 u 1Pu 40 u 0.5 9 2 u 0.1 4.9 PF (34) The next highest standard 20% capacitor value is 6.8 F, but because the actual input source impedance and resistance are not known, two 4.7-F capacitors is used. In general, doubling the calculated value of input capacitance provides a good safety margin. The final calculation is for the RMS current. For boost converters operating in CCM, this can be estimated with Equation 35. IRMS = 0.29 x iL(MAX) (35) From the inductor section, maximum inductor ripple current is 0.58 A, hence the input capacitor or capacitors must be rated to handle 0.29 x 0.58 = 170 mARMS. The input capacitors can be ceramic, tantalum, aluminum, or almost any type, however, the low capacitance requirement makes ceramic capacitors particularly attractive. As with the output capacitors, the minimum quality dielectric used must be X5R, with X7R or better preferred. The voltage rating for input capacitors requirement does not need to be as conservative as the output capacitors, as the requirement for capacitance decreases as input voltage increases. For this example, the capacitor selected is 4.7 F 20%, rated to 50 V in the 1812 case size. The RMS current rating of these capacitors is over 2 A each, more than enough for this application. 8.2.2.8 Current Sense Filter Parasitic circuit capacitance, inductance, and gate drive current create a spike in the current sense voltage at the point where Q1 turns on. To prevent this spike from terminating the on-time prematurely, every circuit must have a low-pass filter that consists of CCS and RS1, shown in Figure 14. The time constant of this filter must be long enough to reduce the parasitic spike without significantly affecting the shape of the actual current sense voltage. The recommended range for RS1 is between 10 and 500 , and the recommended range for CCS is between 100 pF and 2.2 nF. For this example, the values of RS1 and CCS is 100 and 1 nF, respectively. 20 Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 8.2.2.9 RSNS, RS2, and Current Limit The current sensing resistor, RSNS, is used for steady-state regulation of the inductor current and to sense overcurrent conditions. The slope compensation resistor is used to ensure control loop stability, and both resistors affect the current limit threshold. The RSNS value selected must be low enough to keep the power dissipation to a minimum, yet high enough to provide good signal-to-noise ratio for the current sensing circuitry. RSNS and RS2 must be set so that the current limit comparator, with a threshold of 0.5 V, trips before the sensed current exceeds the peak current rating of the inductor, without limiting the output power in steady state. For this example, the peak current at VIN(MIN) is 2.5 A, while the inductor itself is rated to 3.2 A. The threshold for current limit, ILIM, is set slightly between these two values to account for tolerance of the circuit components, at a level of 3 A. The required resistor calculation must take both the switch current through RSNS and the compensation ramp current flowing through the internal 2-k RS1 and RS2 resistors into account. RSNS must be selected first because it is a power resistor with more limited selection. Equation 36 and Equation 37 must be evaluated at VIN(MIN) when duty cycle is highest. R SNS L u f SW u V CL VO V IN u 3 u D L u f SW uI LIM (36) R SNS 40 33 u 0.5 u 0.5 9 u 3 u 0.78 33 u 0.5 u 3 where * * L is in H fSW in MHz (37) The closest 5% value is 100 m. Power dissipation in RSNS can be estimated by calculating the average current. The worst-case average current through RSNS occurs at minimum input voltage/maximum duty cycle and can be calculated with Equation 38 and Equation 39. PCS 2 I * O u R SNS u D (c) 1 D 1/4 (38) (39) PCS = [(0.5 / 0.22)2 x 0.1] x 0.78 = 0.4 W For this example, a 0.1 1%, thick-film chip resistor in a 1210 case size rated to 0.5 W is used. With RSNS selected, RS2 can be determined using Equation 40 and Equation 41. R S2 R S2 V CL I ILIM u R SNS 2000 45P u D 0.5 3 u 0.1 45P u 0.78 R S1 (40) 2000 100 3598: (41) The closest 1% tolerance value is 3.57 k. 8.2.2.10 Control Loop Compensation The LM5022 uses peak current-mode PWM control to correct changes in output voltage due to line and load transients. Peak current-mode provides inherent cycle-by-cycle current limiting, improved line transient response, and easier control loop compensation. The control loop is comprised of two parts. The first is the power stage, which consists of the pulse width modulator, output filter, and the load. The second part is the error amplifier, which is an op-amp configured as an inverting amplifier. Figure 17 shows the regulator control loop components. Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 21 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com L + D VIN CO RO + - RSNS RC + RFB2 R1 C2 C1 + VREF RFB1 + - Figure 17. Power Stage and Error Amplifier One popular method for selecting the compensation components is to create Bode plots of gain and phase for the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the regulator easy to determine. Software tools such as Excel, MathCAD, and Matlab are useful for observing how changes in compensation or the power stage affect system gain and phase. The power stage in a CCM peak current mode boost converter consists of the DC gain, APS, a single lowfrequency pole, LFP, the ESR zero, ZESR, a right-half plane zero, RHP, and a double pole resulting from the sampling of the peak current. The power stage transfer function (also called the control-to-output transfer function) can be written with Equation 42, Equation 43, and Equation 44. ae s oae s o c1 + / c1 / wZESR o e wRHP o e GPS = APS ae s oae s s2 o / + c1 + / cc 1 + Qn wn w2n o/ wLEP o e e where * A PS 22 the DC gain is defined as: (42) (1 D) u R O 2 u R SNS where (43) RO = VO / IO (44) Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 The system ESR zero is calculated with Equation 45. ZZESR 1 RCu CO (45) The low-frequency pole is calculated with Equation 46. 1 Z LEP 0.5 u R O ESR u C O (46) The right-half plane zero is calculated with Equation 47. V IN * ROu VO (c) L Z RHP 2 (47) The sampling double-pole quality factor is calculated with Equation 48. Qn 1 S D 0.5 (1 D) Se S n 1/4 (48) The sampling double corner frequency is calculated with Equation 49. n = x fSW (49) The natural inductor current slope is calculated with Equation 50. Sn = RSNS x VIN / L (50) The external ramp slope is calculated with Equation 51. Se = 45 A x (2000 + RS1 + RS2)] x SW (51) In Equation 43, DC gain is highest when input voltage and output current are at the maximum. In this example, those conditions are VIN = 16 V and IO = 500 mA. DC gain is 44 dB. The low-frequency pole, fP = P / 2, is at 423 Hz, the ESR zero, fZ = Z / 2, is at 5.6 MHz, and the right-half plane zero, RHP = RHP / 2, is at 61 kHz. The sampling double-pole occurs at one-half of the switching frequency. Proper selection of slope compensation (through RS2) is most evident the sampling double pole. A well-selected RS2 value eliminates peaking in the gain and reduces the rate of change of the phase lag. Gain and phase plots for the power stage are shown in Figure 18 and Figure 19. 60 180 45 120 POWER STAGE PHASE () POWER STAGE GAIN (dB) SPACE 30 15 0 -15 -30 100 1k 10k 100k 60 0 -60 -120 -180 100 1M FREQUENCY (Hz) 1k 10k 100k 1M FREQUENCY (Hz) Figure 18. Power Stage Gain and Phase Figure 19. Power Stage Gain and Phase Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 23 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com The single pole causes a rolloff in the gain of -20 dB/decade at lower frequency. The combination of the RHP zero and sampling double pole maintain the slope out to beyond the switching frequency. The phase tends towards -90 at lower frequency but then increases to -180 and beyond from the RHP zero and the sampling double pole. The effect of the ESR zero is not seen because its frequency is several decades above the switching frequency. The combination of increasing gain and decreasing phase makes converters with RHP zeroes difficult to compensate. Setting the overall control loop bandwidth to 1/3 to 1/10 of the RHP zero frequency minimizes these negative effects, but requires a compromise in the control loop bandwidth. If this loop were left uncompensated, the bandwidth would be 89 kHz and the phase margin -54. The converter would oscillate, and therefore is compensated using the error amplifier and a few passive components. The transfer function of the compensation block (GEA) can be derived by treating the error amplifier as an inverting op amp with input impedance ZI and feedback impedance ZF. The majority of applications require a Type II, or two-pole one-zero amplifier, shown in Figure 17. The LaPlace domain transfer function for this Type II network is given by Equation 52. G EA ZF ZI 1 R FB2 (C1 C2) u s u R1 u C2 1 s u R1 u C1 u C2 * s 1 C1 C2 (c) (52) Many techniques exist for selecting the compensation component values. The following method is based upon setting the mid-band gain of the error amplifier transfer function first and then positioning the compensation zero and pole: 1. Determine the desired control loop bandwidth: The control loop bandwidth (0dB) is the point at which the total control loop gain (H = GPS x GEA) is equal to 0 dB. For this example, a low bandwidth of 10 kHz, or approximately 1/6th of the RHP zero frequency, is chosen because of the wide variation in input voltage. 2. Determine the gain of the power stage at 0dB: This value, A, can be read graphically from the gain plot of GPS or calculated by replacing the `s' terms in GPS with `2 f0dB'. For this example, the gain at 10 kHz is approximately 16 dB. 3. Calculate the negative of A and convert it to a linear gain: By setting the mid-band gain of the error amplifier to the negative of the power stage gain at f0dB, the control loop gain equals 0 dB at that frequency. For this example, -16 dB = 0.15 V/V. 4. Select the resistance of the top feedback divider resistor RFB2: This value is arbitrary, however, selecting a resistance between 10 k and 100 k leads to practical values of R1, C1, and C2. For this example, RFB2 = 20 k 1%. 5. Set Equation 55: R1 = A x RFB2 (53) For this example: R1 = 0.15 x 20000 = 3 k 6. Select a frequency for the compensation zero, Z1: The suggested placement for this zero is at the lowfrequency pole of the power stage, LFP = LFP / 2. For this example, Z1 = LFP = 423 Hz. 7. Set Equation 54. C2 1 : 2S u R1 u fZ1 (54) For this example, C2 = 125 nF 8. Select a frequency for the compensation pole, P1: The suggested placement for this pole is at one-fifth of the switching frequency. For this example, P1 = 100 kHz 9. Set Equation 55. C1 = C2 2OExC2xR1xf P1 -1 (55) For this example, C1 = 530 pF 24 Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 10. Plug the closest 1% tolerance values for RFB2 and R1, then the closest 10% values for C1 and C2 into GEA and model the error amp: The open-loop gain and bandwidth of the internal error amplifier of the LM5022 are 75 dB and 4 MHz, respectively. Their effect on GEA can be modeled using Equation 56: OPG 2S u GBW 2S u GBW s A DC (56) ADC is a linear gain, the linear equivalent of 75 dB is approximately 5600 V/V. C1 = 560 pF 10%, C2 = 120 nF 10%, R1 = 3.01 k 1% 11. Plot or evaluate the actual error amplifier transfer function: G EA G EA u OPG ACTUAL 1 G EA u OPG (57) 60 OVERALL LOOP GAIN (dB) 40 20 0 -20 -40 -60 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 20. Overall Loop Gain and Phase OVERALL LOOP PHASE () 180 120 60 0 -60 -120 -180 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 21. Overall Loop Gain and Phase 12. Plot or evaluate the complete control loop transfer function: The complete control loop transfer function is obtained by multiplying the power stage and error amplifier functions together. The bandwidth and phase margin can then be read graphically or evaluated numerically. The bandwidth of this example circuit at VIN = 16 V is 10.5 kHz with a phase margin of 66. Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 25 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com 13. Re-evaluate at the corners of input voltage and output current: Boost converters exhibit significant change in their loop response when VIN and IO change. With the compensation fixed, the total control loop gain and phase must be checked to ensure a minimum phase margin of 45 over both line and load. 8.2.2.11 Efficiency Calculations A reasonable estimation for the efficiency of a boost regulator controlled by the LM5022 can be obtained by adding together the loss is each current carrying element and using Equation 58. K PO PO P total loss (58) The following shows an efficiency calculation to complement the circuit design. Output power for this circuit is 40 V x 0.5 A = 20 W. Input voltage is assumed to be 13.8 V, and the calculations used assume that the converter runs in CCM. Duty cycle for VIN = 13.8 V is 66%, and the average inductor current is 1.5 A. 8.2.2.11.1 Chip Operating Loss This term accounts for the current drawn at the VIN pin. This current, IIN, drives the logic circuitry and the power MOSFETs. The gate driving loss term from MOSFET is included in the chip operating loss. For the LM5022, IIN is equal to the steady-state operating current, ICC, plus the MOSFET driving current, IGC. Power is lost as this current passes through the internal linear regulator of the LM5022 in Equation 59. IGC = QG x SW IGC = 27 nC x 500 kHz = 13.5 mA (59) ICC is typically 3.5 mA (taken from the Electrical Characteristics). Chip operating loss is then calculated with Equation 60. PQ = VIN x (IQ + IGC) PQ = 13.8 x (3.5 m + 13.5m) = 235 mW (60) 8.2.2.11.2 MOSFET Switching Loss PSW = 0.5 x VIN x IL x (tR + tF) x fSW PSW = 0.5 x 13.8 x 1.5 x (10 ns + 12 ns) x 5 x 105 = 114 mW (61) 8.2.2.11.3 MOSFET and RSNS Conduction Loss PC = D x (IL2 x (RDSON x 1.3 + RSNS)) PC = 0.66 x (1.52 x (0.029 + 0.1)) = 192 mW (62) 8.2.2.11.4 Output Diode Loss The average output diode current is equal to IO or 0.5 A. The estimated forward drop (VD) is 0.5 V. The output diode loss is Equation 63. PD1 = IO x VD PD1 = 0.5 x 0.5 = 0.25 W (63) 8.2.2.11.5 Input Capacitor Loss This term represents the loss as input ripple current passes through the ESR of the input capacitor bank. In this equation, `n' is the number of capacitors in parallel. The 4.7-F input capacitors selected have a combined ESR of approximately 1.5 m, and iL for a 13.8-V input is 0.55 A in Equation 64 and Equation 65. PCIN I IN 2 RMS u ESR n IIN-RMS = 0.29 x iL = 0.29 x 0.55 = 0.16 A PCIN = [0.162 x 0.0015] / 2 = 0.02 mW (negligible) (64) (65) 8.2.2.11.6 Output Capacitor Loss This term is calculated using the same method as the input capacitor loss, substituting the output capacitor RMS current for VIN = 13.8 V. The combined ESR of the output capacitors is also approximately 1.5 m in Equation 66. IO-RMS = 1.13 x 1.5 x (0.66 x 0.34)0.5 = 0.8 A PCO = [0.8 x 0.0015] / 2 = 0.6 mW 26 Submit Documentation Feedback (66) Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 8.2.2.11.7 Boost Inductor Loss The typical DCR of the selected inductor is 40 m in Equation 67. PDCR = IL2 x DCR PDCR = 1.52 x 0.04 = 90 mW (67) Core loss in the inductor is estimated to be equal to the DCR loss, adding an additional 90 mW to the total inductor loss. 8.2.2.11.8 Total Loss PLOSS = Sum of All Loss Terms = 972 mW (68) 8.2.2.11.9 Efficiency = 20 / (20 + 0.972) = 95% (69) Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 27 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com 8.2.3 Application Curves 10V/DIV VO SW 10V/DIV 1 es/DIV VIN = 9 V, IO = 0.5 A Figure 23. Switch Node Voltage Figure 22. Efficiency 10V/DIV VO VO 50 mV/DIV SW 10V/DIV 1 es/DIV 1 es/DIV VIN = 16 V, IO = 0.5 A VIN = 9 V, IO = 0.5 A Figure 24. Switch Node Voltage Figure 25. Output Voltage Ripple AC Coupled 200 mA/DIV IO VO VO 2V/DIV 50 mV/DIV 400 es/DIV 1 es/DIV VIN = 9 V, IO = 50 mA to 0.5 A VIN = 16 V, IO = 0.5 A Figure 26. Output Voltage Ripple AC Coupled 28 Submit Documentation Feedback Figure 27. Load Transient Response Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 200 mA/DIV IO VO 1V/DIV 1 ms/DIV VIN = 16 V, IO = 50 mA to 0.5 A Figure 28. Load Transient Response 9 Power Supply Recommendations The LM5022 is a power management device. The power supply for the device can be any DC voltage source within the specified input range. Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 29 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com 10 Layout 10.1 Layout Guidelines To produce an optimal power solution with the LM5022, good layout and design of the PCB are as critical as component selection. The following are the several guidelines to create a good layout of the PCB, as based on Figure 14: 1. Using a low-ESR ceramic capacitor, place CINX as close as possible to the VIN and GND pins of the LM5022. 2. Using a low-ESR ceramic capacitor, place COX close to the load as possible of the LM5022. 3. Using a low-ESR ceramic capacitor, place CF close to the VCC and GND pins of the LM5022. 4. Minimize the loop area formed by the output capacitor connections (Co1, Co2) by D1 and Rsns. Make sure the cathode of D1 and Rsns are positioned next to each other, and place Co1(+) and Co1(-) close to D1 cathode and Rsns(-) respectively. 5. Rsns(+) must be connected to the CS pin with a separate trace made as short as possible. This trace must be routed away from the inductor and the switch node (where D1, Q1, and L1 connect). 6. Minimize the trace length to the FB pin by positioning RFB1 and RFB2 close to the LM5022. 7. Route the VOUT sense path away from noisy node and connect it as close as possible to the positive side of COX. 10.1.1 Filter Capacitors The low-value ceramic filter capacitors are most effective when the inductance of the current loops that they filter is minimized. Place CINX as close as possible to the VIN and GND pins of the LM5022. Place COX close to the load, and CF next to the VCC and GND pins of the LM5022. 10.1.2 Sense Lines The top of RSNS must be connected to the CS pin with a separate trace made as short as possible. Route this trace away from the inductor and the switch node (where D1, Q1, and L1 connect). For the voltage loop, keep RFB1/2 close to the LM5022 and run a trace from as close as possible to the positive side of COX to RFB2. As with the CS line, the FB line must be routed away from the inductor and the switch node. These measures minimize the length of high impedance lines and reduce noise pickup. 10.1.3 Compact Layout Parasitic inductance can be reduced by keeping the power path components close together. As described in the Layout Guidelines, keep the high slew-rate current loops as tight as possible. Short, thick traces or copper pours (shapes) are best. The switch node must be just large enough to connect all the components together without excessive heating from the current it carries. The LM5022 (boost converter) operates in two distinct cycles whose high current paths are shown in Figure 29. + - Figure 29. Boost Converter Current Loops 30 Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 Layout Guidelines (continued) The dark grey, inner loops represents the high current paths during the MOSFET on-time. The light grey, outer loop represents the high current path during the off-time. 10.1.4 Ground Plane and Shape Routing The diagram of Figure 29 is also useful for analyzing the flow of continuous current versus the flow of pulsating currents. The circuit paths with current flow during both the on-time and off-time are considered to be continuous current, while those that carry current during the on-time or off-time only are pulsating currents. Preference in routing must be given to the pulsating current paths, as these are the portions of the circuit most likely to emit EMI. The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just as any other circuit path. The continuous current paths on the ground net can be routed on the system ground plane with less risk of injecting noise into other circuits. The path between the input source, input capacitor and the MOSFET and the path between the output capacitor and the load are examples of continuous current paths. In contrast, the path between the grounded side of the power switch and the negative output capacitor terminal carries a large pulsating current. This path must be routed with a short, thick shape, preferably on the component side of the PCB. Multiple vias in parallel must be used right at the negative pads of the input and output capacitors to connect the component side shapes to the ground plane. Vias must not be placed directly at the grounded side of the MOSFET (or RSNS) as they tend to inject noise into the ground plane. A second pulsating current loop that is often ignored but must be kept small is the gate drive loop formed by the OUT and VCC pins, Q1, RSNS, and capacitor CF. 10.2 Layout Examples Figure 30. Top Layer and Top Overlay Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 31 LM5022 SNVS480J - JANUARY 2007 - REVISED JULY 2020 www.ti.com Layout Examples (continued) Figure 31. Bottom Layer 32 Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 LM5022 www.ti.com SNVS480J - JANUARY 2007 - REVISED JULY 2020 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Development Support WEBENCH(R) software uses an iterative design procedure and accesses comprehensive databases of components. For more details, go to www.ti.com/webench. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: AN-1557 LM5022 Evaluation Board (SNVA203) 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Support Resources TI E2ETM support forums are an engineer's go-to source for fast, verified answers and design help -- straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.5 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.7 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2007-2020, Texas Instruments Incorporated Product Folder Links: LM5022 33 PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LM5022MM NRND VSSOP DGS 10 1000 Non-RoHS & Green Call TI Call TI -40 to 125 5022 LM5022MM/NOPB ACTIVE VSSOP DGS 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5022 LM5022MME/NOPB ACTIVE VSSOP DGS 10 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5022 LM5022MMX/NOPB ACTIVE VSSOP DGS 10 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5022 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM5022 : * Automotive: LM5022-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5022MM VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5022MM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5022MME/NOPB VSSOP DGS 10 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5022MMX/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5022MM VSSOP DGS 10 1000 210.0 185.0 35.0 LM5022MM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LM5022MME/NOPB VSSOP DGS 10 250 210.0 185.0 35.0 LM5022MMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DGS0010A VSSOP - 1.1 mm max height SCALE 3.200 SMALL OUTLINE PACKAGE C 5.05 TYP 4.75 SEATING PLANE PIN 1 ID AREA A 0.1 C 10 1 3.1 2.9 NOTE 3 8X 0.5 2X 2 5 6 B 10X 3.1 2.9 NOTE 4 SEE DETAIL A 0.27 0.17 0.1 C A 1.1 MAX B 0.23 TYP 0.13 0.25 GAGE PLANE 0 -8 0.15 0.05 0.7 0.4 DETAIL A TYPICAL 4221984/A 05/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA. www.ti.com EXAMPLE BOARD LAYOUT DGS0010A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 10X (0.3) 10X (1.45) (R0.05) TYP SYMM 1 10 SYMM 8X (0.5) 6 5 (4.4) LAND PATTERN EXAMPLE SCALE:10X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221984/A 05/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DGS0010A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 10X (1.45) 10X (0.3) SYMM 1 (R0.05) TYP 10 SYMM 8X (0.5) 6 5 (4.4) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221984/A 05/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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