FEATURES TYPICAL APPLICATION CIRCUIT Input supply voltage range: 2.15 V to 6.50 V Operates down to 2.00 V voltage Ultralow 180 nA quiescent current Selectable output voltage of 0.8 V to 5.0 V 1.5% output accuracy over full temperature range in PWM mode Selectable hysteresis mode or PWM operation mode Output current Up to 50 mA in hysteresis mode Up to 500 mA in PWM mode VOUTOK flag monitors the output voltage Ultrafast stop switching control 100% duty cycle operation mode 2.0 MHz typical switching frequency in PWM mode with optional SYNC clock range from 1.5 MHz to 2.5 MHz Quick output discharge (QOD) option UVLO, OCP, and TSD protection 10-lead, 3 mm x 3 mm LFCSP -40C to +125C operating temperature range 2.2H VIN = 2.15 TO 6.50V SW PVIN VOUT 10F ADP5300 10F ON PGND EN OFF PWM SYNC/MODE HYS STOP SW STOP AGND FB VOUTOK VID EPAD R0 VID0: 1.2V VID1: 1.5V VID2: 1.8V VID3: 2.0V VID4: 2.1V VID5: 2.2V VID6: 2.3V VID7: 2.4V VID8: 2.5V VID9: 2.6V VID10: 2.7V VID11: 2.8V VID12: 2.9V VID13: 3.0V VID14: 3.3V VID15: 3.6V 13366-001 Data Sheet 50 mA/500 mA, High Efficiency, Ultralow Power Step-Down Regulator ADP5300 Figure 1. APPLICATIONS Energy (gas and water) metering Portable and battery-powered equipment Medical applications Keep-alive power supplies GENERAL DESCRIPTION The ADP5300 is a high efficiency, ultralow quiescent current step-down regulator that draws only 180 nA quiescent current to regulate the output. The ADP5300 runs from an input supply voltage range of 2.15 V to 6.50 V, allowing the use of multiple alkaline or NiMH, Li-Ion cells, or other power sources. The output voltage is selectable from 0.8 V to 5.0 V by an external VID resistor and factory fuse. The total solution requires only four tiny external components. The ADP5300 can operate between hysteresis mode and pulsewidth modulation (PWM) mode via the SYNC/MODE pin. The regulator in hysteresis mode achieves excellent efficiency at a power of less than 1 mW and provides up to 50 mA of output current. The regulator in PWM mode produces a lower output ripple and supplies up to 500 mA of output current. The flexible configuration capability during operation of the device enables very efficient power management to meet both the longest battery life and low system noise requirements. Rev. B The ADP5300 contains a VOUTOK flag, which monitors the output voltage and runs at a 2 MHz switching frequency in PWM mode. SYNC/MODE can be synchronized to an external clock from 1.5 MHz to 2.5 MHz. The ADP5300 includes an STOP pin that can disable the regulator switching temporarily, in this way a quiet system environment can be achieved to benefit noise sensitive circuitry, such as data conversion, RF data transmission, and analog sensing. Other key features in the ADP5300 include separate enabling, QOD, and safety features such as overcurrent protection (OCP), thermal shutdown (TSD), and input undervoltage lockout (UVLO). The ADP5300 is available in a 10-lead, 3 mm x 3 mm LFCSP rated for a -40C to +125C operating temperature range. Multifunction pin names may be referenced by their relevant function only. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2015-2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP5300 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Short-Circuit Protection............................................................ 15 Applications ....................................................................................... 1 Soft Start ...................................................................................... 15 Typical Application Circuit ............................................................. 1 Startup with Precharged Output .............................................. 15 General Description ......................................................................... 1 100% Duty Operation ................................................................ 15 Revision History ............................................................................... 2 Active Discharge ......................................................................... 15 Detailed Functional Block Diagram .............................................. 3 VOUTOK Function ................................................................... 15 Specifications..................................................................................... 4 Stop Switching ............................................................................ 16 Absolute Maximum Ratings ............................................................ 6 Thermal Shutdown .................................................................... 16 Thermal Resistance ...................................................................... 6 Applications Information .............................................................. 17 ESD Caution .................................................................................. 6 External Component Selection ................................................ 17 Pin Configuration and Function Descriptions ............................. 7 Selecting the Inductor ................................................................ 17 Typical Performance Characteristics ............................................. 8 Output Capacitor........................................................................ 17 Theory of Operation ...................................................................... 14 Input Capacitor ........................................................................... 18 Buck Regulator Operational Modes......................................... 14 Efficiency ..................................................................................... 18 Osillator and Synchronization .................................................. 14 Circuit Board Layout Recommendations ............................... 18 Adjustable and Fixed Output Voltages .................................... 14 Typical Application Circuits ......................................................... 19 Undervoltage Lockout (UVLO) ............................................... 15 Factory Programmable Options ................................................... 20 Enable/Disable ............................................................................ 15 Outline Dimensions ....................................................................... 21 Current Limit .............................................................................. 15 Ordering Guide .......................................................................... 21 REVISION HISTORY 11/2017--Rev A. to Rev. B Change to Figure 44 ....................................................................... 19 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21 6/2016--Rev. 0 to Rev. A Changes to Features Section and General Description Section....... 1 Change to SYNC Clock Range Parameter, Table 1 ...................... 4 Change to Table 4 ............................................................................. 7 Change to Oscillator and Synchronization Section ................... 14 Changes to Table 8 .......................................................................... 20 Changes to Ordering Guide .......................................................... 21 8/2015--Revision 0: Initial Version Rev. B | Page 2 of 21 Data Sheet ADP5300 DETAILED FUNCTIONAL BLOCK DIAGRAM VOUTOK PVIN PVIN 90% 87% DRIVER ILIM_PWM FB SW ILIM_HYS 1.2V STOP -0.6A (PWM) 0A (HYS) CONTROL LOGIC FORCE SLEEP 0.4V PWM PVIN SLOPE COMPENSATION DRIVER PGND STANDBY 0.808V 0.8V FB INTERNAL FEEDBACK RESISTOR DIVIDER 0.8V V TO I VID MODE 1.2V 0.4V SOFT START EN PVIN UVLO AGND BAND GAP BIAS AND HOUSEKEEPING 2.06V 2.00V SYNC/ MODE SYNC KEEP ALIVE BLOCK MODE Figure 2. Rev. B | Page 3 of 21 2MHz OSC 13366-002 1.2V 0.4V ADP5300 Data Sheet SPECIFICATIONS VIN = 3.6 V, VOUT = 2.5 V, TJ = -40C to +125C for minimum and maximum specifications, and TA = 25C for typical specifications, unless otherwise noted. Table 1. Parameter INPUT SUPPLY VOLTAGE RANGE SHUTDOWN CURRENT Symbol VIN ISHUTDOWN QUIESCENT CURRENT Operating Quiescent Current in Hysteresis Mode IQ_HYS Operating Quiescent Current in Hysteresis Mode Operating Quiescent Current in PWM Mode UNDERVOLTAGE LOCKOUT UVLO Threshold Rising Falling OSCILLATOR CIRCUIT Switching Frequency in PWM Mode Feedback (FB) Threshold of Frequency Fold SYNCHRONIZATION THRESHOLD SYNC Clock Range SYNC High Level Threshold SYNC Low Level Threshold SYNC Duty Cycle Range SYNC/MODE Leakage Current MODE TRANSITION Transition Delay from Hysteresis Mode to PWM Mode EN PIN Input Voltage Threshold High Low Input Leakage Current STOP Switching PWM Switching Stop Delay PWM Switching Resume Delay FB PIN Output Options by VID Resistor PWM Mode Fixed VID Code Voltage Accuracy Adjustable VID Code Voltage Accuracy Min 2.15 Typ Unit V nA nA Test Conditions/Comments 18 18 Max 6.50 40 130 180 260 nA -40C TJ +85C 180 570 350 1400 nA nA IQ-HYS2 2.3 3.2 A -40C TJ +125C 100% duty cycle operation, VIN = 3.0 V, VOUT set to 3.3 V VIN = 3.6 V, VSTOP = 3.6 V IQ_PWM 425 630 A 2.06 2.00 2.14 V V 2.0 0.3 2.3 MHz V 2.5 MHz V V ns nA VEN = 0 V, -40C TJ +85C VEN = 0 V, -40C TJ +125C UVLO VUVLO_RISING VUVLO_FALLING 1.90 fSW VOSC_FOLD 1.7 SYNCCLOCK SYNCHIGH SYNCLOW SYNCDUTY ISYNC_LEAKAGE 1.5 1.2 100 50 tHYS_TO_PWM VIH VIL IEN_LEAKAGE 0.4 1/fSW - 150 150 20 Clock cycles 1.2 0.4 25 tSTOP-RISE-DELAY tSTOP-FALL-DELAY 10 20 VSYNC/MODE = 3.6 V SYNC/MODE goes logic high from logic low V V nA ns ns STOP goes logic high from low STOP goes logic low from high VOUT_OPT 0.8 5.0 V 0.8 V to 5.0 V in various factory options VFB_PWM_FIX -0.6 +0.6 % VFB_PWM_ADJ -1.2 -1.5 +1.2 +1.5 % % TJ = 25C, output voltage setting via factory fuse -40C TJ +125C Output voltage setting via VID resistor Rev. B | Page 4 of 21 Data Sheet Parameter Hysteresis Mode Fixed VID Code Threshold Accuracy from Active Mode to Standby Mode Adjustable VID Code Threshold Accuracy from Active Mode to Standby Mode Hysteresis of Threshold Accuracy from Active Mode to Standby Mode Feedback Bias Current SW PIN High-Side Power FET On Resistance Low-Side Power FET On Resistance Current Limit in PWM Mode Peak Current in Hysteresis Mode Minimum On Time VOUTOK PIN Monitor Threshold Monitor Hysteresis Monitor Rising Delay Monitor Falling Delay Leakage Current Output Low Voltage SOFT START Default Soft Start Time Start-Up Delay COUT DISCHARGE SWITCH ON RESISTANCE THERMAL SHUTDOWN Threshold Hysteresis ADP5300 Symbol Min VFB_HYS_FIX VFB_HYS_ADJ Typ Max Unit Test Conditions/Comments -0.75 +0.75 % TJ = 25C -2.5 -3 +2.5 +3 % % -40C TJ +125C -40C TJ +125C VFB_HYS (HYS) 1 IFB 66 25 95 45 nA nA Output Option 0, VOUT = 2.5 V Output Option 1, VOUT = 1.3 V RDS (ON) H RDS (ON) L ILIM_PWM ILIM_HYS tMIN_ON 386 299 1000 265 40 520 470 1200 m m mA mA ns Pin to pin measurement Pin to pin measurement SYNC/MODE = high SYNC/MODE = low 90 3 40 10 0.1 50 93 VOUTOK (RISE) VOUTOK (HYS) tVOUTOK_RISE tVOUTOK_FALL IVOUTOK_LEAKAGE VOUTOK_LOW 800 87 % 70 1 80 % % s s A mV tSS 350 s tSTART_DELAY 2 ms RDIS 290 TSHDN THYS 142 127 C C Rev. B | Page 5 of 21 IVOUTOK = 100 A Factory trim, 1 bit (350 s and 2800 s) Delay from the EN pin being pulled high ADP5300 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter PVIN to PGND SW to PGND FB to AGND VID to AGND EN to AGND VOUTOK to AGND SYNC/MODE to AGND STOP to AGND PGND to AGND Storage Temperate Range Operating Temperature Range Rating -0.3 V to +7 V -0.3 V to PVIN + 0.3 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +0.3 V -65C to +150C -40C to +125C JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. JC is the thermal resistance from the operating portion of the device to the outside surface of the package (case) closest to the device mounting area. Table 3. Thermal Resistance Package Type 10-Lead, 3 mm x 3 mm LFCSP ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 6 of 21 JA 57 JC 0.86 Unit C/W Data Sheet ADP5300 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EN 1 SYNC/MODE 3 VID 4 FB 5 10 PVIN ADP5300 TOP VIEW (Not to Scale) 9 SW 8 PGND 7 AGND 6 VOUTOK NOTES 1. THE EXPOSED PAD MUST BE SOLDERED TO A LARGE EXTERNAL COPPER GROUND PLANE UNDERNEATH THE IC FOR THERMAL DISSIPATION. 13366-003 STOP 2 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic EN STOP 3 SYNC/MODE 4 VID 5 6 7 8 9 10 FB VOUTOK AGND PGND SW PVIN EPAD Description Enable Input for the Regulator. Set to logic low to disable the regulator. Stop Switching Input Signal. When this pin is logic high, the regulator stops the regulator switching. When this pin is logic low, the regulator resumes the regulator switching. Synchronization Input Pin (SYNC). To synchronize the switching frequency of the device to an external clock, connect this pin to an external clock with a frequency from 1.5 MHz to 2.5 MHz. PWM or Hysteresis Mode Selection Pin (MODE). When this pin is logic high, the regulator operates in PWM mode. When this pin is logic low, the regulator operates in hysteresis mode. Voltage Configuration Pin. Connect an external resistor (RVID) from this pin to ground to configure the output voltage of the regulator (see Table 5). Feedback Sensing Input for the Regulator. Output Power-Good Signal. This open-drain output is the power-good signal for the output voltage. Analog Ground. Power Ground. Switching Node Output for the Regulator. Power Input for the Regulator. Exposed Pad. The exposed pad must be soldered to a large external copper ground plane underneath the IC for thermal dissipation. Rev. B | Page 7 of 21 ADP5300 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.6 V, VOUT = 2.5 V, L = 2.2 H, CIN = COUT = 10 F, fSW = 2 MHz, TA = 25C, unless otherwise noted. 100 100 90 90 60 VIN = 2.5V VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 50 40 0.01 0.1 1 LOAD CURRENT (mA) 10 40 0.001 0.01 0.1 1 LOAD CURRENT (mA) 10 Figure 7. Hysteresis Efficiency vs. Load Current, VOUT = 1.5 V 100 100 90 90 EFFICIENCY (%) 80 70 VIN = 2.5V VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 60 50 0.01 0.1 1 LOAD CURRENT (mA) 10 80 70 VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 60 50 0.001 13366-005 EFFICIENCY (%) VIN = 2.5V VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 60 50 Figure 4. Hysteresis Efficiency vs. Load Current, VOUT = 1.2 V 40 0.001 70 Figure 5. Hysteresis Efficiency vs. Load Current, VOUT = 1.8 V 0.01 0.1 1 LOAD CURRENT (mA) 13366-008 30 0.001 80 13366-007 EFFICIENCY (%) 70 13366-004 EFFICIENCY (%) 80 10 Figure 8. Hysteresis Efficiency vs. Load Current, VOUT = 2.5 V 100 100 90 90 80 60 50 40 VIN = 2.5V VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 30 VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 60 50 0.001 0.01 0.1 1 LOAD CURRENT (mA) 10 20 10 0 0 Figure 6. Hysteresis Efficiency vs. Load Current, VOUT = 3.3 V 100 200 300 LOAD CURRENT (mA) 400 Figure 9. PWM Efficiency vs. Load Current, VOUT = 1.2 V Rev. B | Page 8 of 21 500 13366-009 EFFICIENCY (%) 70 13366-006 EFFICIENCY (%) 70 80 Data Sheet ADP5300 100 90 80 80 70 70 EFFICIENCY (%) 90 60 50 40 VIN = 2.5V VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 10 100 200 300 LOAD CURRENT (mA) 400 40 20 10 500 0 0 100 90 90 80 80 70 70 EFFICIENCY (%) 100 60 50 40 10 100 200 300 LOAD CURRENT (mA) 400 50 40 500 0 0 200 300 LOAD CURRENT (mA) 400 350 QUIESCENT CURRENT (nA) -40C +25C +85C +125C 100 80 60 40 300 -40C +25C +85C +125C 250 200 150 0 2.3 2.9 3.5 4.1 4.7 VIN (V) 5.3 5.9 6.5 100 2.3 2.9 3.5 4.1 4.7 VIN (V) 5.3 5.9 6.5 Figure 15. Hysteresis Quiescent Current vs. VIN, SYNC/MODE = Low Figure 12. Shutdown Current vs. VIN, EN = Low Rev. B | Page 9 of 21 13366-015 20 13366-012 SHUTDOWN CURRENT (nA) 100 Figure 14. PWM Efficiency vs. Load Current, VOUT = 3.3 V 160 120 VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 10 Figure 11. PWM Efficiency vs. Load Current, VOUT = 2.5 V 140 500 60 20 0 0 500 30 VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 20 400 300 200 LOAD CURRENT (mA) 100 Figure 13. PWM Efficiency vs. Load Current, VOUT = 1.8 V 13366-011 EFFICIENCY (%) Figure 10. PWM Efficiency vs. Load Current, VOUT = 1.5 V 30 VIN = 2.5V VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 30 0 0 50 13366-013 20 60 13366-014 30 13366-010 EFFICIENCY (%) 100 ADP5300 Data Sheet 810 801 808 FEEDBACK VOLTAGE (mV) FEEDBACK VOLTAGE (mV) ACTIVE TO STANDBY 800 799 798 806 804 STANDBY TO ACTIVE 802 800 798 796 794 25 85 TEMPERATURE (C) 125 792 -40 Figure 16. Feedback Voltage vs. Temperature, PWM Mode 400 -40C +25C +125C -40C +25C +125C 350 LOW-SIDE RDS (ON) L (m) 500 400 300 200 300 250 200 3.5 4.1 4.7 VIN (V) 5.3 5.9 6.5 100 2.3 13366-017 2.9 2.9 Figure 17. High-Side RDS (ON) H vs. VIN 3.5 4.1 4.7 VIN (V) 5.3 5.9 6.5 5.9 6.5 13366-020 150 Figure 20. Low-Side RDS (ON) L vs. VIN 1090 1200 1150 PEAK CURRENT LIMIT (mA) 1040 990 940 890 1100 -40C +25C +125C 1050 1000 950 900 840 -40 25 85 TEMPERATURE (C) 125 13366-018 850 Figure 18. Peak Current Limit vs. Temperature 800 2.3 2.9 3.5 4.1 4.7 VIN (V) 5.3 Figure 21. Peak Current Limit vs. VIN Rev. B | Page 10 of 21 13366-021 HIGH-SIDE RDS (ON) H (m) 600 PEAK CURRENT LIMIT (mA) 125 Figure 19. Feedback Voltage vs. Temperature, Hysteresis Mode 700 100 2.3 25 85 TEMPERATURE (C) 13366-019 -40 13366-016 797 Data Sheet ADP5300 2.10 2.3 SWITCHING FREQUENCY (kHz) 2.08 2.06 2.04 2.02 FALLING 2.00 -40C +25C +125C 2.2 2.1 2.0 1.9 25 85 TEMPERATURE (C) -40 13366-022 1.96 125 1.7 2.3 2.9 Figure 22. UVLO Threshold, Rising and Falling vs. Temperature 3.5 4.1 4.7 VIN (V) 5.3 5.9 6.5 Figure 25. Switching Frequency vs. VIN VOUT 1 VOUT (AC) 1 SW IL 2 4 IL 4 2 M 200s A CH4 T 39.60% 140mA CH1 10.0mV Figure 23. Steady Waveform of Hysteresis Mode, ILOAD = 1 mA (IL is the Inductor Current) CH2 2.00V CH4 200mA M 400ns A CH2 T 90.60% 2.72V 13366-026 CH2 2.00V CH4 500mA 13366-023 SW CH1 100mV Figure 26. Steady Waveform of PWM Mode, ILOAD = 300 mA (IL is the Inductor Current) VIN VIN 3 VOUT VOUT 1 1 IL IL 4 4 SW SW 2 CH1 1.00V CH3 2.00V CH2 5.00V CH4 500mA M 200s A CH1 T 50.60% 1.22V CH1 500mV CH3 2.00V Figure 24. Soft Start, ILOAD = 300 mA (IL is the Inductor Current) CH2 5.00V CH4 500mA M 100s A CH1 T 40.00% Figure 27. Soft Start with Precharge Function (IL is the Inductor Current) Rev. B | Page 11 of 21 1.05V 13366-027 2 13366-025 1.8 1.98 13366-024 UVLO THRESHOLD (V) RISING ADP5300 Data Sheet VOUT (AC) 1 1 VOUT (AC) IOUT IOUT 4 CH4 50.0mA M 200s A CH4 T 20.80% 111mA CH1 50.0mV CH4 200mA Figure 28. Load Transient of Hysteresis Mode, ILOAD from 0 mA to 50 mA M 200s A CH4 T 20.40% 308mA 13366-031 CH1 50.0mV 13366-028 4 Figure 31. Load Transient of PWM Mode, ILOAD from 125 mA to 375 mA 1 1 VOUT (AC) VOUT (AC) VIN VIN IL 4 3 IL 4 2 SW 2 CH2 5.00V CH4 500mA M 2.00ms A CH3 T 30.00% 4.72V CH2 5.00V CH4 500mA CH1 10.0mV CH3 2.00V Figure 29. Line Transient of Hysteresis Mode, ILOAD = 10 A (IL is the Inductor Current) M 2.00ms A CH3 T 30.20% 4.28V 13366-032 CH1 50.0mV CH3 2.00V 13366-029 SW Figure 32. Line Transient of PWM Mode, ILOAD = 500 mA (IL is the Inductor Current) VIN VOUT VOUT 1 VOUTOK 3 1 IL SW 4 CH4 200mA M 10.0ms A CH3 T 40.20% 4.80V CH1 1.00V CH3 1.00V Figure 30. Input Voltage Ramp Up and Ramp Down in Hysteresis Mode (IL is the Inductor Current) Rev. B | Page 12 of 21 CH2 2.00V M 200s A CH1 T 40.00% Figure 33. VOUTOK Function 1.32V 13366-033 CH1 1.00V CH3 1.00V 13366-030 2 Data Sheet ADP5300 VOUT VOUT 1 1 IL IL 4 4 SW SW M 10.0s A CH1 T 40.20% 1.44V CH1 2.00V CH2 2.00V CH4 500mA Figure 34. Output Short Protection (IL is the Inductor Current) M 1.00ms A CH1 T 40.20% 1.44V 13366-036 CH2 2.00V CH4 500mA 13366-034 CH1 2.00V 1.64V 13366-037 2 2 Figure 37. Output Short Recovery (IL is the Inductor Current) EN 1 SYNC/ MODE 3 VOUT SW 1 2 2 CH1 2.00V CH2 2.00V M 400ns A CH2 T 50.00% 1.40V 13366-035 SW CH1 1.00V CH3 2.00V CH2 2.00V M 4.00ms A CH3 T 40.00% Figure 38. Quick Output Discharge Function Figure 35. Synchronized to 2.5 MHz 1 VOUT VOUT 1 VSTOP SYNC/MODE 3 3 SW SW CH2 2.00V M 20.0s A CH3 T 39.80% 1.56V 13366-136 CH1 100mV CH3 2.00V BW CH1 2.00V CH3 2.00V Figure 36. Hysteresis Mode to PWM Mode with 10 mA Load Current B W CH2 2.00V M 100ms A CH3 B W Figure 39. STOP Switching Function Rev. B | Page 13 of 21 520mV 13366-137 2 2 ADP5300 Data Sheet THEORY OF OPERATION The ADP5300 is a high efficient, ultralow quiescent current, step-down regulator in a 10-lead LFCSP package to meet demanding performance and board space requirements. The device enables direct connection to a wide input voltage range of 2.15 V to 6.50 V, allowing the use of multiple alkaline/NiMH or, Li-Ion cells and other power sources. BUCK REGULATOR OPERATIONAL MODES PWM Mode In PWM mode, the buck regulator in the ADP5300 operates at a fixed frequency that is set by an internal oscillator. At the start of each oscillator cycle, the high-side MOSFET switch turns on and sends a positive voltage across the inductor. The inductor current increases until the current sense signal exceeds the peak inductor current threshold, which turns off the high-side MOSFET switch. This threshold is set by the error amplifier output. During the high-side MOSFET off time, the inductor current decreases through the low-side MOSFET until the next oscillator clock pulse starts a new cycle. Hysteresis Mode In hysteresis mode, the buck regulator in the ADP5300 charges the output voltage slightly higher than its nominal output voltage with PWM pulses by regulating the constant peak inductor current. When the output voltage increases until the output sense signal exceeds the hysteresis upper threshold, the regulator enters standby mode. In standby mode, the high-side and low-side MOSFETs and a majority of the circuitry are disabled to allow a low quiescent current as well as high efficiency performance. During standby mode, the output capacitor supplies energy into the load, and the output voltage decreases until it falls below the hysteresis comparator lower threshold. The buck regulator wakes up and generates the PWM pulses to charge the output again. Because the output voltage occasionally enters standby mode and then recovers, the output voltage ripple in hysteresis mode is larger than the ripple in PWM mode. Mode Selection The ADP5300 includes the SYNC/MODE pin to allow flexible configuration in hysteresis mode or PWM mode. When a logic high level is applied to the SYNC/MODE pin, the buck regulator is forced to operate in PWM mode. In PWM mode, the regulator can supply up to 500 mA of output current. The regulator can provide lower output ripple and output noise in PWM mode, which is useful for noise sensitive applications. When a logic low level is applied to the SYNC/MODE pin, the buck regulator is forced to operate in hysteresis mode. In hysteresis mode, the regulator draws only 180 nA of quiescent current typical to regulate the output under zero load, which allows the regulator to act as a keep-alive power supply in a battery-powered system. In hysteresis mode, the regulator supplies up to 50 mA of output current with a relatively large output ripple compared to PWM mode. The user can alternate between hysteresis mode and PWM mode during operation. The flexible configuration capability during operation of the device enables efficient power management to meet high efficiency and low output ripple requirements when the system switches between active mode and standby mode. OSILLATOR AND SYNCHRONIZATION The ADP5300 operates at a 2 MHz switching frequency typical in PWM operation mode. The switching frequency of the ADP5300 can be synchronized to an external clock with a frequency range from 1.5 MHz to 2.5 MHz. The ADP5300 automatically detects the presence of an external clock applied to the SYNC/MODE pin, and the switching frequency transitions to the frequency of the external clock. When the external clock signal stops, the device automatically switches back to the internal clock. ADJUSTABLE AND FIXED OUTPUT VOLTAGES The ADP5300 provides adjustable output voltage settings by connecting one resistor through the VID pin to AGND. The VID detection circuitry works in the start-up period, and the voltage ID code is sampled and held in the internal register and does not change until the next power recycle. Furthermore, the ADP5300 provides a fixed output voltage programmed via the factory fuse. In this condition, connect the VID pin to the PVIN pin. For the output voltage settings, the feedback resistor divider is built into the ADP5300, and the feedback pin (FB) must be tied directly to the output. An ultralow power voltage reference and an integrated high impedance (50 M typical) feedback divider network contribute to the low quiescent current. Table 5 lists the output voltage options by the VID pin configurations. A 1% accuracy resistor through VID to ground is recommended. Table 5. Output Voltage (VOUT) Options by the VID Pin VID Configuration Short to Ground Short to PVIN RVID = 499 k RVID = 316 k RVID = 226 k RVID = 174 k RVID = 127 k RVID = 97.6 k RVID = 76.8 k RVID = 56.2 k RVID = 43 k RVID = 32.4 k RVID = 25.5 k RVID = 19.6 k RVID = 15 k RVID = 11.8 k Rev. B | Page 14 of 21 VOUT (V) Factory Option 0 Factory Option 1 3.0 3.1 2.5 1.3 3.6 5.0 3.3 4.5 2.9 4.2 2.8 3.9 2.7 3.4 2.6 3.2 2.4 1.9 2.3 1.7 2.2 1.6 2.1 1.4 2.0 1.1 1.8 1.0 1.5 0.9 1.2 0.8 Data Sheet ADP5300 UNDERVOLTAGE LOCKOUT (UVLO) STARTUP WITH PRECHARGED OUTPUT The undervoltage lockout circuitry monitors the input voltage level on the PVIN pin. If the input voltage falls below 2.00 V (typical), the regulator turns off. After the input voltage rises above 2.06 V (typical), the soft start period initiates, and when the EN pin is high, the regulator enables. The buck regulators in the ADP5300 include a precharged start-up feature to protect the low-side MOSFET from damage during startup. If the output voltage is precharged before the regulator turns on, the regulator prevents reverse inductor current, which discharges the output capacitor, until the internal soft start reference voltage exceeds the precharged voltage on the FB pin. ENABLE/DISABLE The ADP5300 includes a separate enable (EN) pin. A logic high on the EN pin starts the regulator. Due to the low quiescent current design, it is typical for the regulator to start switching after a delay of a few milliseconds from the EN pin being pulled high. A logic low on the EN pin immediately disables the regulator and brings the regulator into extremely low current consumption. CURRENT LIMIT The buck regulators in the ADP5300 have protection circuitry that limits the direction and the amount of current to a certain level that flows through the high-side MOSFET and the lowside MOSFET in cycle-by-cycle mode. The positive current limit on the high-side MOSFET limits the amount of current that can flow from the input to the output. The negative current limit on the low-side MOSFET prevents the inductor current from reversing direction and flowing out of the load. SHORT-CIRCUIT PROTECTION The buck regulators in the ADP5300 include frequency foldback to prevent current runaway on a hard short. When the output voltage at the feedback (FB) pin falls below 0.3 V typical, indicating the possibility of a hard short at the output, the switching frequency (in PWM mode) is reduced to one-fourth of the internal oscillator frequency. The reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. SOFT START The ADP5300 has an internal soft start function that ramps up the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This feature prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the device. The default typical soft start time is 350 s for the regulator. 100% DUTY OPERATION When the input voltage approaches the output voltage, the ADP5300 stops switching and enters 100% duty cycle operation. It connects the output via the inductor and the internal high-side power switch to the input. When the input voltage is charged again and the required duty cycle falls to 95% typical, the buck immediately restarts switching and regulation without allowing overshoot on the output voltage. In hysteresis mode, the ADP5300 draws an ultralow quiescent current of only 570 nA typical during 100% duty cycle operation. ACTIVE DISCHARGE The regulator in the ADP5300 integrates an optional, factory programmable discharge switch from the switching node to ground. This switch turns on when its associated regulator is disabled, which helps discharge the output capacitor quickly. The typical value of the discharge switch is 290 for the regulator. By default, the discharge function is not enabled. The factory fuse can enable the active discharge function. VOUTOK FUNCTION The ADP5300 includes an open-drain, power-good output (VOUTOK pin) that is active high when the buck regulator operates normally. By default, the VOUTOK pin monitors the output voltage. A logic high on the VOUTOK pin indicates that the regulated output voltage of the buck regulator is above 90% (typical) of its nominal output. When the regulated output voltage of the buck regulator falls below 87% (typical) of its nominal output for a delay time greater than approximately 10 s, the VOUTOK pin goes low. A different soft start time (2800 s) can be programmed for ADP5300 by the factory fuse. Rev. B | Page 15 of 21 ADP5300 Data Sheet STOP SWITCHING 2.540V The ADP5300 includes a stop input pin (STOP) that can temporarily stop the regulator switching in hysteresis mode. 2.500V DC TO DC OUTPUT When a logic high level is applied to the STOP pin, the buck regulator is forced to stop switching immediately. When a logic low level is applied to the STOP pin, the buck regulator resumes switching. Note that tens of nanoseconds delay time exists from when the STOP signal goes high to fully stop switching. When the regulator is enabled with EN pin pulled high, the STOP signal control is valid, and when EN pin is logic low, the STOP signal is ignored. DC TO DC SWITCHING 10ms OF mA 2A OUTPUT LOAD STOP SIGNAL VOUTOK FLAG Figure 40. STOP Switching Operation Status THERMAL SHUTDOWN If the ADP5300 junction temperature exceeds 142C, the thermal shutdown circuit turns off the IC except for the internal linear regulator. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 15C hysteresis is included so that the ADP5300 does not return to operation after thermal shutdown until the junction temperature falls below 127C. When the device exits thermal shutdown, a soft start initiates for each enabled channel. Rev. B | Page 16 of 21 13366-040 In some battery-powered systems, the microcontroller unit (MCU) can command the regulator to stop switching via the STOP signal, and the regulator then relies on the output capacitor to supply the load. In this period, a quiet system environment can be achieved which benefits the noise sensitive circuitry, such as data conversion, RF data transmission, and analog sensing. After the noise sensitive circuitry completes its task, the MCU can control the regulator and resume switching regulation mode. If needed, the VOUTOK signal can monitor the output voltage in the event it dips too low to latch up the system. Figure 40 shows the STOP switching operation status in ADP5300. 2.175V TO VOUTOK THRESHOLD Data Sheet ADP5300 APPLICATIONS INFORMATION This section describes the external components selection for the ADP5300. The typical application circuit is shown in Figure 41. 2.2H PVIN 10F MLCC SW ADP5300 EN 10F MLCC PGND SYNC/MODE STOP VOUT = 1.8V I L VOUT R2 1M FB VOUTOK AGND VID EPAD 1 - VOUT VIN L f SW I I PK I LOAD(MAX) L 2 R1 19.6k Use the inductor series from the different vendors shown in Table 6. 13366-041 VIN = 2.15V TO 6.50V A minimum requirement of the dc current rating of the inductor is for it to be equal to the maximum load current plus half of the inductor current ripple (IL), as shown by the following equations: Figure 41. Typical Application Circuit EXTERNAL COMPONENT SELECTION The ADP5300 is optimized for operation with a 2.2 H inductor and 10 F output capacitors for various output voltages using the closed-loop compensation and adaptive slope compensation circuits. The selection of components depends on the efficiency, the load current transient, and other application requirements. The trade-offs among performance parameters, such as efficiency and transient response, are made by varying the choice of external components. SELECTING THE INDUCTOR The high switching frequency of the ADP5300 allows the use of small surface-mount power inductors. The dc resistance (DCR) value of the selected inductor affects efficiency. In addition, it is recommended to select a multilayer inductor rather than a magnetic iron inductor because the high switching frequency increases the core temperature rise and enlarges the core loss. OUTPUT CAPACITOR Output capacitance is required to minimize the voltage overshoot, the voltage undershoot, and the ripple voltage present on the output. Capacitors with low equivalent series resistance (ESR) values produce the lowest output ripple. Furthermore, use capacitors such as X5R and X7R dielectric capacitors. Do not use Y5V and Z5U capacitors, because they are unsuitable choices due to their large capacitance variation over temperature and their dc bias voltage changes. Because ESR is important, select the capacitor using the following equation: ESR COUT V RIPPLE I L where: ESRCOUT is the ESR of the chosen capacitor. VRIPPLE is the peak-to-peak output voltage ripple. Increasing the output capacitor value has no effect on stability and may reduce output ripple and enhance load transient response. When choosing the output capacitor value, it is important to account for the loss of capacitance due to output voltage dc bias. Use the capacitor series from the different vendors shown in Table 7. Table 6. Recommended Inductors Vendor TDK Wurth Coilcraft 1 Model MLP2016V2R2MT0S1 74479889222 LPS3314-222MR Inductance (H) 2.2 2.2 2.2 Dimensions (mm) 2.0 x 1.6 x 0.85 2.5 x 2.0 x 1.2 3.3 x 3.3 x 1.3 DCR (m) 280 250 100 ISAT1 (A) 1.0 1.7 1.5 ISAT is the dc current at which the inductance drops 30% (typical) from its value without current. Table 7. Input and Output Capacitors Vendor Murata Murata Murata Model GRM188D71A106MA73 GRM21BR71A106KE51 GRM31CR71A106KA01 Capacitance (F) 10 10 10 Rev. B | Page 17 of 21 Size 0603 0805 1206 ADP5300 Data Sheet INPUT CAPACITOR Driver Losses An input capacitor is required to reduce the input voltage ripple, input ripple current, and source impedance. Place the input capacitor as close as possible to the PVIN pin. A low ESR X7R or X5R capacitor is highly recommended to minimize the input voltage ripple. Use the following equation to determine the rms input current: Driver losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. Each time a power device gate is turned on and turned off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground. I RMS I LOAD( MAX ) VOUT (VIN - VOUT ) VIN PDRIVER = (CGATE_H + CGATE_L) x VIN2 x fSW For most applications, a 10 F capacitor is sufficient. The input capacitor can be increased without any limit for improved input voltage filtering. EFFICIENCY Efficiency is the ratio of output power to input power. The high efficiency of the ADP5300 has two distinct advantages. First, only a small amount of power is lost in the dc-to-dc converter package, which in turn reduces thermal constraints. Second, the high efficiency delivers the maximum output power for the given input power, thereby extending battery life in portable applications. Power Switch Conduction Losses Power switch dc conduction losses are caused by the flow of output current through the high-side, P-channel power switch and the low-side, N-channel synchronous rectifier, which have internal resistances (RDS (ON)) associated with them. The amount of power loss is approximated by PSW_COND = (RDS (ON) H x D + RDS (ON) L x (1 - D)) x IOUT2 where: CGATE_H is the gate capacitance of the internal high-side switch. CGATE_L is the gate capacitance of the internal low-side switch. fSW is the switching frequency in PWM mode. The typical values for the gate capacitances are 69 pF for CGATE_H and 31 pF for CGATE_L. Transition Losses Transition losses occur because the P-channel switch cannot turn on or turn off instantaneously. In the middle of a switch node transition, the power switch provides all of the inductor current. The source to drain voltage of the power switch is half of the input voltage, resulting in power loss. Transition losses increase with both load current and input voltage and occur twice for each switching cycle. Use the following equation to estimate transition losses: PTRAN = VIN/2 x IOUT x (tR + tF) x fSW where: tR is the rise time of the SW node. tF is the fall time of the SW node. The typical value for the rise and fall times, tR and tF, is 2 ns. where: D= Estimate driver losses using the following equation: CIRCUIT BOARD LAYOUT RECOMMENDATIONS VOUT VIN 10F 10V/XR5 0603 The internal resistance of the power switches increases with temperature and with the input voltage decrease. To estimate the total amount of power lost in the inductor, use the following equation: PL = DCR x IOUT2 + Core Losses ADP5300 TOP VIEW 10F 6.3V/XR5 0603 4.6 Figure 42. Typical PCB Layout Rev. B | Page 18 of 21 5.7 13366-042 Inductor conduction losses are caused by the flow of current through the inductor, which has an internal DCR associated with it. Larger size inductors have smaller DCR, which can decrease inductor conduction losses. Inductor core losses relate to the magnetic permeability of the core material. Because the ADP5300 is a high switching frequency dc-to-dc regulator, shielded ferrite core material is recommended because of its low core losses and low electromagnetic interference (EMI). L1-2.2H 0603 Inductor Losses Data Sheet ADP5300 TYPICAL APPLICATION CIRCUITS controlled by a microcontroller or a processor (see Figure 44). The STOP switching function can achieve a quiet system environment for a noise sensitive application. The ADP5300 can be used as a keep-alive, ultralow power stepdown regulator to extend the battery life (see Figure 43), and as a battery-powered equipment or wireless sensor network VIN = 3.0V TO 4.2V Li-Ion BATTERY 2.2H 10F VOUT = 3.0V SW PVIN ADP5300 ADC/RF/AFE 10F EN PGND VID FB R1 1M MCU (ALWAYS ON) VOUTOK STOP SYNC/MODE 13366-043 AGND Figure 43. Typical ADP5300 Application with Li-Ion Battery and STOP Switching Functionality VIN = 2.0V TO 3.0V 2.2H 10F R1 19.6k 1% VOUT = 1.8V SW PVIN ADP5300 ADC/RF/AFE 10F EN PGND VID FB R1 1M VOUTOK MCU (ALWAYS ON) STOP SYNC/MODE AGND 13366-044 TWO ALKALINE OR NiMH BATTERIES Figure 44. Typical ADP5300 Application with Two Alkaline/NiMH Batteries Rev. B | Page 19 of 21 ADP5300 Data Sheet FACTORY PROGRAMMABLE OPTIONS To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative. Table 8. Output Voltage VID Setting Options Option Option 0 Option 1 Description VID resistor to set the output voltage as: 1.2 V, 1.5 V, 1.8 V, 2.0 V, 2.1 V, 2.2 V, 2.3 V, 2.4 V, 2.5 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.3 V, 3.6 V, or 3.3 V. VID resistor to set the output voltage as: 0.8 V, 0.9 V, 1.0 V, 1.1 V, 1.3 V, 1.4 V, 1.6 V, 1.7 V, 1.9 V, 3.1 V, 3.2 V, 3.4 V, 3.9 V, 4.2 V, 4.5 V, or 5.0 V. Table 9. Output Discharge Functionality Options Option Option 0 Option 1 Description Output discharge function disabled for buck regulator (default) Output discharge function enabled form buck regulator Table 10. Soft-Start Timer Options Option Option 0 Option 1 Description 350 s (default) 2800 s Rev. B | Page 20 of 21 Data Sheet ADP5300 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 1 5 BOTTOM VIE W TOP VIEW PKG-004362 0.80 0.75 0.70 SEATING PLANE SIDE VIEW 0.30 0.25 0.20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 MIN PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF 02-07-2017-C PIN 1 INDEX AREA Figure 45. 10-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP5300ACPZ-1-R7 ADP5300ACPZ-2-R7 ADP5300ACPZ-3-R7 ADP5300ACPZ-4-R7 ADP5300-EVALZ 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 10-Lead LFCSP, Output Voltage Option 0 with Output Discharge 10-Lead LFCSP, Output Voltage Option 0 without Output Discharge 10-Lead LFCSP, Output Voltage Option 1 without Output Discharge 10-Lead LFCSP, 3.6 V Fixed Output without Output Discharge, 2800 s Soft Start Time Evaluation Board Z = RoHS Compliant Part. (c)2015-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13366-0-11/17(B) Rev. B | Page 21 of 21 Package Option CP-10-9 CP-10-9 CP-10-9 CP-10-9