MC68HC05B6FNR2 - Freescale Semiconductor, Inc.

HC05

MC68HC05B6/D

Rev. 4

MC68HC05B4

MC68HC705B5

MC68HC05B6

MC68HC05B8

MC68HC05B16

MC68HC705B16

MC68HC705B16N

MC68HC05B32

MC68HC705B32

TECHNICAL

DATA

MC68HC05B6 TECHNICAL DATA

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

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INTRODUCTION
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
INPUT/OUTPUT PORTS
PROGRAMMABLE TIMER
SERIAL COMMUNICATIONS INTERFACE
PULSE LENGTH D/A CONVERTERS
ANALOG TO DIGITAL CONVERTER
RESETS AND INTERRUPTS
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
ORDERING INFORMATION
APPENDICES
HIGH SPEED OPERATION
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15
 
INTRODUCTION
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
INPUT/OUTPUT PORTS
PROGRAMMABLE TIMER
SERIAL COMMUNICATIONS INTERFACE
PULSE LENGTH D/A CONVERTERS
ANALOG TO DIGITAL CONVERTER
RESETS AND INTERRUPTS
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
ORDERING INFORMATION
APPENDICES
HIGH SPEED OPERATION
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05B6Book  Page 4  Tuesday, April 6, 1999  8:24 am

CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05B6/D rev. 4)

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SECTION 1 INTRODUCTION

SECTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS

SECTION 3 MEMORY AND REGISTERS

SECTION 4 INPUT/OUTPUT PORTS

SECTION 5 PROGRAMMABLE TIMER

SECTION 6 SERIAL COMMUNICATIONS INTERFACE

SECTION 7 PULSE LENGTH D/A CONVERTERS

SECTION 8 ANALOG TO DIGITAL CONVERTER

SECTION 9 RESETS AND INTERRUPTS

SECTION 10 CPU CORE AND INSTRUCTION SET

SECTION 11 ELECTRICAL SPECIFICATIONS

SECTION 12 MECHANICAL DATA

SECTION 13 ORDERING INFORMATION

SECTION 14 APPENDICES

SECTION 15 HIGH SPEED OPERATION

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05B6Book Page v Tuesday, April 6, 1999 8:24 am

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05B6Book Page vi Tuesday, April 6, 1999 8:24 am

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,

representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including

without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets

and/or specifications can and do vary in different applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Motorola

does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or

authorized for use as components in systems intended for surgical implant into the body, or other applications intended to

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harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of

Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

All products are sold on Motorola’s Terms & Conditions of Supply. In ordering a product covered by this document the

Customer agrees to be bound by those Terms & Conditions and nothing contained in this document constitutes or forms part

of a contract (with the exception of the contents of this Notice). A copy of Motorola’s Terms & Conditions of Supply is available

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This document supersedes any earlier documentation relating to the products referred to herein. The information contained

in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn.



MOTOROLA LTD., 1999

All Trade Marks recognized. This document contains information on new products. Speciﬁcations and information herein are

subject to change without notice.

MC68HC05B6

High-density Complementary

Metal Oxide Semiconductor

(HCMOS) Microcomputer Unit

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05B6Book Page 7 Tuesday, April 6, 1999 8:24 am

Conventions

Where abbreviations are used in the text, an explanation can be found in the

glossary, at the back of this manual. Register and bit mnemonics are deﬁned in the

paragraphs describing them.

An overbar is used to designate an active-low signal, eg: RESET.

Unless otherwise stated, shaded cells in a register diagram indicate that the bit is

either unused or reserved; ‘u’ is used to indicate an undeﬁned state (on reset).

Unless otherwise stated, pins labelled “NU” should be tied to VSS in an electrically

noisy environment. Pins labelled “NC” can be left ﬂoating, since the y are not bonded

to any part of the device.

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05B6Book Page 8 Tuesday, April 6, 1999 8:24 am

MC68HC05B6
Rev. 4 MOTOROLA
i
TABLE OF CONTENTS
Paragraph
Number Page
NumberTITLE
 TABLE OF CONTENTS
1 
INTRODUCTION
1.1 Features.............................................................................................................1–2
1.2 Mask options for the MC68HC05B6..................................................................1–3
2 
MODES OF OPERATION AND PIN DESCRIPTIONS
2.1 Modes of operation............................................................................................2–1
2.1.1 Single chip mode .........................................................................................2–1
2.2 Serial RAM loader .............................................................................................2–2
2.3 ‘Jump to any address’........................................................................................2–4
2.4 Low power modes..............................................................................................2–6
2.4.1 STOP ...........................................................................................................2–6
2.4.2 WAIT............................................................................................................2–8
2.4.2.1 Power consumption during WAIT mode .................................................2–8
2.4.3 SLOW mode.................................................................................................2–9
2.4.3.1  Miscellaneous register...........................................................................2–9
2.5  Pin descriptions ..............................................................................................2–10
2.5.1 VDD and VSS ............................................................................................2–10
2.5.2 IRQ ............................................................................................................2–10
2.5.3 RESET.......................................................................................................2–10
2.5.4 TCAP1 .......................................................................................................2–10
2.5.5 TCAP2 .......................................................................................................2–11
2.5.6 TCMP1.......................................................................................................2–11
2.5.7 TCMP2.......................................................................................................2–11
2.5.8 OSC1, OSC2 .............................................................................................2–11
2.5.8.1 Crystal..................................................................................................2–11
2.5.8.2 Ceramic resonator................................................................................2–11
2.5.8.3 External clock.......................................................................................2–12
2.5.9 RDI (Receive data in).................................................................................2–13
2.5.10 TDO (Transmit data out) ............................................................................2–13
2.5.11 SCLK..........................................................................................................2–13
2.5.12 PLMA.........................................................................................................2–13
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05B6Book  Page i  Tuesday, April 6, 1999  8:24 am

MOTOROLA
ii MC68HC05B6
Rev. 4
TABLE OF CONTENTS
Paragraph
Number Page
NumberTABLE OF CONTENTS
5.13 PLMB.........................................................................................................2–13
5.14 VPP1..........................................................................................................2–13
5.15 VRH...........................................................................................................2–13
5.16 VRL............................................................................................................2–13
5.17 PA0 – PA7/PB0 – PB7/PC0 – PC7 ............................................................2–13
5.18 PD0/AN0–PD7/AN7...................................................................................2–13

MEMORY AND REGISTERS
1 Registers ...........................................................................................................3–1
2 RAM ..................................................................................................................3–1
3 ROM..................................................................................................................3–1
4 Self-check ROM ................................................................................................3–2
5 EEPROM...........................................................................................................3–3
5.1 EEPROM control register.............................................................................3–3
5.2 EEPROM read operation.............................................................................3–5
5.3 EEPROM erase operation ...........................................................................3–5
5.4 EEPROM programming operation...............................................................3–6
5.5 Options register (OPTR)..............................................................................3–6
6 EEPROM during STOP mode...........................................................................3–7
7 EEPROM during WAIT mode............................................................................3–7
8  Miscellaneous register......................................................................................3–9

INPUT/OUTPUT PORTS
1 Input/output programming .................................................................................4–1
2 Ports A and B ....................................................................................................4–2
3 Port C ................................................................................................................4–3
4 Port D ................................................................................................................4–3
5 Port registers.....................................................................................................4–4
5.1 Port data registers A and B (PORTA and PORTB)......................................4–4
5.2 Port data register C (PORTC)......................................................................4–4
5.3 Port data register D (PORTD)......................................................................4–5
5.3.1 A/D status/control register......................................................................4–5
5.4 Data direction registers (DDRA, DDRB and DDRC)....................................4–5
6 Other port considerations..................................................................................4–6
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MC68HC05B6
Rev. 4 MOTOROLA
iii
TABLE OF CONTENTS
Paragraph
Number Page
NumberTABLE OF CONTENTS

PROGRAMMABLE TIMER
1 Counter..............................................................................................................5–1
1.1 Counter register and alternate counter register...........................................5–3
2 Timer control and status....................................................................................5–4
2.1 Timer control register (TCR)........................................................................5–4
2.2 Timer status register (TSR)..........................................................................5–6
3 Input capture......................................................................................................5–7
3.1 Input capture register 1 (ICR1) ....................................................................5–7
3.2 Input capture register 2 (ICR2) ....................................................................5–8
4 Output compare.................................................................................................5–9
4.1 Output compare register 1 (OCR1)..............................................................5–9
4.2 Output compare register 2 (OCR2)............................................................5–10
4.3 Software force compare.............................................................................5–11
5 Pulse Length Modulation (PLM) ......................................................................5–11
5.1 Pulse length modulation registers A and B (PLMA/PLMB)........................5–11
6 Timer during STOP mode................................................................................5–12
7 Timer during WAIT mode.................................................................................5–12
8 Timer state diagrams.......................................................................................5–12

SERIAL COMMUNICATIONS INTERFACE
1 SCI two-wire system features............................................................................6–1
2 SCI receiver features.........................................................................................6–3
3 SCI transmitter features.....................................................................................6–3
4 Functional description........................................................................................6–3
5 Data format........................................................................................................6–5
6 Receiver wake-up operation..............................................................................6–5
6.1 Idle line wake-up..........................................................................................6–6
6.2 Address mark wake-up................................................................................6–6
7 Receive data in (RDI) ........................................................................................6–6
8 Start bit detection...............................................................................................6–6
9 Transmit data out (TDO)....................................................................................6–8
10 SCI synchronous transmission..........................................................................6–9
11 SCI registers....................................................................................................6–10
11.1 Serial communications data register (SCDR)............................................6–10
11.2 Serial communications control register 1 (SCCR1) ...................................6–10
11.3 Serial communications control register 2 (SCCR2) ...................................6–14
11.4 Serial communications status register (SCSR)..........................................6–16
11.5 Baud rate register (BAUD).........................................................................6–18
12 Baud rate selection..........................................................................................6–19
13 SCI during STOP mode...................................................................................6–21
14 SCI during WAIT mode....................................................................................6–21
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MOTOROLA
iv MC68HC05B6
Rev. 4
TABLE OF CONTENTS
Paragraph
Number Page
NumberTABLE OF CONTENTS

PULSE LENGTH D/A CONVERTERS
1 Miscellaneous register.......................................................................................7–3
2 PLM clock selection...........................................................................................7–4
3 PLM during STOP mode ...................................................................................7–4
4 PLM during WAIT mode ....................................................................................7–4

ANALOG TO DIGITAL CONVERTER
1 A/D converter operation.....................................................................................8–1
2 A/D registers......................................................................................................8–3
2.1 Port D data register (PORTD)......................................................................8–3
2.2 A/D result data register (ADDATA)...............................................................8–3
2.3 A/D status/control register (ADSTAT)...........................................................8–4
3 A/D converter during STOP mode.....................................................................8–6
4 A/D converter during WAIT mode......................................................................8–6
5 Port D analog input............................................................................................8–6

RESETS AND INTERRUPTS
1 Resets ...............................................................................................................9–1
1.1 Power-on reset.............................................................................................9–2
1.2  Miscellaneous register................................................................................9–2
1.3 RESET pin...................................................................................................9–3
1.4 Computer operating properly (COP) watchdog reset ..................................9–3
1.4.1 COP watchdog during STOP mode .......................................................9–4
1.4.2 COP watchdog during WAIT mode........................................................9–4
1.5 Functions affected by reset..........................................................................9–5
2 Interrupts ...........................................................................................................9–6
2.1 Interrupt priorities.........................................................................................9–6
2.2 Nonmaskable software interrupt (SWI)........................................................9–6
2.3 Maskable hardware interrupts......................................................................9–7
2.3.1 External interrupt (IRQ)..........................................................................9–7
2.3.2  Miscellaneous register ..........................................................................9–9
2.3.3 Timer interrupts....................................................................................9–10
2.3.4 Serial communications interface (SCI) interrupts.................................9–10
2.4 Hardware controlled interrupt sequence....................................................9–11
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MC68HC05B6
Rev. 4 MOTOROLA
v
TABLE OF CONTENTS
Paragraph
Number Page
NumberTABLE OF CONTENTS

CPU CORE AND INSTRUCTION SET
1 Registers .........................................................................................................10–1
1.1 Accumulator (A).........................................................................................10–2
1.2 Index register (X)........................................................................................10–2
1.3 Program counter (PC)................................................................................10–2
1.4 Stack pointer (SP)......................................................................................10–2
1.5 Condition code register (CCR)...................................................................10–2
2 Instruction set ..................................................................................................10–3
2.1 Register/memory Instructions....................................................................10–4
2.2 Branch instructions ....................................................................................10–4
2.3 Bit manipulation instructions......................................................................10–4
2.4 Read/modify/write instructions...................................................................10–4
2.5 Control instructions....................................................................................10–4
2.6 Tables.........................................................................................................10–4
3 Addressing modes.........................................................................................10–11
3.1 Inherent....................................................................................................10–11
3.2 Immediate................................................................................................10–11
3.3 Direct........................................................................................................10–11
3.4 Extended..................................................................................................10–12
3.5 Indexed, no offset.....................................................................................10–12
3.6 Indexed, 8-bit offset..................................................................................10–12
3.7 Indexed, 16-bit offset................................................................................10–12
3.8 Relative....................................................................................................10–13
3.9 Bit set/clear..............................................................................................10–13
3.10 Bit test and branch...................................................................................10–13

ELECTRICAL SPECIFICATIONS
1 Absolute maximum ratings ..............................................................................11–1
2 DC electrical characteristics ............................................................................11–2
2.1 IDD trends for 5V operation ........................................................................11–3
2.2 IDD trends for 3.3V operation .....................................................................11–6
3 A/D converter characteristics...........................................................................11–8
4 Control timing ................................................................................................11–10

MECHANICAL DATA
1 MC68HC05B family pin conﬁgurations............................................................12–1
1.1 52-pin plastic leaded chip carrier (PLCC)..................................................12–1
1.2 64-pin quad ﬂat pack (QFP).......................................................................12–2
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MOTOROLA
vi MC68HC05B6
Rev. 4
TABLE OF CONTENTS
Paragraph
Number Page
NumberTABLE OF CONTENTS
12.1.3 56-pin shrink dual in line package (SDIP)..................................................12–3
12.2 MC68HC05B6 mechanical dimensions...........................................................12–4
12.2.1 52-pin plastic leaded chip carrier (PLCC)..................................................12–4
12.2.2 64-pin quad ﬂat pack (QFP).......................................................................12–5
12.2.3 56-pin shrink dual in line package (SDIP)..................................................12–6
13 
ORDERING INFORMATION
13.1 EPROMS.........................................................................................................13–2
13.2 Veriﬁcation media............................................................................................13–2
13.3 ROM veriﬁcation units (RVU)...........................................................................13–2
A 
MC68HC05B4
A.1 Features ........................................................................................................... A–1
A.2 Self-check mode............................................................................................... A–5
B 
MC68HC05B8
B.1 Features ........................................................................................................... B–1
C 
MC68HC705B5
C.1 Features ...........................................................................................................C–1
C.2 EPROM ............................................................................................................C–5
C.2.1 EPROM programming operation.................................................................C–5
C.3 EPROM registers..............................................................................................C–6
C.3.1 EPROM control register..............................................................................C–6
C.4 Options register (OPTR)...................................................................................C–7
C.5 Bootstrap mode................................................................................................C–8
C.5.1 Erased EPROM veriﬁcation......................................................................C–11
C.5.2 EPROM parallel bootstrap load ................................................................C–11
C.5.3 EPROM (RAM) serial bootstrap load and execute ...................................C–13
C.5.4 RAM parallel bootstrap load and execute.................................................C–14
C.5.5 Bootstrap loader timing diagrams.............................................................C–17
C.6 DC electrical characteristics...........................................................................C–19
C.7 Control timing.................................................................................................C–19
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MC68HC05B6
Rev. 4 MOTOROLA
vii
TABLE OF CONTENTS
Paragraph
Number Page
NumberTABLE OF CONTENTS
D 
MC68HC05B16
D.1 Features............................................................................................................D–1
D.2 Self-check routines...........................................................................................D–2
D.3 External clock ...................................................................................................D–4
E 
MC68HC705B16
E.1 Features............................................................................................................E–2
E.2 External clock ...................................................................................................E–5
E.3 EPROM.............................................................................................................E–5
E.3.1 EPROM read operation...............................................................................E–5
E.3.2 EPROM program operation.........................................................................E–5
E.3.3 EPROM/EEPROM/ECLK control register...................................................E–6
E.3.4 Mask option register....................................................................................E–8
E.3.5 EEPROM options register (OPTR)..............................................................E–9
E.4 Bootstrap mode ..............................................................................................E–10
E.4.1 Erased EPROM veriﬁcation ......................................................................E–13
E.4.2 EPROM/EEPROM parallel bootstrap........................................................E–13
E.4.3 EEPROM/EPROM/RAM serial bootstrap..................................................E–16
E.4.4 RAM parallel bootstrap .............................................................................E–19
E.4.4.1 Jump to start of RAM ($0050).............................................................E–20
E.5 Absolute maximum ratings .............................................................................E–21
E.6 DC electrical characteristics ...........................................................................E–22
E.7 A/D converter characteristics..........................................................................E–24
E.8 Control timing .................................................................................................E–26
E.9 EPROM electrical characteristics ...................................................................E–28
F 
MC68HC705B16N
F.1 Features............................................................................................................ F–2
F.2 External clock ................................................................................................... F–5
F.3 RESET pin........................................................................................................ F–5
F.4 EPROM............................................................................................................. F–5
F.4.1 EPROM read operation............................................................................... F–5
F.4.2 EPROM program operation......................................................................... F–6
F.4.3 EPROM/EEPROM/ECLK control register................................................... F–6
F.4.4 Mask option register.................................................................................... F–8
F.4.5 EEPROM options register (OPTR).............................................................. F–9
F.5 Bootstrap mode .............................................................................................. F–10
F.5.1 Erased EPROM veriﬁcation ...................................................................... F–13
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MOTOROLA
viii MC68HC05B6
Rev. 4
TABLE OF CONTENTS
Paragraph
Number Page
NumberTABLE OF CONTENTS
F.5.2 EPROM/EEPROM parallel bootstrap.........................................................F–13
F.5.3 Serial RAM loader......................................................................................F–16
F.5.3.1 Jump to start of RAM ($0051)..............................................................F–16
F.6 Absolute maximum ratings..............................................................................F–19
F.7 DC electrical characteristics............................................................................F–20
F.8 A/D converter characteristics...........................................................................F–22
F.9 Control timing ..................................................................................................F–24
F.10 EPROM electrical characteristics....................................................................F–26
G 
MC68HC05B32
G.1 Features ...........................................................................................................G–1
G.2 External clock...................................................................................................G–2
H 
MC68HC705B32
H.1 Features ...........................................................................................................H–3
H.2 External clock...................................................................................................H–7
H.3 RESET pin........................................................................................................H–7
H.4 EPROM ............................................................................................................H–7
H.4.1 EPROM read operation...............................................................................H–8
H.4.2 EPROM program operation ........................................................................H–8
H.4.3 EPROM/EEPROM control register .............................................................H–8
H.4.4 Mask option register .................................................................................H–11
H.4.5 Options register (OPTR)...........................................................................H–12
H.5 Bootstrap mode..............................................................................................H–13
H.5.1 Erased EPROM veriﬁcation......................................................................H–16
H.5.2 EPROM/EEPROM parallel bootstrap........................................................H–16
H.5.3 Serial RAM loader.....................................................................................H–19
H.5.3.1 Jump to start of RAM ($0051).............................................................H–19
H.6 Absolute maximum ratings.............................................................................H–22
H.7 DC electrical characteristics...........................................................................H–23
H.8 A/D converter characteristics..........................................................................H–25
H.9 Control timing .................................................................................................H–27
H.10 EPROM electrical characteristics...................................................................H–29
I 
HIGH SPEED OPERATION
I.1 DC electrical characteristics...............................................................................I–2
I.2 A/D converter characteristics..............................................................................I–3
I.3 Control timing for 5V operation...........................................................................I–4
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MC68HC05B6
Rev. 4 MOTOROLA
ix
LIST OF FIGURES
Figure
Number Page
NumberTITLE
LIST OF FIGURES
1-1 MC68HC05B6 block diagram.............................................................................1–3
2-1 MC68HC05B6 ‘load program in RAM and execute’ schematic diagram.............2–3
2-2 MC68HC05B6 ‘jump to any address’ schematic diagram...................................2–5
2-3 STOP and WAIT ﬂowcharts................................................................................2–7
2-4 Slow mode divider block diagram.......................................................................2–9
2-5 Oscillator connections ......................................................................................2–12
3-1 Memory map of the MC68HC05B6 ....................................................................3–2
4-1 Standard I/O port structure.................................................................................4–2
4-2 ECLK timing diagram..........................................................................................4–3
4-3 Port logic levels...................................................................................................4–6
5-1 16-bit programmable timer block diagram ..........................................................5–2
5-2 Timer state timing diagram for reset.................................................................5–13
5-3 Timer state timing diagram for input capture....................................................5–13
5-4 Timer state timing diagram for output compare................................................5–14
5-5 Timer state timing diagram for timer overﬂow...................................................5–14
6-1 Serial communications interface block diagram .................................................6–2
6-2 SCI rate generator division.................................................................................6–4
6-3 Data format.........................................................................................................6–5
6-4 SCI examples of start bit sampling technique ....................................................6–7
6-5 SCI sampling technique used on all bits.............................................................6–7
6-6 Artiﬁcial start following a framing error ...............................................................6–8
6-7 SCI start bit following a break.............................................................................6–8
6-8 SCI example of synchronous and asynchronous transmission..........................6–9
6-9 SCI data clock timing diagram (M=0) ...............................................................6–12
6-10 SCI data clock timing diagram (M=1) ...............................................................6–13
7-1 PLM system block diagram.................................................................................7–1
7-2 PLM output waveform examples.........................................................................7–2
7-3 PLM clock selection............................................................................................7–4
8-1 A/D converter block diagram ..............................................................................8–2
8-2 Electrical model of an A/D input pin....................................................................8–6
9-1 Reset timing diagram..........................................................................................9–1
9-2 Watchdog system block diagram........................................................................9–3
9-3 Interrupt ﬂow chart..............................................................................................9–8
TPG
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MOTOROLA
xMC68HC05B6
Rev. 4
LIST OF FIGURES
Figure
Number Page
NumberTITLE
10-1 Programming model.........................................................................................10–1
10-2 Stacking order ..................................................................................................10–1
11-1 Run IDD vs internal operating frequency (4.5V, 5.5V)......................................11–3
11-2 Run IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V).......................11–3
11-3 Wait IDD vs internal operating frequency (4.5V, 5.5V)......................................11–3
11-4 Wait IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V).......................11–4
11-5 Increase in IDD vs frequency for A/D, SCI systems active, VDD = 5.5V...........11–4
11-6 IDD vs mode vs internal operating frequency, VDD = 5.5V................................11–4
11-7 Run IDD vs internal operating frequency (3V, 3.6V).........................................11–6
11-8 Run IDD (SM = 1) vs internal operating frequency (3V,3.6V)...........................11–6
11-9 Wait IDD vs internal operating frequency (3V, 3.6V).........................................11–6
11-10 Wait IDD (SM = 1) vs internal operating frequency (3V, 3.6V)..........................11–7
11-11 Increase in IDD vs frequency for A/D, SCI systems active, VDD = 3.6V............11–7
11-12 IDD vs mode vs internal operating frequency, VDD = 3.6V................................11–7
11-13 Timer relationship...........................................................................................11–12
12-1 52-pin PLCC pinout for the MC68HC05B6.......................................................12–1
12-2 64-pin QFP pinout for the MC68HC05B6.........................................................12–2
12-3 56-pin SDIP pinout for the MC68HC05B6........................................................12–3
12-4 52-pin PLCC mechanical dimensions ..............................................................12–4
12-5 64-pin QFP mechanical dimensions.................................................................12–5
12-6 56-pin SDIP mechanical dimensions................................................................12–6
A-1 MC68HC05B4 block diagram.............................................................................A–2
A-2 Memory map of the MC68HC05B4....................................................................A–3
A-3 MC68HC05B4 self-check schematic diagram....................................................A–7
B-1 MC68HC05B8 block diagram.............................................................................B–2
B-2 Memory map of the MC68HC05B8....................................................................B–3
C-1 MC68HC705B5 block diagram.......................................................................... C–2
C-2 Memory map of the MC68HC705B5................................................................. C–3
C-3 Modes of operation ﬂow chart (1 of 2)............................................................... C–9
C-4 Modes of operation ﬂow chart (2 of 2)............................................................. C–10
C-5 Timing diagram with handshake...................................................................... C–11
C-6 EPROM(RAM) parallel bootstrap schematic diagram..................................... C–12
C-7 EPROM (RAM) serial bootstrap schematic diagram....................................... C–15
C-8 RAM parallel bootstrap schematic diagram..................................................... C–16
C-9 EPROM parallel bootstrap loader timing diagram........................................... C–17
C-10  RAM parallel loader timing diagram............................................................... C–18
D-1 MC68HC05B16 block diagram.......................................................................... D–3
D-2 Oscillator connections....................................................................................... D–4
D-3 Memory map of the MC68HC05B16................................................................. D–5
E-1 MC68HC705B16 block diagram.........................................................................E–2
E-2 Memory map of the MC68HC705B16................................................................E–3
E-3 Modes of operation ﬂow chart (1 of 2)..............................................................E–11
TPG
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MC68HC05B6
Rev. 4 MOTOROLA
xi
LIST OF FIGURES
Figure
Number Page
NumberTITLE
E-4 Modes of operation ﬂow chart (2 of 2)............................................................. E–12
E-5 Timing diagram with handshake...................................................................... E–14
E-6 Parallel EPROM loader timing diagram........................................................... E–14
E-7 EPROM Parallel bootstrap schematic diagram................................................ E–15
E-8 RAM/EPROM/EEPROM serial bootstrap schematic diagram......................... E–17
E-9 Parallel RAM loader timing diagram................................................................ E–19
E-10 RAM parallel bootstrap schematic diagram..................................................... E–20
E-11 Timer relationship............................................................................................ E–28
F-1 MC68HC705B16N block diagram.......................................................................F–2
F-2 Memory map of the MC68HC705B16N..............................................................F–3
F-3 Modes of operation ﬂow chart (1 of 2)..............................................................F–11
F-4 Modes of operation ﬂow chart (2 of 2)..............................................................F–12
F-5 Timing diagram with handshake.......................................................................F–14
F-6 Parallel EPROM loader timing diagram............................................................F–14
F-7 EPROM parallel bootstrap schematic diagram.................................................F–15
F-8 RAM load and execute schematic diagram......................................................F–17
F-9 Parallel RAM loader timing diagram.................................................................F–18
F-10 Timer relationship.............................................................................................F–26
G-1 MC68HC05B32 block diagram..........................................................................G–2
G-2 Memory map of the MC68HC05B32.................................................................G–3
H-1 MC68HC705B32 block diagram........................................................................ H–4
H-2 Memory map of the MC68HC705B32 ............................................................... H–5
H-3 Modes of operation ﬂow chart (1 of 2)............................................................. H–14
H-4 Modes of operation ﬂow chart (2 of 2)............................................................. H–15
H-5 Timing diagram with handshake......................................................................H–17
H-6 Parallel EPROM loader timing diagram...........................................................H–17
H-7 EPROM parallel bootstrap schematic diagram................................................ H–18
H-8 RAM load and execute schematic diagram..................................................... H–20
H-9 Parallel RAM loader timing diagram................................................................ H–21
H-10 Timer relationship............................................................................................H–29
I-1 Timer relationship................................................................................................I–5
TPG
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LIST OF FIGURES

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MC68HC05B6
Rev. 4 MOTOROLA
xiii
LIST OF TABLES
Table
Number Page
NumberTITLE
LIST OF TABLES
1-1 Data sheet appendices.......................................................................................1–1
2-1 Mode of operation selection ...............................................................................2–1
3-1 EEPROM control bits description .......................................................................3–4
3-2 Register outline...................................................................................................3–8
3-3 IRQ sensitivity.....................................................................................................3–9
4-1 I/O pin states ......................................................................................................4–2
6-1 Method of receiver wake-up .............................................................................6–11
6-2 SCI clock on SCLK pin .....................................................................................6–13
6-3 First prescaler stage.........................................................................................6–18
6-4 Second prescaler stage (transmitter) ...............................................................6–18
6-5 Second prescaler stage (receiver)....................................................................6–19
6-6 SCI baud rate selection....................................................................................6–20
8-1 A/D clock selection .............................................................................................8–4
8-2 A/D channel assignment.....................................................................................8–5
9-1 Effect of RESET, POR, STOP and WAIT............................................................9–5
9-2 Interrupt priorities ...............................................................................................9–7
9-3 IRQ sensitivity.....................................................................................................9–9
10-1 MUL instruction.................................................................................................10–5
10-2 Register/memory instructions...........................................................................10–5
10-3 Branch instructions...........................................................................................10–6
10-4 Bit manipulation instructions.............................................................................10–6
10-5 Read/modify/write instructions .........................................................................10–7
10-6 Control instructions...........................................................................................10–7
10-7 Instruction set (1 of 2).......................................................................................10–8
10-8 Instruction set (2 of 2).......................................................................................10–9
10-9 M68HC05 opcode map...................................................................................10–10
11-1 Absolute maximum ratings ...............................................................................11–1
11-2 DC electrical characteristics for 5V operation...................................................11–2
11-3 DC electrical characteristics for 3.3V operation................................................11–5
11-4 A/D characteristics for 5V operation.................................................................11–8
11-5 A/D characteristics for 3.3V operation..............................................................11–9
11-6 Control timing for 5V operation.......................................................................11–10
11-7 Control timing for 3.3V operation....................................................................11–11
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MOTOROLA
xiv MC68HC05B6
Rev. 4
LIST OF TABLES
Table
Number Page
NumberTITLE
13-1 MC order numbers ...........................................................................................13–1
13-2 EPROMs for pattern generation.......................................................................13–2
A-1 Mode of operation selection...............................................................................A–1
A-2 Register outline ..................................................................................................A–4
A-3 MC68HC05B4 self-check results .......................................................................A–6
B-1 Register outline ..................................................................................................B–4
C-1 Register outline ................................................................................................. C–4
C-2 Mode of operation selection.............................................................................. C–8
C-3 Bootstrap vector targets in RAM ..................................................................... C–14
C-4 Additional DC electrical characteristics for MC68HC705B5............................ C–19
C-5 Additional control timing for MC68HC705B5................................................... C–19
D-1 Mode of operation selection.............................................................................. D–2
D-2 Register outline ................................................................................................. D–6
E-1 Register outline ..................................................................................................E–4
E-2 EPROM control bits description .........................................................................E–6
E-3 EEPROM control bits description.......................................................................E–7
E-4 Mode of operation selection.............................................................................E–10
E-5 Bootstrap vector targets in RAM ......................................................................E–18
E-6 Absolute maximum ratings...............................................................................E–21
E-7 DC electrical characteristics for 5V operation ..................................................E–22
E-8 DC electrical characteristics for 3.3V operation ...............................................E–23
E-9 A/D characteristics for 5V operation.................................................................E–24
E-10 A/D characteristics for 3.3V operation..............................................................E–25
E-11 Control timing for 5V operation.........................................................................E–26
E-12 Control timing for 3.3V operation......................................................................E–27
E-13 DC electrical characteristics for 5V operation ..................................................E–28
E-14 Control timing for 5V operation.........................................................................E–28
E-15 Control timing for 3.3V operation......................................................................E–28
F-1 Register outline ..................................................................................................F–4
F-2 EPROM control bits description .........................................................................F–7
F-3 EEPROM control bits description.......................................................................F–8
F-4 Mode of operation selection.............................................................................F–10
F-5 Bootstrap vector targets in RAM ......................................................................F–16
F-6 Absolute maximum ratings...............................................................................F–19
F-7 DC electrical characteristics for 5V operation ..................................................F–20
F-8 DC electrical characteristics for 3.3V operation ...............................................F–21
F-9 A/D characteristics for 5V operation.................................................................F–22
F-10 A/D characteristics for 3.3V operation..............................................................F–23
F-11 Control timing for 5V operation.........................................................................F–24
F-12 Control timing for 3.3V operation......................................................................F–25
F-13 DC electrical characteristics for 5V operation ..................................................F–26
F-14 Control timing for 5V operation.........................................................................F–26
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MC68HC05B6
Rev. 4 MOTOROLA
xv
LIST OF TABLES
Table
Number Page
NumberTITLE
F-15 Control timing for 3.3V operation......................................................................F–26
G-1 Register outline..................................................................................................G–4
H-1 Register outline..................................................................................................H–6
H-2 EPROM control bits description......................................................................... H–9
H-3 EEPROM control bits description ....................................................................H–10
H-4 Mode of operation selection ............................................................................ H–13
H-5 Bootstrap vector targets in RAM...................................................................... H–19
H-6 Absolute Maximum ratings ..............................................................................H–22
H-7 DC electrical characteristics for 5V operation.................................................. H–23
H-8 DC electrical characteristics for 3.3V operation............................................... H–24
H-9 A/D characteristics for 5V operation................................................................ H–25
H-10 A/D characteristics for 3.3V operation.............................................................H–26
H-11 Control timing for 5V operation........................................................................ H–27
H-12 Control timing for operation at 3.3V................................................................. H–28
H-13 DC electrical characteristics for 5V operation..................................................H–29
H-14 Control timing for 5V operation........................................................................ H–29
H-15 Control timing for 3.3V operation..................................................................... H–29
I-1 Ordering information............................................................................................I–1
I-2 DC electrical characteristics for 5V operation......................................................I–2
I-3 A/D characteristics for 5V operation....................................................................I–3
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MC68HC05B6

Rev. 4 MOTOROLA

1-1

INTRODUCTION

The MC68HC05B6 microcomputer (MCU) is a member of Motorola’s MC68HC05 family of

low-cost single chip microcomputers. This 8-bit MCU contains an on-chip oscillator, CPU, RAM,

ROM, EEPROM, A/D converter, pulse length modulated outputs, I/O, serial communications

interface, programmable timer system and watchdog. The fully static design allows operation at

frequencies down to dc to further reduce the already low power consumption to a f ew micro-amps.

This data sheet is structured such that devices similar to the MC68HC05B6 are described in a set

of appendices (see Table 1-1).

Table 1-1 Data sheet appendices

Device Appendix Differences from MC68HC05B6

MC68HC05B4 A 4K bytes ROM; no EEPROM

MC68HC05B8 B 7.25K bytes ROM

MC68HC705B5 C 6K bytes EPROM; self-check replaced by bootstrap

ﬁrmware; no EEPROM

MC68HC05B16 D 16K bytes ROM; increased RAM and self-check ROM

MC68HC705B16 E 16K bytes EPROM; increased RAM; self-chec k replaced

by bootstrap ﬁrmware; modiﬁed power-on reset routine

MC68HC705B16N F 16K bytes EPROM; increased RAM; self-chec k replaced

by bootstrap ﬁrmware; modiﬁed power-on reset routine

MC68HC05B32 G 32K bytes ROM; no page zero ROM; increased RAM

MC68HC705B32 H 32K b ytes EPROM; no page zero ROM; increased RAM;

self-check mode replaced by bootstrap ﬁrmware

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MOTOROLA

1-2 MC68HC05B6

Rev. 4

INTRODUCTION

11.1 Features

Hardware features

• Fully static design featuring the industry standard M68HC05 family CPU core

• On chip crystal oscillator with divide by 2 or a software selectab le divide by 32 option (SLO W

mode)

• 2.1 MHz internal operating frequency at 5V; 1.0 MHz at 3V

• High speed version available

• 176 bytes of RAM

• 5936 bytes of user ROM plus 14 bytes of user vectors

• 256 bytes of byte erasable EEPROM with internal charge pump and security bit

• Write/erase protect bit for 224 of the 256 bytes EEPROM

• Self test/bootstrap mode

• Power saving STOP, WAIT and SLOW modes

• Three 8-bit parallel I/O ports and one 8-bit input-only port

• Software option available to output the internal E-clock to port pin PC2

• 16-bit timer with 2 input captures and 2 output compares

• Computer operating properly (COP) watchdog timer

• Serial communications interface system (SCI) with independent transmitter/receiver baud rate

selection; receiver wake-up function for use in multi-receiver systems

• 8 channel A/D converter

• 2 pulse length modulation systems which can be used as D/A converters

• One interrupt request input plus 4 on-board hardware interrupt sources

• Av ailab le in 52-pin plastic leaded chip carrier (PLCC), 64-pin quad ﬂat pack (QFP) and 56-pin

shrink dual in line (SDIP) packages

• Complete development system support available using the MMDS05 development station with

the M68HC05B32EM emulation module

• Extended operating temperature range of -40 to +125 °C

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MC68HC05B6

Rev. 4 MOTOROLA

1-3

INTRODUCTION

1.2 Mask options for the MC68HC05B6

The MC68HC05B6 has three mask options that are programmed during manuf acture and must be

speciﬁed on the order form.

• Power-on-reset delay (tPORL) = 16 or 4064 cycles

• Automatic watchdog enable/disable following a power-on or external reset

• Watchdog enable/disable during WAIT mode

Warning: It is recommended that an e xternal clock is alwa ys used if tPORL is set to 16 cycles. This

will prevent any problems arising with oscillator stability when the device is put into

STOP mode.

Figure 1-1 MC68HC05B6 block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

programmable

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

176 bytes

RAM

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP1

256 bytes

EEPROM

Charge pump

÷ 2 / ÷ 32

PLMA D/A

PLMB D/A

8-bit

432 bytes

User ROM

5950 bytes

self check ROM

(including 14 bytes

User vectors)

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MOTOROLA

1-4 MC68HC05B6

Rev. 4

INTRODUCTION

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2-1

MODES OF OPERATION AND PIN DESCRIPTIONS

MODES OF OPERATION AND PIN

DESCRIPTIONS

2.1 Modes of operation

The MC68HC05B6 MCU has two modes of operation, namely single chip and self check modes.

Table 2-1 shows the conditions required to enter each mode on the rising edge of RESET.

2.1.1 Single chip mode

This is the normal operating mode of the MC68HC05B6. In this mode the device functions as a

self-contained microcomputer (MCU) with all on-board peripherals, including the three 8-bit I/O

ports and the 8-bit input-only port, availab le to the user . All address and data activity occurs within

the MCU.

Table 2-1 Mode of operation selection

IRQ pin TCAP1 pin PD3 PD4 Mode

VSS to VDD VSS to VDD X X Single chip

2VDD VDD 1 0 Serial RAM loader

2VDD VDD 1 1 Jump to any address

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MOTOROLA

2-2 MC68HC05B6

Rev. 4

MODES OF OPERATION AND PIN DESCRIPTIONS

22.2 Serial RAM loader

The ‘load program in RAM and execute’ mode is entered if the following conditions are satisﬁed

when the reset pin is released to VDD. The format used is identical to the format used for the

MC68HC805C4. The SEC bit in the options register must be inactive, i.e. set to ‘1’.

– IRQ at 2xVDD

– TCAP1 at VDD

– PD3 at VDD for at least 30 machine cycles after reset

– PD4 at VSS for at least 30 machine cycles after reset

In the ‘load program in RAM and execute’ routine, user programs are loaded into MCU RAM via

the SCI port and then executed. Data is loaded sequentially, starting at RAM location $0050, until

the last byte is loaded. Program control is then transf erred to the RAM program starting at location

$0051. The ﬁrst byte loaded is the count of the total number of b ytes in the program plus the count

byte. The program star ts at the second byte in RAM. Dur ing the ﬁr mware initialization stage, the

SCI is conﬁgured f or the NRZ data format (idle line, start bit, eight data bits and stop bit). The baud

rate is 9600 with a 4 MHz crystal. A prog ram to con v ert ASCII S-records to the format required by

the RAM loader is available from Motorola.

If immediate execution is not desired after loading the RAM program, it is possible to hold off

e x ecution. This is accomplished by setting the byte count to a v alue that is greater than the o v erall

length of the loaded data. When the last byte is loaded, the ﬁrmware will halt operation e xpecting

additional data to arrive. At this point, the reset s witch is placed in the reset position which will reset

the MCU, but keep the RAM program intact. All routines can now be entered from this state,

including the one which will execute the program in RAM (see Section 2.3).

To load a program in the EEPROM, the ‘load program in RAM and execute’ function is also used.

In this instance the process involves two distinct steps. Firstly, the RAM is loaded with a program

which will control the loading of the EEPROM, and when the RAM contents are e xecuted, the MCU

is instructed to load the EEPROM.

The erased state of the EEPROM is $FF.

Figure 2-1 shows the schematic diagram of the circuit required for the serial RAM loader.

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MC68HC05B6

Rev. 4 MOTOROLA

2-3

MODES OF OPERATION AND PIN DESCRIPTIONS

Figure 2-1 MC68HC05B6 ‘load prog ram in RAM and execute’ schematic diagram

OSC1

OSC2

IRQ

TCAP2

TCMP2

TCAP1

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

VSS

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

RESET

VDD

10 kΩ

0.01 µF

10 nF 47 µF

10 MΩ

4 MHz

22 pF 22 pF

P1 GND

+5V

2xVDD

RESET 10

VRH

VRL

VPP1

PLMA

PLMB

TCMP1

RDI

TDO

RS232 level translator

suggested:

MC145406 or MAX232

9600 Bd

RS232

SCLK

10 kΩ

Connect as required

for the application

Connect as required

for the application

MC68HC05B6 (52-pin package)

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MOTOROLA

2-4 MC68HC05B6

Rev. 4

MODES OF OPERATION AND PIN DESCRIPTIONS

22.3 ‘Jump to any address’

The ‘jump to any address’ mode is entered when the reset pin is released to VDD, if the following

conditions are satisﬁed:

– IRQ at 2xVDD

– TCAP1 at VDD

– PD3 at VDD for at least 30 machine cycles after reset

– PD4 at VDD for at least 30 machine cycles after reset

This function allows execution of programs previously loaded in RAM or EEPROM using the

methods outlined in Section 2.2.

To execute the ‘jump to any address’ function, data input at port A has to be $CC and data input at

port B and por t C should represent the MSB and LSB respectively, of the address to jump to for

e xecution of the user progr am. A schematic diagram of the circuit required is shown in Figure 2-2.

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MC68HC05B6

Rev. 4 MOTOROLA

2-5

MODES OF OPERATION AND PIN DESCRIPTIONS

Figure 2-2 MC68HC05B6 ‘jump to any address’ schematic diagram

OSC1

OSC2

IRQ

TCAP2

TCMP2

TCAP1

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

VSS

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

RESET

VDD

10 kΩ

0.01 µF

10 nF 47 µF

10 MΩ

4 MHz

22 pF 22 pF

P1 GND

+5V

2xVDD

RESET 10

VRH

VRL

VPP1

PLMA

PLMB

TCMP1

RDI

TDO

SCLK

10 kΩ

52 Connect as required

for the application

8 x 10 kΩoptional (see note)

8 x 10 kΩ

MSBLSB

Select required address

Note: These eight resistors are optional; direct connection is possible if pins PA0-PA7, PB0-PB7 and PC0-PC7 are

kept in input mode during application.

MC68HC05B6 (52-pin package)

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MOTOROLA
2-6 MC68HC05B6
Rev. 4
MODES OF OPERATION AND PIN DESCRIPTIONS
22.4 Low power modes
The STOP and WAIT instructions have different effects on the programmable timer, the serial
communications interface, the watchdog system, the EEPROM and the A/D converter. These
different effects are described in the following sections.
2.4.1 STOP
The ST OP instruction places the MCU in its lowest po wer consumption mode. In STOP mode , the
internal oscillator is turned off, halting all internal processing including timer, serial
communications interface and the A/D conver ter (see ﬂowchar t in Figure 2-3). The only way for
the MCU to wak e-up from the ST OP mode is by receipt of an e xternal interrupt or by the detection
of a reset (logic low on RESET pin or a power-on reset). 
During STOP mode, the I-bit in the CCR is cleared to enable external interrupts (see
Section 10.1.5).  The SM bit is cleared to allow nominal speed operation f or the 4064 cycles count
while exiting STOP mode (see Section 2.4.3). 
All other registers and memory remain unaltered and all input/output lines remain unchanged.   This
continues until an external interr upt (IRQ) or reset is sensed, at which time the internal oscillator
is turned on. The external interrupt or reset causes the program counter to vector to the
corresponding locations ($1FFA, B and $1FFE, F respectively).
When leaving STOP mode, a tPORL internal cycles delay is provided to give the oscillator time to
stabilise bef ore releasing CPU operation.   This dela y is selectable via a mask option to be either 16
or 4064 cycles. The CPU will resume operation by servicing the interrupt that wakes it up, or by
fetching the reset vector, if reset wakes it up. 
Warning: If tPORL is selected to be 16 cycles, it is recommended that an external clock signal is
used to avoid problems with oscillator stability while the device is in STOP mode.
Note:
The stacking corresponding to an eventual interrupt to go out of STOP mode will only
be executed when going out of STOP mode.
The following list summarizes the effect of STOP mode on the individual modules of the
MC68HC05B6.
– The watchdog timer is reset; refer to Section 9.1.4.1
– The EEPROM acts as read-only memory (ROM); refer to Section 3.6
– All SCI activity stopped; refer to Section 6.13
– The timer stops counting; refer to Section 5.6
– The PLM outputs remain at current level; refer to Section 7.3
– The A/D converter is disabled; refer to Section 8.3
– The I-bit in the CCR is cleared
TPG
32
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Rev. 4 MOTOROLA

2-7

MODES OF OPERATION AND PIN DESCRIPTIONS

Figure 2-3 STOP and WAIT ﬂowcharts

Timer interrupt?

IRQ

external

interrupt?

SCI interrupt?

Stop oscillator and all

clocks.

Clear I bit.

STOP WAIT

Reset?

IRQ

external

interrupt?

Generate

watchdog reset

Reset?

Watchdog active?

(1) Fetch reset vector or

(2) Service interrupt:

a. stack

b. set I-bit

c. vector to interrupt

routine

(1) Fetch reset vector or

(2) Service interrupt:

a. stack

b. set I-bit

c. vector to interrupt

routine

Turn on oscillator.

Wait for time delay to

stabilise Restart processor clock

YES

Oscillator active. Timer, SCI,

A/D, EEPROM cloc ks activ e .

Processor clocks stopped

Clear I-bit

TPG

05B6Book Page 7 Tuesday, April 6, 1999 8:24 am

MOTOROLA

2-8 MC68HC05B6

Rev. 4

MODES OF OPERATION AND PIN DESCRIPTIONS

22.4.2 WAIT

The WAIT instruction places the MCU in a low power consumption mode, but WAIT mode

consumes more power than STOP mode. All CPU action is suspended and the watchdog is

disabled, b ut the timer, A/D and SCI systems remain active and operate as normal (see ﬂowchart

in Figure 2-3). All other memory and registers remain unaltered and all parallel input/output lines

remain unchanged. The programming or erase mechanism of the EEPROM is also unaff ected, as

well as the charge pump high voltage generator.

During WAIT mode the I-bit in the CCR is cleared to enable all interrupts. The INTE bit in the

miscellaneous register (Section 2.5) is not affected b y WAIT mode. When an y interrupt or reset is

sensed, the program counter vectors to the locations containing the start address of the interrupt

or reset service routine.

Any IRQ, timer (overﬂow, input capture or output compare) or SCI interrupt (in addition to a logic

low on the RESET pin) causes the processor to exit WAIT mode.

If a non-reset e xit from WAIT mode is performed (i.e. timer o v erﬂo w interrupt e xit), the state of the

remaining systems will be unchanged.

If a reset exit from WAIT mode is performed the entire system reverts to the disabled reset state.

Note:

The stacking corresponding to an eventual interrupt to leave WAIT mode will only be

executed when leaving WAIT mode.

The following list summarizes the effect of WAIT mode on the modules of the MC68HC05B6.

– The watchdog timer functions according to the mask option selected; refer

to Section 9.1.4.2

– The EEPROM is not affected; refer to Section 3.7

– The SCI is not affected; refer to Section 6.14

– The timer is not affected; refer to Section 5.7

– The PLM is not affected; refer to Section 7.4

– The A/D converter is not affected; refer to Section 8.4

– The I-bit in the CCR is cleared

2.4.2.1 Power consumption during WAIT mode

Power consumption during WAIT mode depends on how many systems are active. The power

consumption will be highest when all the systems (A/D, timer, EEPROM and SCI) are activ e, and

lowest when the EEPROM erase and programming mechanism, SCI and A/D are disabled. The

timer cannot be disabled in WAIT mode. It is important that before entering WAIT mode, the

programmer sets the relevant control bits for the individual modules to reﬂect the desired

functionality during WAIT mode.

Power consumption may be further reduced by the use of SLOW mode.

TPG

05B6Book Page 8 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

2-9

MODES OF OPERATION AND PIN DESCRIPTIONS

2.4.3 SLOW mode

The SLOW mode function is controlled by the SM bit in the miscellaneous register at location

$000C. It allows the user to insert, under software control, an extra divide-by-16 between the

oscillator and the internal clock driver (see Figure 2-4). This feature permits a slow down of all the

internal operations and thus reduces power consumption. The SLOW mode function should not be

enabled while using the A/D converter or while erasing/programming the EEPROM unless the

internal A/D RC oscillator is turned on.

2.4.3.1 Miscellaneous register

SM — Slow mode

1 (set) – The system runs at a bus speed 16 times lower than normal

(fOSC/32). SLOW mode affects all sections of the device, including

SCI, A/D and timer.

0 (clear) – The system runs at normal bus speed (fOSC/2).

The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when

entering STOP mode.

Note:

The bits shown shaded in the above representation are explained individually in the

relevant sections of this manual. The complete register plus an explanation of each bit

can be found in Section 3.8.

Figure 2-4 Slow mode divider block diagram

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Miscellaneous $000C POR INTP INTN INTE SFA SFB SM WDOG ?001 000?

OSC1

pin OSC2

Oscillator fOSC

Control logicSM–bit

fOSC/2

÷ 2 ÷ 16

Main internal clock

fOSC/32

(bit 1, $000C)

TPG

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MOTOROLA

2-10 MC68HC05B6

Rev. 4

MODES OF OPERATION AND PIN DESCRIPTIONS

22.5 Pin descriptions

2.5.1 VDD and VSS

P o w er is supplied to the microcontroller using these two pins . VDD is the positiv e supply and VSS

is ground.

It is in the nature of CMOS designs that very fast signal tr ansitions occur on the MCU pins . These

shor t r ise and fall times place very high short-duration current demands on the power supply. To

prevent noise problems, special care must be taken to provide good power supply by-passing at

the MCU . By-pass capacitors should have good high-frequency char acteristics and be as close to

the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are

loaded.

2.5.2 IRQ

This is an input-only pin for external interrupt sources. Interrupt triggering is selected using the

INTP and INTN bits in the miscellaneous register, to be one of four options detailed in Table 9-3.

In addition, the external interrupt facility (IRQ) can be disabled using the INTE bit in the

miscellaneous register (see Section 3.8). It is only possible to change the interrupt option bits in

the miscellaneous register while the I-bit is set. Selecting a different interrupt option will

automatically clear any pending interrupts. Further details of the external interrupt procedure can

be found in Section 9.2.3.1.

The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity.

2.5.3 RESET

This active lo w I/O pin is used to reset the MCU. Applying a logic zero to this pin forces the device

to a known start-up state. An external RC-circuit can be connected to this pin to generate a

power-on-reset (POR) if required. In this case, the time constant must be great enough to allow

the oscillator circuit to stabilize. This input has an internal Schmitt trigger to improve noise

immunity. When a reset condition occurs internally, i.e. from the COP watchdog, the RESET pin

provides an active-low open drain output signal that may be used to reset external hardware.

2.5.4 TCAP1

The TCAP1 input controls the input capture 1 function of the on-chip prog rammable timer system.

TPG

05B6Book Page 10 Tuesday, April 6, 1999 8:24 am

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Rev. 4 MOTOROLA

2-11

MODES OF OPERATION AND PIN DESCRIPTIONS

2.5.5 TCAP2

The TCAP2 input controls the input capture 2 function of the on-chip prog rammable timer system.

2.5.6 TCMP1

The TCMP1 pin is the output of the output compare 1 function of the timer system.

2.5.7 TCMP2

The TCMP2 pin is the output of the output compare 2 function of the timer system.

2.5.8 OSC1, OSC2

These pins provide control input for an on-chip oscillator circuit. A crystal, ceramic resonator or

e xternal clock signal connected to these pins supplies the oscillator clock. The oscillator frequency

(fOSC) is divided by two to give the internal bus frequency (fOP). There is also a software option

which introduces an additional divide by 16 into the oscillator clock, giving an internal bus

frequency of fOSC/32.

2.5.8.1 Crystal

The circuit shown in Figure 2-5(a) is recommended when using either a crystal or a ceramic

resonator . Figure 2-5(d) lists the recommended capacitance and f eedback resistance values. The

internal oscillator is designed to interface with an AT-cut parallel-resonant quartz crystal resonator

in the frequency range speciﬁed for fOSC (see Section 11.4). Use of an external CMOS oscillator

is recommended when crystals outside the speciﬁed ranges are to be used. The crystal and

associated components should be mounted as close as possible to the input pins to minimise

output distor tion and start-up stabilisation time. The manufacturer of the particular cr ystal being

considered should be consulted for speciﬁc information.

2.5.8.2 Ceramic resonator

A ceramic resonator ma y be used instead of a crystal in cost sensitive applications. The circuit sho wn

in Figure 2-5(a) is recommended when using either a crystal or a ceramic resonator . Figure 2-5(d) lists

the recommended capacitance and feedback resistance values. The manufacturer of the particular

ceramic resonator being considered should be consulted f or speciﬁc information.

TPG

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MOTOROLA

2-12 MC68HC05B6

Rev. 4

MODES OF OPERATION AND PIN DESCRIPTIONS

22.5.8.3 External clock

An exter nal clock should be applied to the OSC1 input, with the OSC2 pin left unconnected, as

shown in Figure 2-5(c). The tOXOV or tILCH speciﬁcations (see Section 11.4) do not apply when

using an exter nal clock input. The equivalent speciﬁcation of the external clock source should be

used in lieu of tOXOV or tILCH.

Figure 2-5 Oscillator connections

Ceramic resonator

2 – 4MHz Unit

RS(typ) 10 Ω

C040 pF

C14.3 pF

COSC1 30 pF

COSC2 30 pF

RP1 – 10 MΩ

Q 1250 —

Crystal

2MHz 4MHz Unit

RS(max) 400 75 Ω

C057pF

C1812ƒF

COSC1 15 – 40 15 – 30 pF

COSC2 15 – 30 15 – 25 pF

RP10 10 MΩ

Q 30 000 40 000 —

OSC1 OSC2

MCU

COSC2

COSC1

OSC1 OSC2

MCU

NCExternal

clock

OSC1 OSC2

(d) Typical crystal and ceramic resonator parameters

(b) Crystal equivalent circuit

(a) Crystal/ceramic resonator

oscillator connections

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

2-13

MODES OF OPERATION AND PIN DESCRIPTIONS

2.5.9 RDI (Receive data in)

The RDI pin is the input pin of the SCI receiver.

2.5.10 TDO (Transmit data out)

The TDO pin is the output pin of the SCI transmitter.

2.5.11 SCLK

The SCLK pin is the clock output pin of the SCI transmitter.

2.5.12 PLMA

The PLMA pin is the output of pulse length modulation converter A.

2.5.13 PLMB

The PLMB pin is the output of pulse length modulation converter B.

2.5.14 VPP1

The VPP1 pin is the output of the charge pump for the EEPROM1 array.

2.5.15 VRH

The VRH pin is the positive reference voltage for the A/D converter.

2.5.16 VRL

The VRL pin is the negative reference voltage for the A/D converter.

2.5.17 PA0 – PA7/PB0 – PB7/PC0 – PC7

These 24 I/O lines comprise ports A, B and C. The state of any pin is software progr ammable , and

all the pins are conﬁgured as inputs during power-on or reset.

Under software control the PC2 pin can output the internal E-clock (see Section 4.2).

2.5.18 PD0/AN0–PD7/AN7

This 8-bit input only port (D) shares its pins with the A/D converter. When enabled, the A/D

converter uses pins PD0/AN0 – PD7/AN7 as its analog inputs. On reset, the A/D converter is

disabled which forces the port D pins to be input only port pins (see Section 8.5).

TPG

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MOTOROLA

2-14 MC68HC05B6

Rev. 4

MODES OF OPERATION AND PIN DESCRIPTIONS

THIS PAGE LEFT BLANK INTENTIONALLY

TPG

05B6Book Page 14 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

3-1

MEMORY AND REGISTERS

The MC68HC05B6 MCU is capable of addressing 8192 bytes of memory and registers with its

program counter. The memory map includes 5950 bytes of User ROM (including User vectors),

432 bytes of self check ROM, 176 bytes of RAM and 256 bytes of EEPROM.

3.1 Registers

All the I/O , control and status registers of the MC68HC05B6 are contained within the ﬁrst 32-byte

block of the memory map, as shown in Figure 3-1. The miscellaneous register is shown in

Section 3.8 as this register contains bits which are relevant to several modules.

3.2 RAM

The user RAM comprises 176 bytes of memory , from $0050 to $00FF. This is shared with a 64 b yte

stack area. The stack begins at $00FF and may extend down to $00C0.

Note:

Using the stack area f or data stor age or temporary work locations requires care to prev ent

the data from being ov erwritten due to stacking from an interrupt or subroutine call.

3.3 ROM

The User ROM consists of 5950 bytes of ROM mapped as follows:

• 48 bytes of page zero ROM from $0020 to $004F

• 5888 bytes of User ROM from $0800 to $1EFF

• 14 bytes of User vectors from $1FF2 to $1FFF

TPG

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MOTOROLA

3-2 MC68HC05B6

Rev. 4

MEMORY AND REGISTERS

3.4 Self-check ROM

There are two areas of self-check ROM (ROMI and ROMII) located from $0200 to $02BF (192

bytes) and $1F00 to $1FEF (240 bytes) respectively.

Figure 3-1 Memory map of the MC68HC05B6

$1FFE–F

$1FF6–7

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

User vectors

(14 bytes)

$0000 I/O

(32 bytes)

$0020

$00C0

$0100

$1FF0

Stack

RAM

(176 bytes)

$02C0

$0200

$1F00

$0050

Port A data direction register

Port B data direction register

Port C data direction register

EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Page 0 User

ROM

(48 bytes)

Self-check ROM I

(192 bytes)

User ROM

(5888 bytes)

Self-check ROM II

(240 bytes)

$0800

$1FF2–3

OPTR (1 byte)

Non protected (31 bytes)

Protected (224 bytes)

EEPROM

(256 bytes)

$0101

$0120

$0100Options register

Reserved

MC68HC05B6 Registers

SCI

Timer overﬂow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$1FF4–5

$1FF8–9

$1FFA–B

$1FFC–D

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

3-3

MEMORY AND REGISTERS

3.5 EEPROM

The user EEPROM consists of 256 bytes of memor y located from address $0100 to $01FF. 255

bytes are gener al purpose and 1 byte is used b y the option register. The non-v olatile EEPROM is

byte erasable.

An internal charge pump provides the EEPROM voltage (VPP1), which remov es the need to supply

a high voltage f or er ase and programming functions . The charge pump is a capacitor/diode ladder

network which will give a very high impedance output of around 20-30 MΩ. The voltage of the

charge pump is visible at the VPP1 pin. During normal operation of the device, where

programming/er asing of the EEPROM arr a y will occur, VPP1 should nev er be connected to either

VDD or VSS as this could pre vent the charge pump reaching the necessary programming voltage .

Where it is considered dangerous to leav e VPP1 unconnected for reasons of e xcessiv e noise in a

system, it may be tied to VDD; this will protect the EEPROM data but will also increase power

consumption, and therefore it is recommended that the protect bit function is used for regular

protection of EEPROM data (see Section 3.5.5).

In order to achie ve a higher degree of security f or stored data, there is no capability f or bulk or ro w

erase operations.

The EEPROM control register ($0007) provides control of the EEPROM programming and erase

operations.

Warning: The VPP1 pin should never be connected to VSS, as this could cause permanent

damage to the device.

3.5.1 EEPROM control register

ECLK

See Section 4.3 for a description of this bit.

E1ERA — EEPROM erase/programming bit

Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the

EEPROM is for erasing or programming purposes.

1 (set) – An erase operation will take place.

0 (clear) – A programming operation will take place.

Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

EEPROM/ECLK control $0007 0000ECLK E1ERA E1LAT E1PGM 0000 0000

TPG

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MOTOROLA

3-4 MC68HC05B6

Rev. 4

MEMORY AND REGISTERS

E1LAT — EEPROM programming latch enable bit

1 (set) – Address and data can be latched into the EEPROM for further

program or erase operations, providing the E1PGM bit is cleared.

0 (clear) – Data can be read from the EEPROM. The E1ERA bit and the E1PGM

bit are reset to zero when E1LAT is ‘0’.

STOP, power-on and external reset clear the E1LAT bit.

Note:

After the tERA1 erase time or tPROG1 programming time, the E1LAT bit has to be reset

to zero in order to clear the E1ERA bit and the E1PGM bit.

E1PGM — EEPROM charge pump enable/disable

1 (set) – Internal charge pump generator switched on.

0 (clear) – Internal charge pump generator switched off.

When the charge pump generator is on, the resulting high voltage is applied to the EEPROM arra y .

This bit cannot be set before the data is selected, and once this bit has been set it can only be

cleared by clearing the E1LAT bit.

A summary of the eff ects of setting/clearing bits 0, 1 and 2 of the control register are giv e in Tab le 3-1.

Note:

All combinations are not shown in the above table, since the E1PGM and E1ERA bits

are cleared when the E1LAT bit is at zero, and will result in a read condition.

Table 3-1 EEPROM control bits description

E1ERA E1LAT E1PGM Description

0 0 0 Read condition

0 1 0 Ready to load address/data for program/erase

0 1 1 Byte programming in progress

1 1 0 Ready for byte erase (load address)

1 1 1 Byte erase in progress

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

3-5

MEMORY AND REGISTERS

3.5.2 EEPROM read operation

To be able to read from EEPROM, the E1LAT bit has to be at logic zero, as shown in Table 3-1.

While this bit is at logic zero , the E1PGM bit and the E1ERA bit are permanently reset to zero and

the 256 bytes of EEPR OM may be read as if it were a normal ROM area. The internal charge pump

generator is automatically switched off since the E1PGM bit is reset.

If a read operation is ex ecuted while the E1LAT bit is set (erase or progr amming sequence), data

resulting from the operation will be $FF.

Note:

When not performing any programming or erase operation, it is recommended that

EEPROM should remain in the read mode (E1LAT = 0)

3.5.3 EEPROM erase operation

To erase the contents of a byte of the EEPROM, the following steps should be taken:

1 Set the E1LAT bit.

1) Set the E1ERA bit (1& 2 may be done simultaneously with the same

instruction).

2) Write address/data to the EEPROM address to be erased.

3) Set the E1PGM bit.

4) Wait for a time tERA1.

5) Reset the E1LAT bit (to logic zero).

While an erase operation is being performed, any access of the EEPROM array will not be

successful.

The erased state of the EEPROM is $FF and the programmed state is $00.

Note:

Data written to the address to be erased is not used, therefore its v alue is not signiﬁcant.

If a second word is to be erased, it is important that the E1LAT bit be reset before restar ting the

erasing sequence otherwise any write to a new address will hav e no effect. This condition provides

a higher degree of security for the stored data.

User programs m ust be running from the RAM or ROM as the EEPR OM will hav e its address and

data buses latched.

TPG

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MOTOROLA

3-6 MC68HC05B6

Rev. 4

MEMORY AND REGISTERS

3.5.4 EEPROM programming operation

To program a byte of EEPROM, the following steps should be taken:

1 Set the E1LAT bit.

2 Write address/data to the EEPROM address to be programmed.

3 Set the E1PGM bit.

4 Wait for time tPROG1.

5 Reset the E1LAT bit (to logic zero).

While a programming oper ation is being performed, any access of the EEPROM array will not be

successful.

Warning: To program a byte correctly, it has to have been pre viously erased. It is advised that this

is done only for 0→1 transitions, as this saves excessive overwriting of EEPROM.

If a second word is to be progr ammed, it is important that the E1LAT bit be reset before restarting

the programming sequence otherwise any write to a new address will have no effect. This condition

provides a higher degree of security for the stored data.

User programs m ust be running from the RAM or ROM as the EEPR OM will hav e its address and

data buses latched.

Note:

224 bytes of EEPR OM (address $0120 to $01FF) can be program and er ase protected

under the control of bit 1 of the OPTR register detailed in Section 3.5.5.

3.5.5 Options register (OPTR)

This register (OPTR), located at $0100, contains the secure and protect functions for the EEPROM

and allows the user to select options in a non-volatile manner. The contents of the OPTR register

are loaded into data latches with each power-on or external reset.

(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Options (OPTR)(1) $0100 EE1P SEC Not affected

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

3-7

MEMORY AND REGISTERS

EE1P – EEPROM protect bit

In order to achieve a higher degree of protection, the EEPROM is effectively split into two par ts,

both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to

$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected b y the EE1P bit

of the options register.

1 (set) – Part 2 of the EEPROM arra y is not protected; all 256 bytes of EEPROM

can be accessed f or any read, er ase or progr amming operations

0 (clear) – Part 2 of the EEPROM array is protected; any attempt to erase or

program a location will be unsuccessful

When this bit is set to 1 (erased), the protection will remain until the next power-on or external

reset. EE1P can only be written to ‘0’ when the ELAT bit in the EEPROM control register is set.

SEC – Security bit

This high security bit allows the user to secure the EEPROM data from external accesses. When

the SEC bit is at ‘0’, the EEPR OM contents are secured b y pre venting an y entry to test mode. The

only wa y to er ase the SEC bit to ‘1’ e xternally is to enter self-check mode , at which time the entire

EEPROM contents will be er ased. When the SEC bit is changed, its new v alue will ha ve no effect

until the next external or power-on reset.

3.6 EEPROM during STOP mode

When entering STOP mode, the EEPROM is automatically set to the read mode and the VPP1

high voltage charge pump generator is automatically disabled.

3.7 EEPROM during WAIT mode

The EEPROM is not affected by WAIT mode. Any program/erase operation will continue as in

normal operating mode. The charge pump is not affected by WAIT mode, theref ore it is possible to

wait the tERA1 erase time or tPROG1 programming time in WAIT mode.

Under normal operating conditions, the charge pump generator is driven by the internal CPU

clocks . When the operating frequency is lo w, e.g. during WAIT mode, the clocking should be done

by the internal A/D RC oscillator. The RC oscillator is enabled by setting the ADRC bit of the A/D

status/control register at $0009.

TPG

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Rev. 4

MEMORY AND REGISTERS

(1) The POR bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

Table 3-2 Register outline

reset

Port A data (PORTA) $0000 Undeﬁned

Port B data (PORTB) $0001 Undeﬁned

Port C data (PORTC) $0002 PC2/

ECLK Undeﬁned

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undeﬁned

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EEPROM/ECLK control $0007 0000ECLK E1ERA E1LAT E1PGM 0000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR (1) INTP INTN INTE SFA SFB SM WDOG (2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undeﬁned

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undeﬁned

Input capture high 1 $0014 Undeﬁned

Input capture low 1 $0015 Undeﬁned

Output compare high 1 $0016 Undeﬁned

Output compare low 1 $0017 Undeﬁned

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undeﬁned

Input capture low 2 $001D Undeﬁned

Output compare high 2 $001E Undeﬁned

Output compare low 2 $001F Undeﬁned

Options (OPTR)(3) $0100 EE1P SEC Not affected

TPG

05B6Book Page 8 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

3-9

MEMORY AND REGISTERS

3.8 Miscellaneous register

POR — Power-on reset bit (see Section 9.1)

This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the

user to make a softw are distinction betw een a power-on and an external reset. This bit cannot be

set by software and is cleared by writing it to zero.

1 (set) – A power-on reset has occurred.

0 (clear) – No power-on reset has occurred.

INTP, INTN — External interrupt sensitivity options (see Section 9.2)

These two bits allow the user to select which edge the IRQ pin will be sensitive to (see Table 3-3).

Both bits can be written to only while the I-bit is set, and are cleared by pow er-on or external reset,

thus the device is initialised with negative edge and low level sensitivity.

INTE — External interrupt enable (see Section 9.2)

1 (set) – External interrupt function (IRQ) enabled.

0 (clear) – External interrupt function (IRQ) disabled.

The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,

thus enabling the external interrupt function.

(1) The POR bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Miscellaneous $000C POR (1) INTP INTN INTE SFA SFB SM WDOG (2) ?001 000?

Table 3-3 IRQ sensitivity

INTP INTN IRQ sensitivity

0 0 Negative edge and low level sensitive

0 1 Negative edge only

1 0 Positive edge only

1 1 Positive and negative edge sensitive

TPG

05B6Book Page 9 Tuesday, April 6, 1999 8:24 am

MOTOROLA

3-10 MC68HC05B6

Rev. 4

MEMORY AND REGISTERS

SFA — Slow or fast mode selection for PLMA (see Section 7.1)

This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation output.

1 (set) – Slow mode PLMA (4096 x timer clock period).

0 (clear) – Fast mode PLMA (256 x timer clock period).

SFB — Slow or fast mode selection for PLMB (see Section 7.1)

This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation output.

1 (set) – Slow mode PLMB (4096 x timer clock period).

0 (clear) – Fast mode PLMB (256 x timer clock period).

Note:

The highest speed of the PLM system corresponds to the frequency of the TOF bit

being set, multiplied by 256. The lowest speed of the PLM system corresponds to the

frequency of the TOF bit being set, multiplied by 16.

Warning: Because the SF A bit and SFB bit are not doub le buff ered, it is mandatory to set the SF A

bit and SFB bit to the desired values before writing to the PLM registers; not doing so

could temporarily give incorrect values at the PLM outputs.

SM — Slow mode (see Section 2.4.3)

1 (set) – The system runs at a bus speed 16 times lower than normal

(fOSC/32). SLOW mode affects all sections of the device, including

SCI, A/D and timer.

0 (clear) – The system runs at normal bus speed (fOSC/2).

The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when

entering STOP mode.

WDOG — Watchdog enable/disable (see Section 9.1.4)

The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.

F ollo wing a w atchdog reset the state of the WDOG bit is as deﬁned b y the mask option speciﬁed.

Once the watchdog is enabled, the WDOG bit acts as a reset mechanism for the watchdog counter.

Writing a’1’ to this bit clears the counter to its initial value and prevents a watchdog timeout.

1 (set) – Watchdog counter cleared and enabled.

0 (clear) – The watchdog cannot be disabled by software; writing a zero to this

bit has no effect.

TPG

05B6Book Page 10 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

4-1

INPUT/OUTPUT PORTS

In single-chip mode, the MC68HC05B6 has a total of 24 I/O lines , arranged as three 8-bit ports (A,

B and C), and eight input-only lines, arranged as one 8-bit port (D). Each I/O line is individually

programmab le as either input or output, under the softw are control of the data direction registers.

The 8-bit input-only port (D) shares its pins with the A/D converter, when the A/D converter is

enabled. To avoid glitches on the output pins, data should be written to the I/O port data register

bef ore writing ones to the corresponding data direction register bits to set the pins to output mode.

4.1 Input/output programming

The bidirectional port lines may be programmed as inputs or outputs under software control. The

direction of each pin is determined by the state of the corresponding bit in the port data direction

its corresponding DDR bit is set to a logic one. A pin is conﬁgured as an input if its corresponding

DDR bit is cleared to a logic zero.

At power-on or reset, all DDRs are cleared, thus conﬁguring all port pins as inputs. The data

direction registers can be written to or read by the MCU. During the programmed output state, a

read of the data register actually reads the value of the output data latch and not the I/O pin. The

operation of the standard port hardware is shown schematically in Figure 4-1.

TPG

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

MOTOROLA

4-2 MC68HC05B6

Rev. 4

INPUT/OUTPUT PORTS

Table 4-1 shows the effect of reading from or writing to an I/O pin in various circumstances. Note

that the read/write signal shown is internal and not available to the user.

4.2 Ports A and B

These ports are standard M68HC05 bidirectional I/O ports, each comprising a data register and a

data direction register.

Reset does not affect the state of the data register, but clears the data direction register, thereby

returning all port pins to input mode. Writing a ‘1’ to any DDR bit sets the corresponding port pin

to output mode.

Figure 4-1 Standard I/O port structure

Table 4-1 I/O pin states

R/W DDRn Action of MCU write to/read of data bit

0 0 The I/O pin is in input mode. Data is written into the output data latch.

0 1 Data is written into the output data latch, and output to the I/O pin.

1 0 The state of the I/O pin is read.

1 1 The I/O pin is in output mode. The output data latch is read.

Latched data

DDRn

DATA

Input

buffer

Output

buffer

O/P

data

buffer

M68HC05 internal connections

DDRn DATA I/O Pin

100

111

0 0 tristate

0 1 tristate

I/O

Output 



Input

Data direction









TPG

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

4-3

INPUT/OUTPUT PORTS

4.3 Port C

In addition to the standard port functions described for port A and B, port C pin 2 can be

conﬁgured, using the ECLK bit of the EEPROM/ECLK control register, to output the CPU clock. If

this is selected the corresponding DDR bit is automatically set and bit 2 of port C will alwa ys read

the output data latch. The other port C pins are not affected by this feature.

ECLK — External clock output bit

1 (set) – ECLK CPU clock is output on PC2.

0 (clear) – ECLK CPU clock is not output on PC2; port C acts as a normal I/O port.

The ECLK bit is cleared by po wer-on or external reset. It is not affected b y the ex ecution of a STOP

or W AIT instruction.

The timing diagram of the clock output is shown in Figure 4-2.

4.4 Port D

This 8-bit input-only port shares its pins with the A/D converter subsystem. When the A/D

conv erter is enabled, pins PD0-PD7 read the eight analog inputs to the A/D converter. P ort D can

be read at any time, however, if it is read during an A/D conversion sequence noise, may be

injected on the analog inputs, resulting in reduced accuracy of the A/D. Further more, performing

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

EEPROM/ECLK control $0007 0000ECLK E1ERA E1LAT E1PGM 0000 0000

Figure 4-2 ECLK timing diagram

Internal clock (PHI2)

External clock (ECLK/PC2)

Output port (if write to output port)

TPG

05B6Book Page 3 Tuesday, April 6, 1999 8:24 am

MOTOROLA

4-4 MC68HC05B6

Rev. 4

INPUT/OUTPUT PORTS

a digital read of por t D with levels other than VDD or VSS on the por t D pins will result in greater

power dissipation during the read cycle.

As por t D is an input-only por t there is no DDR associated with it. Also, at power up or exter nal

reset, the A/D converter is disabled, thus the port is conﬁgured as a standard input-only port.

Note:

It is recommended that all unused input por ts and I/O por ts be tied to an appropriate

logic level (i.e. either VDD or VSS).

4.5 Port registers

The following sections explain in detail the individual bits in the data and control registers

associated with the ports.

4.5.1 Port data registers A and B (PORTA and PORTB)

Each bit can be conﬁgured as input or output via the corresponding data direction bit in the por t

data direction register (DDRx).

The state of the port data registers following reset is not deﬁned.

4.5.2 Port data register C (PORTC)

Each bit can be conﬁgured as input or output via the corresponding data direction bit in the por t

data direction register (DDRx).

In addition, bit 2 of port C is used to output the CPU clock if the ECLK bit in the EEPROM

CTL/ECLK register is set (see Section 4.3).

The state of the port data registers following reset is not deﬁned.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Port A data (PORTA) $0000 Undeﬁned

Port B data (PORTB) $0001 Undeﬁned

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Port C data (PORTC) $0002 PC2/

ECLK Undeﬁned

TPG

05B6Book Page 4 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

4-5

INPUT/OUTPUT PORTS

4.5.3 Port data register D (PORTD)

All the port D bits are input-only and are shared with the A/D conv erter. The function of each bit is

determined by the ADON bit in the A/D status/control register.

The state of the port data registers following reset is not deﬁned.

4.5.3.1 A/D status/control register

ADON — A/D converter on

1 (set) – A/D con v erter is switched on; all port D pins act as analog inputs for

the A/D converter.

0 (clear) – A/D converter is switched off; all port D pins act as input only pins.

Reset clears the ADON bit, thus conﬁguring port D as an input only port.

4.5.4 Data direction registers (DDRA, DDRB and DDRC)

Writing a ‘1’ to any bit conﬁgures the corresponding port pin as an output; conversely, writing any

bit to ‘0’ conﬁgures the corresponding port pin as an input.

Reset clears these registers, thus conﬁguring all ports as inputs.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undeﬁned

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

A/D status/control $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

TPG

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MOTOROLA

4-6 MC68HC05B6

Rev. 4

INPUT/OUTPUT PORTS

4.6 Other port considerations

All output ports can emulate ‘open-dr ain’ outputs. This is achiev ed by writing a zero to the rele v ant

output port latch. By toggling the corresponding data direction bit, the port pin will either be an

output zero or tri-state (an input). This is shown diagrammatically in Figure 4-3.

When using a port pin as an ‘open-drain’ output, cer tain precautions must be taken in the user

software. If a read-modify-write instruction is used on a port where the ‘open-drain’ is assigned and

the pin at this time is programmed as an input, it will read it as a ‘one’. The read-modify-write

instruction will then wr ite this ‘one’ into the output data latch on the next cycle. This would cause

the ‘open-drain’ pin not to output a ‘zero’ when desired.

Note:

‘Open-drain’ outputs should not be pulled above VDD.

Figure 4-3 Port logic levels

DDRn A Y

(b)

100

Normal operation – tri state

111

0 0 tri state

0 1 tri state

1 0 low

‘Open-drain’

11—

0 0 high

0 1 high

















Read buffer output

Data direction register bit DDRn

Px0

VDD

DDRx, bit 0 = 0

Portx, bit 0 = 0 DDRx, bit 0 = 0

Portx, bit 0 = 0

(c)

(a)

‘Open-drain’ output

TPG

05B6Book Page 6 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

5-1

PROGRAMMABLE TIMER

The programmab le timer on the MC68HC05B6 consists of a 16-bit read-only free-running counter ,

with a ﬁx ed divide-by-f our prescaler , plus the input capture/output compare circuitry. The timer can

be used f or man y purposes including measuring pulse length of two input signals and generating

two output signals. Pulse lengths for both input and output signals can vary from several

microseconds to many seconds. In addition, it works in conjunction with the pulse length

modulation (PLM) system, which can also be ref erred to as the pulse width modulation system, to

execute two 8-bit D/A PLM (pulse length modulation) conversions, with a choice of two repetition

rates. The timer is also capable of generating periodic interrupts or indicating passage of an

arbitrary multiple of four CPU cycles . A b lock diag ram is shown in Figure 5-1, and timing diagrams

are shown in Figure 5-2, Figure 5-3, Figure 5-4 and Figure 5-5.

The timer has a 16-bit architecture, hence each speciﬁc functional segment is represented b y two

8-bit registers (e xcept the PLMA and PLMB which use one 8-bit register for each). These registers

contain the high and low b yte of that functional segment. Accessing the low b yte of a speciﬁc timer

function allows full control of that function; howev er , an access of the high byte inhibits that speciﬁc

timer function until the low byte is also accessed.

The 16-bit programmable timer is monitored and controlled by a group of sixteen registers, full

details of which are contained in this section.

Note:

A problem may arise if an interrupt occurs in the time between the high and low bytes

being accessed. To prevent this, the I-bit in the condition code register (CCR) should be

set while manipulating both the high and low byte register of a speciﬁc timer function,

ensuring that an interrupt does not occur.

5.1 Counter

The key element in the programmable timer is a 16-bit, free-running counter or counter register,

preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the

timer a resolution of 2µs if the internal bus clock is 2 MHz. The counter is incremented during the

low portion of the inter nal bus clock. Software can read the counter at any time without affecting

its value.

TPG

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MOTOROLA

5-2 MC68HC05B6

Rev. 4

PROGRAMMABLE TIMER

Figure 5-1 16-bit programmable timer block diagram

Internal

Internal bus

Output

compare

processor

clock

8-bit

buffer

÷4

High Low

16-bit

free-running

counter

Counter

alternate

Internal timer bus

Overﬂow

detect

circuit

Edge

detect

TCAP1

TCMP2

TCMP1

Latch

compare

Output register 2

Input capture

byte byte

High

byte Low

byte

High

byte Low

byte High

byte Low

byte

High

byte

circuit 1

compare

Output

circuit 2

compare

Output

circuit 1

Edge

detect

circuit 2 TCAP2

Latch

76543Timer status

$0013

$0012

$0018

$0019

$001A

$001B

$001C

$0016

$0017 $0014

$0015

$001E

$001F $001D

To PLM

ICF1 OCF1 TOF ICF2 OCF2

ICIE OCIE TOIE FOLV2 OLVL2 IEDG1 OLVL1

FOLV1

Interrupt circuit

Input capture

interrupt

$1FF8,9

Output compare

interrupt

$1FF6,7

Overﬂow interrupt

$1FF4,5

COP watchdog

counter input

TPG

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

5-3

PROGRAMMABLE TIMER

5.1.1 Counter register and alternate counter register

The double-byte, free-running counter can be read from either of two locations, $18-$19 (counter

of the free-running counter ($19 or $1B) receives the count v alue at the time of the read. If a read

of the free-running counter or alter nate counter register ﬁrst addresses the more signiﬁcant byte

(MSB) ($18 or $1A), the LSB is transf erred to a buff er . This buff er value remains ﬁx ed after the ﬁrst

MSB read, e ven if the user reads the MSB se veral times . This b uffer is accessed when reading the

free-running counter or alternate counter register LSB and thus completes a read sequence of the

total counter value. In reading either the free-running counter or alternate counter register, if the

MSB is read, the LSB must also be read to complete the sequence. If the timer ov erﬂow ﬂag (T OF)

is set when the counter register LSB is read then a read of the timer status register (TSR) will clear

the ﬂag.

The alternate counter register differs from the counter register only in that a read of the LSB does

not clear TOF. Therefore, where it is critical to avoid the possibility of missing timer overﬂow

interrupts due to clearing of TOF, the alternate counter register should be used.

The free-running counter is set to $FFFC during power-on and external reset and is always a

read-only register . During a power-on reset, the counter begins running after the oscillator start-up

delay. Because the free-running counter is 16 bits preceded by a ﬁxed divide-by-4 prescaler, the

value in the free-running counter repeats e very 262,144 internal bus cloc k cycles. T OF is set when

the counter overﬂows (from $FFFF to $0000); this will cause an interrupt if TOIE is set.

In some par ticular timing control applications it may be desirable to reset the 16-bit free running

counter under software control. When the low byte of the counter ($19 or $1B) is written to, the

counter is conﬁgured to its reset value ($FFFC).

The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of

the ﬂags and enable bits remain unaltered by this operation. If access has previously been made

to the high byte of the free-running counter ($18 or $1A), then the reset counter operation

terminates the access sequence.

Warning: This operation ma y aff ect the function of the watchdog system (see Section 9.1.4). The

PLM results will also be affected while resetting the counter.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

TPG

05B6Book Page 3 Tuesday, April 6, 1999 8:24 am

MOTOROLA

5-4 MC68HC05B6

Rev. 4

PROGRAMMABLE TIMER

5.2 Timer control and status

The various functions of the timer are monitored and controlled using the timer control and status

registers described below.

5.2.1 Timer control register (TCR)

The timer control register ($0012) is used to enable the input captures (ICIE), output compares

(OCIE), and timer overﬂow (TOIE) functions as well as forcing output compares (FOLV1 and

FOLV2), selecting input edge sensitivity (IEDG1) and levels of output polarity (OLV1 and OLV2).

ICIE — Input captures interrupt enable

If this bit is set, a timer interrupt is enabled whenever the ICF1 or ICF2 status ﬂag (in the timer

status register) is set.

1 (set) – Interrupt enabled.

0 (clear) – Interrupt disabled.

OCIE — Output compares interrupt enable

If this bit is set, a timer interrupt is enabled whenever the OCF1 or OCF2 status ﬂag (in the timer

status register) is set.

1 (set) – Interrupt enabled.

0 (clear) – Interrupt disabled.

TOIE — Timer overﬂow interrupt enable

If this bit is set, a timer interrupt is enabled whenever the TOF status ﬂag (in the timer status

1 (set) – Interrupt enabled.

0 (clear) – Interrupt disabled.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

5-5

PROGRAMMABLE TIMER

FOLV2 — Force output compare 2

This bit alwa ys reads as zero , hence writing a zero to this bit has no eff ect. Writing a one at this position

will f orce the OLV2 bit to the corresponding output lev el latch, thus appearing at the TCMP2 pin. Note

that this bit does not aff ect the OCF2 bit of the status register (see Section 5.4.3).

1 (set) – OLV2 bit forced to output level latch.

0 (clear) – No effect.

FOLV1 — Force output compare 1

This bit alwa ys reads as zero , hence writing a zero to this bit has no eff ect. Writing a one at this position

will f orce the OLV1 bit to the corresponding output lev el latch, thus appearing at the TCMP1 pin. Note

that this bit does not aff ect the OCF1 bit of the status register (see Section 5.4.3).

1 (set) – OLV1 bit forced to output level latch.

0 (clear) – No effect.

OLV2 — Output level 2

When OLV2 is set a high output level will be clocked into the output level register by the next

successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level

which will appear on the TCMP2 pin.

1 (set) – A high output level will appear on the TCMP2 pin.

0 (clear) – A low output level will appear on the TCMP2 pin.

IEDG1 — Input edge 1

When IEDG1 is set, a positive-going edge on the TCAP1 pin will trigger a transfer of the

free-running counter value to the input capture register 1. When clear, a negative-going edge

triggers the transfer.

1 (set) – TCAP1 is positive-going edge sensitive.

0 (clear) – TCAP1 is negative-going edge sensitive.

Note:

There is no need for an equivalent bit for the input capture register 2 as TCAP2 is

negative-going edge sensitive only.

OLV1 — Output level 1

When OLV1 is set a high output level will be clocked into the output level register by the next

successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level

which will appear on the TCMP1 pin.

1 (set) – A high output level will appear on the TCMP1 pin.

0 (clear) – A low output level will appear on the TCMP1 pin.

TPG

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MOTOROLA

5-6 MC68HC05B6

Rev. 4

PROGRAMMABLE TIMER

5.2.2 Timer status register (TSR)

The timer status register ($13) is a read only register and contains the status bits corresponding

to the four timer interrupt conditions – ICF1,OCF1, TOF, ICF2 and OCF2.

Accessing the timer status register satisﬁes the ﬁrst condition required to clear the status bits. The

remaining step is to access the register corresponding to the status bit.

ICF1 — Input capture ﬂag 1

This bit is set when the selected polarity of edge is detected by the input capture edge detector 1

at TCAP1; an input capture interrupt will be generated, if ICIE is set. ICF1 is cleared by reading

the TSR and then the input capture low register 1 ($15).

1 (set) – A valid input capture has occurred.

0 (clear) – No input capture has occurred.

OCF1 — Output compare ﬂag 1

This bit is set when the output compare 1 register contents match those of the free-running

counter; an output compare interrupt will be generated if OCIE is set. OCF1 is cleared by reading

the TSR and then reading or writing the output compare 1 low register ($17).

1 (set) – A valid output compare has occurred.

0 (clear) – No output compare has occurred.

TOF — Timer overﬂow status ﬂag

This bit is set when the free-running counter overﬂo ws from $FFFF to $0000; a timer overﬂo w interrupt

will occur if TOIE is set. TOF is cleared b y reading the TSR and the counter low register ($19).

1 (set) – Timer overﬂow has occurred.

0 (clear) – No timer overﬂow has occurred.

When using the timer overﬂow function and reading the free-running counter at random times to

measure an elapsed time, a prob lem may occur whereb y the timer overﬂow ﬂag is unintentionally

cleared if:

1 The timer status register is read or written when TOF is set, and

1) The LSB of the free-running counter is read, but not for the purpose of

servicing the ﬂag.

Reading the alternate counter register instead of the counter register will avoid this potential

problem.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undeﬁned

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

5-7

PROGRAMMABLE TIMER

ICF2 — Input capture ﬂag 2

This bit is set when a negative edge is detected by the input capture edge detector 2 at TCAP2;

an input capture interrupt will be generated if ICIE is set. ICF2 is cleared by reading the TSR and

then the input capture low register 2 ($1D).

1 (set) – A valid (negative) input capture has occurred.

0 (clear) – No input capture has occurred.

OCF2 — Output compare ﬂag 2

This bit is set when the output compare 2 register contents match those of the free-running

counter; an output compare interrupt will be generated if OCIE is set. OCF2 is cleared by reading

the TSR and then reading or writing the output compare 2 low register ($1F).

1 (set) – A valid output compare has occurred.

0 (clear) – No output compare has occurred.

5.3 Input capture

‘Input capture’ is a technique whereby an external signal is used to trigger a read of the free

running counter. In this way it is possible to relate the timing of an exter nal signal to the internal

counter value, and hence to elapsed time.

There are two input capture registers: input capture register 1 (ICR1) and input capture register 2 (ICR2).

The same input capture interrupt enable bit (ICIE) is used for the two input captures.

5.3.1 Input capture register 1 (ICR1)

The two 8-bit registers that mak e up the 16-bit input capture register 1 are read-only, and are used

to latch the value of the free-running counter after the input capture edge detector circuit 1 senses

a valid transition at TCAP1. The level transition that triggers the counter transfer is deﬁned by the

input edge bit (IEDG1). When an input capture 1 occurs, the corresponding ﬂag ICF1 in TSR is set.

An interrupt can also accompany an input capture 1 provided the ICIE bit in TCR is set. The 8 most

signiﬁcant bits are stored in the input capture high 1 register at $14, the 8 least signiﬁcant bits in

the input capture low 1 register at $15.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Input capture high 1 $0014 Undeﬁned

Input capture low 1 $0015 Undeﬁned

TPG

05B6Book Page 7 Tuesday, April 6, 1999 8:24 am

MOTOROLA

5-8 MC68HC05B6

Rev. 4

PROGRAMMABLE TIMER

The result obtained from an input capture will be one greater than the value of the free-running

counter on the rising edge of the internal bus cloc k preceding the e xternal transition. This delay is

required f or internal synchronization. Resolution is one count of the free-running counter , which is

four internal bus clock cycles. The free-running counter contents are transferred to the input

capture register 1 on each valid signal transition whether the input capture 1 ﬂag (ICF1) is set or

clear . The input capture register 1 always contains the free-running counter value that corresponds

to the most recent input capture 1. After a read of the input capture 1 register MSB ($14), the

counter transfer is inhibited until the LSB ($15) is also read. This character istic causes the time

used in the input capture software routine and its interaction with the main program to determine

the minimum pulse period. A read of the input capture 1 register LSB ($15) does not inhibit the

free-running counter transfer since the two actions occur on opposite edges of the internal bus

clock.

Reset does not aff ect the contents of the input capture 1 register, e xcept when e xiting STOP mode

(see Section 5.6).

5.3.2 Input capture register 2 (ICR2)

The two 8-bit registers that mak e up the 16-bit input capture register 2 are read-only, and are used

to latch the value of the free-running counter after the input capture edge detector circuit 2 senses

a negative transition at pin TCAP2. When an input capture 2 occurs, the corresponding ﬂag ICF2

in TSR is set. An interrupt can also accompany an input capture 2 provided the ICIE bit in TCR is

set.The 8 most signiﬁcant bits are stored in the input capture 2 high register at $1C, the 8 least

signiﬁcant bits in the input capture 2 low register at $1D.

The result obtained from an input capture will be one greater than the value of the free-running

counter on the rising edge of the internal bus cloc k preceding the e xternal transition. This delay is

required f or internal synchronization. Resolution is one count of the free-running counter , which is

four internal bus clock cycles. The free-running counter contents are transferred to the input

capture register 2 on each negative signal tr ansition whether the input capture 2 ﬂag (IC2F) is set

or clear. The input capture register 2 always contains the free-running counter value that

corresponds to the most recent input capture 2. After a read of the input capture register 2 MSB

($1C), the counter transf er is inhibited until the LSB ($1D) is also read. This char acteristic causes

the time used in the input capture software routine and its interaction with the main program to

determine the minimum pulse per iod. A read of the input capture register 2 LSB ($1C) does not

inhibit the free-running counter transfer since the two actions occur on opposite edges of the

internal bus clock.

Reset does not aff ect the contents of the input capture 2 register, e xcept when e xiting STOP mode

(see Section 5.6).

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Input capture high 2 $001C Undeﬁned

Input capture low 2 $001D Undeﬁned

TPG

05B6Book Page 8 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

5-9

PROGRAMMABLE TIMER

5.4 Output compare

‘Output compare’ is a technique which ma y be used, for e xample, to generate an output wav eform,

or to signal when a speciﬁc time period has elapsed, by presetting the output compare register to

the appropriate value.

There are two output compare registers: output compare register 1 (OCR1) and output compare

Note:

The same output compare interrupt enable bit (OCIE) is used for the two output

compares.

5.4.1 Output compare register 1 (OCR1)

The 16-bit output compare register 1 is made up of two 8-bit registers at locations $16 (MSB) and

$17 (LSB). The contents of the output compare register 1 are compared with the contents of the

free-running counter continually and, if a match is found, the corresponding output compare ﬂag

(OCF1) in the timer status register is set and the output le vel (OLVL1) is transferred to pin TCMP1.

The output compare register 1 values and the output level bit should be changed after each

successful comparison to establish a new elapsed timeout. An interrupt can also accompany a

successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The

free-running counter is updated every four internal bus clock cycles.)

After a processor write cycle to the output compare register 1 containing the MSB ($16), the output

compare function is inhibited until the LSB ($17) is also written. The user must write both bytes

(locations) if the MSB is written ﬁrst. A write made only to the LSB ($17) will not inhibit the compare

1 function. The processor can write to either byte of the output compare register 1 without aff ecting

the other byte . The output lev el (OLVL1) bit is clocked to the output lev el register and hence to the

TCMP1 pin whether the output compare ﬂag 1 (OCF1) is set or clear. The minim um time required

to update the output compare register 1 is a function of the program rather than the internal

hardware. Because the output compare ﬂag 1 and the output compare register 1 are not deﬁned

at power on, and not affected by reset, care must be taken when initializing output compare

functions with software. The following procedure is recommended:

– Write to output compare high 1 to inhibit further compares;

– Read the timer status register to clear OCF1 (if set);

– Write to output compare low 1 to enable the output compare 1 function.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Output compare high 1 $0016 Undeﬁned

Output compare low 1 $0017 Undeﬁned

TPG

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MOTOROLA

5-10 MC68HC05B6

Rev. 4

PROGRAMMABLE TIMER

The purpose of this procedure is to pre vent the OCF1 bit from being set between the time it is read

and the write to the corresponding output compare register.

All bits of the output compare register are readable and writable and are not altered by the timer

hardware or reset. If the compare function is not needed, the two bytes of the output compare

5.4.2 Output compare register 2 (OCR2)

The 16-bit output compare register 2 is made up of two 8-bit registers at locations $1E (MSB) and

$1F (LSB). The contents of the output compare register 2 are compared with the contents of the

free-running counter continually and, if a match is found, the corresponding output compare ﬂag

(OCF2) in the timer status register is set and the output le vel (OLVL2) is transferred to pin TCMP2.

The output compare register 2 values and the output level bit should be changed after each

successful comparison to establish a new elapsed timeout. An interrupt can also accompany a

successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The

free-running counter is updated every four internal bus clock cycles.)

After a processor write cycle to the output compare register 2 containing the MSB ($1E), the output

compare function is inhibited until the LSB ($1F) is also written. The user must write both bytes

(locations) if the MSB is written ﬁrst. A write made only to the LSB ($1F) will not inhibit the compare

2 function. The processor can write to either byte of the output compare register 2 without aff ecting

the other byte . The output lev el (OLVL2) bit is clocked to the output lev el register and hence to the

TCMP2 pin whether the output compare ﬂag 2 (OCF2) is set or clear. The minim um time required

to update the output compare register 2 is a function of the program rather than the internal

hardware. Because the output compare ﬂag 2 and the output compare register 2 are not deﬁned

at power on, and not affected by reset, care must be taken when initializing output compare

functions with software. The following procedure is recommended:

– Write to output compare high 2 to inhibit further compares;

– Read the timer status register to clear OCF2 (if set);

– Write to output compare low 2 to enable the output compare 2 function.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Output compare high 2 $001E Undeﬁned

Output compare low 2 $001F Undeﬁned

TPG

05B6Book Page 10 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

5-11

PROGRAMMABLE TIMER

The purpose of this procedure is to pre vent the OCF1 bit from being set between the time it is read

and the write to the corresponding output compare register.

All bits of the output compare register are readable and writable and are not altered by the timer

hardware or reset. If the compare function is not needed, the two bytes of the output compare

5.4.3 Software force compare

A software f orce compare is required in many applications. To achiev e this, bit 3 (FOLV1 f or OCR1)

and bit 4 (FOLV2 f or OCR2) in the timer control register are used. These bits alwa ys read as ‘zero’,

but a write to ‘one’ causes the respective OLVL1 or OLVL2 values to be copied to the respective

output level (TCMP1 and TCMP2 pins).

Internal logic is arranged such that in a single instruction, one can change OLVL1 and/or OLVL2,

at the same time causing a forced output compare with the new values of OLVL1 and OLVL2. In

conjunction with normal compare, this function allows a wide range of applications including ﬁx ed

frequency generation.

Note:

A software force compare will affect the corresponding output pin TCMP1 and/or

TCMP2, but will not affect the compare ﬂag, thus it will not generate an interrupt.

5.5 Pulse Length Modulation (PLM)

The programmab le timer w orks in conjunction with the PLM system to execute two 8-bit D/A PLM

conversions, with a choice of two repetition rates (see Section 7).

5.5.1 Pulse length modulation registers A and B (PLMA/PLMB)

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Pulse length modulation A (PLMA) $000A 0000 0000

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Pulse length modulation B (PLMB) $000B 0000 0000

TPG

05B6Book Page 11 Tuesday, April 6, 1999 8:24 am

MOTOROLA

5-12 MC68HC05B6

Rev. 4

PROGRAMMABLE TIMER

5.6 Timer during STOP mode

When the MCU enters STOP mode, the timer counter stops counting and remains at that particular

count value until STOP mode is exited by an interrupt. If STOP mode is exited by power-on or

e xternal reset, the counter is forced to $FFFC b ut if it is e xited b y e xternal interrupt (IRQ) then the

counter resumes from its stopped value.

Another f eature of the programmab le timer is that if at least one valid input capture edge occurs at

one of the TCAP pins while in STOP mode, the corresponding input capture detect circuitry is

armed. This action does not wake the MCU or set any timer ﬂags, but when the MCU does wake-up

there will be an active input capture ﬂag (and data) from that ﬁrst v alid edge which occurred during

STOP mode.

If STOP mode is exited by an external reset then no such input capture ﬂag or data action takes

place even if there was a valid input capture edge (at one of the TCAP pins) during STOP mode.

5.7 Timer during WAIT mode

The timer system is not affected by WAIT mode and continues nor mal operation. Any valid timer

interrupt will wake-up the system.

5.8 Timer state diagrams

The relationships between the internal clock signals, the counter contents and the status of the

ﬂag bits are shown in the following ﬁgures. It should be noted that the signals labelled ‘inter nal’

(processor clock, timer clocks and reset) are not available to the user.

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

5-13

PROGRAMMABLE TIMER

Figure 5-2 Timer state timing diagram for reset

Figure 5-3 Timer state timing diagram for input capture

Internal

processor clock

Internal

reset

16-bit

counter

External reset

or end of POR

Internal

timer clocks











$FFFC $FFFD $FFFE $FFFF

Note: The counter and timer control registers are the only ones affected by power-on or external reset.

T00

T01

T11

T10

Internal

processor clock

16-bit

counter $F123 $F124 $F125 $F126

Internal

timer clocks











T00

T01

T11

T10

Internal

capture latch

$F124$????

Input capture

ﬂag

Input

edge

}

Note: If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then

the input capture ﬂag will be set during the next T11 state.

TPG

05B6Book Page 13 Tuesday, April 6, 1999 8:24 am

MOTOROLA

5-14 MC68HC05B6

Rev. 4

PROGRAMMABLE TIMER

Figure 5-4 Timer state timing diagram for output compare

Figure 5-5 Timer state timing diagram for timer overﬂow

Internal

processor clock

16-bit

counter $F456 $F457 $F458 $F459

Internal

timer clocks











T00

T01

T11

T10

$F457CPU writes $F457

Output compare

ﬂag and TCMP1,2

Note: 1 The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state

T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare.

1) The output compare ﬂag is set at the timer state T11 that f ollo ws the comparison match ($F457 in this example).

Output compare

Compare register

latch

(Note 2)

(Note 1)

Internal

processor clock

16-bit

counter $FFFF $0000 $0001 $0002

Internal

timer clocks











T00

T01

T11

T10

Note: The timer overﬂow ﬂag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared

by a read of the timer status register during the internal processor clock high time, followed by a read of the

counter low register.

Timer overﬂow

ﬂag

TPG

05B6Book Page 14 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

6-1

SERIAL COMMUNICATIONS INTERFACE

A full-duplex asynchronous serial communications interface (SCI) is provided with a standard

non-return-to-zero (NRZ) format and a variety of baud rates . The SCI tr ansmitter and receiv er are

functionally independent and have their own baud r ate generator; how ever they share a common

baud rate prescaler and data format.

The serial data format is standard mark/space (NRZ) and provides one start bit, eight or nine data

bits, and one stop bit.

The SCLK pin is the output of the transmitter clock. It outputs the transmitter data clock for

synchronous transmission (no cloc ks on start bit and stop bit, and a software option to send cloc k

on last data bit). This allows control of peripherals containing shift registers (e.g. LCD drivers).

Phase and polarity of these clocks are software programmable.

Any SCI bidirectional communication requires a two-wire system: receive data in (RDI) and

transmit data out (TDO).

‘Baud’ and ‘bit rate’ are used synonymously in the following description.

6.1 SCI two-wire system features

• Standard NRZ (mark/space) format

• Adv anced error detection method with noise detection f or noise dur ation of up to 1/16th bit time

• Full-duplex operation (simultaneous transmit and receive)

• 32 software selectable baud rates

• Different baud rates for transmit and receive; for each transmit baud rate, 8 possible receive

baud rates

• Software selectable word length (eight or nine bits)

• Separate transmitter and receiver enable bits

• Capable of being interrupt driven

• Transmitter clocks available without altering the regular transmitter or receiver functions

• Four separate enable bits for interrupt control

TPG

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

MOTOROLA

6-2 MC68HC05B6

Rev. 4

SERIAL COMMUNICATIONS INTERFACE

Figure 6-1 Serial communications interface block diagram

& & & &

Internal bus

SCI interrupt

Transmit Receive

TDO

pin RDI

Transmitter

control Receiver

control

clock

Clock extraction

phase and

polarity control

Receiver

clock

Transmitter

Flag

control

data register data register

TIE

TCIE

RIE

ILIE

SBK

RWU

$000F

SCCR2

SCSR

$0010

SCCR1

$000E

TRDE TC RDRF IDLE OR NF FE

TE SBK

$0011

(See note) (See note)

R8 T8 M WAKE CPOL CPHA LBCL

012

765 2

SCLK

Wake up

unit

Receive

data shift

Transmit

data shift

$0011

Note: The serial communications data register (SCI SCDR) is controlled by the internal

R/W signal. It is the transmit data register when written to and the receive data

TPG

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

6-3

SERIAL COMMUNICATIONS INTERFACE

6.2 SCI receiver features

• Receiver wake-up function (idle line or address bit)

• Idle line detection

• Framing error detection

• Noise detection

• Overrun detection

• Receiver data register full ﬂag

6.3 SCI transmitter features

• Transmit data register empty ﬂag

• Transmit complete ﬂag

• Send break

6.4 Functional description

A bloc k diag r am of the SCI is sho wn in Figure 6-1. Option bits in serial control register1 (SCCR1)

select the ‘w ak e-up’ method (W AKE bit) and data w ord length (M-bit) of the SCI. SCCR2 provides

control bits that individually enable the transmitter and receiver, enable system interrupts and

provide the w ake-up enab le bit (RWU) and the send break code bit (SBK). Control bits in the baud

rate register (BAUD) allo w the user to select one of 32 different baud rates for the transmitter and

receiver (see Section 6.11.5).

Data transmission is initiated by writing to the serial communications data register (SCDR).

Provided the transmitter is enabled, data stored in the SCDR is transferred to the transmit data

shift register. This transfer of data sets the transmit data register empty ﬂag (TDRE) in the SCI

status register (SCSR) and generates an interrupt (if transmitter interrupts are enabled). The

transfer of data to the transmit data shift register is synchronized with the bit rate clock (see

Figure 6-2). All data is tr ansmitted least signiﬁcant bit ﬁrst. Upon completion of data tr ansmission,

the transmission complete ﬂag (TC) in the SCSR is set (provided no pending data, preamble or

break is to be sent) and an interrupt is generated (if the transmit complete interrupt is enabled). If

the transmitter is disab led, and the data, preamble or break (in the transmit data shift register) has

been sent, the TC bit will also be set. This will also generate an interrupt if the transmission

complete interrupt enable bit (TCIE) is set. If the tr ansmitter is disab led during a transmission, the

character being transmitted will be completed before the transmitter gives up control of the

TDO pin.

TPG

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6-4 MC68HC05B6

Rev. 4

SERIAL COMMUNICATIONS INTERFACE

When SCDR is read, it contains the last data byte receiv ed, pro vided that the receiv er is enab led.

The receive data register full ﬂag bit (RDRF) in the SCSR is set to indicate that a data byte has

been transferred from the input serial shift register to the SCDR; this will cause an interrupt if the

receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is

synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error

ﬂags in the SCSR may be set if data reception errors occurred.

An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects

idle line transmission) in SCSR is set. This allows a receiver that is not in the wake-up mode to

detect the end of a message or the preamble of a new message, or to resynchronize with the

transmitter . A valid character m ust be received bef ore the idle line condition or the IDLE bit will not

be set and idle line interrupt will not be generated.

The SCP0 and SCP1 bits function as a prescaler f or SCR0–SCR2 to generate the receiv er baud rate

and f or SCT0–SCT2 to generate the transmitter baud rate . Together , these eight bits provide multiple

transmitter/receiver rate combinations for a given crystal frequency (see Figure 6-2). This register

should only be written to while both the transmitter and receiver are disab led (TE=0, RE=0).

Figure 6-2 SCI rate generator division

SCP1 SPC0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

Internal processor clock

SCP0 – SCP1

prescaler

rate control

(÷ NP)

SCR0 – SCR2

receiver

(÷ NR)

SCT0 – SCT2

transmitter

rate control

(÷ NT)

÷16

Transmitter clock Receiver clock

rate control

76543210

$000D

Baud rate register

Note: There is a ﬁxed rate divide-by-16 before the transmitter to compensate for the inherent divide-by-16 of the receiver (sampling)

This means that by loading the same value for both the transmitter and receiver baud r ate selector, the same baud rates can be

obtained.

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

6-5

SERIAL COMMUNICATIONS INTERFACE

6.5 Data format

Receive data or tr ansmit data is the serial data that is transf erred to the internal data bus from the

receive data input pin (RDI) or from the internal bus to the transmit data output pin (TDO). The

non-return-to-zero (NRZ) data format shown in Figure 6-3 is used and must meet the following

criteria:

– The idle line is brought to a logic one state prior to transmission/reception of

a character.

– A start bit (logic zero) is used to indicate the start of a frame.

– The data is transmitted and received least signiﬁcant bit ﬁrst.

– A stop bit (logic one) is used to indicate the end of a frame. A frame consists

of a start bit, a character of eight or nine data bits, and a stop bit.

– A break is deﬁned as the transmission or reception of a low (logic z ero) for at

least one complete frame time (10 zeros for 8-bit f ormat, 11 zeros f or 9-bit).

6.6 Receiver wake-up operation

The receiver logic hardware also supports a receiver wake-up function which is intended for

systems having more than one receiv er. With this function a transmitting device directs messages

to an individual receiver or group of receivers by passing addressing information as the initial

byte(s) of each message. The wake-up function allows receivers not addressed to remain in a

dormant state for the remainder of the unwanted message. This eliminates any fur ther software

overhead to service the remaining characters of the unwanted message and thus improves system

performance.

The receiver is placed in wake-up mode by setting the receiver wake-up bit (RWU) in the SCCR2

are inhibited (cannot become set). Note that the idle line detect function is inhibited while the R WU

bit is set. Although RWU ma y be cleared by a software write to SCCR2, it would be unusual to do

so. Normally RWU is set by software and is cleared automatically in hardware by one of the two

methods described below.

Figure 6-3 Data format

StartStop

Control bit M selects

8 or 9 bit data

Start

Idle line 012345678







TPG

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6-6 MC68HC05B6

Rev. 4

SERIAL COMMUNICATIONS INTERFACE

6.6.1 Idle line wake-up

In idle line wak e-up mode, a dormant receiver w akes up as soon as the RDI line becomes idle. Idle

is deﬁned as a continuous logic high le v el on the RDI line for ten (or ele v en) full bit times . Systems

using this type of wake-up must provide at least one character time of idle between messages to

wake up sleeping receivers, but must not allow any idle time between characters within a message.

6.6.2 Address mark wake-up

In address mark wake-up , the most signiﬁcant bit (MSB) in a character is used to indicate whether

it is an address (1) or data (0) character. Sleeping receivers will wake up whenever an address

character is received. Systems using this method for wake-up would set the MSB of the ﬁrst

character of each message and lea v e it clear for all other characters in the message. Idle periods

ma y be present within messages and no idle time is required between messages f or this wak e-up

method.

6.7 Receive data in (RDI)

Receive data is the serial data that is applied through the input line and the SCI to the internal bus.

The receiver circuitry clocks the input at a rate equal to 16 times the baud r ate. This time is referred

to as the RT rate in Figure 6-4 and as the receiver clock in Figure 6-2.

The receiver clock generator is controlled by the baud rate register, as shown in Figure 6-1 and

Figure 6-2; however, the SCI is synchronized by the start bit, independent of the transmitter.

Once a valid start bit is detected, the star t bit, each data bit and the stop bit are sampled three

times at R T intervals 8 R T, 9 RT and 10 R T (1 R T is the position where the bit is expected to start),

as shown in Figure 6-5. The value of the bit is determined by voting logic which tak es the value of

the majority of the samples. A noise ﬂag is set when all three samples on a valid star t bit or data

bit or the stop bit do not agree.

6.8 Start bit detection

When the input (idle) line is detected low, it is tested for three more sample times (referred to as

the start edge veriﬁcation samples in Figure 6-4). If at least two of these three v eriﬁcation samples

detect a logic zero, a valid start bit has been detected, otherwise the line is assumed to be idle. A

noise ﬂag is set if one of the three veriﬁcation samples detect a logic one, thus a v alid start bit could

be assumed with a set noise ﬂag present.

TPG

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Rev. 4 MOTOROLA

6-7

SERIAL COMMUNICATIONS INTERFACE

If there has been a framing error without detection of a break (10 zeros f or 8 bit f ormat or 11 zeros

for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the star t

edge will be placed ar tiﬁcially. The last bit received in the data shift register is inverted to a logic

one, and the three logic one start qualiﬁers (shown in Figure 6-4) are forced into the sample shift

the start bit will be accepted no sooner than it is anticipated.

Figure 6-4 SCI examples of start bit sampling technique

Figure 6-5 SCI sampling technique used on all bits

111 111 111110000

1RT 2RT 3RT 5RT 7RT4RT 6RT 8RT

Start

qualiﬁers

Idle

Start edge

veriﬁcation samples

16X internal sampling clock

RT clock edges for all three examples

Noise

Start

111 111 1110 1 0000

111 111 1111 1 0010

Start

Noise

RDI

SamplesPresent bit Next bitPrevious bit

16RT1RT 8RT 9RT 10RT 16RT1RT

RDI

TPG

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6-8 MC68HC05B6

Rev. 4

SERIAL COMMUNICATIONS INTERFACE

If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $0000) produced

the framing error, the start bit will not be artiﬁcially induced and the receiver must actually detect

a logic one before the start bit can be recognised (see Figure 6-7).

6.9 Transmit data out (TDO)

Transmit data is the serial data from the inter nal data bus that is applied through the SCI to the

output line. Data format is as discussed in Section 6.5 and shown in Figure 6-3. The transmitter

generates a bit time by using a derivative of the R T clock, thus producing a transmission r ate equal

to 1/16th that of the receiver sample clock (assuming the same baud rate is selected for both the

receiver and transmitter).

Figure 6-6 Artiﬁcial start following a framing error

Figure 6-7 SCI start bit following a break

Data Expected stop

Data samples

Artiﬁcial edge

Start bit

Data

RDI

Data Expected stop

Data samples

Start edge

Start bit

Data

RDI

a) Case 1: receive line low during artiﬁcial edge

b) Case 2: receive line high during expected start edge

Expected stop

Data samples

Detected as valid start edge

Start bit

RDI

Break









Start

qualiﬁers Start edge

veriﬁcation

samples

TPG

05B6Book Page 8 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

6-9

SERIAL COMMUNICATIONS INTERFACE

6.10 SCI synchronous transmission

The SCI transmitter allows the user to control a one way synchronous serial transmission. The

SCLK pin is the clock output of the SCI transmitter. No clocks are sent to that pin during start bit

and stop bit. Depending on the state of the LBCL bit (bit 0 of SCCR1), clocks will or will not be

activated during the last valid data bit (address mark). The CPOL bit (bit 2 of SCCR1) allows the

user to select the clock polarity, and the CPHA bit (bit 1 of SCCR1) allows the user to select the

phase of the external clock (see Figure 6-8, Figure 6-9 and Figure 6-10).

During idle, preamble and send break, the external SCLK clock is not activated.

These options allow the user to serially control peripherals which consist of shift registers, without

losing any functions of the SCI transmitter which can still talk to other SCI receiv ers. These options

do not affect the SCI receiver which is independent of the transmitter.

The SCLK pin works in conjunction with the TDO pin. When the SCI transmitter is disabled

(TE = 0), the SCLK and TDO pins go to the high impedance state.

Note:

The LBCL, CPOL and CPHA bits hav e to be selected bef ore enabling the transmitter to

ensure that the clocks function correctly. These bits should not be changed while the

transmitter is enabled.

Figure 6-8 SCI example of synchronous and asynchronous transmission

RDI

TDO

SCLK

Output port

Data out

Data in

Clock

Enable

Asynchronous

MC68HC05B6

(e.g. Modem)

Synchronous

(e.g. shift register,

display driver, etc.)

TPG

05B6Book Page 9 Tuesday, April 6, 1999 8:24 am

MOTOROLA

6-10 MC68HC05B6

Rev. 4

SERIAL COMMUNICATIONS INTERFACE

6.11 SCI registers

The SCI system is conﬁgured and controlled by ﬁve registers: SCDR, SCCR1, SCCR2, SCSR,

and BAUD.

6.11.1 Serial communications data register (SCDR)

The SCDR is controlled by the internal R/W signal and perfor ms two functions in the SCI. It acts

as the receive data register (RDR) when it is read and as the tr ansmit data register (TDR) when it

is written. Figure 6-1 shows this register as two separate registers, RDR and TDR. The RDR

provides the interf ace from the receiv e shift register to the internal data bus and the TDR pro vides

the parallel interface from the internal data bus to the transmit shift register.

The receive data register is a read-only register containing the last byte of data receiv ed from the

shift register f or the internal data bus. The RDR full bit (RDRF) in the serial communications status

SCDR. The transfer is synchronized with the receiver bit rate clock (from the receiver control) as

shown in Figure 6-1. All data is received with the least signiﬁcant bit ﬁrst.

The transmit data register (TDR) is a write-only register containing the next byte of data to be

applied to the transmit shift register from the internal data bus. As long as the transmitter is

enabled, data stored in the SCDR is tr ansferred to the tr ansmit shift register (after the current byte

in the shift register has been transmitted).

The transfer is synchronized with the transmitter bit rate clock (from the transmitter control) as

shown in Figure 6-1. All data is received with the least signiﬁcant bit ﬁrst.

6.11.2 Serial communications control register 1 (SCCR1)

The SCI control register 1 (SCCR1) contains control bits related to the nine data bit character

format, the receiver wake-up feature and the options to output the transmitter clocks for

synchronous transmissions.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

SCI data (SCDR) $0011 0000 0000

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undeﬁned

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

6-11

SERIAL COMMUNICATIONS INTERFACE

R8 — Receive data bit 8

This read-only bit is the ninth serial data bit received when the SCI system is conﬁgured for nine

data bit operation (M = 1). The most signiﬁcant bit (bit 8) of the received character is transferred

into this bit at the same time as the remaining eight bits (bits 0–7) are transferred from the serial

receive shifter to the SCI receive data register.

T8 — Transmit data bit 8

This read/write bit is the ninth data bit to be transmitted when the SCI system is conﬁgured for nine

data bit operation (M = 1). When the eight low order bits (bits 0–7) of a transmit character are

transferred from the SCI data register to the serial transmit shift register, this bit (bit 8) is transferred

to the ninth bit position of the shifter.

M — Mode (select character format)

The read/write M-bit controls the character length for both the tr ansmitter and receiver at the same

time. The 9th data bit is most commonly used as an extr a stop bit or it can also be used as a parity

bit (see Table 6-1).

1 (set) – Start bit, 9 data bits, 1 stop bit.

0 (clear) – Start bit, 8 data bits, 1 stop bit.

WAKE — Wake-up mode select

This bit allows the user to select the method for receiver wake-up. The WAKE bit can be read or

written to any time. See Table 6-1.

1 (set) – W ak e-up on address mark; if R WU is set, SCI will w ak e-up if the 8th

(if M=0) or 9th (if M=1) bit received on the Rx line is set.

0 (clear) – W ake-up on idle line; if RWU is set, SCI will w ake-up after 11 (if M=0)

or 12 (if M=1) consecutive ‘1’s on the Rx line.

Table 6-1 Method of receiver wake-up

WAKE M Method of receiver wake-up

Detection of an idle line allows the next data type received to cause the receive

data register to ﬁll and produce an RDRF ﬂag.

Detection of a received one in the eighth data bit allows an RDRF ﬂag and

associated error ﬂags.

Detection of a received one in the ninth data bit allows an RDRF ﬂag and

associated error ﬂags.

x = Don’t care

TPG

05B6Book Page 11 Tuesday, April 6, 1999 8:24 am

MOTOROLA

6-12 MC68HC05B6

Rev. 4

SERIAL COMMUNICATIONS INTERFACE

CPOL – Clock polarity

This bit allows the user to select the polarity of the clocks to be sent to the SCLK pin. It works in

conjunction with the CPHA bit to produce the desired clock-data relation (see Figure 6-9 and

Figure 6-10).

1 (set) – Steady high value at SCLK pin outside transmission window.

0 (clear) – Steady low value at SCLK pin outside transmission window.

This bit should not be manipulated while the transmitter is enabled.

CPHA – Clock phase

This bit allows the user to select the phase of the cloc ks to be sent to the SCLK pin. This bit works

in conjunction with the CPOL bit to produce the desired clock-data relation (see Figure 6-9 and

Figure 6-10).

1 (set) – SCLK clock line activated at beginning of data bit.

0 (clear) – SCLK clock line activated in middle of data bit.

This bit should not be manipulated while the transmitter is enabled.

Figure 6-9 SCI data clock timing diagram (M=0)

Idle or preceding

transmission

clock

Stop

Start

LSB

data

M = 0 (8 data bits) Idle or next

LBCL bit controls last data clock

transmission

clock

Start Stop

0123456

MSB

(CPOL = 0, CPHA = 0)

(CPOL = 0, CPHA = 1)

(CPOL = 1, CPHA = 0)

(CPOL = 1, CPHA = 1)

TPG

05B6Book Page 12 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

6-13

SERIAL COMMUNICATIONS INTERFACE

LBCL – Last bit clock

This bit allows the user to select whether the clock associated with the last data bit transmitted

(MSB) has to be output to the SCLK pin. The clock of the last data bit is output to the SCLK pin if

the LBCL bit is a logic one, and is not output if it is a logic zero.

The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit f ormat selected by M-bit

(seeTable 6-2).

This bit should not be manipulated while the transmitter is enabled.

Figure 6-10 SCI data clock timing diagram (M=1)

Table 6-2 SCI clock on SCLK pin

Data format M-bit LBCL bit Number of clocks on

SCLK pin

8 bit 0 0 7

8 bit 0 1 8

9 bit 1 0 8

9 bit 1 1 9

Idle or preceding

transmission

clock

StopStart

LSB

data

M = 1 (9 data bits) Idle or next

LBCL bit controls last data clock

transmission

clock

Start Stop

0123456

MSB

(CPOL = 0, CPHA = 0)

(CPOL = 0, CPHA = 1)

(CPOL = 1, CPHA = 0)

(CPOL = 1, CPHA = 1)

TPG

05B6Book Page 13 Tuesday, April 6, 1999 8:24 am

MOTOROLA

6-14 MC68HC05B6

Rev. 4

SERIAL COMMUNICATIONS INTERFACE

6.11.3 Serial communications control register 2 (SCCR2)

The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI

functions.

TIE — Transmit interrupt enable

1 (set) – TDRE interrupts enabled.

0 (clear) – TDRE interrupts disabled.

TCIE — Transmit complete interrupt enable

1 (set) – TC interrupts enabled.

0 (clear) – TC interrupts disabled.

RIE — Receiver interrupt enable

1 (set) – RDRF and OR interrupts enabled.

0 (clear) – RDRF and OR interrupts disabled.

ILIE — Idle line interrupt enable

1 (set) – IDLE interrupts enabled.

0 (clear) – IDLE interrupts disabled.

TE — Transmitter enable

When the transmit enab le bit is set, the transmit shift register output is applied to the TDO line and

the corresponding clocks are applied to the SCLK pin. Depending on the state of control bit M

(SCCR1), a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones is transmitted when software

sets the TE bit from a cleared state.

If a transmission is in progress and a zero is written to TE, the transmitter will wait until after the

present byte has been transmitted before placing the TDO and the SCLK pin in the idle, high

impedance state.

If the TE bit has been written to a zero and then set to a one bef ore the current byte is tr ansmitted,

the transmitter will wait for that byte to be transmitted and will then initiate transmission of a new

preamble. After this latest transmission, and provided the TDRE bit is set (no new data to transmit),

the line remains idle (driven high while TE = 1); otherwise, normal transmission occurs. This

function allows the user to neatly terminate a transmission sequence.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

SCI control (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

TPG

05B6Book Page 14 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

6-15

SERIAL COMMUNICATIONS INTERFACE

After loading the last byte in the serial communications data register and receiving the TDRE ﬂag,

the user should clear TE. Transmission of the last byte will then be completed and the line will go

idle.

1 (set) – Transmitter enabled.

0 (clear) – Transmitter disabled.

RE — Receiver enable

1 (set) – Receiver enabled.

0 (clear) – Receiver disabled.

When RE is clear (receiver disabled) all the status bits associated with the receiv er (RDRF, IDLE,

OR, NF and FE) are inhibited.

RWU — Receiver wake-up

When the receiver w ake-up bit is set b y the user software, it puts the receiv er to sleep and enables

the wake-up function. The type of wake-up mode for the receiver is deter mined by the WAKE bit

discussed abov e (in the SCCR1). When the R WU bit is set, no status ﬂags will be set. Flags which

were set previously will not be cleared when RWU is set.

If the WAKE bit is cleared, R WU is cleared b y the SCI logic after receiving 10 (M = 0) or 11 (M =1)

consecutive ones . Under these conditions, R WU cannot be set if the line is idle. If the WAKE bit is

set, R WU is cleared after receiving an address bit. The RDRF ﬂag will then be set and the address

byte stored in the receiver data register.

SBK — Send break

If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11 (M = 1) zeros

and then reverts to idle sending data. If SBK remains set, the transmitter will continually send

whole blocks of zeros (sets of 10 or 11) until cleared. At the completion of the break code, the

transmitter sends at least one high bit to guarantee recognition of a valid start bit.

TPG

05B6Book Page 15 Tuesday, April 6, 1999 8:24 am

MOTOROLA

6-16 MC68HC05B6

Rev. 4

SERIAL COMMUNICATIONS INTERFACE

6.11.4 Serial communications status register (SCSR)

The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for

generation of the SCI system interrupt. In addition, a noise ﬂag bit and a framing error bit are also

contained in the SCSR.

TDRE — Transmit data register empty ﬂag

This bit is set when the contents of the transmit data register are transferred to the serial shift

transmit data register to clear the TDRE ﬂag.

If the TDRE bit is clear , this indicates that the transf er has not yet occurred and a write to the serial

communications data register will overwrite the previous value. The TDRE bit is cleared by

accessing the serial communications status register (with TDRE set) followed by writing to the

serial communications data register.

TC — Transmit complete ﬂag

This bit is set to indicate that the SCI transmitter has no meaningful information to transmit (no data

in shifter, no preamble, no break). When TC is set the ser ial line will go idle (continuous MARK).

The TC bit is cleared by accessing the serial communications status register (with TC set) followed

by writing to the serial communications data register. It does not inhibit the transmitter function in

any way.

RDRF — Receive data register full ﬂag

This bit is set when the contents of the receiver serial shift register are transferred to the receiver

data register.

If multiple errors are detected in any one received word, the NF and RDRF bits will be affected as

appropriate during the same clock cycle . The RDRF bit is cleared when the serial communications

status register is accessed (with RDRF set) f ollo wed by a read of the serial communications data

IDLE — Idle line detected ﬂag

This bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven

consecutive “1”s). This bit will not be set by the idle line condition when the RWU bit is set. This

allows a receiver that is not in the wake-up mode to detect the end of a message, detect the

preamble of a new message or resynchronize with the transmitter. The IDLE bit is cleared by

accessing the serial communications status register (with IDLE set) follo wed by a read of the serial

communications data register . Once cleared, IDLE will not be set again until after RDRF has been

set, (i.e. until after the line has been active and becomes idle again).

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

TPG

05B6Book Page 16 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

6-17

SERIAL COMMUNICATIONS INTERFACE

OR — Overrun error ﬂag

This bit is set when a new byte is ready to be transferred from the receiver shift register to the

receiver data register and the receive data register is already full (RDRF bit is set). Data transfer

is inhibited until the RDRF bit is cleared. Data in the serial communications data register is v alid in

this case, b ut additional data receiv ed during an ov errun condition (including the byte causing the

overrun) will be lost.

The OR bit is cleared when the serial communications status register is accessed (with OR set)

followed by a read of the serial communications data register.

NF — Noise error ﬂag

This bit is set if there is noise on a ‘v alid’ start bit, any of the data bits or on the stop bit. The NF bit

is not set by noise on the idle line nor b y inv alid start bits. If there is noise, the NF bit is not set until

the RDRF ﬂag is set. Each data bit is sampled three times as described in Section 6.7.

The NF bit represents the status of the byte in the serial communications data register . For the b yte

being received (shifted in) there will be also a ‘working’ noise ﬂag, the value of which will be

transferred to the NF bit when the serial data is loaded into the serial communications data

be used to generate the interrupt.

The NF bit is cleared when the serial communications status register is accessed (with NF set)

followed by a read of the serial communications data register.

FE — Framing error ﬂag

This bit is set when the word boundaries in the bit stream are not synchronized with the receiver

bit counter (generated b y the reception of a logic z ero bit where a stop bit was e xpected). The FE

bit reﬂects the status of the byte in the receiv e data register and the transfer from the receive shifter

to the receive data register is inhibited by an overrun. The FE bit is set during the same cycle as

the RDRF bit but does not get set in the case of an overrun (OR). The framing error ﬂag inhibits

further transfer of data into the receive data register until it is cleared.

The FE bit is cleared when the serial communications status register is accessed (with FE set)

followed by a read of the serial communications data register.

TPG

05B6Book Page 17 Tuesday, April 6, 1999 8:24 am

MOTOROLA

6-18 MC68HC05B6

Rev. 4

SERIAL COMMUNICATIONS INTERFACE

6.11.5 Baud rate register (BAUD)

The baud rate register provides the means to select two different or equivalent baud rates for the

transmitter and receiver.

SCP1, SCP0 — Serial prescaler select bits

These read/write bits deter mine the prescale factor, NP, by which the inter nal processor clock is

divided before it is applied to the transmitter and receiver rate control dividers, NT and NR. This

common prescaled output is used as the input to a divider that is controlled by the SCR0–SCR2

bits for the SCI receiver, and by the SCT0–SCT2 bits for the transmitter.

SCT2, SCT1,SCT0 — SCI rate select bits (transmitter)

These three read/write bits select the baud rates for the transmitter . The prescaler output is divided

by the factors shown in Table 6-4.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

SCI baud rate (BAUD) $000D SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 00uu uuuu

Table 6-3 First prescaler stage

SCP1 SCP0 Prescaler

division ratio (NP)

00 1

01 3

10 4

11 13

Table 6-4 Second prescaler stage (transmitter)

SCT2 SCT1 SCT0 Transmitter

division ratio (NT)

000 1

001 2

010 4

011 8

100 16

101 32

110 64

111 128

TPG

05B6Book Page 18 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

6-19

SERIAL COMMUNICATIONS INTERFACE

SCR2, SCR1, SCR0 — SCI rate select bits (receiver)

These three read/write bits select the baud rates for the receiver. The prescaler output described

above is divided by the factors shown in Table 6-5.

The following equations are used to calculate the receiver and transmitter baud rates:

where:

NP = prescaler divide ratio

NT = transmitter baud rate divide ratio

NR = receiver baud rate divide ratio

baudTx = transmitter baud rate

baudRx = receiver baud rate

fOSC = oscillator frequency

6.12 Baud rate selection

The ﬂexibility of the baud rate generator allows many different baud rates to be selected. A

particular baud rate ma y be gener ated in sev er al w ays b y manipulating the various prescaler and

division ratio bits. Table 6-6 shows the baud rates that can be achieved, for ﬁve typical crystal

frequencies. These are effectively the highest baud rates which can be achieved using a given

crystal.

Table 6-5 Second prescaler stage (receiver)

SCR2 SCR1 SCR0 Receiver

division ratio (NR)

000 1

001 2

010 4

011 8

100 16

101 32

110 64

111 128

baudTx fop

16 NP NT••

-----------------------------------

baudRx fop

16 NP NR••

-----------------------------------

TPG

05B6Book Page 19 Tuesday, April 6, 1999 8:24 am

MOTOROLA

6-20 MC68HC05B6

Rev. 4

SERIAL COMMUNICATIONS INTERFACE

Note:

The e xamples shown abo v e do not apply when the part is operating in slow mode (see

Section 2.4.3).

Table 6-6 SCI baud rate selection

Crystal frequency – fOSC (MHz)

SCP1 SCP0 SCT/R2 SCT/R1 SCT/R0 NP NT/NR 4.194304 4.00 2.4576 2.00 1.8432

0000011131072 125000 76800 62500 57600

000011265536 62500 38400 31250 28800

000101432768 31250 19200 15625 14400

000111816384 15625 9600 7813 7200

001001168192 7813 4800 3906 3600

001011324096 3906 2400 1953 1800

001101642048 1953 1200 977 900

0011111281024 977 600 488 450

010003143691 41667 25600 20833 19200

010013221845 20833 12800 10417 9600

010103410923 10417 6400 5208 4800

01011385461 5208 3200 2604 2400

011003162731 2604 1600 1302 1200

011013321365 1302 800 651 600

01110364683651400326300

011113128341326200163150

100004132768 31250 19200 15625 14400

100014216384 15625 9600 7813 7200

10010448192 7813 4800 3906 3600

10011484096 3906 2400 1953 1800

101004162048 1953 1200 977 900

101014321024 977 600 488 450

10110464512488300244225

101114128256244150122113

1100013110082 9615 5908 4808 4431

110011325041 4808 2954 2404 2215

110101342521 2404 1477 1202 1108

110111381260 1202 738 601 554

111001316630601369300277

111011332315300185150138

11110136415815092 75 69

111111312879 75 46 38 35

TPG

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6-21

SERIAL COMMUNICATIONS INTERFACE

6.13 SCI during STOP mode

When the MCU enters STOP mode, the baud rate generator driving the receiver and transmitter

is shut down. This stops all SCI activity . Both the receiver and the transmitter are unable to operate.

If the STOP instruction is executed during a transmitter transfer , that transfer is halted. When STOP

mode is exited as a result of an external interrupt, that particular transmission resumes.

If the receiver is receiving data when the STOP instruction is e xecuted, receiv ed data sampling is

stopped (baud generator stops) and the rest of the data is lost.

Warning: F or the abo ve reasons, all SCI tr ansactions should be in the idle state when the STOP

instruction is executed.

6.14 SCI during WAIT mode

The SCI system is not affected by WAIT mode and continues normal operation. Any valid SCI

interrupt will wake-up the system. If required, the SCI system can be disabled prior to entering

WAIT mode by writing a zero to the transmitter and receiver enable bits in the serial communication

control register 2 at $000F. This action will result in a reduction of po wer consumption during W AIT

mode.

TPG

05B6Book Page 21 Tuesday, April 6, 1999 8:24 am

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6-22 MC68HC05B6

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SERIAL COMMUNICATIONS INTERFACE

THIS PAGE LEFT BLANK INTENTIONALLY

TPG

05B6Book Page 22 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

7-1

PULSE LENGTH D/A CONVERTERS

The pulse length D/A conver ter (PLM) system wor ks in conjunction with the timer to execute two

8-bit D/A conversions, with a choice of two repetition rates. (See Figure 7-1.)

Figure 7-1 PLM system block diagram

PLMA

PLMB

‘A’ register

buffer ‘B’ register

‘A’

comparator ‘B’

Latch

Zero detector

SFA bit

SFB

D/A

Timer bus From timer

Data bus

multiplexer

‘A’ ‘B’

buffer

comparator

multiplexer

PLMA

PLMB

D/A R

bit

Zero detector

Latch

TPG

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

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7-2 MC68HC05B6

Rev. 4

PULSE LENGTH D/A CONVERTERS

The D/A converter has two data registers associated with it, PLMA and PLMB.

This is a dual 8-bit resolution D/A conver ter associated with two output pins (PLMA and PLMB).

The outputs are pulse length modulated signals whose duty cycle ratio may be modiﬁed. These

signals can be used directly as PLMs, or the ﬁltered average may be used as general pur pose

analog outputs.

The longest repetition period is 4096 times the programmable timer clock period (CPU clock

multiplied by four), and the shortest repetition per iod is 256 times the programmable timer clock

period (the repetition rate frequencies for a 4 MHz crystal are 122 Hz and 1953 Hz respectively).

Registers PLMA ($0A) and PLMB ($0B) are associated with the pulse length values of the two

counters. A value of $00 loaded into these registers results in a continuously low output on the

corresponding D/A output pin. A v alue of $80 results in a 50% duty cycle output, and so on, to the

maximum value $FF corresponding to an output which is at ‘1’ for 255/256 of the cycle. When the

MCU makes a write to register PLMA or PLMB the new value will only be picked up by the D/A

conv erters at the end of a complete cycle of conversion. This results in a monotonic change of the

DC component at the output without ov ershoots or vicious starts (a vicious start is an output which

gives totally erroneous PLM during the period immediately following an update of the PLM D/A

registers). This feature is achieved by double buffering of the PLM D/A registers. Examples of

PWM output waveforms are shown in Figure 7-2.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Figure 7-2 PLM output waveform examples

256 T

255 T

128 T

$80

$FF

T = 4 CPU clocks in fast mode and 64 CPU clocks in slow mode

128 T

$00

$01

255 T

TPG

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Rev. 4 MOTOROLA

7-3

PULSE LENGTH D/A CONVERTERS

Note:

Since the PLM system uses the timer counter, PLM results will be affected while resetting

the timer counter. Both D/A registers are reset to $00 dur ing power-on or external reset.

WAIT mode does not aff ect the output w a v eform of the D/A conv erters.

7.1 Miscellaneous register

SFA — Slow or fast mode selection for PLMA

This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation output.

1 (set) – Slow mode PLMA (4096 x timer clock period).

0 (clear) – Fast mode PLMA (256 x timer clock period).

SFB — Slow or fast mode selection for PLMB

This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation output.

1 (set) – Slow mode PLMB (4096 x timer clock period).

0 (clear) – Fast mode PLMB (256 x timer clock period).

The highest speed of the PLM system corresponds to the frequency of the TOF bit being set,

multiplied by 256. The lowest speed of the PLM system corresponds to the frequency of the TOF

bit being set, multiplied by 16. Because the SFA bit and SFB bit are not double buffered, it is

mandatory to set them to the desired values bef ore writing to the PLM registers; not doing so could

temporarily give incorrect values at the PLM outputs.

SM — Slow mode

1 (set) – The system runs at a bus speed 16 times lower than normal

(fOSC/32). SLOW mode affects all sections of the device, including

SCI, A/D and timer.

0 (clear) – The system runs at normal bus speed (fOSC/2).

The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when

entering STOP mode.

Note:

The bits that are shown shaded in the above representation are explained individually

in the relevant sections of this manual. The complete register plus an explanation of

each bit can be found in Section 3.8

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Miscellaneous $000C POR INTP INTN INTE SFA SFB SM WDOG ?001 000?

TPG

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7-4 MC68HC05B6

Rev. 4

PULSE LENGTH D/A CONVERTERS

7.2 PLM clock selection

The slow/f ast mode of the PLM D/A con verters is selected by bits 1, 2, and 3 of the miscellaneous

effect on the D/A converters’ 8-bit resolution (see Figure 7-3).

7.3 PLM during STOP mode

On entering STOP mode, the PLM outputs remain at their par ticular level. When STOP mode is

exited by an interrupt, the PLM systems resume regular operation. If STOP mode is exited by

power-on or external reset the registers values are forced to $00.

7.4 PLM during WAIT mode

The PLM system is not affected by WAIT mode and continues normal operation.

Figure 7-3 PLM clock selection

fOSC ÷2

÷32

SM bit = 0

SM bit = 1

÷4 x4096

x256

SF bit = 1

SF bit = 0

Timer

clock PLM

clock

Bus

frequency (fOP)

TPG

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Rev. 4 MOTOROLA

8-1

ANALOG TO DIGITAL CONVERTER

The analog to digital converter system consists of a single 8-bit successive approximation

converter and a sixteen channel multiplexer. Eight of the channels are connected to the

PD0/AN0 – PD7/AN7 pins of the MC68HC05B6 and the other eight channels are dedicated to

internal reference points f or test functions . The channel input pins do not ha ve any internal output

driver circuitry connected to them because such circuitry would load the analog input signals due

to output buff er leakage current. There is one 8-bit result data register (address $08) and one 8-bit

status/control register (address $09).

The A/D conver ter is ratiometric and two dedicated pins, VRH and VRL, are used to supply the

reference voltage levels for all analog inputs. These pins are used in preference to the system

power supply lines because any voltage drops in the bonding wires of the heavily loaded supply

pins could degrade the accuracy of the A/D conversion. An input voltage equal to or greater than

VRH converts to $FF (full scale) with no overﬂow indication and an input voltage equal to VRL

converts to $00.

The A/D converter can operate from either the bus clock or an internal RC type oscillator. The

internal RC type oscillator is activated by the ADRC bit in the A/D status/control register (ADSTAT)

and can be used to give a sufﬁciently high cloc k rate to the A/D con verter when the bus speed is too

low to provide accurate results. When the A/D converter is not being used it can be disconnected,

by clearing the ADON bit in the ADSTAT register, in order to save power (see Section 8.2.3).

For further information on A/D converter operation please refer to the M68HC11 Reference

Manual — M68HC11RM/AD.

8.1 A/D converter operation

The A/D converter consists of an analog multiple xer, an 8-bit digital to analog converter capacitor

array, a comparator and a successive approximation register (SAR) (see Figure 8-1).

There are eleven options that can be selected by the multiplexer; AN0–AN7, VRH, (VRH+VRL)/2

or VRL. Selection is done via the CHx bits in the ADSTAT register (see Section 8.2.3). AN0–AN7

are the only input points f or A/D conversion oper ations; the others are reference points that can be

used for test purposes.

TPG

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8-2 MC68HC05B6

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ANALOG TO DIGITAL CONVERTER

The A/D ref erence input (AN0–AN7) is applied to a precision internal D/A converter. Control logic

drives this D/A converter and the analog output is successively compared with the analog input

sampled at the beginning of the conversion. The conversion is monotonic with no missing codes.

The result of each successive comparison is stored in the SAR and, when the conversion is

complete, the contents of the SAR are transferred to the read-only result data register ($08), and

the conversion complete ﬂag, COCO, is set in the A/D status/control register ($09).

Warning: Any write to the A/D status/control register will abor t the current conversion, reset the

conversion complete ﬂag and start a new conversion on the selected channel.

At power-on or e xternal reset, both the ADRC and ADON bits are cleared; thus the A/D is disabled.

Figure 8-1 A/D converter block diagram

AN0

VRH

(VRH+VRL)/2

VRL

Analog MUX

A/D result register (ADDATA) $08

8-bit capacitive DAC

with sample and hold

VRH

VRL

Result

A/D status/control register (ADSTAT)$09

(Channel assignment)

COCO

ADRCADON0CH3CH2CH1CH0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

Successive approximation

TPG

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8-3

ANALOG TO DIGITAL CONVERTER

8.2 A/D registers

8.2.1 Port D data register (PORTD)

Por t D is an input-only por t which routes the eight analog inputs to the A/D conver ter. When the

A/D converter is disabled, the pins are conﬁgured as standard input-only port pins, which can be

read via the port D data register.

Note:

When the A/D function is enabled, pins PD0–PD7 will act as analog inputs . Using a pin

or pins as A/D inputs does not aff ect the ability to read port D as static inputs; ho we v er ,

reading port D during an A/D conversion sequence may inject noise on the analog

inputs and result in reduced accuracy of the A/D result.

Performing a digital read of por t D with levels other than VDD or VSS on the pins will

result in greater power dissipation during the read cycle, and may give unpredictable

results on the corresponding port D pins.

8.2.2 A/D result data register (ADDATA)

ADDATA is a read-only register which is used to store the results of A/D conversions. Each result

is loaded into the register from the SAR and the conv ersion complete ﬂag, COCO, in the ADSTAT

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undeﬁned

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

A/D data (ADDATA) $0008 0000 0000

TPG

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ANALOG TO DIGITAL CONVERTER

8.2.3 A/D status/control register (ADSTAT)

COCO — Conversion complete ﬂag

1 (set) – COCO is set each time a conversion is complete, allowing the new

result to be read from the A/D result data register ($08). The

converter then starts a new conversion.

0 (clear) – COCO is cleared by reading the result data register or writing to the

status/control register.

Reset clears the COCO ﬂag.

ADRC — A/D RC oscillator control

The ADRC bit allows the user to control the A/D RC oscillator, which is used to provide a

sufﬁciently high clock rate to the A/D to ensure accuracy when the chip is running at low speeds.

1 (set) – When the ADRC bit is set, the A/D RC oscillator is turned on and, if

ADON is set, the A/D runs from the RC oscillator clock. See Table 8-1.

0 (clear) – When the ADRC bit is cleared, the A/D RC oscillator is turned-off

and, if ADON is set, the A/D runs from the CPU clock.

When the A/D RC oscillator is turned on, it takes a time tADRC to stabilize (see Table 11-6 and

Table 11-7). During this time A/D conversion results may be inaccurate.

Note:

If the MCU bus clock falls below 1MHz, the A/D RC oscillator should be switched on.

Power-on or external reset clears the ADRC bit.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Table 8-1 A/D clock selection

ADRC ADON RC

oscillator A/D

converter Comments

0 0 OFF OFF A/D switched off.

0 1 OFF ON A/D using CPU clock.

1 0 ON OFF Allows the RC oscillator to stabilize.

1 1 ON ON A/D using RC oscillator clock.

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ANALOG TO DIGITAL CONVERTER

ADON — A/D converter on

The ADON bit allows the user to enable/disable the A/D converter.

1 (set) – A/D converter is switched on.

0 (clear) – A/D converter is switched off.

When the A/D conver ter is switched on, it takes a time tADON for the current sources to stabilize

(see Table 11-6 and Table 11-7). Using the A/D converter before this time has elapsed ma y result

in the incorrect operation of the A/D, ev en after tADON has elapsed. In this case ADON would hav e

to be cleared and set again.

Power-on or external reset will clear the ADON bit, thus disabling the A/D converter.

CH3–CH0 — A/D channels 3, 2, 1 and 0

The CH3–CH0 bits allow the user to determine which channel of the A/D converter multiplexer is

selected. See Table 8-2 for channel selection.

Reset clears the CH0–CH3 bits.

Table 8-2 A/D channel assignment

CH3 CH2 CH1 CH0 Channel selected

0000 AN0

0001 AN1

0010 AN2

0011 AN3

0100 AN4

0101 AN5

0110 AN6

0111 AN7

1000 VRH pin (high)

1001(VRH + VRL) / 2

1010 VRL pin (low)

1011 VRL pin (low)

1100 VRL pin (low)

1101 VRL pin (low)

1110 VRL pin (low)

1111 VRL pin (low)

TPG

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ANALOG TO DIGITAL CONVERTER

8.3 A/D converter during STOP mode

When the MCU enters ST OP mode with the A/D conv erter turned on, the A/D clocks are stopped

and the A/D converter is disabled for the duration of STOP mode, including the 4064 cycles

start-up time. If the A/D RC oscillator is in operation it will also be disabled.

8.4 A/D converter during WAIT mode

The A/D converter is not affected by WAIT mode and continues normal operation.

In order to reduce power consumption the A/D converter can be disconnected, under software

control using the ADON bit and the ADRC bit in the A/D status/control register at $0009, before

entering W AIT mode.

8.5 Port D analog input

The e xternal analog voltage v alue to be processed b y the A/D conv erter is sampled on an internal

capacitor through a resistive path, provided by input-selection switches and a sampling aper ture

time switch, as shown in Figure 8-2. Sampling time is limited to 12 bus clock cycles. After sampling,

the analog value is stored on the capacitor and held until the end of conversion. During this hold

time, the analog input is disconnected from the internal A/D system and the external voltage

source sees a high impedance input.

The equivalent analog input during sampling is an RC low-pass ﬁlter with a minimum resistance

of 50 kΩ and a capacitance of at least 10pF. It should be noted that these are typical values

measured at room temperature.

Figure 8-2 Electrical model of an A/D input pin

Analog

input

Input protection device

VRL

< 2pF + ∼20V

- ∼0.7V

1 µA

junction

leakage

≥ 50kΩ

≥ 10pF

DAC

capacitance

Note: The analog switch is closed during the 12 cycle sample time only.

TPG

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9-1

RESETS AND INTERRUPTS

9.1 Resets

The MC68HC05B6 can be reset in three ways: b y the initial power-on reset function, b y an active

low input to the RESET pin or by a computer operating properly (COP) watchdog reset. Any of

these resets will cause the program to go to its starting address, speciﬁed by the contents of

memory locations $1FFE and $1FFF, and cause the interrupt mask bit in the condition code

Figure 9-1 Reset timing diagram

VDD

RESET

1FFF1FFE

1FFE

New

1FFF1FFE1FFE1FFE PC

OSC1

New

Internal

processor clock

1FFE

code

New

PCL

New

PCH

tVDDR

code

New

PCL

New

PCH

address bus

Internal

data bus

tOXOV

tCYC

tPORL

1FFE

Program

execution

begins

Program

execution

begins

tRL(or tDOGL)

(Internal power-on reset) (External hardware reset)

VDD threshold (1-2V typical)

Reset sequence Reset sequence

TPG

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RESETS AND INTERRUPTS

9.1.1 Power-on reset

A power-on reset occurs when a positive transition is detected on VDD. The power-on reset

function is strictly for power turn-on conditions and should not be used to detect drops in the power

supply voltage. The power-on circuitry provides a stabilization delay (tPORL) from when the

oscillator becomes active. If the external RESET pin is low at the end of this delay then the

processor remains in the reset state until RESET goes high. The user must ensure that the voltage

on VDD has risen to a point where the MCU can operate properly by the time tPORL has elapsed.

If there is doubt, the e xternal RESET pin should remain low until the voltage on VDD has reached

the speciﬁed minimum operating v oltage. This may be accomplished by connecting an external RC

circuit to this pin to generate a pow er-on reset (POR). In this case, the time constant must be g reat

enough to allow the oscillator circuit to stabilize.

During power-on reset, the RESET pin is driven lo w during a tPORL delay start-up sequence. tPORL is

deﬁned by a user speciﬁed mask option to be either 16 cycles or 4064 cycles (see Section 1.2).

A software distinction between a power-on reset and an external reset can be made using the POR

bit in the miscellaneous register (see Section 9.1.2).

9.1.2 Miscellaneous register

POR — Power-on reset bit

This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the

user to make a softw are distinction betw een a power-on and an external reset. This bit cannot be

set by software and is cleared by writing it to zero.

1 (set) – A power-on reset has occurred.

0 (clear) – No power-on reset has occurred.

Note:

The bits shown shaded in the above representation are explained individually in the

relevant sections of this manual. The complete register plus an explanation of each bit

can be found in Section 3.8.

(1) The POR bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Miscellaneous $000C POR (1) INTP INTN INTE SFA SFB SM WDOG (2) ?001 000?

TPG

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RESETS AND INTERRUPTS

9.1.3 RESET pin

When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied

to the RESET input f or a minimum period of 1.5 machine cycles (tCYC). An internal Schmitt Trigger

is used to improve noise immunity on this pin. When the RESET pin goes high, the MCU will

resume operation on the following cycle. When a reset condition occurs internally, i.e. from POR

or the COP watchdog, the RESET pin pro vides an active-low open dr ain output signal which may

be used to reset exter nal hardware. Current limitation to protect the pull-down device is provided

in case an RC type external reset circuit is used.

9.1.4 Computer operating properly (COP) watchdog reset

The watchdog counter system consists of a divide-by-8 counter, preceded by a ﬁxed divide-by-4

and a ﬁxed divide-by-256 prescaler, plus control logic as shown in Figure 9-2. The divide-by-8

counter can be reset by software.

Warning: The input to the watchdog system is derived from the carry output of bit 7 of the free

running timer counter. Therefore, a reset of the timer may affect the period of the

watchdog timeout.

The watchdog system can be automatically enabled, following power-on or external reset, via a

mask option (see Section 1.2), or it can be enabled b y software b y writing a ‘1’ to the WDOG bit in

the miscellaneous register at $000C (see Section 9.1.2). Once enabled, the watchdog system

Figure 9-2 Watchdog system block diagram

÷ 256

(Bit 7 of free

fOSC/2

fOSC/32

Main CPU

÷ 8 watchdog

counter

WDOG bit Control logic

Latch

Reset

Schmitt Input

protectiontrigger

Power-on

Enable

Reset

clock

÷ 4

prescaler running counter)

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RESETS AND INTERRUPTS

cannot be disabled by software (writing a ‘zero’ to the WDOG bit has no effect at any time). In

addition, the WDOG bit acts as a reset mechanism for the watchdog counter. Writing a ‘1’ to this

bit clears the counter to its initial value and prevents a watchdog timeout.

WDOG — Watchdog enable/disable

The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.

F ollo wing a w atchdog reset the state of the WDOG bit is as deﬁned b y the mask option speciﬁed.

1 (set) – Watchdog enabled and counter cleared.

0 (clear) – The watchdog cannot be disabled by software; writing a zero to this

bit has no effect.

The divide-by-8 watchdog counter will generate a main reset of the chip when it reaches its ﬁnal

state; seven clocks are necessary to bring the watchdog counter from its clear state to its ﬁnal

state. This reset appears after time tDOG since the last clear or since the enable of the watchdog

counter system. The watchdog counter , theref ore, has to be cleared periodically, b y software , with

a period less than tDOG.

The reset generated b y the w atchdog system is apparent at the RESET pin (see Figure 9-2). The

RESET pin le vel is re-entered in the control logic, and when it has been maintained at level ‘z ero’

for a minimum of tDOGL, the RESET pin is released.

9.1.4.1 COP watchdog during STOP mode

The STOP instruction is inhibited when the watchdog system is enabled. If a STOP instruction is

e x ecuted while the w atchdog system is enabled, then a w atchdog reset will occur as if there w ere

a watchdog timeout. In the case of a watchdog reset due to a STOP instruction, the oscillator will

not be aff ected, thus there will be no tPORL cycles start-up delay. On start-up, the w atchdog will be

conﬁgured according to the user speciﬁed mask option.

9.1.4.2 COP watchdog during WAIT mode

The state of the watchdog during WAIT mode is selected via a mask option (see Section 1.2) to

be one of the options below:

Watchdog enabled — the watchdog counter will continue to operate during W AIT mode and a reset

will occur after time tDOG.

Watchdog disabled — on entering WAIT mode, the watchdog counter system is reset and

disabled. On exiting WAIT mode the counter resumes normal operation.

TPG

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RESETS AND INTERRUPTS

9.1.5 Functions affected by reset

When processing stops within the MCU f or any reason, i.e. power-on reset, e xternal reset or the

execution of a STOP or WAIT instruction, various internal functions of the MCU are affected.

Table 9-1 shows the resulting action of any type of system reset, b ut not necessarily in the order

in which they occur.

Table 9-1 Effect of RESET, POR, STOP and WAIT

Function/effect RESET POR WAIT STOP

Timer prescaler set to zero x x – –

Timer counter set to $FFFC x x – –

All timer enable bits cleared (disable) x x – –

Data direction registers cleared (inputs) x x – –

Stack pointer set to $00FF x x – –

Force internal address bus to restart x x – –

Vector $1FFE, $1FFF x x – –

Interrupt mask bit (I-bit CCR) set to 1 x x – –

Interrupt mask bit (I-bit CCR) cleared – – x x

Set interrupt enable bit (INTE) x x – –

Set POR bit in miscellaneous register – x – –

Reset STOP latch x x – –

Reset IRQ latch x x – –

Reset W AIT latch x x – –

SCI disabled x x – –

SCI status bits cleared (except TDRE and TC) x x – –

SCI interrupt enable bits cleared x x – –

SCI status bits TDRE and TC set x x – –

Oscillator disabled for 4064 cycles –x–x

Timer clock cleared –x–x

SCI clock cleared –x–x

A/D disabled x x – x

SM bit in the miscellaneous register cleared x x – x

Watchdog counter reset xxxx

WDOG bit in the miscellaneous register reset x x – x

EEPROM control bits (see Section 3.5.1) x x – x

x = Described action takes place

– = Described action does not take place

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RESETS AND INTERRUPTS

9.2 Interrupts

The MCU can be interrupted by four different sources: three maskable hardware interrupts and

one non maskable software interrupt:

• External signal on the IRQ pin

• Serial communications interface (SCI)

• Programmable timer

• Software interrupt instruction (SWI)

Interrupts cause the processor to save the register contents on the stack and to set the interrupt

mask (I-bit) to pre vent additional interrupts. The R TI instruction (ReTurn from Interrupt) causes the

e x ecuting the R TI instruction, the value of the I-bit is replaced b y the corresponding I-bit stored on

the stack.

Unlike reset, hardware interrupts do not cause the current instr uction execution to be halted, but

are considered pending until the current instruction is complete. The current instruction is the one

already fetched and being operated on. When the current instruction is complete, the processor

checks all pending hardware interrupts. If interrupts are not masked (I-bit clear) and the

corresponding interrupt enable bit is set, the processor proceeds with interrupt processing;

otherwise, the next instruction is fetched and executed.

Note:

Power-on and external reset clear all interrupt enable bits, but set the INTE bit in the

miscellaneous register, thus preventing interrupts during the reset sequence.

9.2.1 Interrupt priorities

Each potential interrupt source is assigned a priority level, which means that if more than one

interrupt is pending at the same time, the processor will ser vice the one with the highest prior ity

ﬁrst. F or example , if both an external interrupt and a timer interrupt are pending after an instruction

execution, the external interrupt is serviced ﬁrst.

Table 9-2 shows the relative priority of all the possible interrupt sources. Figure 9-3 shows

the interrupt processing ﬂow.

9.2.2 Nonmaskable software interrupt (SWI)

The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt: it is

e xecuted regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI

is executed after interrupts that were pending when the SWI was fetched, but before interrupts

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RESETS AND INTERRUPTS

generated after the SWI was f etched. The SWI interrupt service routine address is speciﬁed by the

contents of memory locations $1FFC and $1FFD.

9.2.3 Maskable hardware interrupts

If the interrupt mask bit in the CCR is set, all maskable interrupts (internal and external) are

masked. Clearing the I-bit allows interrupt processing to occur.

Note:

The internal interrupt latch is cleared in the ﬁrst part of the interrupt service routine;

therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit

is cleared.

9.2.3.1 External interrupt (IRQ)

If the interrupt mask in the condition code register has been cleared and the interr upt enable bit

(INTE) is set and the signal on the exter nal interrupt pin (IRQ) satisﬁes the condition selected by

the option control bits (INTP and INTN), then the e xternal interrupt is recognized. INTE, INTP and

INTN are all bits contained in the miscellaneous register at $000C. When the interrupt is

recognized, the current state of the CPU is pushed onto the stack and the I-bit is set. This masks

fur ther interrupts until the present one is serviced. The external interr upt service routine address

is speciﬁed by the content of memory locations $1FFA and $1FFB.

Table 9-2 Interrupt priorities

Source Register Flags Vector address Priority

Reset — — $1FFE, $1FFF highest

Software interrupt (SWI) — — $1FFC, $1FFD

External interrupt (IRQ) — — $1FFA, $1FFB

Timer input captures TSR ICF1, ICF2 $1FF8, $1FF9

Timer output compares TSR OCF1, OCF2 $1FF6, $1FF7

Timer overﬂow TSR TOF $1FF4, $1FF5

Serial communications

interface (SCI) SCSR TDRE, TC, OR,

RDRF, IDLE $1FF2, $1FF3 lowest

TPG

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RESETS AND INTERRUPTS

Figure 9-3 Interrupt ﬂow chart

Reset

Is I-bit set?

IRQ

external interrupt?

Timer

internal interrupt?

SCI

internal interrupt?

Fetch next

instruction

Execute instruction

Clear IRQ request

latch

Stack

PC, X, A, CC

Set I-bit

Load PC from:

IRQ: $1FFA-$1FFB

Timer IC: $1FF8-$1FF9

Timer OC: $1FF6-$1FF7

Timer O VF:$1FF4-$1FF5

SCI: $1FF2-$1FF3

Complete interrupt routine

and ex ecute RTI

TPG

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RESETS AND INTERRUPTS

9.2.3.2 Miscellaneous register

Note:

The bits shown shaded in the above representation are explained individually in the

relevant sections of this manual. The complete register plus an explanation of each bit

can be found in Section 3.8.

INTP, INTN — External interrupt sensitivity options

These two bits allow the user to select which edge the IRQ pin is sensitive to as shown in Table 9-3.

Both bits can be written to only while the I-bit is set, and are cleared by pow er-on or external reset.

Therefore the device is initialised with negative edge and low level sensitivity.

INTE — External interrupt enable

1 (set) – External interrupt function (IRQ) enabled.

0 (clear) – External interrupt function (IRQ) disabled.

The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,

thus enabling the external interrupt function.

Table 9-3 describes the various triggering options availab le for the IRQ pin, howe ver it is important

to re-emphasize here that in order to a void an y conﬂict and spurious interrupt, it is only possible to

change the external interrupt options while the I-bit is set. Any attempt to change the external

interrupt option while the I-bit is clear will be unsuccessful. If an e xternal interrupt is pending, it will

automatically be cleared when selecting a different interrupt option.

Note:

If the external interrupt function is disabled by the INTE bit and an external interr upt is

sensed by the edge detector circuitry, then the interrupt request is latched and the

interrupt stays pending until the INTE bit is set. The internal latch of the external

interrupt is cleared in the ﬁrst part of the service routine (except for the low level

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Miscellaneous $000C POR INTP INTN INTE SFA SFB SM WDOG ?001 000?

Table 9-3 IRQ sensitivity

INTP INTN IRQ sensitivity

0 0 Negative edge and low level sensitive

0 1 Negative edge only

1 0 Positive edge only

1 1 Positive and negative edge sensitive

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RESETS AND INTERRUPTS

interrupt which is not latched); therefore, only one external interrupt pulse can be

latched during tILIL and serviced as soon as the I-bit is cleared.

9.2.3.3 Timer interrupts

There are ﬁve different timer interrupt ﬂags (ICF1, ICF2, OCF1, OCF2 and TOF) that will cause a

timer interrupt whenever they are set and enabled. These ﬁve interrupt ﬂags are found in the ﬁve

most signiﬁcant bits of the timer status register (TSR) at location $0013. ICF1 and ICF2 will v ector

to the service routine deﬁned by $1FF8-$1FF9, OCF1 and OCF2 will v ector to the service routine

deﬁned by $1FF6–$1FF7 and TOF will vector to the ser vice routine deﬁned by $1FF4–$1FF5 as

shown in Figure 5.1.

There are three corresponding enable bits; ICIE for ICF1 and ICF2, OCIE for OCF1 and OCF2,

and TOIE for TOF. These enable bits are located in the timer control register (TCR) at address

$0012. See Section 5.2.1 and Section 5.2.2 for further information.

9.2.3.4 Serial communications interface (SCI) interrupts

There are ﬁve diff erent interrupt ﬂags (TDRE, TC , OR, RDRF and IDLE) that cause SCI interrupts

whene ver the y are set and enabled. These ﬁv e interrupt ﬂags are found in the ﬁv e most signiﬁcant

bits of the SCI status register (SCSR) at location $0010.

There are f our corresponding enable bits: TIE for TDRE, TCIE for TC, RIE for OR and RDRF, and

ILIE for IDLE. These enable bits are located in the serial communications control register 2

(SCCR2) at address $000F. See Section 6.11.3 and Section 6.11.4.

The SCI interrupt causes the program counter to vector to the address pointed to by memory

locations $1FF2 and $1FF3 which contain the starting address of the interrupt ser vice routine.

Software in the SCI interrupt service routine must determine the priority and cause of the interrupt

by examining the interrupt ﬂags and the status bits located in the serial communications status

The general sequence for clearing an interrupt is a software sequence of accessing the serial

communications status register while the ﬂag is set followed by a read or write of an associated

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RESETS AND INTERRUPTS

9.2.4 Hardware controlled interrupt sequence

The following three functions: reset, STOP and W AIT, are not in the strictest sense interrupts. Howe ver ,

they are acted upon in a similar manner. Flo wcharts f or STOP and WAIT are sho wn in Figure 2.4.

RESET: A reset condition causes the program to vector to its starting address, which is contained

in memory locations $1FFE (MSB) and $1FFF (LSB). The I-bit in the condition code

ST OP: The ST OP instruction causes the oscillator to be turned off and the processor to ‘sleep’

until an external interrupt (IRQ) or occurs or the device is reset.

WAIT: The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks

running. This ‘rest’ state of the processor can be cleared by reset, an external interrupt

(IRQ), a timer interrupt or an SCI interrupt. There are no special WAIT vectors f or these

individual interrupts.

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RESETS AND INTERRUPTS

THIS PAGE LEFT BLANK INTENTIONALLY

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10-1

CPU CORE AND INSTRUCTION SET

This section provides a description of the CPU core registers, the instruction set and the

addressing modes of the MC68HC05B6.

10.1 Registers

The MCU contains ﬁve registers , as shown in the programming model of Figure 10-1. The interrupt

stacking order is shown in Figure 10-2.

Figure 10-1 Programming model

Figure 10-2 Stacking order

Accumulator

Index register

Program counter

Stack pointer

Condition code register

Carry / borrow

Zero

Negative

Interrupt mask

Half carry

15 7 0

000000011

11 1 H I N Z C

Condition code register

Accumulator

Index register

Program counter high

Program counter low

Stack

Unstack

Decreasing

memory

address

Increasing

memory

address

Interrupt

Return

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CPU CORE AND INSTRUCTION SET

10.1.1 Accumulator (A)

The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic

calculations or data manipulations.

10.1.2 Index register (X)

The index register is an 8-bit register, which can contain the indexed addressing value used to

create an effective address. The index register may also be used as a temporary storage area.

10.1.3 Program counter (PC)

The program counter is a 16-bit register , which contains the address of the ne xt byte to be f etched.

10.1.4 Stack pointer (SP)

The stack pointer is a 16-bit register, which contains the address of the next free location on the

stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to

location $00FF. The stack pointer is then decremented as data is pushed onto the stack and

incremented as data is pulled from the stack.

When accessing memory, the ten most signiﬁcant bits are permanently set to 0000000011. These

ten bits are appended to the six least signiﬁcant register bits to produce an address within the

range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64

locations are exceeded, the stack pointer wraps around and overwrites the previously stored

inf ormation. A subroutine call occupies tw o locations on the stack; an interrupt uses ﬁve locations .

10.1.5 Condition code register (CCR)

The CCR is a 5-bit register in which f our bits are used to indicate the results of the instruction just

e xecuted, and the ﬁfth bit indicates whether interrupts are masked. These bits can be individually

tested by a program, and speciﬁc actions can be taken as a result of their state. Each bit is

explained in the following paragraphs.

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CPU CORE AND INSTRUCTION SET

Half carry (H)

This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.

Interrupt (I)

When this bit is set all maskable interrupts are masked. If an interrupt occurs while this bit is set,

the interrupt is latched and remains pending until the interrupt bit is cleared.

Negative (N)

When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was

negative.

Zero (Z)

When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was z ero .

Carry/borrow (C)

When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred

during the last arithmetic operation. This bit is also affected during bit test and branch instructions

and during shifts and rotates.

10.2 Instruction set

The MCU has a set of 62 basic instructions. They can be grouped into ﬁve different types as

follows:

– Register/memory

– Read/modify/write

– Branch

– Bit manipulation

– Control

The following paragraphs brieﬂy explain each type. All the instructions within a given type are

presented in individual tables.

This MCU uses all the instructions available in the M146805 CMOS family plus one more: the

unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents

of the accumulator (A) and the index register (X). The high-order product is then stored in the index

instruction is shown in Table 10-1.

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CPU CORE AND INSTRUCTION SET

10.2.1 Register/memory Instructions

Most of these instructions use two operands. The ﬁrst operand is either the accumulator or the

inde x register . The second operand is obtained from memory using one of the addressing modes.

The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand.

Refer to Table 10-2 for a complete list of register/memory instructions.

10.2.2 Branch instructions

These instructions cause the program to branch if a particular condition is met; otherwise, no

operation is performed. Branch instructions are two-byte instructions. Refer to Table 10-3.

10.2.3 Bit manipulation instructions

The MCU can set or clear any writable bit that resides in the ﬁrst 256 bytes of the memory space

(page 0). All port data and data direction registers, timer and serial interface registers,

control/status registers and a por tion of the on-chip RAM reside in page 0. An additional feature

allows the softw are to test and branch on the state of any bit within these locations . The bit set, bit

clear, bit test and branch functions are all implemented with single instructions. For the test and

branch instructions, the value of the bit tested is also placed in the carry bit of the condition code

10.2.4 Read/modify/write instructions

These instructions read a memory location or a register, modify or test its contents, and write the

modiﬁed value bac k to memory or to the register . The test f or negative or zero (TST) instruction is

an exception to this sequence of reading, modifying and writing, since it does not modify the value.

Refer to Table 10-5 for a complete list of read/modify/write instructions.

10.2.5 Control instructions

These instructions are register reference instructions and are used to control processor operation

during program execution. Refer to Table 10-6 for a complete list of control instructions.

10.2.6 Tables

Tables for all the instruction types listed above follow. In addition there is a complete alphabetical

listing of all the instructions (see Table 10-7 and Table 10-8), and an opcode map for the instruction

set of the M68HC05 MCU family (see Table 10-9).

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10-5

CPU CORE AND INSTRUCTION SET

Table 10-1 MUL instruction

Operation X:A ← X*A

Description Multiplies the eight bits in the index register by the eight

bits in the accumulator and places the 16-bit result in the

concatenated accumulator and index register.

Condition

codes

H : Cleared

I : Not affected

N : Not affected

Z : Not affected

C : Cleared

Source MUL

Form Addressing mode Cycles Bytes Opcode

Inherent 11 1 $42

Table 10-2 Register/memory instructions

Addressing modes

Immediate Direct Extended Indexed

(no

offset)

Indexed

(8-bit

offset)

Indexed

(16-bit

offset)

Function

Mnemonic

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Load A from memory LDA A6 2 2 B6 2 3 C6 3 4 F6 1 3 E6 2 4 D6 3 5

Load X from memory LDX AE 2 2 BE 2 3 CE 3 4 FE 1 3 EE 2 4 DE 3 5

Store A in memory STA B7 2 4 C7 3 5 F7 1 4 E7 2 5 D7 3 6

Store X in memory STX BF 2 4 CF 3 5 FF 1 4 EF 2 5 DF 3 6

Add memory to A ADD AB 2 2 BB 2 3 CB 3 4 FB 1 3 EB 2 4 DB 3 5

Add memory and carry to A ADC A9 2 2 B9 2 3 C9 3 4 F9 1 3 E9 2 4 D9 3 5

Subtract memory SUB A0 2 2 B0 2 3 C0 3 4 F0 1 3 E0 2 4 D0 3 5

Subtract memory from A

with borrow SBC A2 2 2 B2 2 3 C2 3 4 F2 1 3 E2 2 4 D2 3 5

AND memory with A AND A4 2 2 B4 2 3 C4 3 4 F4 1 3 E4 2 4 D4 3 5

OR memory with A ORA AA 2 2 BA 2 3 CA 3 4 FA 1 3 EA 2 4 DA 3 5

Exclusive OR memory with A EOR A8 2 2 B8 2 3 C8 3 4 F8 1 3 E8 2 4 D8 3 5

Arithmetic compare A

with memory CMP A1 2 2 B1 2 3 C1 3 4 F1 1 3 E1 2 4 D1 3 5

Arithmetic compare X

with memory CPX A3 2 2 B3 2 3 C3 3 4 F3 1 3 E3 2 4 D3 3 5

Bit test memory with A

(logical compare) BIT A5 2 2 B5 2 3 C5 3 4 F5 1 3 E5 2 4 D5 3 5

Jump unconditional JMP BC 2 2 CC 3 3 FC 1 2 EC 2 3 DC 3 4

Jump to subroutine JSR BD 2 5 CD 3 6 FD 1 5 ED 2 6 DD 3 7

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CPU CORE AND INSTRUCTION SET

Table 10-3 Branch instructions

Relative addressing mode

Function Mnemonic Opcode # Bytes # Cycles

Branch always BRA 20 2 3

Branch never BRN 21 2 3

Branch if higher BHI 22 2 3

Branch if lower or same BLS 23 2 3

Branch if carry clear BCC 24 2 3

(Branch if higher or same) (BHS) 24 2 3

Branch if carry set BCS 25 2 3

(Branch if lower) (BLO) 25 2 3

Branch if not equal BNE 26 2 3

Branch if equal BEQ 27 2 3

Branch if half carry clear BHCC 28 2 3

Branch if half carry set BHCS 29 2 3

Branch if plus BPL 2A 2 3

Branch if minus BMI 2B 2 3

Branch if interrupt mask bit is clear BMC 2C 2 3

Branch if interrupt mask bit is set BMS 2D 2 3

Branch if interrupt line is low BIL 2E 2 3

Branch if interrupt line is high BIH 2F 2 3

Branch to subroutine BSR AD 2 6

Table 10-4 Bit manipulation instructions

Addressing Modes

Bit set/clear Bit test and branch

Function Mnemonic Opcode # Bytes # Cycles Opcode # Bytes # Cycles

Branch if bit n is set BRSET n (n=0–7) 2•n 3 5

Branch if bit n is clear BRCLR n (n=0–7) 01+2•n 3 5

Set bit n BSET n (n=0–7) 10+2•n 2 5

Clear bit n BCLR n (n=0–7) 11+2•n 2 5

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10-7

CPU CORE AND INSTRUCTION SET

Table 10-5 Read/modify/write instructions

Addressing modes

Inherent

(A) Inherent

(X) Direct Indexed

(no

offset)

Indexed

(8-bit

offset)

Function

Mnemonic

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Increment INC 4C 1 3 5C 1 3 3C 2 5 7C 1 5 6C 2 6

Decrement DEC 4A 1 3 5A 1 3 3A 2 5 7A 1 5 6A 2 6

Clear CLR 4F 1 3 5F 1 3 3F 2 5 7F 1 5 6F 2 6

Complement COM 43 1 3 53 1 3 33 2 5 73 1 5 63 2 6

Negate (two’s complement) NEG 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6

Rotate left through carry ROL 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6

Rotate right through carry ROR 46 1 3 56 1 3 36 2 5 76 1 5 66 2 6

Logical shift left LSL 48 1 3 58 1 3 38 2 5 78 1 5 68 2 6

Logical shift right LSR 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6

Arithmetic shift right ASR 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6

Test for negative or zero TST 4D 1 3 5D 1 3 3D 2 4 7D 1 4 6D 2 5

Multiply MUL 42 1 11

Table 10-6 Control instructions

Inherent addressing mode

Function Mnemonic Opcode # Bytes # Cycles

Transfer A to X TAX 97 1 2

Transfer X to A TXA 9F 1 2

Set carry bit SEC 99 1 2

Clear carry bit CLC 98 1 2

Set interrupt mask bit SEI 9B 1 2

Clear interrupt mask bit CLI 9A 1 2

Software interrupt SWI 83 1 10

Return from subroutine RTS 81 1 6

Return from interrupt RTI 80 1 9

Reset stack pointer RSP 9C 1 2

No-operation NOP 9D 1 2

Stop STOP 8E 1 2

Wait WAIT 8F 1 2

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CPU CORE AND INSTRUCTION SET

Table 10-7 Instruction set (1 of 2)

Mnemonic Addressing modes Condition codes

INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H I N Z C

ADC

◊

•

◊◊◊

ADD

◊

•

◊◊◊

AND ••

◊◊

•

ASL ••

◊◊◊

ASR ••

◊◊◊

BCC •••••

BCLR •••••

BCS •••••

BEQ •••••

BHCC •••••

BHCS •••••

BHI •••••

BHS •••••

BIH •••••

BIL •••••

BIT ••

◊◊

•

BLO •••••

BLS •••••

BMC •••••

BMI •••••

BMS •••••

BNE •••••

BPL •••••

BRA •••••

BRN •••••

BRCLR ••••

◊

BRSET ••••

◊

BSET •••••

BSR •••••

CLC ••••0

CLI •0•••

CLR ••01•

CMP • •

◊◊◊

Condition code symbols

H Half carry (from bit 3)

◊

Tested and set if true,

cleared otherwise

I Interrupt mask • Not affected

N Negate (sign bit) ? Load CCR from stack

Z Zero 0 Cleared

C Carry/borrow 1 Set

Not implemented

Address mode abbreviations

BSC Bit set/clear IMM Immediate

BTB Bit test & branch IX Indexed (no offset)

DIR Direct IX1 Indexed, 1 byte offset

EXT Extended IX2 Indexed, 2 byte offset

INH Inherent REL Relative

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CPU CORE AND INSTRUCTION SET

Table 10-8 Instruction set (2 of 2)

Mnemonic Addressing modes Condition codes

INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H I N Z C

COM ••

◊◊

CPX ••

◊◊◊

DEC ••

◊◊

•

EOR ••

◊◊

•

INC ••

◊◊

•

JMP •••••

JSR •••••

LDA ••

◊◊

•

LDX ••

◊◊

•

LSL ••

◊◊◊

LSR ••0

◊◊

MUL 0•••0

NEG ••

◊◊◊

NOP •••••

ORA ••

◊◊

•

ROL ••

◊◊◊

ROR ••

◊◊◊

RSP •••••

RTI ?????

RTS •••••

SBC ••

◊◊◊

SEC ••••1

SEI •1•••

STA ••

◊◊

•

STOP •0•••

STX ••

◊◊

•

SUB ••

◊◊◊

SWI •1•••

TAX •••••

TST ••

◊◊

•

TXA •••••

WAIT • 0 • • •

Condition code symbols

H Half carry (from bit 3)

◊

Tested and set if true,

cleared otherwise

I Interrupt mask • Not affected

N Negate (sign bit) ? Load CCR from stack

Z Zero 0 Cleared

C Carry/borrow 1 Set

Not implemented

Address mode abbreviations

BSC Bit set/clear IMM Immediate

BTB Bit test & branch IX Indexed (no offset)

DIR Direct IX1 Indexed, 1 byte offset

EXT Extended IX2 Indexed, 2 byte offset

INH Inherent REL Relative

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CPU CORE AND INSTRUCTION SET

Table 10-9 M68HC05 opcode map

Bit manipulation Branch Read/modify/write Control Register/memor y

BTB BSC REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX

High 0123456789ABCDEF

High

Low 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Low

0000 553533659 234543

0000

BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG RTI SUB SUB SUB SUB SUB SUB

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

0001 553 6234543

0001

BRCLR0 BCLR0 BRN RTS CMP CMP CMP CMP CMP CMP

3 BTB 2 BSC 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

0010 553 11 234543

0010

BRSET1 BSET1 BHI MUL SBC SBC SBC SBC SBC SBC

3 BTB 2 BSC 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

0011 5535336510 234543

0011

BRCLR1 BCLR1 BLS COM COMA COMX COM COM SWI CPX CPX CPX CPX CPX CPX

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

0100 55353365 234543

0100

BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR AND AND AND AND AND AND

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

0101 553 234543

0101

BRCLR2 BCLR2 BCS BIT BIT BIT BIT BIT BIT

3 BTB 2 BSC 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

0110 55353365 234543

0110

BRSET3 BSET3 BNE ROR RORA RORX ROR ROR LDA LDA LDA LDA LDA LDA

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

0111 55353365 245654

0111

BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR TAX STA STA STA STA STA

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

1000 55353365 2234543

1000

BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL CLC EOR EOR EOR EOR EOR EOR

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

1001 55353365 2234543

1001

BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL SEC ADC ADC ADC ADC ADC ADC

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

1010 55353365 2234543

1010

BRSET5 BSET5 BPL DEC DECA DECX DEC DEC CLI ORA ORA ORA ORA ORA ORA

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

1011 553 2234543

1011

BRCLR5 BCLR5 BMI SEI ADD ADD ADD ADD ADD ADD

3 BTB 2 BSC 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

1100 55353365 223432

1100

BRSET6 BSET6 BMC INC INCA INCX INC INC RSP JMP JMP JMP JMP JMP

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

1101 55343354 2656765

1101

BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST NOP BSR JSR JSR JSR JSR JSR

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

1110 553 2234543

1110

BRSET7 BSET7 BIL STOP LDX LDX LDX LDX LDX LDX

3 BTB 2 BSC 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

1111 5535336522 45654

1111

BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR WAIT TXA STX STX STX STX STX

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

1111 30

0000

SUB

1IX

Opcode in hexadecimal

Opcode in binary

Address mode

Cycles

Bytes

Mnemonic

Legend

Abbreviations for address modes and registers

BSC

BTB

DIR

EXT

INH

IMM

IX1

IX2

REL

Bit set/clear

Bit test and branch

Direct

Extended

Inherent

Immediate

Indexed (no offset)

Indexed, 1 byte (8-bit) offset

Indexed, 2 byte (16-bit) offset

Relative

Accumulator

Index register Not implemented

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CPU CORE AND INSTRUCTION SET

10.3 Addressing modes

Ten different addressing modes provide programmers with the ﬂexibility to optimize their code for

all situations. The various indexed addressing modes mak e it possible to locate data tables, code

conv ersion tab les and scaling tables an ywhere in the memory space. Short index ed accesses are

single byte instructions; the longest instructions (three bytes) enable access to tables throughout

memory. Short absolute (direct) and long absolute (extended) addressing are also included. One

or two byte direct addressing instructions access all data bytes in most applications. Extended

addressing permits jump instructions to reach all memory locations.

The term ‘effectiv e address’ (EA) is used in describing the various addressing modes. The effective

address is deﬁned as the address from which the argument f or an instruction is fetched or stored.

The ten addressing modes of the processor are described below . Parentheses are used to indicate

‘contents of ’ the location or register referred to. For example, (PC) indicates the contents of the

location pointed to by the PC (program counter). An arrow indicates ‘is replaced by’ and a colon

indicates concatenation of two b ytes. For additional details and gr aphical illustrations, refer to the

M6805 HMOS/M146805 CMOS Family Microcomputer/ Microprocessor User's Manual

or to

the

M68HC05 Applications Guide.

10.3.1 Inherent

In the inherent addressing mode, all the information necessary to execute the instruction is

contained in the opcode. Operations specifying only the index register or accumulator, as well as

the control instruction, with no other arguments are included in this mode. These instructions are

one byte long.

10.3.2 Immediate

In the immediate addressing mode, the operand is contained in the b yte immediately f ollowing the

opcode. The immediate addressing mode is used to access constants that do not change during

program execution (e.g. a constant used to initialize a loop counter).

EA = PC+1; PC ← PC+2

10.3.3 Direct

In the direct addressing mode, the effectiv e address of the argument is contained in a single byte

following the opcode byte. Direct addressing allows the user to directly address the lowest 256

bytes in memory with a single two-byte instruction.

EA = (PC+1); PC ← PC+2

Address bus high ← 0; Address bus low ← (PC+1)

TPG

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10-12 MC68HC05B6

Rev. 4

CPU CORE AND INSTRUCTION SET

10.3.4 Extended

In the extended addressing mode, the effective address of the argument is contained in the two

bytes following the opcode byte. Instructions with extended addressing mode are capable of

referencing arguments anywhere in memory with a single three-byte instruction. When using the

Motorola assembler, the user need not specify whether an instruction uses direct or extended

addressing. The assembler automatically selects the short form of the instruction.

EA = (PC+1):(PC+2); PC ← PC+3

Address bus high ← (PC+1); Address bus low ← (PC+2)

10.3.5 Indexed, no offset

In the indexed, no offset addressing mode, the effective address of the argument is contained in

the 8-bit index register. This addressing mode can access the ﬁrst 256 memory locations. These

instructions are only one byte long. This mode is often used to move a pointer through a table or

to hold the address of a frequently referenced RAM or I/O location.

EA = X; PC ← PC+1

Address bus high ← 0; Address bus low ← X

10.3.6 Indexed, 8-bit offset

In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of

the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the

operand can be located anywhere within the lo west 511 memory locations. This addressing mode

is useful for selecting the mth element in an n element table.

EA = X+(PC+1); PC ← PC+2

Address bus high ← K; Address bus low ← X+(PC+1)

where K = the carry from the addition of X and (PC+1)

10.3.7 Indexed, 16-bit offset

In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of

the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address

mode can be used in a manner similar to indexed, 8-bit offset e xcept that this three-byte instruction

allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola

assembler determines the shortest form of indexed addressing.

EA = X+[(PC+1):(PC+2)]; PC ← PC+3

Address bus high ← (PC+1)+K; Address bus low ← X+(PC+2)

where K = the carry from the addition of X and (PC+2)

TPG

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10-13

CPU CORE AND INSTRUCTION SET

10.3.8 Relative

The relative addressing mode is only used in branch instructions. In relative addressing, the

contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only

if , the br anch conditions are true. Otherwise, control proceeds to the ne xt instruction. The span of

relative addressing is from –126 to +129 from the opcode address. The programmer need not

calculate the offset when using the Motorola assembler, since it calculates the proper offset and

checks to see that it is within the span of the branch.

EA = PC+2+(PC+1); PC ← EA if branch taken;

otherwise EA = PC ← PC+2

10.3.9 Bit set/clear

In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte

following the opcode speciﬁes the address of the byte in which the speciﬁed bit is to be set or

cleared. Any read/write bit in the ﬁrst 256 locations of memory, including I/O, can be selectiv ely set

or cleared with a single two-byte instruction.

EA = (PC+1); PC ← PC+2

Address bus high ← 0; Address bus low ← (PC+1)

10.3.10 Bit test and branch

The bit test and branch addressing mode is a combination of direct addressing and relative

addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The

address of the byte to be tested is in the single b yte immediately f ollo wing the opcode byte (EA1).

The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the speciﬁed bit is set

or cleared in the speciﬁed memory location. This single three-byte instruction allows the program

to branch based on the condition of any readab le bit in the ﬁrst 256 locations of memory. The span

of branch is from –125 to +130 from the opcode address. The state of the tested bit is also

transferred to the carry bit of the condition code register.

EA1 = (PC+1); PC ← PC+2

Address bus high ← 0; Address bus low ← (PC+1)

EA2 = PC+3+(PC+2); PC ← EA2 if branch taken;

otherwise PC ← PC+3

TPG

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10-14 MC68HC05B6

Rev. 4

CPU CORE AND INSTRUCTION SET

THIS PAGE LEFT BLANK INTENTIONALLY

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

11-1

ELECTRICAL SPECIFICATIONS

This section contains the electrical speciﬁcations and associated timing information for the

MC68HC05B6.

11.1 Absolute maximum ratings

Note:

This device contains circuitry designed to protect against damage due to high

electrostatic voltages or electric ﬁelds. However, it is recommended that normal

precautions be taken to a void the application of an y voltages higher than those giv en in

the maximum ratings table to this high impedance circuit. For maximum reliability all

unused inputs should be tied to either VSS or VDD.

(1) All voltages are with respect to V

SS.

(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.

Table 11-1 Absolute maximum ratings

Rating Symbol Value Unit

Supply voltage(1) VDD – 0.5 to +7.0 V

Input voltage (Except VPP1)V

IN VSS – 0.5 to VDD + 0.5 V

Input voltage

– Self-check mode (IRQ pin only) VIN VSS – 0.5 to 2VDD + 0.5 V

Operating temperature range

– Standard (MC68HC05B6)

– Extended (MC68HC05B6C)

– Automotive (MC68HC05B6M)

TATL to TH

0 to +70

–40 to +85

–40 to +125

°C

Storage temperature range TSTG – 65 to +150 °C

Current drain per pin (excluding VDD and VSS)(2)

– Source

– Sink ID

45 mA

TPG

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MOTOROLA

11-2 MC68HC05B6

Rev. 4

ELECTRICAL SPECIFICATIONS

11.2 DC electrical characteristics

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient

switching currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 4.2MHz); all inputs 0.2 V from

rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports conﬁgured as inputs; V

IL = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with

OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

Table 11-2 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic(1) Symbol Min Typ (2) Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µAVOH

VOL VDD – 0.1

——

0.1 V

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.8

VDD – 0.4

—

—V

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

VOL

— 0.1

0.4

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ ,

RESET,TCAP1, TCAP2, RDI VIL VSS — 0.2VDD V

Supply current(3)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP 0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (extended)

– 40 to 125 (automotive)

IDD

—

3.5

0.5

0.35

—

1.5

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK IIL —±0.2 ±1µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN —±0.2

±0.2 ±1

±1mA

Input current (– 40 to 125)

IRQ, OSC1, TCAP1, TCAP2, RDI, IIN ——±5µA

Capacitance

Ports (as input or output), RESET, TDO , SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

11-3

ELECTRICAL SPECIFICATIONS

11.2.1 IDD trends for 5V operation

For the examples below, typical values are at the mid-point of the voltage range and at a

temperature of 25°C only.

Figure 11-1 Run IDD vs internal operating frequency (4.5V, 5.5V)

Figure 11-2 Run IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V)

Figure 11-3 Wait IDD vs internal operating frequency (4.5V, 5.5V)

00 0.5 1 1.5 2 2.5 3 3.5 4

IDD (mA)

Internal operating frequency (MHz)

5.5V

4.5V

1.2

00 0.5 1 1.5 2 2.5 3 3.5 4

IDD (mA)

Internal operating frequency (MHz)

5.5V

4.5V

0.8

0.6

0.4

0.2

2.5

00 0.5 1 1.5 2 2.5 3 3.5 4

IDD (mA)

Internal operating frequency (MHz)

5.5V

4.5V

1.5

0.5

TPG

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MOTOROLA

11-4 MC68HC05B6

Rev. 4

ELECTRICAL SPECIFICATIONS

Figure 11-4 Wait IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V)

Figure 11-5 Increase in IDD vs frequency f or A/D , SCI systems activ e, VDD = 5.5V

Figure 11-6 IDD vs mode vs internal operating frequency, VDD = 5.5V

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

00 0.5 1 1.5 2 2.5 3 3.5 4

IDD (mA)

Internal operating frequency (MHz)

5.5V

4.5V

0.9

1.4

1.2

0.8

0.6

0.4

0.2

00 0.5 1 1.5 2 2.5 3

IDD (mA)

Internal operating frequency (MHz)

A/D + SCI

A/D

1.6

SCI

00 0.5 1 1.5 2 2.5 3 3.5 4

IDD (mA)

Internal operating frequency (MHz)

Wait IDD (SM = 1)

Run IDD

Wait IDD

Run IDD (SM = 1)

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

11-5

ELECTRICAL SPECIFICATIONS

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the

transient switching currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

(3) RUN and WAIT IDD: measured using an e xternal square-wav e cloc k source (fOSC = 2.0MHz); all inputs 0.2 V

from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).

ST OP /WAIT IDD: all ports conﬁgured as inputs; V

IL = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with

OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

Table 11-3 DC electrical characteristics for 3.3V operation

(VDD = 3.3Vdc ± 10%, VSS = 0Vdc, TA = TL to TH)

Characteristic(1) Symbol Min Typ (2) Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µAVOH

VOL VDD – 0.1

——

0.1 V

Output high voltage (ILOAD = 0.2mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 0.4mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.3

VDD – 0.1

—

—V

Output low voltage (ILOAD = 0.4mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 0.4mA)

RESET

VOL

— 0.1

0.2

0.3

0.6 V

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ ,

RESET, TCAP1, TCAP2, RDI VIL VSS — 0.2VDD V

Supply current(3)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP 0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (extended)

– 40 to 125 (automotive)

IDD

—

1.2

0.2

0.4

0.15

—

1.5

0.5

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK IIL —±0.2 ±1µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN —±0.2

±0.2 ±1

±1µA

Input current (– 40 to 125)

IRQ, OSC1, TCAP1, TCAP2, RDI, I IN ——±5µA

Capacitance

P orts (as input or output), RESET, TDO, SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

TPG

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MOTOROLA

11-6 MC68HC05B6

Rev. 4

ELECTRICAL SPECIFICATIONS

11.2.2 IDD trends for 3.3V operation

For the examples below, typical values are at the mid-point of the voltage range and at a

temperature of 25°C only.

Figure 11-7 Run IDD vs internal operating frequency (3V, 3.6V)

Figure 11-8 Run IDD (SM = 1) vs internal operating frequency (3V,3.6V)

Figure 11-9 Wait IDD vs internal operating frequency (3V, 3.6V)

2.5

00 0.5 1 1.5 2 2.5

IDD (mA)

Internal operating frequency (MHz)

3.6V

3.0V

1.5

0.5

0.6

00 0.5 1 1.5 2 2.5

IDD (mA)

Internal operating frequency (MHz)

3.6V

3.0V

0.5

0.4

0.3

0.2

0.1

1.2

00 0.5 1 1.5 2 2.5

IDD (mA)

Internal operating frequency (MHz)

3.6V

3.0V

0.8

0.6

0.4

0.2

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

11-7

ELECTRICAL SPECIFICATIONS

Figure 11-10 Wait IDD (SM = 1) vs internal operating frequency (3V, 3.6V)

Figure 11-11 Increase in IDD vs frequency f or A/D , SCI systems active, VDD = 3.6V

Figure 11-12 IDD vs mode vs internal operating frequency, VDD = 3.6V

0.5

00 0.5 1 1.5 2 2.5

IDD (mA)

Internal operating frequency (MHz)

3.6V

3.0V

0.4

0.3

0.2

0.1

0.7

0.6

0.5

0.4

0.3

0.2

0.1

00 0.5 1 1.5 2 2.5

IDD (mA)

Internal operating frequency (MHz)

A/D

SCI

A/D + SCI

2.5

1.5

0.5

00 0.5 1 1.5 2 2.5

IDD (mA)

Internal operating frequency (MHz)

Run IDD

Wait IDD

Run IDD (SM=1)

Wait IDD (SM=1)

TPG

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MOTOROLA

11-8 MC68HC05B6

Rev. 4

ELECTRICAL SPECIFICATIONS

11.3 A/D converter characteristics

(1) Performance veriﬁed down to 2.5V ∆VR, but accuracy is tested and guaranteed at ∆VR = 5V±10%.

(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

(3) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

Table 11-4 A/D characteristics for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V) —± 0.5 LSB

Quantization error Uncertainty due to converter resolution — ± 0.5 LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors —± 1 LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VR(1) Minimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

a. External clock (OSC1, OSC2)

b. Internal RC oscillator —

—32

32 tCYC

µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

a. External clock (OSC1, OSC2)

b. Internal RC oscillator(2) —

—12

12 tCYC

µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(3) Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

11-9

ELECTRICAL SPECIFICATIONS

(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

(2) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

Table 11-5 A/D characteristics for 3.3V operation

(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V) —± 1 LSB

Quantization error Uncertainty due to converter resolution — ± 1 LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors —± 2 LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VRMinimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

Internal RC oscillator — 32 µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

Internal RC oscillator(1) —12µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(2) Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

TPG

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MOTOROLA

11-10 MC68HC05B6

Rev. 4

ELECTRICAL SPECIFICATIONS

11.4 Control timing

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

(2) Since a 2-bit prescaler in the timer must count four external cycles (t

CYC), this is the limiting

factor in determining the timer resolution.

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute

the capture interrupt service routine plus 24 t

CYC.

(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute

the interrupt service routine plus 21 t

CYC.

(5) tOH and tOL should not total less than 238ns.

(6) At a temperature of 85°C

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

Table 11-6 Control timing for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option fOSC

fOSC

—

dc 4.2

4.2 MHz

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock fOP

fOP

dc 2.1

2.1 MHz

MHz

Cycle time (see Figure 9-1) tCYC 476 — ns

Crystal oscillator start-up time (see Figure 9-1) t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) t

ILCH 100 ms

RC oscillator stabilization time t

ADRC 5µs

A/D converter stabilization time t

ADON 500 µs

External RESET input pulse width tRL 1.5 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle tPORL

tPORL

4064

16 —

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 125 (automotive)

tERA

—

EEPROM byte program time (1)

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 125 (automotive)

tPROG

—

Timer (see Figure 11-13)

Resolution(2)

Input capture pulse width

Input capture pulse period

tRESL

tTH, tTL

tTLTL

125

—(3)

—

tCYC

Interrupt pulse width (edge-triggered) t

ILIH 125 — ns

Interrupt pulse period tILIL —(4) —t

CYC

OSC1 pulse width(5) tOH, tOL 90 — ns

Write/Erase endurance(6)(7) — 10000 cycles

Data retention(6)(7) — 10 years

TPG

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MC68HC05B6

Rev. 4 MOTOROLA

11-11

ELECTRICAL SPECIFICATIONS

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

(2) Since a 2-bit prescaler in the timer must count four external cycles (t

CYC), this is the limiting

factor in determining the timer resolution.

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to

execute the capture interrupt service routine plus 24 t

CYC.

(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute

the interrupt service routine plus 21 t

CYC.

(5) tOH and tOL should not total less than 500ns.

(6) At a temperature of 85°C

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

Table 11-7 Control timing for 3.3V operation

(VDD = 3.3Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option fOSC

fOSC

—

dc 2.0

2.0 MHz

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock fOP

fOP

—

dc 1.0

1.0 MHz

MHz

Cycle time (see Figure 9-1) tCYC 1000 — ns

Crystal oscillator start-up time (see Figure 9-1) t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) t

ILCH 100 ms

RC oscillator stabilization time t

ADRC 5µs

A/D converter stabilization time t

ADON 500 µs

External RESET input pulse width tRL 1.5 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle tPORL

tPORL

4064

16 —

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 125 (automotive)

tERA

—

EEPROM byte program time (1)

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 125 (automotive)

tPROG

—

Timer (see Figure 11-13)

Resolution(2)

Input capture pulse width

Input capture pulse period

tRESL

tTH, tTL

tTLTL

250

—(3)

—

tCYC

Interrupt pulse width (edge-triggered) t

ILIH 250 — ns

Interrupt pulse period tILIL —(4) —t

CYC

OSC1 pulse width(5) tOH, tOL 200 — ns

Write/Erase endurance(6)(7) — 10000 cycles

Data retention(6)(7) — 10 years

TPG

139

05B6Book Page 11 Tuesday, April 6, 1999 8:24 am

MOTOROLA

11-12 MC68HC05B6

Rev. 4

ELECTRICAL SPECIFICATIONS

Figure 11-13 Timer relationship

External

signal

(TCAP1,

TCAP2)

tTLTL tTH tTL

TPG

140

05B6Book Page 12 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

12-1

MECHANICAL DATA

12.1 MC68HC05B family pin conﬁgurations

12.1.1 52-pin plastic leaded chip carrier (PLCC)

Figure 12-1 52-pin PLCC pinout for the MC68HC05B6

PC3

PC4

PC5

PC6

PC7

VSS

VPP1/NU

PB0

PB1

PB2

PB3

PB4

PB5

VRH

PD4/AN4

VDD

PD3/AN3

PD2/AN2

PD1/AN1

PD0/AN0

NC/VPP6

OSC1

OSC2

RESET

IRQ

PLMA

PLMB

TCAP1

TCAP2

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PB7

PB6

VRL

NC/NU

PD5/AN5

PD6/AN6

PD7/AN7

TCMP1

TCMP2

TDO

SCLK

RDI

PC0

PC1

PC2/ECLK

Device Pin 6 Pin 15 Pin 40

MC68HC05B4 NC NC NU

MC68HC05B6 NC NC VPP1

MC68HC05B8 NC NC VPP1

MC68HC05B16 NC NC VPP1

MC68HC05B32 NC NC VPP1

MC68HC705B5 NC VPP6 NU

MC68HC705B16 NU VPP6 VPP1

MC68HC705B16N NU VPP6 VPP1

MC68HC705B32 NU VPP6 VPP1

NC = Not connected

NU = Non-user pin (Should be tied to VSS

in an electrically noisy environment)

TPG

141

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

MOTOROLA

12-2 MC68HC05B6

Rev. 4

MECHANICAL DATA

12.1.2 64-pin quad ﬂat pack (QFP)

Figure 12-2 64-pin QFP pinout for the MC68HC05B6

PB0

NC/NU

VPP1/NC

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

TCAP2

TCAP1

PLMB D/A

PC1

PC0

RDI

SCLK

TDO

TCMP2

TCMP1

PD7/AN7

PD6/AN6

PD5/AN5

VRL

VRH

VDD

PD3/AN3

PD2/AN2

PD1/AN1

NC/VPP6

OSC1

OSC2

RESET

IRQ

PLMA D/A

PD4/AN4

PC2/ECLK

PC3

PC5

PC6

PC7

VSS

PB1

PB2

PB3

PB4

PB5

PC4

PD0/AN0

Device Pin 27 Pin 55 Pin 57

MC68HC05B4 NC NC NC

MC68HC05B6

MC68HC05B8

MC68HC05B16

MC68HC05B32

NC NC VPP1

MC68HC705B5 Not available in this package

MC68HC705B16 VPP6 NU VPP1

MC68HC705B16N VPP6 NU VPP1

MC68HC705B32 VPP6 NC VPP1

NC = Not connected

NU = Non-user pin (Should be tied to VSS in an electrically noisy environment)

TPG

142

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

12-3

MECHANICAL DATA

12.1.3 56-pin shrink dual in line package (SDIP)

Figure 12-3 56-pin SDIP pinout for the MC68HC05B6

TCMP1

PD7

PD6

PD5

NC/NU

VRL

VRH

PD4

VDD

PD3

PD2

PD1

PD0

NC/VPP6

OSC1

OSC2

RESET

IRQ

PLMA 22

56 TCMP2

TDO

SCLK

RDI

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

VSS

VPP1/NC

PB0

PB1

PB2

PB3

PB4

PB5

PLMB

TCAP1

TCAP2

PA7

PA6

PA5

PA4

PB6

PB7

PA0

PA1

PA2

PA3

Device Pin 6 Pin 16 Pin 42

MC68HC05B4 NC NC NC

MC68HC05B6 NC NC VPP1

MC68HC05B8 NC NC VPP1

MC68HC05B16 NC NC VPP1

MC68HC05B32 NC NC VPP1

MC68HC705B5 NC VPP6 NC

MC68HC705B16 Not available in this package

MC68HC705B16N Contact Sales

MC68HC705B32 NU VPP6 VPP1

NC = Not connected

NU = Non-user pin (Should be tied to VSS in an electrically noisy environment)

TPG

143

05B6Book Page 3 Tuesday, April 6, 1999 8:24 am

MOTOROLA

12-4 MC68HC05B6

Rev. 4

MECHANICAL DATA

12.2 MC68HC05B6 mechanical dimensions

12.2.1 52-pin plastic leaded chip carrier (PLCC)

Figure 12-4 52-pin PLCC mechanical dimensions

–L– –M–

–P–

–N–

pin 1

pin 52

Y BRK

J E

0.10

–T– SEATING PLANE

0.18 T N –P L –M

S S S

Case No. 778-02

52 Lead PLCC

w/o pedestal

Dim. Min. Max. Notes Dim. Min. Max.

A 19.94 20.19

1. Datums –L–, –M–, –N– and –P– are determined where top of lead

shoulder exits plastic body at mould parting line.

2. Dimension G1, true position to be measured at datum –T– (seating

plane).

3. Dimensions R and U do not include mould protrusion. Allowable

mould protrusion is 0.25mm per side.

4. Dimensions and tolerancing per ANSI Y 14.5M, 1982.

5. All dimensions in mm.

U 19.05 19.20

B 19.94 20.19 V 1.07 1.21

C 4.20 4.57 W 1.07 1.21

E 2.29 2.79 X 1.07 1.42

F 0.33 0.48 Y — 0.50

G 1.27 BSC Z 2 °10°

H 0.66 0.81 G1 18.04 18.54

J 0.51 — K1 1.02 —

K 0.64 — Z1 2 °10°

R 19.05 19.20

0.18 T L –M N –P

S S S

0.18 T L –M N –P

S S S

0.18 T N –P L –M

S S S

0.25 T L –M N –P

S S S

TPG

144

05B6Book Page 4 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

12-5

MECHANICAL DATA

12.2.2 64-pin quad ﬂat pack (QFP)

Figure 12-5 64-pin QFP mechanical dimensions

64 lead QFP

0.20 MC A – B SDS

3348

161

- B - B V

0.05 A – B

- D - A

0.20 MH A – B SDS

L- A -

Detail “A”

- A, B, D -

Detail “A”

Section B–B

Base

Metal

-C-

Detail “C”

-H- Datum

Plane

Seating

Plane

Dim. Min. Max. Notes Dim. Min. Max.

A 13.90 14.10 1. Datum Plane –H– is located at bottom of lead and is coincident with

the lead where the lead exits the plastic body at the bottom of the

parting line.

2. Datums A–B and –D to be determined at Datum Plane –H–.

3. Dimensions S and V to be determined at seating plane –C–.

4. Dimensions A and B do not include mould protrusion. Allowable

mould protrusion is 0.25mm per side. Dimensions A and B do

include mould mismatch and are determined at Datum Plane –H–.

5. Dimension D does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08 total in excess of the D dimension

at maximum material condition. Dambar cannot be located on the

lower radius or the foot.

6. Dimensions and tolerancing per ANSI Y 14.5M, 1982.

7. All dimensions in mm.

M5°10°

B 13.90 14.10 N 0.130 0.170

C 2.067 2.457 P 0.40 BSC

D 0.30 0.45 Q 2 °8°

E 2.00 2.40 R 0.13 0.30

F 0.30 — S 16.20 16.60

G 0.80 BSC T 0.20 REF

H 0.067 0.250 U 9 °15°

J 0.130 0.230 V 16.20 16.60

K 0.50 0.66 W 0.042 NOM

L 12.00 REF X 1.10 1.30

0.20 MC A – B SDS

0.05 A – B

0.20 MH A – B SDS

0.20 MC A – B SDS

Case No. 840C

TPG

145

05B6Book Page 5 Tuesday, April 6, 1999 8:24 am

MOTOROLA

12-6 MC68HC05B6

Rev. 4

MECHANICAL DATA

12.2.3 56-pin shrink dual in line package (SDIP)

Figure 12-6 56-pin SDIP mechanical dimensions

128

56 29

- A -

Plane

Seating

Dim. Min. Max. Notes Dim. Min. Max.

A 51.69 52.45 1. Due to space limitations, this case shall be represented by a

general case outline, rather than one showing all the leads.

2. Dimensions and tolerancing per ANSI Y 14.5 1982.

3. All dimensions in mm.

4. Dimension L to centre of lead when formed parallel.

5. Dimensions A and B do not include mould ﬂash. Allowable mould

ﬂash is 0.25 mm.

H 7.62 BSC

B 13.72 14.22 J 0.20 0.38

C 3.94 5.08 K 2.92 3.43

D 0.36 0.56 L 15.24 BSC

E 0.89 BSC M 0 °15°

F 0.81 1.17 N 0.51 1.02

G 1.778 BSC

Case No. 859-01

56 lead SDIP - B - H

- T -

0.25 T A

0.25 T B

TPG

146

05B6Book Page 6 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

13-1

ORDERING INFORMATION

This section describes the information needed to order the MC68HC05B6 and other family members .

To initiate a ROM pattern for the MCU , it is necessary to contact your local ﬁeld service ofﬁce, local

sales person or Motorola representative . Please note that you will need to supply details such as:

mask option selections; temperature range; oscillator frequency; package type; electrical test

requirements; and device marking details so that an order can be processed, and a customer

speciﬁc part number allocated. Ref er to Table 13-1 for appropriate part numbers . The part number

consists of the device title plus the appropriate sufﬁx. For example, the MC68HC05B6 in 52-pin

PLCC package at –40 to +85°C would be ordered as: MC68HC05B6CFN.

Table 13-1 MC order numbers

Device Title Package T ype Sufﬁx

0 to 70°CSufﬁx

-40 to +85°CSufﬁx

-40 to +105°CSufﬁx

-40 to +125°C

MC68HC05B6 52-pin PLCC FN CFN VFN MFN

64-pin QFP FU CFU VFU MFU

56-pin SDIP B CB VB MB

MC68HC05B4 52-pin PLCC FN CFN VFN MFN

64-pin QFP FU CFU VFU MFU

56-pin SDIP B CB VB MB

MC68HC05B8 52-pin PLCC FN CFN VFN MFN

64-pin QFP FU CFU VFU MFU

56-pin SDIP B CB VB MB

MC68HC05B16 52-pin PLCC FN CFN VFN MFN

64-pin QFP FU CFU VFU MFU

56-pin SDIP B CB VB MB

MC68HC05B32 52-pin PLCC FN CFN N/A N/A

64-pin QFP FU CFU N/A N/A

56-pin SDIP B Contact Sales N/A N/A

MC68HC705B5 52-pin PLCC FN CFN VFN MFN

56-pin SDIP B CB VB MB

MC68HC705B16 52-pin PLCC FN CFN VFN MFN

64-pin QFP FU CFU VFU MFU

MC68HC705B16N 52-pin PLCC FN CFN VFN MFN

64-pin QFP FU CFU VFU MFU

56-pin SDIP Contact Sales

MC68HC705B32 52-pin PLCC FN CFN N/A N/A

64-pin QFP FU CFU N/A N/A

56-pin SDIP B CB N/A N/A

TPG

147

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

MOTOROLA

13-2 MC68HC05B6

Rev. 4

ORDERING INFORMATION

13.1 EPROMS

For the MC68HC05B6, an 8 kbyte EPROM programmed with the customer’s software (positive

logic f or address and data) should be submitted for pattern generation. All unused b ytes should be

programmed to $00. The size of EPROM which should be used for all other family members is

listed in Table 13-2.

The EPROM should be clearly labelled, placed in a conductive IC carrier and securely packed.

13.2 Veriﬁcation media

All original pattern media (EPROMs) are ﬁled for contractual purposes and are not returned. A

computer listing of the ROM code will be generated and retur ned with a listing veriﬁcation form.

The listing should be thoroughly check ed and the veriﬁcation form completed, signed and returned

to Motorola. The signed veriﬁcation form constitutes the contractual agreement for creation of the

custom mask. If desired, Motorola will program blank EPROMs (supplied by the customer) from

the data ﬁle used to create the custom mask, to aid in the veriﬁcation process.

13.3 ROM veriﬁcation units (RVU)

Ten MCUs containing the customer’ s ROM pattern will be provided f or program v eriﬁcation. These

units will have been made using the custom mask but are for ROM veriﬁcation only. For

expediency, they are usually unmarked and are tested only at room temperature (25 °C) and at

5 Volts. These RVUs are included in the mask charge and are not production parts. They are

neither backed nor guaranteed by Motorola Quality Assurance.

Table 13-2 EPROMs for pattern generation

Device Size of EPROM

MC68HC05B4 8 kbyte

MC68HC05B8 8 kbyte

MC68HC05B16 16 kbyte

MC68HC05B32 32 kbyte

TPG

148

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

A-1

MC68HC05B4

The MC68HC05B4 is a device similar to the MC68HC05B6, but without EEPROM and having a

reduced ROM siz e of 4 kbytes. The entire MC68HC05B6 data sheet applies to the MC68HC05B4,

with the exceptions outlined in this appendix.

A.1 Features

• 4158 bytes User ROM (including 14 bytes User vectors)

• No EEPROM

• High speed version not available

Section 3.5, ‘EEPROM’, therefore, does not apply to the MC68HC05B4, and the register at

address $07 only allows the user to select whether or not the ECLK should appear at PC2, using

bit 3 of $07. All other bits of this register read as ‘0’.

Table A-1 Mode of operation selection

IRQ pin TCAP1 pin PD3 PD4 Mode

VSS to VDD VSS to VDD X X Single chip

2VDD VDD 0 X Self check

2VDD VDD 1 0 Serial RAM loader

2VDD VDD 1 1 Jump to any address

TPG

149

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

MOTOROLA

A-2 MC68HC05B6

Rev. 4

MC68HC05B4

Figure A-1 MC68HC05B4 block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

programmable

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

176 bytes

RAM

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

÷ 2 / ÷32

PLMA D/A

PLMB D/A

8-bit

432 bytes

User ROM

4158 bytes

self check ROM

(including 14 bytes

User vectors)

TPG

150

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

A-3

MC68HC05B4

Figure A-2 Memory map of the MC68HC05B4

User vectors

(14 bytes)

$1FF2–3 SCI

Timer overﬂow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000 I/O

(32 bytes)

$0020

$00C0

$0100

$1FF0

Stack

RAM

(176 bytes)

$02C0

$0200

$1F00

$0050

Port A data direction register

Port B data direction register

Port C data direction register

EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Page 0 User

ROM

(48 bytes)

Self-check ROM I

(192 bytes)

User ROM

(4096 bytes)

Self-check ROM II

(240 bytes)

$0F00

Reserved

MC68HC05B4 Registers

$1FF4–5

$1FF6–7

$1FF8–9

$1FFA–B

$1FFC–D

$1FFE–F

TPG

151

05B6Book Page 3 Tuesday, April 6, 1999 8:24 am

MOTOROLA

A-4 MC68HC05B6

Rev. 4

MC68HC05B4

(1) This bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

Table A-2 Register outline

reset

Port A data (PORTA) $0000 Undeﬁned

Port B data (PORTB) $0001 Undeﬁned

Port C data (PORTC) $0002 PC2/

ECLK Undeﬁned

Port D data (PORTD) $0003 PD7/

AN7 PD6/

AN6 PD5/

AN5 PD4/

AN4 PD3/

AN3 PD2/

AN2 PD1/

AN1 PD0/

AN0 Undeﬁned

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

ECLK control $0007 0000ECLK 0 0 0 0000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR (1) INTP INTN INTE SFA SFB SM WDOG

(2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL uuuu uuuu

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 uuuu uuuu

Input capture high 1 $0014 Undeﬁned

Input capture low 1 $0015 Undeﬁned

Output compare high 1 $0016 Undeﬁned

Output compare low 1 $0017 Undeﬁned

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undeﬁned

Input capture low 2 $001D Undeﬁned

Output compare high 2 $001E Undeﬁned

Output compare low 2 $001F Undeﬁned

TPG

152

05B6Book Page 4 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

A-5

MC68HC05B4

A.2 Self-check mode

The self-check function available on the MC68HC05B4 provides an internal capability to determine

if the device is functional. Self-check is performed using the circuit shown in Figure A-3. Port C

pins PC0–PC3 are monitored f or the self-check results (light emitting diodes are shown but other

devices could be used), and are interpreted as described in Table A-3. The self-check mode is

entered by applying 2 x VDD dc (via a 4.7kΩ resistor) to the IRQ pin and 5V dc input (via a 4.7kΩ

resistor) to the TCAP1 pin and then depressing the reset s witch to e xecute a reset. After reset, the

following tests are perfor med automatically and once completed they continually repeat. A good

de vice will exhibit ﬂashing LEDs; a bad device will be indicated by the LEDs holding at one value.

Note:

Self-check code can be obtained from your local Motorola representative.

I/0 — Functionally exercises ports A, B, C and D

RAM — Counter test for each RAM byte

ROM — Exclusive OR with odd ones parity result

Timer — Tracks counter registers and checks ICF1, ICF2, OCF1, OCF2 and TOF

ﬂags

SCI — Transmission test; check for RDRF, TDRE, TC and FE ﬂags

A/D — Check A/D functionality on internal channels: VRL, VRH and (VRL +

VRH)/2

PLM — Checks the PLM basic functionality

Interrupts — Tests external timer and SCI interrupts

Watchdog— Tests the watchdog

Caution: This document includes descriptions of the various self-check and bootstrap

mechanisms that are currently implemented as ﬁrmware in the non-user ROM areas of

the MC68HC05B6 and related devices.

As these ﬁrmware routines are intended primarily to help Motorola’ s engineers test the

devices, they may be changed or removed at any time.

For this reason, Motorola recommends the self-check and bootstrap routines are not

called from the user software. Customers who do call these routines from the user

software do so at their own risk.

TPG

153

05B6Book Page 5 Tuesday, April 6, 1999 8:24 am

MOTOROLA

A-6 MC68HC05B6

Rev. 4

MC68HC05B4

Table A-3 MC68HC05B4 self-check results

PC3 PC2 PC1 PC0 Remarks

1001Bad port

0110Bad port

1010Bad RAM

1011Bad ROM

1100Bad Timer

1101Bad SCI

1110Bad A/D

0001Bad PLM

0010Bad interrupts

0011Bad watchdog

Flashing Good device

All others Bad device, bad port etc.

‘0’ indicates LED on; ‘1’ indicates LED off

TPG

154

05B6Book Page 6 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

A-7

MC68HC05B4

Figure A-3 MC68HC05B4 self-check schematic diagram

OSC1

OSC2

IRQ

TCAP2

TCMP2

TCAP1

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

VRLVSS

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

TCMP1

SCLK

PLMB

PLMA

TDO

RDI

VPP1

RESET

NC VRH VDD

41 7

0.01 µF

10 nF 47 µF

10 MΩ

4 MHz

22 pF 4k7 Ω

4k7 Ω

680 Ω

22 pF

4k7 Ω

680 Ω

BC239

P1 GND

+5V

2xVDD

RESET

EEPROM tested

EEPROM not tested

15 8 10

Note: For the MC68HC05B4, switches on PB5 and PB6 have no effect

All resistors are 10 kΩ, unless otherwise stated.

MC68HC05B4 (52-pin package)

TPG

155

05B6Book Page 7 Tuesday, April 6, 1999 8:24 am

MOTOROLA

A-8 MC68HC05B6

Rev. 4

MC68HC05B4

THIS PAGE LEFT BLANK INTENTIONALLY

TPG

156

05B6Book Page 8 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

B-1

MC68HC05B8

The MC68HC05B8 is a device similar to the MC68HC05B6, but with an increased ROM size of

7.25 kbytes. The entire MC68HC05B6 data sheet applies to the MC68HC05B8, with the

exceptions outlined in this appendix.

B.1 Features

• 7230 bytes User ROM (including 14 bytes User vectors)

• High speed version available

TPG

157

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

MOTOROLA

B-2 MC68HC05B6

Rev. 4

MC68HC05B8

Figure B-1 MC68HC05B8 block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

programmable

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

176 bytes

RAM

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP1

256 bytes

EEPROM

Charge pump

÷ 2 / ÷32

PLMA D/A

PLMB D/A

8-bit

432 bytes

User ROM

7230 bytes

self check ROM

(including 14 bytes

User vectors)

TPG

158

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

B-3

MC68HC05B8

Figure B-2 Memory map of the MC68HC05B8

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000 I/O

(32 bytes)

$0020

$00C0

$0100

$1FF0

Stack

RAM

(176 bytes)

$02C0

$0200

$1F00

$0050

Port A data direction register

Port B data direction register

Port C data direction register

EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Page 0 User

ROM

(48 bytes)

Self-check ROM I

(192 bytes)

User ROM

(7168 bytes)

Self-check ROM II

(240 bytes)

$0300

OPTR (1 byte)

Non protected (31 bytes)

Protected (224 bytes)

EEPROM

(256 bytes)

$0101

$0120

$0100Options register

Reserved

MC68HC05B8 Registers

User vectors

(14 bytes)

$1FF2–3 SCI

Timer overﬂow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$1FF4–5

$1FF6–7

$1FF8–9

$1FFA–B

$1FFC–D

$1FFE–F

TPG

159

05B6Book Page 3 Tuesday, April 6, 1999 8:24 am

MOTOROLA

B-4 MC68HC05B6

Rev. 4

MC68HC05B8

(1) This bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=w atchdog disabled.

(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

Table B-1 Register outline

reset

Port A data (PORTA) $0000 Undeﬁned

Port B data (PORTB) $0001 Undeﬁned

Port C data (PORTC) $0002 PC2/

ECLK Undeﬁned

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undeﬁned

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EEPROM/ECLK control $0007 0000ECLK E1ERA E1LAT E1PGM 0000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR (1) INTP INTN INTE SFA SFB SM WDOG (2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undeﬁned

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undeﬁned

Input capture high 1 $0014 Undeﬁned

Input capture low 1 $0015 Undeﬁned

Output compare high 1 $0016 Undeﬁned

Output compare low 1 $0017 Undeﬁned

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undeﬁned

Input capture low 2 $001D Undeﬁned

Output compare high 2 $001E Undeﬁned

Output compare low 2 $001F Undeﬁned

Options (OPTR)(3) $0100 EE1P SEC Not affected

TPG

160

05B6Book Page 4 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

C-1

MC68HC705B5

The MC68HC705B5 is a de vice similar to the MC68HC05B6, b ut with the 6 kbytes ROM and 256

bytes EEPROM replaced by a single EPROM array. In addition, the self-check routines available

on the MC68HC05B6 are replaced by bootstrap ﬁrmware. The MC68HC705B5 is intended to

operate as a one time progr ammable (O TP) version of the MC68HC05B6 without EEPR OM or the

MC68HC05B4, meaning that the application program can never be erased once it has been

loaded into the EPROM. The entire MC68HC05B6 data sheet applies to the MC68HC705B5, with

the exceptions outlined in this appendix.

C.1 Features

• 6206 bytes EPROM (including 14 bytes User vectors)

• No EEPROM

• Bootstrap ﬁrmware

• Simultaneous programming of up to 4 bytes

• Data protection for program code

• Optional pull-down resistors on port B and port C

• MC68HC05B6 mask options are programmable using control bits held in the options register

• 52-pin PLCC and 56-pin SDIP packages

• High speed version not available

TPG

161

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

MOTOROLA

C-2 MC68HC05B6

Rev. 4

MC68HC705B5

Figure C-1 MC68HC705B5 block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

programmable

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

176 bytes

RAM

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP6

256 bytes

EPROM1

6206 bytes

÷ 2 / ÷32

PLMA D/A

PLMB D/A

8-bit

496 bytes

bootstrap ROM

EPROM

(including 14 bytes

User vectors)

TPG

162

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

C-3

MC68HC705B5

Figure C-2 Memory map of the MC68HC705B5

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000 I/O

(32 bytes)

$0020

$00C0

$0100

$1FF0

Stack

RAM

(176 bytes)

$0300

$0200

$1F00

$0050

Port A data direction register

Port B data direction register

Port C data direction register

EPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Page 0 User

EPROM

(48 bytes)

Bootstrap ROMI

(256 bytes)

User EPROM

(5888 bytes)

Bootstrap ROMII

(240 bytes)

$0800

User EPROM1

(256 bytes)

$1EFEOptions register

Reserved

MC68HC705B5 Registers

Options register

$1EFE

User vectors

(14 bytes)

$1FF2–3 SCI

Timer overﬂow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$1FF2–3

TPG

163

05B6Book Page 3 Tuesday, April 6, 1999 8:24 am

MOTOROLA

C-4 MC68HC05B6

Rev. 4

MC68HC705B5

(1) This bit reﬂects the state of the EPP bit in the options register ($1EFE) at reset.

(2) This bit is set each time the device is powered-on.

(3) The state of the WDOG bit after reset depends on the mask option selected; ‘1’ = watchdog enabled and ‘0’ = watchdog disabled.

(4) Because this register is implemented in EPROM, reset has no effect on the state of the individual bits.

Table C-1 Register outline

reset

Port A data (PORTA) $0000 Undeﬁned

Port B data (PORTB) $0001 Undeﬁned

Port C data (PORTC) $0002 PC2/

ECLK Undeﬁned

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undeﬁned

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EPROM/ECLK control $0007 EPPT(1) ELAT EPGM ECLK u?00 0uuu

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR (2) INTP INTN INTE SFA SFB SM WDOG (3) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL uuuu

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 uuuu

Input capture high 1 $0014 Undeﬁned

Input capture low 1 $0015 Undeﬁned

Output compare high 1 $0016 Undeﬁned

Output compare low 1 $0017 Undeﬁned

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undeﬁned

Input capture low 2 $001D Undeﬁned

Output compare high 2 $001E Undeﬁned

Output compare low 2 $001F Undeﬁned

Options (OPTR)(4) $1EFE EPP 0 RTIM RWAT WWAT PBPD PCPD Not affected

TPG

164

05B6Book Page 4 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

C-5

MC68HC705B5

C.2 EPROM

The MC68HC705B5 has a total of 6206 bytes of EPROM, 256 bytes being reserved for the

EPROM1 array (see Figure C-2). The EPP bit (EPROM protect) is not operative on the EPROM1

array, making it possible to program it after the main EPROM has been programmed and

protected. The reset and interr upt vectors are located at $1FF2-$1FFF and the EPROM control

The EPROM arr ay is supplied b y the VPP6 pin in both read and programming modes. Typically the

user’s software will be loaded in a programming board where VPP6 is controlled by one of the

bootstrap loader routines (bootloader mode). It will then be placed in an application where no

programming occurs (user mode). In this case the VPP6 pin should be hardwired to VDD.

An erased EPROM byte reads as $00.

Warning: A minimum VDD voltage must be applied to the VPP6 pin at all times, including

power-on, as a lower voltage could damage the device. Unless otherwise stated,

EPROM programming is guaranteed at ambient (25°C) temperature only

C.2.1 EPROM programming operation

The User program can be used to program some EPROM locations, provided the proper

procedure is followed. In particular, the programming sequence must be running in RAM, as the

EPROM will not be a vailab le for code e xecution while the ELAT bit is set. The VPP6 switching must

occur e xternally, after the EPGM bit is set, for e xample, under the control of a signal gener ated on

a pin by the programming routine.

Note:

Unless the part has a window for reprogramming, only the cumulative progr amming of

bits to logic 1 is possible if multiple programming is made on the same byte.

To allow simultaneous programming of up to 4 b ytes, they m ust be in the same group of addresses

which share the same most signiﬁcant address bits; only the two LSBs can change.

TPG

165

05B6Book Page 5 Tuesday, April 6, 1999 8:24 am

MOTOROLA

C-6 MC68HC05B6

Rev. 4

MC68HC705B5

C.3 EPROM registers

C.3.1 EPROM control register

Bit 7 — Factory use only

This bit is strictly for factory use only and will always read zero.

EPPT — EPROM protect test bit

This bit is a cop y of the EPROM protect bit (EPP) located in the option register. When ELAT is set,

the EPPT bit can be tested by the softw are to chec k if the EPR OM arra y is protected or not, since

the EPROM content is not available when ELAT is set.

POR or external reset modiﬁes this bit to reﬂect the state of the EPP bit in the options register.

ELAT — EPROM programming latch enable bit

1 (set) – When set, this bit allows latching of the address and up to 4 data

bytes for further programming, provided EPGM is zero.

0 (clear) – When cleared, program and interrupt routines can be executed and

data can be read in the EPROM or ﬁrmware ROM.

STOP, power-on and external reset clear this bit.

EPGM — EPROM programming bit

This bit is the EPROM program enable bit. It can be set to ‘1’ to enable programming only after

ELAT is set and at least one byte is written to the EPROM. It is not possible to clear EPGM by

software, but clearing ELAT will always clear EPGM.

ECLK — External clock option bit

See Section 4.3.

(1) This bit is a copy of the EPP bit in the options register at $1EFE and therefore its state on reset will be the same as that for the

EPP bit.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

EPROM/ECLK control $0007 EPPT(1) ELAT EPGM ECLK u?00 0uuu

TPG

166

05B6Book Page 6 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

C-7

MC68HC705B5

C.4 Options register (OPTR)

Note:

This register can only be written to while the device is in bootloader mode.

Bit 7 — Factory use only

Warning: This bit is strictly for factory use only and will always read zero to avoid accidental

damage to the device. Any attempt to write to this bit could result in physical damage.

EPP — EPROM protect

This bit protects the contents of the main EPROM against accidental modiﬁcation; it has no effect

on reading or executing code in the EPROM.

1 (set) – EPROM contents are protected.

0 (clear) – EPROM contents are not protected.

RTIM — Reset time

This bit can modify tPORL, i.e. the time that the RESET pin is kept low follo wing a power-on reset.

This feature is handled in the ROM part via a mask option.

1 (set) – tPORL = 16 cycles.

0 (clear) – tPORL = 4064 cycles.

RWAT — Watchdog after reset

This bit can modify the status of the watchdog counter after reset.

1 (set) – The watchdog will be active immediately following power-on or

external reset (except in bootstrap mode).

0 (clear) – The watchdog system will be disabled after power-on or external

reset.

WWAT — Watchdog during WAIT mode

This bit can modify the status of the watchdog counter during WAIT mode.

(1) This register is implemented in EPROM, therefore reset has no effect on the state of the individual bits.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Options (OPTR)(1) $1EFE EPP 0 RTIM RWAT WWAT PBPD PCPD Not affected

TPG

167

05B6Book Page 7 Tuesday, April 6, 1999 8:24 am

MOTOROLA

C-8 MC68HC05B6

Rev. 4

MC68HC705B5

1 (set) – The watchdog will be active during WAIT mode.

0 (clear) – The watchdog system will be disabled during WAIT mode.

PBPD – Port B pull-down resistors

1 (set) – Pull-down resistors are connected to all 8 pins of port B; the

pull-down, RPD, is active only while the pin is an input.

0 (clear) – No pull-down resistors are connected.

PCPD — Port C pull-down resistors

1 (set) – Pull-down resistors are connected to all 8 pins of port C; the

pull-down, RPD, is active only while the pin is an input.

0 (clear) – No pull-down resistors are connected.

The combination of bit 0 and bit 1 allows the option of pull-do wn resistors on 0, 8 or 16 inputs. This

feature is not available on the MC68HC05B6.

C.5 Bootstrap mode

The 432 bytes of self-check ﬁrmware on the MC68HC05B6 are replaced with 496 bytes of

bootstrap ﬁrmware. The bootstrap ﬁrmware located from $0200 to $02FF and $1F00 to $1FEF can

be used to program the EPROM, to check if the EPROM is erased and to load and execute data

in RAM.

When the MC68HC705B5 is placed in the bootstrap mode, the bootstrap reset vector is fetched

and the bootstrap ﬁrmware starts to execute. Table C-2 shows the conditions required to enter

each le vel of bootstrap mode on the rising edge of RESET. The hold time on the IRQ and TCAP1

pins after the external RESET pin is brought high is two clock cycles.

Table C-2 Mode of operation selection

IRQ pin TCAP1 pin PD2 PD3 PD4 Mode

VSS to VDD VSS to VDD x x x Single chip

+ 9 Volts VDD 0 1 0 Erased EPROM veriﬁcation

+ 9 Volts VDD x 0 0 EPROM parallel bootstrap load

+ 9 Volts VDD x 1 1 EPROM (RAM) serial bootstrap load and execute

+ 9 Volts VDD x 0 1 RAM parallel bootstrap load and execute

x = Don’t care

TPG

168

05B6Book Page 8 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

C-9

MC68HC705B5

The bootstrap program ﬁrst copies part of itself into RAM, as the program cannot be executed in

ROM during veriﬁcation/programming of the EPROM. It then sets the TCMP1 output to a logic high

level.

Figure C-3 Modes of operation ﬂow chart (1 of 2)

TCAP1 set?

IRQ at 9V?

EPROM

erased?

PD2 set?PD3 set?

PD4 set?

Reset

Program EPROM;

parallel load;

green LED ﬂashes

Programming OK?

User mode

Red LED on

Green LED on

Non-user mode

Red LED on Green LED on

Non-user mode

Bootstrap mode

EPROM not erased

EPROM veriﬁed

Parallel EPROM bootstrap

Bad EPROM programming

TPG

169

05B6Book Page 9 Tuesday, April 6, 1999 8:24 am

MOTOROLA

C-10 MC68HC05B6

Rev. 4

MC68HC705B5

Figure C-4 Modes of operation ﬂow chart (2 of 2)

Programming OK?

Negative

address?

PD4 set?

PD3 set?

Transmit last four

programmed locations

Red LED off

Receive address

Receive four data

Execute RAM

program at $0083

Green LED on

Load next RAM

byte

RAM full?

Execute RAM

program at $0050

Program EPROM data

at address; green LED

ﬂashes

Red LED on

Serial EPROM (RAM) bootstrap

Bad EPROM

Bootstrap RAM

programming

TPG

170

05B6Book Page 10 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

C-11

MC68HC705B5

C.5.1 Erased EPROM veriﬁcation

The ﬂowchart in Figure C-3 and Figure C-4 shows that the on-chip bootstr ap routines can be used

to check if the EPROM is erased (all $00s). If a non $00 byte is detected, the red LED stays on

and the routine will stay in a loop. Only when the whole EPROM content is veriﬁed as erased will

the green LED be turned on.

C.5.2 EPROM parallel bootstrap load

When this mode is selected, the EPROM is loaded in increasing address order with non EPROM

segments being skipped by the loader. Simultaneous programming is performed by reading four

bytes of data bef ore actual programming is performed, thus dividing the loading time of the internal

EPROM by four.

When PD2=0, the programming time is set to 5 milliseconds and the prog ram/verify routine takes

approximately 15 seconds.

Parallel data is entered through Port A, while the 13-bit address is output on por t B and PC0 to

PC4. If the data comes from an external EPROM, the handshake can be disabled by connecting

together PC5 and PC6. If the data is supplied via a parallel interf ace, handshaking will be pro vided

by PC5 and PC6 according to the timing diagram of Figure C-5.

During programming, the green LED ﬂashes at about 3 Hz.

Upon completion of the programming operation, the EPROM content is checked against the

e xternal data source. If programming is veriﬁed the green LED sta ys on, while an error causes the

red LED to be turned on. Figure C-6 shows a circuit that can be used to progr am the EPROM (or

to load and execute data in the RAM).

Note:

The entire EPROM can be loaded from the external source; if it is desired to leave a

segment undisturbed, the data for this segment should be all zeros.

Figure C-5 Timing diagram with handshake

Data read Data read

Address

HDSK out

(PC5)

DATA

HDSK in

(PC6)

F29

TPG

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05B6Book Page 11 Tuesday, April 6, 1999 8:24 am

MOTOROLA

C-12 MC68HC05B6

Rev. 4

MC68HC705B5

14 Figure C-6 EPROM(RAM) parallel bootstrap schematic diagram

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

GND OE

VCCPGMVPP

14 22

1262728

+5V

P1 GND

+5V

100µF

22pF 4.0 MHz

1N914

1kΩ

1.0µF

22pF

10MΩ

100kΩ

1N914

RESET RUN

0.01µF

TDO

SCLK

RDI

VRL

TCAP2

PD7

PD6

PD5

PD3

PD2

PD1

PD0

PD4

+5V

3VPP

VPP6

PC7

PC5

PC4

PC3

PC2

PC1

PC0

PC6

A10

A12

A11

A12

A11

A10

HDSK out

HDSK in

Short circuit if

handshake not used

100 kΩ

TCMP1

TCMP2

PLMA

PLMB

470Ω

red LED

green LED

4k7Ω

12 kΩ

BC239C

BC309C

10 kΩ

27C64

VRH

red LED — programming failed

green LED — programming OK

1nF

1N5819

1 kΩ

RAM

EPROM

47µF+

MC68HC705B5

Note:

This circuit is recommended for programming only at 25°C and not for use in the

end application, or at temperatures other than 25°C . If used in the end application,

VPP6 should be tied to VDD to avoid damaging the device.

TPG

172

05B6Book Page 12 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

C-13

MC68HC705B5

C.5.3 EPROM (RAM) serial bootstrap load and execute

The serial routine communicates through the SCI with an external host, typically a PC , by means

of an RS232 link at 9600 baud, 8-bit, no parity and full duplex.

Data f ormat is not ASCII, but 8-bit binary, so a complementary program must be run by the host to

supply the required format. Such a program is available for the IBM PC from Motorola.

The EPROM bootstrap routines are used to customise the OTP EPROM. To increase the speed

of programming, four bytes are programmed in parallel while the data is simultaneously

transmitted and receiv ed in full duplex. This implies that while 4 bytes are being programmed, the

ne xt 4 bytes are received and the preceding 4 b ytes are echoed. The format accepted by the serial

loader is as follows:

[address n high] [address n low] [data(n)] [data (n+1)] [data (n+2)] [data (n+3)]

Address n must have the two LSBs at zero so that n, n+1, n+2 and n+3 hav e identical MSBs. These

blocks of four bytes do not need to be contiguous, as a new address is transmitted for each new

group.

The protocol is as follows:

1 The MC68HC705B5 sends the last two bytes programmed to the host as a

prompt; this allows veriﬁcation by the host of proper programming.

1) In response to the ﬁrst byte prompt, the host sends the ﬁrst address byte.

2) After receiving the ﬁrst address byte, the MC68HC705B5 sends the next

byte programmed.

3) The exchange of data continues until the MC68HC705B5 has sent the four

data bytes and the host has sent the 2 address data b ytes and 4 data b ytes.

4) If the data is non zero, it is programmed at the address provided, while the

next address and bytes are received and the previous data is echoed.

5) Loop to 1.

After reset, the MC68HC705B5 serial bootstrap routine will ﬁrst echo two blocks of four bytes at

$0000, as no data is programmed yet.

If the data sent in is $00, no programming in the EPROM takes place, and the contents of the

accessed location are returned as a prompt. The entire EPROM memory can be read in this

fashion (serial dump). The red LED will be on if the data read from the EPROM is not $00.

Serial RAM loading and execute can be accomplished in this mode. A RAM byte will be written if

the address sent by the host in the serial protocol points to the RAM.

In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see

Table C-3). This allows programmers to use their own service-routine addresses. Each

pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,

because an explicit jump (JMP) opcode is needed to cause the desired jump to the user’s

service-routine address.

TPG

173

05B6Book Page 13 Tuesday, April 6, 1999 8:24 am

MOTOROLA

C-14 MC68HC05B6

Rev. 4

MC68HC705B5

A 10-byte stac k is also reserved at the top of the RAM allo wing, for e xample, one interrupt and two

sub-routine levels.

Program execution is triggered by sending a negative (bit 7 set) high address; execution starts at

address XADR ($0083).

The RAM addresses between $0050 and $0082 are used by the loader and are therefore not

available to the user during serial loading/executing.

Refer to Figure C-7 shows a suitable circuit. Figure C-9 shows address and data bus timing.

C.5.4 RAM parallel bootstrap load and execute

The RAM bootstrap program will star t loading the RAM with external data (e.g. from a 2564 or

2764 EPROM). Bef ore loading a new b yte, the state of the PD4/AN4 pin is check ed; if this pin goes

to level ‘0’, or if the RAM is full, then control is given to the loaded program at address $0050.

If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6

according to Figure C-10. If the data comes from an external EPROM, the handshake can be

disabled by connecting together PC5 and PC6.

Figure C-8 shows a circuit that can be used to load the RAM with shor t test programs. Up to 8

programs can be loaded in turn from the EPROM. Selection is accomplished by means of the

switches connected to the EPROM higher address lines (A8 through A10). If the user program sets

PC0 to level ‘1’, the external EPROM will be disabled, rendering both por t A outputs and port B

inputs available.

The EPROM parallel bootstrap loader circuit (Figure C-6) can also be used, provided VPP is tied

to VDD. The high order address lines will be at zero. The LEDs will stay off.

Table C-3 Bootstrap vector targets in RAM

Vector targets in RAM

SCI interrupt $00E4

Timer overﬂow $00E7

Timer output compare $00EA

Timer input capture $00ED

IRQ $00F0

SWI $00F3

TPG

174

05B6Book Page 14 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

C-15

MC68HC705B5

Figure C-7 EPROM (RAM) serial bootstrap schematic diagram

Red — programming error

Green — programming OK

VPP6

PC7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

P1 GND

+5V

1N914

1kΩ

1.0µF

100kΩ

1N914

RESET RUN

0.01µF

3VPP

PC5

PC4

PC3

PC2

PC1

PC0

PC6

PLMA

PLMB

470Ω

Red LED

Green LED

VRH

22µF

2 x 3KΩ1

1213

22µF

RS232

Connector MAX

232

+5V

9600 BD

8-bit

no parity

22 8 10

41 7

VRL

TCAP2

TCMP1

TCMP2

SCLK

10nF 47µF

PD0

PD4

PD1

PD2

PD5

PD6

PD7

22pF 4.0 MHz

22pF

10MΩ

4k7Ω

12 kΩ

BC239C

BC309C

10 kΩ

1nF

1N5819

1 kΩ

Serial boot

Erase check

47µF+

PD3

RDI

TDO

Erase check

Red — EPROM not erased

Green — EPROM erased

Serial boot

MC68HC705B5

Note:

A minimum VDD voltage must be applied to the VPP6 pin at all times,

including power-on, as a lower voltage could damage the device. Unless

otherwise stated, EPROM programming is guaranteed at ambient (25°C)

temperature only

TPG

175

05B6Book Page 15 Tuesday, April 6, 1999 8:24 am

MOTOROLA

C-16 MC68HC05B6

Rev. 4

MC68HC705B5

14 Figure C-8 RAM parallel bootstrap schematic diagram

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

TCAP2

TCMP2

TCMP1

PLMB

PLMA

SCLK

TDO

RDI

VRH

VRL

PD7

PD6

PD5

PD3

PD2

PD1

PD0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

OSC1

OSC2

TCAP1

IRQ

RESET

PD4

VPP6

VSS

GND OE

A10

A11

A12

VCCPGMVPP

14 22

1262728

+5V

3 x 4.7kΩ

+5V+5V

16 x 100kΩ

P1 GND

+5V

100µF

22pF 4.0 MHz

1N914

1kΩ

1.0µF

22pF

10MΩ

100kΩ

1N914

RESET RUN

0.01µF

2764

+5V 18 x 100 kΩ

MC68HC705B5

TPG

176

05B6Book Page 16 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

C-17

MC68HC705B5

C.5.5 Bootstrap loader timing diagrams

Figure C-9 EPROM parallel bootstrap loader timing diagram

tCOOE

tADE tDHE

Address

Data

tADE tDHE

tCOOE tCOOE tCDDE

tADE max (address to data delay) 5 machine cycles

tDHA min (data hold time) 14 machine cycles

tCOOE (load cycle time) 117 machine cycles < tCOOE < 150 machine cycles

tCDDE (programming cycle time) tCOOE + tPROG (5ms nominal)

1 machine cycle = 1/(2f0(Xtal))

TPG

177

05B6Book Page 17 Tuesday, April 6, 1999 8:24 am

MOTOROLA

C-18 MC68HC05B6

Rev. 4

MC68HC705B5

Figure C-10 RAM parallel loader timing diagram

tADR tDHR

Address

Data

tCR

PD4 tEXR max

tHO

tHI max

PC5 out

PC6 in

tADR max (address to data delay; PC6=PC5) 16 machine cycles

tDHR min (data hold time) 4 machine cycles

tCR (load cycle time; PC6=PC5) 49 machine cycles

tHO (PC5 handshake out delay) 5 machine cycles

tHI max (PC6 handshake in, data hold time) 10 machine cycles

tEXR max (max delay for transition to be

recognised during this cycle; PC6=PC5 30 machine cycles

1 machine cycle = 1/(2f0(Xtal))

TPG

178

05B6Book Page 18 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

C-19

MC68HC705B5

C.6 DC electrical characteristics

Note:

The complete table of DC electrical characteristics can be found in Section 11.2. The

values contained in the f ollo wing table should be used in conjunction with those quoted

in that section.

C.7 Control timing

Note:

The complete table of control timing can be f ound in Section 11.4. The values contained

in the f ollo wing tab le should be used in conjunction with those quoted in that section.

Table C-4 Additional DC electrical characteristics for MC68HC705B5

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic Symbol Min Typ Max Unit

Input current

Port B and port C pull-down (VIN=VIH)IRPD 80 µA

EPROM absolute maximum voltage V PP6 max VDD —18V

EPROM programming voltage V PP6 15.0 15.5 16 V

EPROM programming current I PP6 — — 18 mA

EPROM read voltage V PP6R VDD VDD VDD V

Table C-5 Additional control timing for MC68HC705B5

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = 25° C)

Characteristic Symbol Min Typ Max Unit

EPROM programming time t PROG 5 — 20 ms

05B6Book Page 19 Tuesday, April 6, 1999 8:24 am

MOTOROLA

C-20 MC68HC05B6

Rev. 4

MC68HC705B5

THIS PAGE LEFT BLANK INTENTIONALLY

05B6Book Page 20 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

D-1

MC68HC05B16

The MC68HC05B16 is a device similar to the MC68HC05B6, but with increased RAM, ROM and

self-check ROM sizes. The entire MC68HC05B6 data sheet, including the electrical

characteristics, applies to the MC68HC05B16, with the exceptions outlined in this appendix.

D.1 Features

• 15 kbytes User ROM

• 352 bytes of RAM

• 496 bytes self-check ROM

• 52-pin PLCC, 56-pin SDIP and 64-pin QFP packages

• High speed version available

Maskset errata

This errata section outlines the differences between previously available masksets

(D20J, F62J and G28F) and all other masksets. Unless otherwise stated, the main

body of Appendix D refers to all these other masksets with any diff erences being noted

in this errata section.

• Certain MC68HC05B16 masksets contain the same oscillator circuitry as the

MC68HC05B6 (see Section 2.5.8.3). These are denoted by D20J , F62J and G28F.

TPG

179

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

MOTOROLA

D-2 MC68HC05B6

Rev. 4

MC68HC05B16

D.2 Self-check routines

The self-check routines f or the MC68HC05B16 are identical to those of the MC68HC05B4 with the

following exception.

The count byte on the MC68HC05B16 can be any value up to 256 ($00). The ﬁrst 176 bytes are

loaded into RAM I and the remainder is loaded into RAM II starting at $0250.

Table D-1 Mode of operation selection

IRQ pin TCAP1 pin PD3 PD4 Mode

VSS to VDD VSS to VDD X X Single chip

2VDD VDD 0 X Self check

2VDD VDD 1 0 Serial RAM loader

2VDD VDD 1 1 Jump to any address

TPG

180

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

D-3

MC68HC05B16

Figure D-1 MC68HC05B16 block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP1

256 bytes

EEPROM

Charge pump

÷ 2 / ÷32

PLMA D/A

PLMB D/A

8-bit

15120 bytes

ROM

352 bytes

static RAM

496 bytes

self-check ROM

TPG

181

05B6Book Page 3 Tuesday, April 6, 1999 8:24 am

MOTOROLA

D-4 MC68HC05B6

Rev. 4

MC68HC05B16

D.3 External clock

When using an e xternal clock the OSC1 and OSC2 pins should be driven in antiphase , as sho wn

in Figure D-2. The tOXOV or tILCH speciﬁcations (see Section 11.4) do not apply when using an

exter nal clock input. The equivalent speciﬁcation of the external clock source should be used in

lieu of tOXOV or tILCH.

Figure D-2 Oscillator connections

Ceramic resonator

2 – 4MHz Unit

RS(typ) 10 Ω

C040 pF

C14.3 pF

COSC1 30 pF

COSC2 30 pF

RP1 – 10 MΩ

Q 1250 —

Crystal

2MHz 4MHz Unit

RS(max) 400 75 Ω

C057pF

C1812ƒF

COSC1 15 – 40 15 – 30 pF

COSC2 15 – 30 15 – 25 pF

RP10 10 MΩ

Q 30 000 40 000 —

OSC1 OSC2

MCU

COSC2

COSC1

OSC1 OSC2

MCU

NCExternal

clock

OSC1 OSC2

(d) Typical crystal and ceramic resonator parameters

(b) Crystal equivalent circuit

(a) Crystal/ceramic resonator

oscillator connections

TPG

182

05B6Book Page 4 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

D-5

MC68HC05B16

Figure D-3 Memory map of the MC68HC05B16

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000 I/O

(32 bytes)

$0020

$00C0

$0100

$3FF0

Stack

RAM1

(176 bytes)

$0250

$0200

$3E00

$0050

Port A data direction register

Port B data direction register

Port C data direction register

EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Page 0 User

ROM

(48 bytes)

User ROM

(15104 bytes)

Self-check ROM

(496 bytes)

$0300

Options register

Unprotected (31 bytes)

Protected (224 bytes)

EEPROM

(256 bytes)

$0101

$0120

$0100Options register

Reserved

MC68HC05B16 Registers

RAM11

(176 bytes)

$3DFE

User vectors

(14 bytes)

$3FF2–3 SCI

Timer overﬂow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$3FF4–5

$3FF6–7

$3FF8–9

$3FFA–B

$3FFC–D

$3FFE–F

TPG

183

05B6Book Page 5 Tuesday, April 6, 1999 8:24 am

MOTOROLA

D-6 MC68HC05B6

Rev. 4

MC68HC05B16

(1) This bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

Table D-2 Register outline

reset

Port A data (PORTA) $0000 Undeﬁned

Port B data (PORTB) $0001 Undeﬁned

Port C data (PORTC) $0002 PC2/

ECLK Undeﬁned

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undeﬁned

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EEPROM/ECLK control $0007 0000ECLK E1ERA E1LAT E1PGM 0000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR (1) INTP INTN INTE SFA SFB SM WDOG (2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undeﬁned

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undeﬁned

Input capture high 1 $0014 Undeﬁned

Input capture low 1 $0015 Undeﬁned

Output compare high 1 $0016 Undeﬁned

Output compare low 1 $0017 Undeﬁned

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undeﬁned

Input capture low 2 $001D Undeﬁned

Output compare high 2 $001E Undeﬁned

Output compare low 2 $001F Undeﬁned

Options (OPTR)(3) $0100 EE1P SEC Not affected

TPG

184

05B6Book Page 6 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

E-1

MC68HC705B16

The MC68HC705B16 is a device similar to the MC68HC05B6, but with increased RAM and

15 kbytes of EPROM instead of 6 kbytes of ROM. In addition, the self-check routines available in

the MC68HC05B6 are replaced by bootstrap ﬁrmware. The MC68HC705B16 is an OTPROM

(one-time programmab le R OM) version of the MC68HC05B16, meaning that once the application

program has been loaded in the EPROM it can never be erased. The entire MC68HC05B6 data

sheet applies to the MC68HC705B16, with the exceptions outlined in this appendix.

To ensure correct operation of the MC68HC705B16 after power-on, the device must

be reset a second time after power-on. This can be done in software using the

MC68HC705B16 watchdog.

The following software sub-routine should be used:

RESET2 BSET 0, $0C Start watchdog

STOP STOP causes immediate watchdog

system reset

The interrupt vector at $3FF0 and $3FF1 must be initialised with the RESET2

address value.

TPG

185

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

MOTOROLA

E-2 MC68HC05B6

Rev. 4

MC68HC705B16

E.1 Features

• 15 kbytes EPROM

• 352 bytes of RAM

• 576 bytes bootstrap ROM

• Simultaneous programming of up to 8 bytes of EPROM

• Optional pull-down resistors available on all port B and port C pins

• 52-pin PLCC and 64-pin QFP packages

• High speed version not available

Note:

The electrical characteristics of the MC68HC05B6 as provided in Section 11 do not

apply to the MC68HC705B16. Data speciﬁc to the MC68HC705B16 can be found in this

appendix.

Figure E-1 MC68HC705B16 block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP1

256 bytes

EEPROM

Charge pump

÷ 2 / ÷ 32

PLMA D/A

PLMB D/A

8-bit

15168 bytes

EPROM

352 bytes

static RAM

576 bytes

VPP6

bootstrap ROM

TPG

186

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

E-3

MC68HC705B16

Figure E-2 Memory map of the MC68HC705B16

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000 I/O

(32 bytes)

$0020

$00C0

$0100

$3FF0–1

Stack

RAM1

(176 bytes)

$0250

$0200

$3E00

$0050

Port A data direction register

Port B data direction register

Port C data direction register

E/EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Page 0 User

EPROM

(48 bytes)

User EPROM

(15104 bytes)

Bootstrap ROM11

(496 bytes)

$0300

Options register

Unprotected (31 bytes)

Protected (224 bytes)

EEPROM

(256 bytes)

$0101

$0120

$0100Options register

Reserved

MC68HC705B16 Registers

RAM11

(176 bytes)

$3DFE

$3DFF Mask option register

Mask option register $3DFE

Bootstrap ROM1

(80 bytes)

User vectors

(14 bytes)

$3FF2–3 SCI

Timer overﬂow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$3FF4–5

$3FF6–7

$3FF8–9

$3FFA–B

$3FFC–D

$3FFE–F

TPG

187

05B6Book Page 3 Tuesday, April 6, 1999 8:24 am

MOTOROLA

E-4 MC68HC05B6

Rev. 4

MC68HC705B16

(1) This bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

(4) This register is implemented in EPROM; therefore reset has no effect on the individual bits.

Table E-1 Register outline

reset

Port A data (PORTA) $0000 Undeﬁned

Port B data (PORTB) $0001 Undeﬁned

Port C data (PORTC) $0002 PC2/

ECLK Undeﬁned

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undeﬁned

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EPROM/EEPROM/ECLK control $0007 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR (1) INTP INTN INTE SFA SFB SM WDOG (2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undeﬁned

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undeﬁned

Input capture high 1 $0014 Undeﬁned

Input capture low 1 $0015 Undeﬁned

Output compare high 1 $0016 Undeﬁned

Output compare low 1 $0017 Undeﬁned

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undeﬁned

Input capture low 2 $001D Undeﬁned

Output compare high 2 $001E Undeﬁned

Output compare low 2 $001F Undeﬁned

Options (OPTR)(3) $0100 EE1P SEC Not affected

Mask option register (MOR)(4) $3DFE RTIM RWAT WWAT PBPD PCPD Not affected

TPG

188

05B6Book Page 4 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

E-5

MC68HC705B16

E.2 External clock

When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see

Figure D-2). The tOXOV or tILCH speciﬁcations (see Section E.8) do not apply when using an

exter nal clock input. The equivalent speciﬁcation of the external clock source should be used in

lieu of tOXOV or tILCH.

E.3 EPROM

The MC68HC705B16 memor y map is given in Figure E-2. The device has a total of 15168 bytes

of EPROM (including 14 bytes for User vectors) and 256 bytes of EEPROM.

The EPROM array is supplied by the VPP6 pin in both read and program modes. Typically the

user’ s softw are would be loaded into a prog ramming board where V PP6 is controlled by one of the

bootstrap loader routines. It would then be placed in an application where no programming occurs .

In this case the VPP6 pin should be hardwired to VDD.

Warning: A minimum VDD voltage must be applied to the VPP6 pin at all times, including

power-on. Failure to do so could result in permanent damage to the device. Unless

otherwise stated, EPROM programming is guaranteed at ambient (25°C) temperature

only.

E.3.1 EPROM read operation

The execution of a program in the EPROM address range or a load from the EPROM are both read

operations. The E6LAT bit in the EPROM/EEPR OM control register should be cleared to ‘0’ which

automatically resets the E6PGM bit. In this way the EPROM is read like a normal ROM. Reading

the EPROM with the E6LAT bit set will give data that does not correspond to the actual memory

content. As interrupt vectors are in EPROM, they will not be loaded when E6LAT is set. Similarly,

the bootstrap ROM routines cannot be executed when E6LAT is set. In read mode, the VPP6 pin

must be at the VDD level. When entering the STOP mode, the EPROM is automatically set to the

read mode.

Note:

An erased byte reads as $00.

E.3.2 EPROM program operation

Typically the EPROM will be programmed by the bootstrap routines resident in the on-chip R OM.

However, the user program can be used to program some EPROM locations if the proper

procedure is followed. In particular, the programming sequence must be running in RAM, as the

TPG

189

05B6Book Page 5 Tuesday, April 6, 1999 8:24 am

MOTOROLA

E-6 MC68HC05B6

Rev. 4

MC68HC705B16

EPROM will not be a vailable f or code ex ecution while the E6LAT bit is set. The VPP6 switching must

occur exter nally after the E6PGM bit is set, for example under control of a signal generated on a

pin by the programming routine.

Note:

When the par t becomes a PROM, only the cumulative programming of bits to logic ‘1’

is possible if multiple programming is made on the same byte.

To allow simultaneous programming of up to eight bytes, these bytes must be in the same group

of addresses which share the same most signiﬁcant address bits; only the three least signiﬁcant

bits can change.

E.3.3 EPROM/EEPROM/ECLK control register

E6LAT — EPROM programming latch enable bit

1 (set) – Address and up to eight data bytes can be latched into the EPROM

for further programming providing the E6PGM bit is cleared.

0 (clear) – Data can be read from the EPROM or ﬁrmware R OM; the E6PGM bit

is reset to zero when E6LAT is ‘0’.

STOP, power-on and external reset clear the E6LAT bit.

Note:

After the tERA1 erase time or tPROG1 programming time, the E6LAT bit has to be reset

to zero in order to clear the E6PGM bit.

E6PGM — EPROM program enable bit

This bit is the EPROM program enable bit. It can be set to ‘1’ to enable programming only after

E6LAT is set and at least one byte is written to the EPROM. It is not possib le to clear this bit using

software but clearing E6LAT will always clear E6PGM.

Note:

The E6PGM bit can never be set while the E6LAT bit is at zero.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

EPROM/EEPROM/ECLK control $0007 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000

Table E-2 EPROM control bits description

E6LAT E6PGM Description

0 0 Read/execute in EPROM

1 0 Ready to write address/data to EPROM

1 1 programming in progress

TPG

190

05B6Book Page 6 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

E-7

MC68HC705B16

ECLK

See Section 4.3.

E1ERA — EEPROM erase/programming bit

Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the

EEPROM is for erasing or programming purposes.

1 (set) – An erase operation will take place.

0 (clear) – A programming operation will take place.

Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.

E1LAT — EEPROM programming latch enable bit

1 (set) – Address and data can be latched into the EEPROM for further

program or erase operations, providing the E1PGM bit is cleared.

0 (clear) – Data can be read from the EEPROM. The E1ERA bit and the E1PGM

bit are reset to zero when E1LAT is ‘0’.

STOP, power-on and external reset clear the E1LAT bit.

Note:

After the tERA1 erase time or tPROG1 programming time, the E1LAT bit has to be reset

to zero in order to clear the E1ERA bit and the E1PGM bit.

E1PGM — EEPROM charge pump enable/disable

1 (set) – Internal charge pump generator switched on.

0 (clear) – Internal charge pump generator switched off.

When the charge pump generator is on, the resulting high voltage is applied to the EEPROM arra y .

This bit cannot be set before the data is selected, and once this bit has been set it can only be

cleared by clearing the E1LAT bit.

A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in Table E-3.

Note:

The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.

Table E-3 EEPROM control bits description

E1ERA E1LAT E1PGM Description

0 0 0 Read condition

0 1 0 Ready to load address/data for program/erase

0 1 1 Byte programming in progress

1 1 0 Ready for byte erase (load address)

1 1 1 Byte erase in progress

TPG

191

05B6Book Page 7 Tuesday, April 6, 1999 8:24 am

MOTOROLA

E-8 MC68HC05B6

Rev. 4

MC68HC705B16

E.3.4 Mask option register

RTIM — Reset time

This bit can modify the time tPORL, where the RESET pin is kept low after a power-on reset.

1 (set) – tPORL = 16 cycles.

0 (clear) – tPORL = 4064 cycles.

RWAT — Watchdog after reset

This bit can modify the status of the watchdog counter after reset. Usually, the watchdog system

is disabled after power-on or exter nal reset but when this bit is set, it will be active immediately

after the following resets (except in bootstrap mode).

WWAT — Watchdog during WAIT mode

This bit can modify the status of the watchdog counter in WAIT mode. Normally, the watchdog

system is disabled in WAIT mode but when this bit is set, the watchdog will be active in WAIT mode.

PBPD — Port B pull-down

This bit, when programmed, connects a resistive pull-down on each pin of port B. This pull-down,

RPD, is active on a given pin only while it is an input.

PCPD — Port C pull-down

This bit, when programmed, connects a resistive pull-down on each pin of port C. This pull-down,

RPD, is active on a given pin only while it is an input.

(1) This register is implemented in EPROM; therefore reset has no effect on the individual bits.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Mask option register (MOR)(1) $3DFE RTIM RWAT WWAT PBPD PCPD Not affected

TPG

192

05B6Book Page 8 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

E-9

MC68HC705B16

E.3.5 EEPROM options register (OPTR)

EE1P – EEPROM protect bit

In order to achieve a higher degree of protection, the EEPROM is effectively split into two par ts,

both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to

$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected b y the EE1P bit

in the options register.

1 (set) – Part 2 of the EEPROM array is not protected; all 256 bytes of

EEPROM can be accessed for any read, erase or programming

operations.

0 (clear) – Part 2 of the EEPROM array is protected; any attempt to erase or

program a location will be unsuccessful.

When this bit is set to 1 (erased), the protection will remain until the next power-on or external

reset. EE1P can only be written to ‘0’ when the E1LAT bit in the EEPROM control register is set.

Note:

The EEPROM1 protect function is disabled while in bootstrap mode.

SEC — Secure bit

This bit allows the EPR OM and EEPROM1 to be secured from e xternal access. When this bit is in

the erased state (set), the EPR OM and EEPR OM1 content is not secured and the device may be

used in non user mode. When the SEC bit is programmed to ‘zero’, the EPROM and EEPROM1

content is secured by prohibiting entry to the non user mode. To deactivate the secure bit, the

EPROM has to be er ased by e xposure to a high density ultraviolet light, and the device has to be

entered into the EPROM erase veriﬁcation mode with PD1 set. When the SEC bit is changed, its

new value will have no effect until the next power-on or external reset.

1 (set) – EEPROM/EPROM not protected.

0 (clear) – EEPROM/EPROM protected.

(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Options (OPTR)(1) $0100 EE1P SEC Not affected

TPG

193

05B6Book Page 9 Tuesday, April 6, 1999 8:24 am

MOTOROLA

E-10 MC68HC05B6

Rev. 4

MC68HC705B16

E.4 Bootstrap mode

The 432 bytes of self-chec k ﬁrmware on the MC68HC05B6 are replaced by 576 b ytes of bootstrap

ﬁrmware. A detailed description of the modes of operation within bootstrap mode is given below.

The bootstrap progr am in mask ROM address locations $0200 to $024F and $3E00 to $3FEF can

be used to program the EPROM and the EEPROM, to check if the EPROM is erased or to load

and execute data in RAM.

After reset, while going to the bootstrap mode, the vector located at address $3FEE and $3FEF

(RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap

mode, the IRQ pin should be at + 9V with the TCAP1 pin ‘high’ during transition of the RESET pin

from low to high. The hold time on the IRQ and TCAP1 pins is two clock cycles after the external

RESET pin is brought high.

When the MC68HC705B16 is placed in the bootstrap mode, the bootstr ap reset vector is fetched

and the bootstrap ﬁrmware starts to execute. Table E-4 shows the conditions required to enter

each level of bootstrap mode on the rising edge of RESET.

The bootstrap program ﬁrst copies part of itself in RAM (except ‘RAM parallel load’), as the

program cannot be executed in ROM during v eriﬁcation/programming of the EPROM. It then sets

the TCMP1 output to a logic high level.

Table E-4 Mode of operation selection

IRQ pin TCAP1 pin PD1 PD2 PD3 PD4 Mode

VSS to VDD VSS to VDD xxxxSingle chip

+ 9 Volts VDD 0 0 x 0 Erased EPROM veriﬁcation (EEV)

+ 9 Volts VDD 1000

Erased EPROM v eriﬁcation; erase EEPR OM; EPROM/EEPROM

parallel program/verify

+ 9 Volts VDD 1010

Erased EPROM veriﬁcation; erase EEPROM;

EPROM/EEPROM/ RAM serial bootstrap load and execute

+ 9 Volts VDD x x 0 1 RAM parallel bootstrap load and execute (if SEC bit = 1)

+ 9 Volts VDD x x 1 1 Serial EPROM/EEPROM/RAM bootloader (if SEC = 1)

x = Don’t care

TPG

194

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MC68HC05B6

Rev. 4 MOTOROLA

E-11

MC68HC705B16

Figure E-3 Modes of operation ﬂow chart (1 of 2)

PD3 set?

EEPROM1 erased?

TCAP1 set?

IRQ at 9V?

PD2 set?PD4 set?

Reset

Program EPROM;

parallel load; g reen LED

ﬂashes

User mode

Green LED on

Red LED on

Non-user mode

Red LED on Green LED on

Non-user mode

Bootstrap mode

EPROM not erased

EPROM veriﬁed

Parallel E/EEPROM bootstrap

Bad EPROM programming

PD1 set?

Bulk erase EEPROM1

Red LED on

Red LED off

Erased EPROM veriﬁcation

SEC bit active?

EPROM

erased?

Programming OK?

TPG

195

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MOTOROLA

E-12 MC68HC05B6

Rev. 4

MC68HC705B16

14 Figure E-4 Modes of operation ﬂow chart (2 of 2)

Negative

address?

PD4 set?

PD3 set?

Transmit last four

programmed locations

Receive address

Receive four data

Execute RAM

program at $008B

Green LED on

Load next RAM

byte

RAM1 full?

Execute RAM

program at $0050

Program E/EEPROM

data at address; green

LED ﬂashes

Serial E/EEPROM (RAM) bootstrap

Parallel bootstrap RAM

SEC bit set?

Red LED ﬂashes

TPG

196

05B6Book Page 12 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

E-13

MC68HC705B16

E.4.1 Erased EPROM veriﬁcation

If a non $00 byte is detected, the red LED is turned on and the routine stops (see Figure E-3 and

Figure E-4). Only when the entire EPROM content is v eriﬁed as erased does the green LED s witch

on. PD1 is then chec ked. If PD1=0, the bootstrap program stops here and no progr amming occurs

until such time as a high level is sensed on PD1. If PD1=1, the bootstrap program proceeds to

erase the EEPROM1 for a nominal 100 ms (4.0 MHz crystal). It is then checked for complete

erasure; if a non $FF b yte is detected, the red LED is turned on, and erase is performed a second

time, and so on until total erasure is veriﬁed. At this point, both EPROM and EEPROM1 are

completely erased and the security bit is cleared. The programming operation can then be

perf ormed. A schematic diagr am of the circuit required f or erased EPR OM v eriﬁcation is shown in

Figure E-7.

E.4.2 EPROM/EEPROM parallel bootstrap

Bef ore the parallel bootstrap routines begin, the erased EPROM veriﬁcation program is executed

as described in Section E.4.1. When PD2=0, the programming time is set to 5 milliseconds with

the bootstrap program and verify for the EPROM taking approximately 15 seconds. The EPROM

is loaded in increasing address order with non EPROM segments being skipped by the loader.

Simultaneous programming is performed by reading eight bytes of data before actual

programming is performed, thus the loading time of the internal EPROM is divided by eight.

Parallel data is entered through Port A, while the 14-bit address is output on port B, PC0 to PC4

and TCMP2. If the data comes from an external EPROM, the handshake can be disabled by

connecting together PC5 and PC6. If the data is supplied b y a par allel interface , handshaking will

be provided b y PC5 and PC6 according to the timing diagram of Figure E-5 (see also Figure E-6).

During programming, the green LED will ﬂash at about 3 Hz.

Upon completion of the programming operation, the contents of the EPROM and EEPROM1 are

check ed against the external data source. If programming is v eriﬁed the green LED stays on, while

an error will cause the red LED to be turned on. Figure E-7 is a schematic diagram of a circuit that

can be used to program the EPROM or to load and execute data in the RAM.

Note:

The entire EPROM and EEPROM1 can be loaded from the external source; if it is

desired to leave a segment undisturbed, the data for this segment should be all zeros

for EPROM data and all $FFs for EEPROM1 data.

TPG

197

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MOTOROLA

E-14 MC68HC05B6

Rev. 4

MC68HC705B16

Figure E-5 Timing diagram with handshake

Figure E-6 Parallel EPROM loader timing diagram

Data read Data read

Address

HDSK out

(PC5)

Data

HDSK in

(PC6)

F29

tCOOE

tADE tDHE

Address

Data

tADE tDHE

tCOOE tCOOE tCDDE

tADE max (address to data delay) 5 machine cycles

tDHA min (data hold time) 14 machine cycles

tCOOE (load cycle time) 117 machine cycles < tCOOE < 150 machine cycles

tCDDE (programming cycle time) tCOOE + tPROG (5ms nominal for EPROM; 10ms for EEPROM1))

1 machine cycle = 1/(2f0(Xtal))

TPG

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05B6Book Page 14 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

E-15

MC68HC705B16

Figure E-7 EPROM Parallel bootstrap schematic diagram

VCC

281

VPP PGM

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

GND OE

14 22

+5V

P1 GND

+5V

100µF

22pF

4.0 MHz

1N914

1kΩ

1.0µF

22pF

100kΩ

1N914

RESET RUN

0.01µF

TDO

SCLK

RDI

VRL

TCAP2

PD7

PD6

PD5

PD3

PD2

PD1

PD0

PD4

+5V

3VPP

VPP6

PC7

PC5

PC4

PC3

PC2

PC1

PC0

PC6

A10

A12

A11

A12

A11

A10

HDSK out

HDSK in

Short circuit if

handshake not used

100 kΩ

TCMP1

TCMP2

PLMA

PLMB

470Ω

red LED

green LED

4k7Ω

12 kΩ

BC239C

BC309C

10k Ω

27C128

VRH

red LED — programming failed

green LED — programming OK

1nF

1N5819

1 kΩ

RAM

EPROM

green LED — EPROM erased

47µF+

Erase check & boot

EPROM erase

check

VPP1

red LED — EPROM not erased

Boot

Erase check

A13

MC68HC705B16

MCU

Note:

This circuit is recommended for programming only at 25°C and not for use in the

end application, or at temperatures other than 25°C . If used in the end application,

VPP6 should be tied to VDD to avoid damaging the device.

TPG

199

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MOTOROLA

E-16 MC68HC05B6

Rev. 4

MC68HC705B16

E.4.3 EEPROM/EPROM/RAM serial bootstrap

For erased EPROM veriﬁcation, PD4 must be at ‘0’. In this case, erased EPROM veriﬁcation

executes as described in Section E.4.1 before control is given to the serial routine.

If PD4 is at ‘1’, the program initially checks the state of the security bit. If the security bit is active

(‘0’), the program will not enter serial bootstrap and the red LED will ﬂash. Otherwise the ser ial

bootstrap program will be executed according to Figure E-3 and Figure E-4.

The serial routine communicates through the SCI with an external host, typically a PC , by means

of an RS232 link at 9600 baud, 8-bit, no parity and full duplex. Refer to Figure E-8 for a schematic

diagram of a suitable circuit.

Note:

Data f ormat is not ASCII, but 8-bit binary, so a complementary program m ust be run by

the host to supply the required f ormat. Such a prog ram is av ailab le for the IBM PC from

Motorola.

The EPROM bootstrap routines are used to customise the OTP EPROM. To increase the speed

of programming the 15 kbytes, four bytes are programmed while the data is simultaneously

transmitted bac k and forward in full duplex. This implies that while 4 b ytes are being prog r ammed

the next 4 bytes are received and the preceding 4 bytes are echoed. The format accepted by the

serial loader is as follows:

1) EPROM locations

[address n high] [address n low] [data(n)] [data (n+1)] [data (n+2)] [data (n+3)]

Address n must ha v e the tw o least signiﬁcant bits at z ero so that n, n+1, n+2 and n+3

have identical most signiﬁcant bits. These blocks of four bytes do not need to be

contiguous, as a new address is transmitted for each new group.

2) EEPROM1 locations

[address n high] [address n low] [data(n)] [dumm y data 1] [dummy data 2] [dumm y data 3]

The same four byte protocol of data exchange is used, but only the ﬁrst data value is

programmed at address n. The three f ollo wing dumm y data v alues must be sent to be

in agreement with the protocol, but are not signiﬁcant.

The protocol is as follows:

1) The MC68HC705B16 sends the last two bytes progr ammed to the host as a

prompt; this also allows the host to verify that programming has been carried

out correctly.

2) In response to the ﬁrst byte prompt, the host sends the ﬁrst address byte.

3) After receiving the ﬁrst address byte, the MC68HC705B16 sends the next

byte programmed.

TPG

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05B6Book Page 16 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

E-17

MC68HC705B16

Figure E-8 RAM/EPROM/EEPROM serial bootstrap schematic diagram

Green LED — programming ended

Flashing green LED — programming

VPP6

PC7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

P1 GND

+5V

1N914

1kΩ

1.0µF

100kΩ

1N914

RESET RUN

0.01µF

3VPP

PC5

PC4

PC3

PC2

PC1

PC0

PC6

PLMA

PLMB

470Ω

Red LED

Green LED

VRH

22µF

2 x 3KΩ1

1213

22µF

RS232

connector MAX

232

+5V

9600 BD

8-bit

no parity

22 8 10

41 7

VRL

TCAP2

TCMP1

TCMP2

SCLK

10nF 47µF

PD0

PD4

PD1

PD2

PD5

PD6

PD7

22pF 4.0 MHz

22pF

4k7Ω

12 kΩ

BC239C

BC309C

10k Ω

1nF

1N5819

1 kΩ

Serial boot

Erase check

47µF+

PD3

RDI

TDO

Erase check

Red LED — EPROM not erased

Green LED — EPROM erased

Serial boot &

serial boot

Erase check and serial boot

EPROM erase check

VPP1

U2 MC68HC705B16

MCU (socket)

Note:

A minimum VDD voltage must be applied to the VPP6 pin at all times,

including power-on, as a lower voltage could damage the device. Unless

otherwise stated, EPROM programming is guaranteed at ambient (25°C)

temperature only

TPG

201

05B6Book Page 17 Tuesday, April 6, 1999 8:24 am

MOTOROLA

E-18 MC68HC05B6

Rev. 4

MC68HC705B16

4) The exchange of data continues until the MC68HC705B16 has sent the f our

data bytes and the host has sent the 2 address data b ytes and 4 data b ytes.

5) If the data is different from $00 for EPROM or $FF for EEPROM, it is

programmed at the address pro vided, while the ne xt address and bytes are

received and the previous data is echoed.

6) Loop to 1.

After reset, the MC68HC705B16 serial bootstrap routine will ﬁrst echo two blocks of four bytes at

$00, as no data is programmed yet.

If the data received is $00 for EPROM locations or $FF for EEPROM locations, no programming

in the EPROM and EEPR OM1 takes place, and the contents of the accessed location are returned

as a prompt. The entire EPROM/EEPROM memory can be read in this fashion (serial dump).

Warning: When using this function with a programmed device, the device must be placed into

RAM/EPROM/EEPR OM serial bootstrap mode without EPR OM erase chec k (PD4 = 1).

Serial RAM loading and execute can be accomplished in this mode. A RAM byte will be written if

the address sent by the host in the serial protocol points to the RAM.

RAM bytes $008B–$00E3 and $0250–$02ED are a vailable f or user test programs. A 10-byte stack

resides at the top of RAM I, allowing, for example, one interrupt and two sub-routine levels. The

RAM addresses between $0050 and $008A are used b y the loader and are therefore not a vailable

to the user during serial loading/executing.

If the SEC bit is at ‘1’, program execution is triggered by sending a negative (bit 7 set) high address;

execution starts at address XADR ($008B).

In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see

Table E-5). This allows programmers to use their own service-routine addresses. Each

pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,

because an e xplicit jump (JMP) opcode is needed to cause the desired jump to the user’s service

routine address.

Table E-5 Bootstrap vector targets in RAM

Vector targets in RAM

SCI interrupt $02EE

Timer overﬂow $02F1

Timer output compare $02F4

Timer input capture $02F7

IRQ $02FA

SWI $02FD

TPG

202

05B6Book Page 18 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

E-19

MC68HC705B16

E.4.4 RAM parallel bootstrap

The program ﬁrst checks the state of the security bit. If the SEC bit is active, i.e. ‘0’, the program

will not enter the RAM bootstrap mode and the red LED will ﬂash. Otherwise the RAM bootstrap

program will start loading the RAM with external data (e.g. from a 2564 or 2764 EPROM). Before

loading a new byte the state of the PD4/AN4 pin is checked. If this pin goes to level ‘0’, or if the

RAM is full, then control is given to the loaded program at address $0050. See Figure E-3 and

Figure E-4.

If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6

according to Figure E-9. If the data comes from an external EPROM, the handshake can be

disabled by connecting together PC5 and PC6.

Figure E-10 provides a schematic diagram of a circuit that can be used to load the RAM with short

test programs. Up to 8 programs can be loaded in turn from the EPROM. Selection is

accomplished by means of the switches connected to the EPROM higher address lines (A8

through A10). If the user prog r am sets PC0 to lev el ‘1’, this will disable the e xternal EPROM, thus

rendering both port A output and port B input available. The EPROM parallel bootstrap loader

schematic can also be used (Figure E-7), provided VPP is at VDD level. The high order address

lines will be at zero. The LEDs will stay off.

Figure E-9 Parallel RAM loader timing diagram

tADR tDHR

Address

Data

PD4 tEXR max

tHO

tHI max

PC5 out

PC6 in

tADR max (address to data delay; PC6=PC5) 16 machine cycles

tDHR min (data hold time) 4 machine cycles

tCR (load cycle time; PC6=PC5) 49 machine cycles

tHO (PC5 handshake out delay) 5 machine cycles

tHI max (PC6 handshake in, data hold time) 10 machine cycles

tEXR max (max delay for transition to be recognised during this cycle; PC6=PC5 30 machine cycles

1 machine cycle = 1/(2f0(Xtal))

TPG

203

05B6Book Page 19 Tuesday, April 6, 1999 8:24 am

MOTOROLA

E-20 MC68HC05B6

Rev. 4

MC68HC705B16

E.4.4.1 Jump to start of RAM ($0050)

PD4 must be high during the ﬁrst 49 program cycles and pulled low before the 68th cycle for

immediate jump execution at address $0050.

Figure E-10 RAM parallel bootstrap schematic diagram

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

TCAP2

TCMP2

TCMP1

PLMB

PLMA

SCLK

TDO

RDI

VRH

VRL

PD7

PD6

PD5

PD3

PD2

PD1

PD0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

OSC1

OSC2

TCAP1

IRQ

RESET

PD4

VPP6

VSS

GND OE

A10

A11

A12

VCCPGMVPP

14 22

1262728

+5V

3 x 4.7kΩ

+5V

16 x 100kΩ

P1 GND

+5V

100µF

22pF 4.0 MHz

1N914

1kΩ

1.0µF

22pF

100kΩ

1N914

RESET RUN

0.01µF

2764

+5V 18 x 100 kΩ

VPP1

U2 MC68HC705B16

MCU (socket)

TPG

204

05B6Book Page 20 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

E-21

MC68HC705B16

E.5 Absolute maximum ratings

Note:

This device contains circuitry designed to protect against damage due to high

electrostatic voltages or electric ﬁelds. However, it is recommended that normal

precautions be taken to a void the application of an y voltages higher than those giv en in

the maximum ratings table to this high impedance circuit. For maximum reliability all

unused inputs should be tied to either VSS or VDD.

(1) All voltages are with respect to V

SS.

(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.

Table E-6 Absolute maximum ratings

Rating Symbol Value Unit

Supply voltage(1) VDD – 0.5 to +7.0 V

Input voltage (Except VPP1 and VPP6)V

IN VSS – 0.5 to VDD + 0.5 V

Input voltage

– Self-check mode (IRQ pin only) VIN VSS – 0.5 to 2VDD + 0.5 V

Operating temperature range

– Standard (MC68HC705B16)

– Extended (MC68HC705B16C)

– Industrial (MC68HC705B16V)

– Automotive (MC68HC705B16M)

TATL to TH

0 to +70

–40 to +85

–40 to +105

–40 to +125

°C

Storage temperature range TSTG – 65 to +150 °C

Current drain per pin (excluding VDD and VSS)(2)

– Source

– Sink ID

45 mA

TPG

205

05B6Book Page 21 Tuesday, April 6, 1999 8:24 am

MOTOROLA

E-22 MC68HC05B6

Rev. 4

MC68HC705B16

E.6 DC electrical characteristics

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the tr ansient switching

currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 4.2MHz); all inputs 0.2 V from rail; no

DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports conﬁgured as inputs; V

IL = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

Table E-7 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic(1) Symbol Min Typ (2) Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µAVOH

VOL VDD – 0.1

——

0.1 V

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.8

VDD – 0.4

—

—V

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

VOL

— 0.1

0.4

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI VIL VSS — 0.2VDD V

Supply current(3)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

IDD

—

5.0

1.0

1.5

0.9

—

1.5

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK IIL —±0.2 ±1µA

Input current

Port B and port C pull-down (VIN=VIH)I

RPD 80 µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN —±0.2 ±1µA

Input current (– 40 to 125)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN ——±5µA

Capacitance

P orts (as input or output), RESET, TDO, SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

TPG

206

05B6Book Page 22 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

E-23

MC68HC705B16

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the tr ansient switching

currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0MHz); all inputs 0.2 V from rail; no

DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports conﬁgured as inputs; V

IL = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

Table E-8 DC electrical characteristics for 3.3V operation

(VDD = 3.3Vdc ± 10%, VSS = 0Vdc, TA = TL to TH)

Characteristic(1) Symbol Min Typ (2) Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µAVOH

VOL

VDD – 0.1

——

0.1 V

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.3

VDD – 0.1

—

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

VOL

— 0.1

0.2

0.4

0.6

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ ,

RESET, TCAP1, TCAP2, RDI VIL VSS — 0.2VDD V

Supply current(3)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP 0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

IDD

—

2.0

0.8

1.0

0.4

—

1.5

0.5

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK IIL —±0.2 ±1µA

Input current

Port B and port C pull-down (VIN=VIH)I

RPD 80 µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN —±0.2 ±1µA

Input current (– 40 to 125)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN ——±5µA

Capacitance

P orts (as input or output), RESET, TDO, SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

TPG

207

05B6Book Page 23 Tuesday, April 6, 1999 8:24 am

MOTOROLA

E-24 MC68HC05B6

Rev. 4

MC68HC705B16

E.7 A/D converter characteristics

(1) Performance veriﬁed down to 2.5V ∆VR, but accuracy is tested and guaranteed at ∆VR = 5V±10%.

(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

(3) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

Table E-9 A/D characteristics for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V) —± 0.5 LSB

Quantization error Uncertainty due to converter resolution — ± 0.5 LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors —± 1 LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VR(1) Minimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

a. External clock (OSC1, OSC2)

b. Internal RC oscillator —

—32

32 tCYC

µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

a. External clock (OSC1, OSC2)

b. Internal RC oscillator(2) —

—12

12 tCYC

µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(3) Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

TPG

208

05B6Book Page 24 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

E-25

MC68HC705B16

(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

(2) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

Table E-10 A/D characteristics for 3.3V operation

(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V) —± 1 LSB

Quantization error Uncertainty due to converter resolution — ± 1 LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors —± 2 LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VRMinimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

Internal RC oscillator — 32 µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

Internal RC oscillator(1) —12µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(2) Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

TPG

209

05B6Book Page 25 Tuesday, April 6, 1999 8:24 am

MOTOROLA

E-26 MC68HC05B6

Rev. 4

MC68HC705B16

E.8 Control timing

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

(2) Since a 2-bit prescaler in the timer must count four external cycles (t

CYC), this is the limiting

factor in determining the timer resolution.

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to

execute the capture interrupt service routine plus 24 t

CYC.

(4) The minimum period tILIL should not be less than the number of cycle times it takes to

execute the interrupt service routine plus 21 t

CYC.

(5) tOH and tOL should not total less than 238ns.

(6) At a temperature of 85°C

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

Table E-11 Control timing for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option fOSC

fOSC

—

dc 4.2

4.2 MHz

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock fOP

fOP

dc 2.1

2.1 MHz

MHz

Cycle time (see Figure 9-1) tCYC 480 — ns

Crystal oscillator start-up time (see Figure 9-1) t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) t

ILCH 100 ms

RC oscillator stabilization time t

ADRC 5µs

A/D converter stabilization time t

ADON 500 µs

External RESET input pulse width tRL 1.5 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle tPORL

tPORL

4064

16 —

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

tERA

—

EEPROM byte program time (1)

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

tPROG

—

Timer (see Figure E-11)

Resolution(2)

Input capture pulse width

Input capture pulse period

tRESL

tTH, tTL

tTLTL

125

—(3)

—

tCYC

Interrupt pulse width (edge-triggered) t

ILIH 125 — ns

Interrupt pulse period tILIL —(4) —t

CYC

OSC1 pulse width(5) tOH, tOL 90 — ns

Write/Erase endurance(6)(7) — 10000 cycles

Data retention(6)(7) — 10 years

TPG

210

05B6Book Page 26 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

E-27

MC68HC705B16

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

(2) Since a 2-bit prescaler in the timer must count four external cycles (t

CYC), this is the limiting

factor in determining the timer resolution.

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to

execute the capture interrupt service routine plus 24 t

CYC.

(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute

the interrupt service routine plus 21 t

CYC.

(5) tOH and tOL should not total less than 500ns.

(6) At a temperature of 85°C

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

Table E-12 Control timing for 3.3V operation

(VDD = 3.3Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option fOSC

fOSC

—

dc 2.0

2.0 MHz

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock fOP

fOP

—

dc 1.0

1.0 MHz

MHz

Cycle time (see Figure 9-1) tCYC 1000 — ns

Crystal oscillator start-up time (see Figure 9-1) t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) t

ILCH 100 ms

RC oscillator stabilization time t

ADRC 5µs

A/D converter stabilization time t

ADON 500 µs

External RESET input pulse width tRL 1.5 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle tPORL

tPORL

4064

16 —

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

tERA

—

EEPROM byte program time (1)

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

tPROG

—

Timer (see Figure E-11)

Resolution(2)

Input capture pulse width

Input capture pulse period

tRESL

tTH, tTL

tTLTL

250

—(3)

—

tCYC

Interrupt pulse width (edge-triggered) t

ILIH 250 — ns

Interrupt pulse period tILIL —(4) —t

CYC

OSC1 pulse width(5) tOH, tOL 200 — ns

Write/Erase endurance(6)(7) — 10000 cycles

Data retention(6)(7) — 10 years

TPG

211

05B6Book Page 27 Tuesday, April 6, 1999 8:24 am

MOTOROLA

E-28 MC68HC05B6

Rev. 4

MC68HC705B16

E.9 EPROM electrical characteristics

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the

transient switching currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

Figure E-11 Timer relationship

Table E-13 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic(1) Symbol Min Typ (2) Max Unit

EPROM

Absolute maximum voltage

Programming voltage

Programming current

Read voltage

VPP6 max

VPP6

IPP6

VPP6R

VDD

—

VDD

—

15.5

VDD

Table E-14 Control timing for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic Symbol Min Max Unit

EPROM programming time t PROG 520ms

Table E-15 Control timing for 3.3V operation

(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic Symbol Min Max Unit

EPROM programming time t PROG 520ms

External

signal

(TCAP1,

TCAP2)

tTLTL tTH tTL

TPG

212

05B6Book Page 28 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

F-1

MC68HC705B16N

The MC68HC705B16N is a device similar to the MC68HC05B6, but with increased RAM and

15 kbytes of EPROM instead of 6 kbytes of ROM. In addition, the self-check routines available in

the MC68HC05B6 are replaced by bootstrap ﬁrmware. The MC68HC705B16N is an OTPROM

(one-time programmab le R OM) version of the MC68HC05B16, meaning that once the application

program has been loaded in the EPROM it can never be erased. The entire MC68HC05B6 data

sheet applies to the MC68HC705B16N, with the exceptions outlined in this appendix.

The MC68HC705B16N is a new de vice identical to the MC68HC705B16 in its memory

map and functionality, except for the following:

• Bootloader

• Reset pulse width

• Reset twice issue

• Electrical characteristics

On the MC68HC705B16 there was a requirement to reset the device a second time

after power-on. On the MC68HC705B16N this reset twice action is now not required.

The interrupt service routine for the vector at address $3FF0–$3FF1 is no longer

required, as the vector will ne ver be f etched. Howe ver , the interrupt service routine and

vector contents required for the MC68HC705B16 (see Section E, page E–1) can also

be kept on the MC68HC705B16N with no detrimental effect, although they will never

be used.

TPG

213

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

MOTOROLA

F-2 MC68HC05B6

Rev. 4

MC68HC705B16N

F.1 Features

• 15 kbytes EPROM

• 352 bytes of RAM

• 576 bytes bootstrap ROM

• Simultaneous programming of up to 8 bytes of EPROM

• Optional pull-down resistors available on all port B and port C pins

• 52-pin PLCC and 64-pin QFP packages

Note:

The electrical characteristics of the MC68HC05B6 as provided in Section 11 do not

apply to the MC68HC705B16N. Data speciﬁc to the MC68HC705B16N can be f ound in

this appendix.

Figure F-1 MC68HC705B16N block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP1

256 bytes

EEPROM

Charge pump

÷ 2 / ÷ 32

PLMA D/A

PLMB D/A

8-bit

15168 bytes

EPROM

352 bytes

static RAM

576 bytes

VPP6

bootstrap ROM

TPG

214

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

F-3

MC68HC705B16N

Figure F-2 Memory map of the MC68HC705B16N

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000 I/O

(32 bytes)

$0020

$00C0

$0100

$3FF0–1

Stack

RAM1

(176 bytes)

$0250

$0200

$3E00

$0050

Port A data direction register

Port B data direction register

Port C data direction register

E/EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Page 0 User

EPROM

(48 bytes)

User EPROM

(15104 bytes)

Bootstrap ROM11

(496 bytes)

$0300

Options register

Unprotected (31 bytes)

Protected (224 bytes)

EEPROM

(256 bytes)

$0101

$0120

$0100Options register

Reserved

MC68HC705B16 Registers

RAM11

(176 bytes)

$3DFE

$3DFF Mask option register

Mask option register $3DFE

Bootstrap ROM1

(80 bytes)

User vectors

(14 bytes)

$3FF2–3 SCI

Timer overﬂow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$3FF4–5

$3FF6–7

$3FF8–9

$3FFA–B

$3FFC–D

$3FFE–F

TPG

215

05B6Book Page 3 Tuesday, April 6, 1999 8:24 am

MOTOROLA

F-4 MC68HC05B6

Rev. 4

MC68HC705B16N

(1) This bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

(4) This register is implemented in EPROM; therefore reset has no effect on the individual bits.

Table F-1 Register outline

reset

Port A data (PORTA) $0000 Undeﬁned

Port B data (PORTB) $0001 Undeﬁned

Port C data (PORTC) $0002 PC2/

ECLK Undeﬁned

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undeﬁned

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EPROM/EEPROM/ECLK control $0007 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR (1) INTP INTN INTE SFA SFB SM WDOG (2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undeﬁned

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undeﬁned

Input capture high 1 $0014 Undeﬁned

Input capture low 1 $0015 Undeﬁned

Output compare high 1 $0016 Undeﬁned

Output compare low 1 $0017 Undeﬁned

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undeﬁned

Input capture low 2 $001D Undeﬁned

Output compare high 2 $001E Undeﬁned

Output compare low 2 $001F Undeﬁned

Options (OPTR)(3) $0100 EE1P SEC Not affected

Mask option register (MOR)(4) $3DFE RTIM RWAT WWAT PBPD PCPD Not affected

TPG

216

05B6Book Page 4 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

F-5

MC68HC705B16N

F.2 External clock

When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see

Figure D-2). The tOXOV or tILCH speciﬁcations (see Section F.9) do not apply when using an

exter nal clock input. The equivalent speciﬁcation of the external clock source should be used in

lieu of tOXOV or tILCH.

F.3 RESET pin

When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied

to the RESET input f or a minimum period of 3.0 machine cycles (tCYC). For more information see

Section 9.1.3.

F.4 EPROM

The MC68HC705B16N memory map is given in Figure F-2. The device has a total of 15168 bytes

of EPROM (including 14 bytes for User vectors) and 256 bytes of EEPROM.

The EPROM array is supplied by the VPP6 pin in both read and program modes. Typically the

user’ s softw are would be loaded into a prog ramming board where V PP6 is controlled by one of the

bootstrap loader routines. It would then be placed in an application where no programming occurs .

In this case the VPP6 pin should be hardwired to VDD.

Warning: A minimum VDD voltage must be applied to the VPP6 pin at all times, including

power-on. Failure to do so could result in permanent damage to the device. Unless

otherwise stated, EPROM programming is guaranteed at ambient (25°C) temperature

only.

F.4.1 EPROM read operation

The execution of a program in the EPROM address range or a load from the EPROM are both read

operations. The E6LAT bit in the EPROM/EEPR OM control register should be cleared to ‘0’ which

automatically resets the E6PGM bit. In this way the EPROM is read like a normal ROM. Reading

the EPROM with the E6LAT bit set will give data that does not correspond to the actual memory

content. As interrupt vectors are in EPROM, they will not be loaded when E6LAT is set. Similarly,

the bootstrap ROM routines cannot be executed when E6LAT is set. In read mode, the VPP6 pin

must be at the VDD level. When entering the STOP mode, the EPROM is automatically set to the

read mode.

Note:

An erased byte reads as $00.

TPG

217

05B6Book Page 5 Tuesday, April 6, 1999 8:24 am

MOTOROLA

F-6 MC68HC05B6

Rev. 4

MC68HC705B16N

F.4.2 EPROM program operation

Typically the EPROM will be programmed by the bootstrap routines resident in the on-chip R OM.

However, the user program can be used to program some EPROM locations if the proper

procedure is followed. In particular, the programming sequence must be running in RAM, as the

EPROM will not be a vailable f or code ex ecution while the E6LAT bit is set. The VPP6 switching must

occur exter nally after the E6PGM bit is set, for example under control of a signal generated on a

pin by the programming routine.

Note:

When the par t becomes a PROM, only the cumulative programming of bits to logic ‘1’

is possible if multiple programming is made on the same byte.

To allow simultaneous programming of up to eight bytes, these bytes must be in the same group

of addresses which share the same most signiﬁcant address bits; only the three least signiﬁcant

bits can change.

F.4.3 EPROM/EEPROM/ECLK control register

E6LAT — EPROM programming latch enable bit

1 (set) – Address and up to eight data bytes can be latched into the EPROM

for further programming providing the E6PGM bit is cleared.

0 (clear) – Data can be read from the EPROM or ﬁrmware R OM; the E6PGM bit

is reset to zero when E6LAT is ‘0’.

STOP, power-on and external reset clear the E6LAT bit.

Note:

After the tERA1 erase time or tPROG1 programming time, the E6LAT bit has to be reset

to zero in order to clear the E6PGM bit.

E6PGM — EPROM program enable bit

This bit is the EPROM program enable bit. It can be set to ‘1’ to enable programming only after

E6LAT is set and at least one byte is written to the EPROM. It is not possib le to clear this bit using

software but clearing E6LAT will always clear E6PGM.

Note:

The E6PGM bit can never be set while the E6LAT bit is at zero.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

EPROM/EEPROM/ECLK control $0007 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000

TPG

218

05B6Book Page 6 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

F-7

MC68HC705B16N

ECLK

See Section 4.3.

E1ERA — EEPROM erase/programming bit

Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the

EEPROM is for erasing or programming purposes.

1 (set) – An erase operation will take place.

0 (clear) – A programming operation will take place.

Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.

E1LAT — EEPROM programming latch enable bit

1 (set) – Address and data can be latched into the EEPROM for further

program or erase operations, providing the E1PGM bit is cleared.

0 (clear) – Data can be read from the EEPROM. The E1ERA bit and the E1PGM

bit are reset to zero when E1LAT is ‘0’.

STOP, power-on and external reset clear the E1LAT bit.

Note:

After the tERA1 erase time or tPROG1 programming time, the E1LAT bit has to be reset

to zero in order to clear the E1ERA bit and the E1PGM bit.

E1PGM — EEPROM charge pump enable/disable

1 (set) – Internal charge pump generator switched on.

0 (clear) – Internal charge pump generator switched off.

When the charge pump generator is on, the resulting high voltage is applied to the EEPROM arra y .

This bit cannot be set before the data is selected, and once this bit has been set it can only be

cleared by clearing the E1LAT bit.

A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in Table F-3.

Note:

The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.

Table F-2 EPROM control bits description

E6LAT E6PGM Description

0 0 Read/execute in EPROM

1 0 Ready to write address/data to EPROM

1 1 programming in progress

TPG

219

05B6Book Page 7 Tuesday, April 6, 1999 8:24 am

MOTOROLA

F-8 MC68HC05B6

Rev. 4

MC68HC705B16N

F.4.4 Mask option register

RTIM — Reset time

This bit can modify the time tPORL, where the RESET pin is kept low after a power-on reset.

1 (set) – tPORL = 16 cycles.

0 (clear) – tPORL = 4064 cycles.

RWAT — Watchdog after reset

This bit can modify the status of the watchdog counter after reset. Usually, the watchdog system

is disabled after power-on or exter nal reset but when this bit is set, it will be active immediately

after the following resets (except in bootstrap mode).

WWAT — Watchdog during WAIT mode

This bit can modify the status of the watchdog counter in WAIT mode. Normally, the watchdog

system is disabled in WAIT mode but when this bit is set, the watchdog will be active in WAIT mode.

PBPD — Port B pull-down

This bit, when programmed, connects a resistive pull-down on each pin of port B. This pull-down,

RPD, is active on a given pin only while it is an input.

(1) This register is implemented in EPROM; therefore reset has no effect on the individual bits.

Table F-3 EEPROM control bits description

E1ERA E1LAT E1PGM Description

0 0 0 Read condition

0 1 0 Ready to load address/data for program/erase

0 1 1 Byte programming in progress

1 1 0 Ready for byte erase (load address)

1 1 1 Byte erase in progress

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Mask option register (MOR)(1) $3DFE RTIM RWAT WWAT PBPD PCPD Not affected

TPG

220

05B6Book Page 8 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

F-9

MC68HC705B16N

PCPD — Port C pull-down

This bit, when programmed, connects a resistiv e pull-do wn on each pin of port C . This pull-down,

RPD, is active on a given pin only while it is an input.

F.4.5 EEPROM options register (OPTR)

EE1P – EEPROM protect bit

In order to achieve a higher degree of protection, the EEPROM is effectively split into two par ts,

both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to

$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected b y the EE1P bit

in the options register.

1 (set) – Part 2 of the EEPROM array is not protected; all 256 bytes of

EEPROM can be accessed for any read, erase or programming

operations.

0 (clear) – Part 2 of the EEPROM array is protected; any attempt to erase or

program a location will be unsuccessful.

When this bit is set to 1 (erased), the protection will remain until the next power-on or external

reset. EE1P can only be written to ‘0’ when the E1LAT bit in the EEPROM control register is set.

Note:

The EEPROM1 protect function is disabled while in bootstrap mode.

SEC — Secure bit

This bit allows the EPR OM and EEPROM1 to be secured from e xternal access. When this bit is in

the erased state (set), the EPR OM and EEPR OM1 content is not secured and the device may be

used in non user mode. When the SEC bit is programmed to ‘zero’, the EPROM and EEPROM1

content is secured by prohibiting entry to the non user mode. To deactivate the secure bit, the

EPROM has to be er ased by e xposure to a high density ultraviolet light, and the device has to be

entered into the EPROM erase veriﬁcation mode with PD1 set. When the SEC bit is changed, its

new value will have no effect until the next power-on or external reset.

1 (set) – EEPROM/EPROM not protected.

0 (clear) – EEPROM/EPROM protected.

(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Options (OPTR)(1) $0100 EE1P SEC Not affected

TPG

221

05B6Book Page 9 Tuesday, April 6, 1999 8:24 am

MOTOROLA

F-10 MC68HC05B6

Rev. 4

MC68HC705B16N

F.5 Bootstrap mode

Oscillator divide-by-two is forced in bootstrap mode.

The 432 bytes of self-chec k ﬁrmware on the MC68HC05B6 are replaced by 576 b ytes of bootstrap

ﬁrmware. A detailed description of the modes of operation within bootstrap mode is given below.

The bootstrap progr am in mask ROM address locations $0200 to $024F and $3E00 to $3FEF can

be used to program the EPROM and the EEPROM, to check if the EPROM is erased or to load

and execute data in RAM.

After reset, while going to the bootstrap mode, the vector located at address $3FEE and $3FEF

(RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap

mode, the IRQ pin should be at 2xVDD with the TCAP1 pin ‘high’ during transition of the RESET

pin from low to high. The hold time on the IRQ and TCAP1 pins is two clock cycles after the external

RESET pin is brought high.

When the MC68HC705B16N is placed in the bootstrap mode, the bootstrap reset vector will be

fetched and the bootstrap ﬁrmware will start to execute. Table F-4 shows the conditions required

to enter each level of bootstrap mode on the rising edge of RESET.

The bootstrap program will ﬁrst copy part of itself in RAM (except ‘RAM parallel load’), as the

program cannot be executed in ROM during veriﬁcation/programming of the EPROM. It will then

set the TCMP1 output to a logic high le vel, unlike the MC68HC05B6 which k eeps TCMP1 low . This

can be used to distinguish between the two circuits and, in particular , for selection of the VPP le vel

and current capability.

Table F-4 Mode of operation selection

IRQ pin TCAP1 pin PD1 PD2 PD3 PD4 Mode

VSS to VDD VSS to VDD xxxxSingle chip

2xVDD VDD 0000Erased EPROM veriﬁcation

2xVDD VDD 0010EPROM veriﬁcation;

2xVDD VDD 1000

EPROM veriﬁcation; erase EEPROM;

EPROM/EEPROM parallel program/verify

2xVDD VDD 1010

Erased EPROM veriﬁcation; erase EEPROM;

EPROM parallel program/verify (no E2)

2xVDD VDD 1001Jump to start of RAM ($0051); SEC bit = NON ACTIVE

2xVDD VDD x011

Serial RAM load/ex ecute – similar to MC68HC05B6 but can ﬁll RAM I

and II

x = Don’t care

TPG

222

05B6Book Page 10 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

F-11

MC68HC705B16N

Figure F-3 Modes of operation ﬂow chart (1 of 2)

IRQ at 2xV DD?

Red LED on

TCAP1=V DD?

SEC bit active?

PD3 set?

User mode

Non-user mode

PD4 set?

Jump to RAM

($0051)

PD1 set?

Red LED on

EPROM erased?

Green LED on

Verify EPROM

SEC bit active?

PD3 set? Y

SEC bit active?

EPROM

veriﬁed?

Red LED on N

Serial RAM

load/execute

Red LED on

Erased EPROM

veriﬁcation

Green LED on

Reset

Erased EPROM veriﬁcation

EPROM verify

PD2 set?

Non-user mode Y

PD2 set? Non-user mode

TPG

223

05B6Book Page 11 Tuesday, April 6, 1999 8:24 am

MOTOROLA

F-12 MC68HC05B6

Rev. 4

MC68HC705B16N

14 Figure F-4 Modes of operation ﬂow chart (2 of 2)

Go to $300

(EPROM only)

PD3 set?

Red LED on

Go to $100

(EPROM and EEPROM)

Green LED on

EEPROM erased?

EEPROM byte

erase and verify

Data veriﬁed?

Parallel program

and verify

Parallel program

TPG

224

05B6Book Page 12 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

F-13

MC68HC705B16N

F.5.1 Erased EPROM veriﬁcation

If a non $00 byte is detected, the red LED will be turned on and the routine will stop (see Figure F-3

and Figure F-4). Only when the whole EPR OM content is v eriﬁed as erased will the green LED be

turned on. PD1 is then check ed. If PD1=0, the bootstr ap program stops here and no progr amming

occurs until such time as a high level is sensed on PD1. If PD1 = 1, the bootstrap program

proceeds to erase the EEPR OM1 for a nominal 2.5 seconds (4.0 MHz crystal). It is then checked

f or complete erasure; if any EEPROM b yte is not erased, the prog r am will stop bef ore er asing the

SEC byte. When both EPROM and EEPROM1 are completely erased and the security bit is

cleared the programming oper ation can be performed. A schematic diagr am of the circuit required

for erased EPROM veriﬁcation is shown in Figure F-8.

F.5.2 EPROM/EEPROM parallel bootstrap

Within this mode there are various subsections which can be utilised by correctly conﬁguring the

port pins shown in Table F-4.

The erased EPROM veriﬁcation program will be executed ﬁrst as described in Section F.5.1. The

EPROM prog ramming time is set to 10 milliseconds with the bootstrap program and verify for the

EPROM taking appro ximately 15 seconds. The EPR OM will be loaded in increasing address order

with non EPROM segments being skipped b y the loader . Simultaneous programming is perf ormed

by reading eight bytes of data before actual programming is performed, thus dividing the loading

time of the internal EPROM by 8. If any block of 8 EPROM bytes or 1 EEPROM byte of data is in

the erased state, no programming takes place, thus speeding up the execution time.

Parallel data is entered through Port A, while the 15-bit address is output on port B, PC0 to PC4

and TCMP1 and TCMP2. If the data comes from an external EPROM, the handshake can be

disabled by connecting together PC5 and PC6. If the data is supplied by a parallel interface,

handshake will be provided by PC5 and PC6 according to the timing diagram of Figure F-6 (see

also Figure F-7).

During programming, the green LED will ﬂash at about 3 Hz.

Upon completion of the programming operation, the EPROM and EEPROM1 content will be

checked against the exter nal data source. If programming is veriﬁed the green LED will stay on,

while an error will cause the red LED to be turned on. Figure F-7 is a schematic diagram of a circuit

which can be used to program the EPROM or to load and execute data in the RAM.

Note:

The entire EPROM and EEPROM1 can be loaded from the external source; if it is

desired to leave a segment undisturbed, the data for this segment should be all $00s

for EPROM data and all $FFs for EEPROM1 data.

TPG

225

05B6Book Page 13 Tuesday, April 6, 1999 8:24 am

MOTOROLA

F-14 MC68HC05B6

Rev. 4

MC68HC705B16N

Figure F-5 Timing diagram with handshake

Figure F-6 Parallel EPROM loader timing diagram

Data read Data read

Address

HDSK out

(PC5)

Data

HDSK in

(PC6)

F29

tCOOE

tADE tDHE

Address

Data

tADE tDHE

tCOOE tCOOE tCDDE

tADE max (address to data delay) 5 machine cycles

tDHA min (data hold time) 14 machine cycles

tCOOE (load cycle time) 117 machine cycles < tCOOE < 150 machine cycles

tCDDE (programming cycle time) tCOOE + tPROG (10 ms nominal for EPROM; 10ms for EEPROM1))

1 machine cycle = 1/(2f0(Xtal))

TPG

226

05B6Book Page 14 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

F-15

MC68HC705B16N

Figure F-7 EPROM parallel bootstrap schematic diagram

VCC

281

VPP PGM

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

GND OE

14 22

+5V

P1 GND

+5V

100µF

22pF

4.0 MHz

1N914

1kΩ

1.0µF

22pF

100kΩ

1N914

RESET RUN

0.01µF

TDO

SCLK

RDI

VRL

TCAP2

PD7

PD6

PD5

PD3

PD2

PD1

PD0

PD4

+5V

3VPP

VPP6

PC7

PC5

PC4

PC3

PC2

PC1

PC0

PC6

A10

A12

A11

A12

A11

A10

HDSK out

HDSK in

Short circuit if

handshake not used

100 kΩ

TCMP1

TCMP2

PLMA

PLMB

470Ω

red LED

green LED

4k7Ω

12 kΩ

BC239C

BC309C

10k Ω

27C256

VRH

red LED — programming failed

green LED — programming OK

1nF

1N5819

1 kΩ

EPROM

green LED — EPROM erased

47µF+

Erase verify & boot

EPROM

check

VPP1

red LED — EPROM not erased

Boot

Erase check

A13

MC68HC705B16N

MCU

A14

Note:

This circuit is recommended for programming only at 25°C and not for use in the

end application, or at temperatures other than 25°C . If used in the end application,

VPP6 should be tied to VDD to avoid damaging the device.

EPROM verify

Erase check

& boot

(EPROM only)

Erase check &

boot (EPROM

& EEPROM)

TPG

227

05B6Book Page 15 Tuesday, April 6, 1999 8:24 am

MOTOROLA

F-16 MC68HC05B6

Rev. 4

MC68HC705B16N

F.5.3 Serial RAM loader

This mode is similar to the RAM load/execute program for the MC68HC05B6 described in

Section 2.2, with the additional features listed below. Table F-4 shows the entry conditions

required for this mode.

If the ﬁrst byte is less than $B0, the bootloader behaves exactly as the MC68HC05B6, i.e. count

byte followed by data stored in $0050 to $00FF. If the count byte is larger than RAM I (176 bytes)

then the code continues to ﬁll RAM II. In this case the count byte is ignored and the program

execution begins at $0051 once the total RAM area is ﬁlled or if no data is received for 5

milliseconds.

The user must tak e care when using branches or jumps as his code will be relocated in RAM I and

II. If the user intends to use the stac k in his program, he should send NOP’ s to ﬁll the desired stac k

area.

In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see

Table F-5). This allows programmers to use their own service-routine addresses. Each

pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,

because an explicit jump (JMP) opcode is needed to cause the desired jump to the users

service-routine address.

F.5.3.1 Jump to start of RAM ($0051)

The Jump to start of RAM program will be executed when the device is brought out of reset with

PD1 and PD4 at ‘1’ and PD2 and PD3 at ‘0’.

Table F-5 Bootstrap vector targets in RAM

Vector targets in RAM

SCI interrupt $0063

Timer overﬂow $0060

Timer output compare $005D

Timer input capture $005A

IRQ $0057

SWI $0054

TPG

228

05B6Book Page 16 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

F-17

MC68HC705B16N

Figure F-8 RAM load and execute schematic diagram

Green LED — programming ended

Flashing green LED — programming

VPP6

PC7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

P1 GND

+5V

1N914

1kΩ

1.0µF

100kΩ

1N914

RESET RUN

0.01µF

3VPP

PC5

PC4

PC3

PC2

PC1

PC0

PC6

PLMA

PLMB

470Ω

Red LED

Green LED

VRH

22µF

2 x 3KΩ1

1213

22µF

RS232

Connector MAX

232

+5V

9600 BD

8-bit

no parity

22 8 10

41 7

VRL

TCAP2

TCMP1

TCMP2

SCLK

10nF 47µF

PD0

PD4

PD1

PD2

PD5

PD6

PD7

22pF 4.0 MHz

22pF

4k7Ω

4k7Ω12 kΩ

BC239C

BC309C

10k Ω

1nF

1N5819

1 kΩ

Serial boot

47µF+

PD3

RDI

TDO

Erase check

Red LED — EPROM not erased

Green LED — EPROM erased

Serial boot

Serial RAM

VPP1

MC68HC705B16N

MCU (socket)

Jump to $51

RAM load

& execute

load & execute

Note:

A minimum VDD voltage must be applied to the VPP6 pin at all times,

including power-on, as a lower voltage could damage the device. Unless

otherwise stated, EPROM programming is guaranteed at ambient (25°C)

temperature only

TPG

229

05B6Book Page 17 Tuesday, April 6, 1999 8:24 am

MOTOROLA

F-18 MC68HC05B6

Rev. 4

MC68HC705B16N

Figure F-9 Parallel RAM loader timing diagram

tADR tDHR

Address

Data

tCR

PD4 tEXR max

tHO

tHI max

PC5 out

PC6 in

tADR max (address to data delay; PC6=PC5) 16 machine cycles

tDHR min (data hold time) 4 machine cycles

tCR (load cycle time; PC6=PC5) 49 machine cycles

tHO (PC5 handshake out delay) 5 machine cycles

tHI max (PC6 handshake in, data hold time) 10 machine cycles

tEXR max (max delay for transition to be recognised during this cycle; PC6=PC5 30 machine cycles

1 machine cycle = 1/(2f0(Xtal))

TPG

230

05B6Book Page 18 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

F-19

MC68HC705B16N

F.6 Absolute maximum ratings

Note:

This device contains circuitry designed to protect against damage due to high

electrostatic voltages or electric ﬁelds. However, it is recommended that normal

precautions be taken to a void the application of an y voltages higher than those giv en in

the maximum ratings table to this high impedance circuit. For maximum reliability all

unused inputs should be tied to either VSS or VDD.

(1) All voltages are with respect to V

SS.

(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.

Table F-6 Absolute maximum ratings

Rating Symbol Value Unit

Supply voltage(1) VDD – 0.5 to +7.0 V

Input voltage (Except VPP1 and VPP6)V

IN VSS – 0.5 to VDD + 0.5 V

Input voltage

– Self-check mode (IRQ pin only) VIN VSS – 0.5 to 2VDD + 0.5 V

Operating temperature range

– Standard (MC68HC705B16N)

– Extended (MC68HC705B16NC)

– Industrial (MC68HC705B16NV)

– Automotive (MC68HC705B16NM)

TATL to TH

0 to +70

–40 to +85

–40 to +105

–40 to +125

°C

Storage temperature range TSTG – 65 to +150 °C

Current drain per pin (excluding VDD and VSS)(2)

– Source

– Sink ID

45 mA

TPG

231

05B6Book Page 19 Tuesday, April 6, 1999 8:24 am

MOTOROLA

F-20 MC68HC05B6

Rev. 4

MC68HC705B16N

F.7 DC electrical characteristics

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the tr ansient switching

currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 4.2MHz); all inputs 0.2 V from rail; no

DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports conﬁgured as inputs; V

IL = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

Table F-7 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic(1) Symbol Min Typ (2) Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µAVOH

VOL VDD – 0.1

——

0.1 V

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.8

VDD – 0.4

—

—V

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

VOL

— 0.1

0.4

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI VIL VSS — 0.2VDD V

Supply current(3)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11.2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

IDD

—

5.0

1.0

1.5

0.9

—

1.5

100

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK IIL —±0.2 ±1µA

Input current

Port B and port C pull-down (VIN=VIH)I

RPD 80 µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN —±0.2 ±1µA

Input current (– 40 to 125)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN ——±5µA

Capacitance

P orts (as input or output), RESET, TDO, SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

TPG

232

05B6Book Page 20 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

F-21

MC68HC705B16N

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the tr ansient switching

currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0MHz); all inputs 0.2 V from rail; no

DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports conﬁgured as inputs; V

IL = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

Table F-8 DC electrical characteristics for 3.3V operation

(VDD = 3.3Vdc ± 10%, VSS = 0Vdc, TA = TL to TH)

Characteristic(1) Symbol Min Typ (2) Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µAVOH

VOL

VDD – 0.1

——

0.1 V

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.3

VDD – 0.1

—

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

VOL

— 0.1

0.2

0.4

0.6

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ ,

RESET, TCAP1, TCAP2, RDI VIL VSS — 0.2VDD V

Supply current(3)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP 0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

IDD

—

2.0

0.8

1.0

0.4

—

1.5

0.5

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK IIL —±0.2 ±1µA

Input current

Port B and port C pull-down (VIN=VIH)I

RPD 80 µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN —±0.2 ±1µA

Input current (– 40 to 125)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN ——±5µA

Capacitance

P orts (as input or output), RESET, TDO, SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

TPG

233

05B6Book Page 21 Tuesday, April 6, 1999 8:24 am

MOTOROLA

F-22 MC68HC05B6

Rev. 4

MC68HC705B16N

F.8 A/D converter characteristics

(1) Performance veriﬁed down to 2.5V ∆VR, but accuracy is tested and guaranteed at ∆VR = 5V±10%.

(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

(3) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

Table F-9 A/D characteristics for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V) —± 0.5 LSB

Quantization error Uncertainty due to converter resolution — ± 0.5 LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors —± 1 LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VR(1) Minimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

a. External clock (OSC1, OSC2)

b. Internal RC oscillator —

—32

32 tCYC

µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

a. External clock (OSC1, OSC2)

b. Internal RC oscillator(2) —

—12

12 tCYC

µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(3) Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

TPG

234

05B6Book Page 22 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

F-23

MC68HC705B16N

(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

(2) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

Table F-10 A/D characteristics for 3.3V operation

(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V) —± 1 LSB

Quantization error Uncertainty due to converter resolution — ± 1 LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors —± 2 LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VRMinimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

Internal RC oscillator — 32 µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

Internal RC oscillator(1) —12µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(2) Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

TPG

235

05B6Book Page 23 Tuesday, April 6, 1999 8:24 am

MOTOROLA

F-24 MC68HC05B6

Rev. 4

MC68HC705B16N

F.9 Control timing

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

(2) Since a 2-bit prescaler in the timer must count four external cycles (t

CYC), this is the limiting

factor in determining the timer resolution.

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to

execute the capture interrupt service routine plus 24 t

CYC.

(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute

the interrupt service routine plus 21 t

CYC.

(5) tOH and tOL should not total less than 238ns.

(6) At a temperature of 85°C

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

Table F-11 Control timing for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option fOSC

fOSC

—

dc 4.2

4.2 MHz

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock fOP

fOP

dc 2.1

2.1 MHz

MHz

Cycle time (see Figure 9-1) tCYC 480 — ns

Crystal oscillator start-up time (see Figure 9-1) t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) t

ILCH 100 ms

RC oscillator stabilization time t

ADRC 5µs

A/D converter stabilization time t

ADON 500 µs

External RESET input pulse width tRL 3.0 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle tPORL

tPORL

4064

16 —

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

tERA

—

EEPROM byte program time (1)

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

tPROG

—

Timer (see Figure F-10)

Resolution(2)

Input capture pulse width

Input capture pulse period

tRESL

tTH, tTL

tTLTL

125

—(3)

—

tCYC

Interrupt pulse width (edge-triggered) t

ILIH 125 — ns

Interrupt pulse period tILIL —(4) —t

CYC

OSC1 pulse width(5) tOH, tOL 90 — ns

Write/Erase endurance(6) — 10000 cycles

Data retention(6)(7) — 10 years

TPG

236

05B6Book Page 24 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

F-25

MC68HC705B16N

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

(2) Since a 2-bit prescaler in the timer must count four external cycles (t

CYC), this is the limiting

factor in determining the timer resolution.

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to

execute the capture interrupt service routine plus 24 t

CYC.

(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute

the interrupt service routine plus 21 t

CYC.

(5) tOH and tOL should not total less than 500ns.

(6) At a temperature of 85°C

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

Table F-12 Control timing for 3.3V operation

(VDD = 3.3Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option fOSC

fOSC

—

dc 2.0

2.0 MHz

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock fOP

fOP

—

dc 1.0

1.0 MHz

MHz

Cycle time (see Figure 9-1) tCYC 1000 — ns

Crystal oscillator start-up time (see Figure 9-1) t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) t

ILCH 100 ms

RC oscillator stabilization time t

ADRC 5µs

A/D converter stabilization time t

ADON 500 µs

External RESET input pulse width tRL 3.0 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle tPORL

tPORL

4064

16 —

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

tERA

—

EEPROM byte program time (1)

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

tPROG

—

Timer (see Figure F-10)

Resolution(2)

Input capture pulse width

Input capture pulse period

tRESL

tTH, tTL

tTLTL

250

—(3)

—

tCYC

Interrupt pulse width (edge-triggered) t

ILIH 250 — ns

Interrupt pulse period tILIL —(4) —t

CYC

OSC1 pulse width(5) tOH, tOL 200 — ns

Write/Erase endurance(6)(7) — 10000 cycles

Data retention(6)(7) — 10 years

TPG

237

05B6Book Page 25 Tuesday, April 6, 1999 8:24 am

MOTOROLA

F-26 MC68HC05B6

Rev. 4

MC68HC705B16N

F.10 EPROM electrical characteristics

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the

transient switching currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

Figure F-10 Timer relationship

Table F-13 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic(1) Symbol Min Typ (2) Max Unit

EPROM

Absolute maximum voltage

Programming voltage

Programming current

Read voltage

VPP6 max

VPP6

IPP6

VPP6R

VDD

—

VDD

—

15.5

VDD

Table F-14 Control timing for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic Symbol Min Max Unit

EPROM programming time t PROG 520ms

Table F-15 Control timing for 3.3V operation

(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic Symbol Min Max Unit

EPROM programming time t PROG 520ms

External

signal

(TCAP1,

TCAP2)

tTLTL tTH tTL

TPG

238

05B6Book Page 26 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

G-1

MC68HC05B32

The MC68HC05B32 is a device similar to the MC68HC05B6, but with increased RAM and ROM

sizes. The entire MC68HC05B6 data sheet applies to the MC68HC05B32, with the exceptions

outlined in this appendix.

G.1 Features

• 31248 bytes User ROM

• No page zero ROM

• 528 bytes of RAM

• 52-pin PLCC and 64-pin QFP packages for -40 to +85°C operating temperature range

(extended)

• 56-pin SDIP package for 0 to 70°C operating temperature range

• High speed version not available

TPG

239

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

MOTOROLA

G-2 MC68HC05B6

Rev. 4

MC68HC05B32

Note:

Preliminar y electrical speciﬁcations for the MC68HC05B32 should be taken as being

similar to those f or the MC68HC705B32. When silicon is fully a vailab le , the part will be

re-characterised and new data made available.

G.2 External clock

When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see

Figure D-2). The tOXOV or tILCH speciﬁcations (see Section H.9) do not apply when using an

exter nal clock input. The equivalent speciﬁcation of the external clock source should be used in

lieu of tOXOV or tILCH.

Figure G-1 MC68HC05B32 block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP1

256 bytes

EEPROM

Charge pump

÷ 2 / ÷32

PLMA D/A

PLMB D/A

8-bit

32 kbytes

ROM

528 bytes

static RAM

638 bytes

VPP6

self-check ROM

TPG

240

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

G-3

MC68HC05B32

Figure G-2 Memory map of the MC68HC05B32

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000 I/O

(32 bytes)

$0020

$00C0

$0100

$7FF0

Stack

RAMI

(176 bytes)

$0250

$0200

$0050

Port A data direction register

Port B data direction register

Port C data direction register

EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

User ROM

(31232 bytes)

Bootloader ROMIII

(478 bytes)

$03B0

$7FE0

Options register

Unprotected (31 bytes)

Protected (224 bytes)

EEPROM

(256 bytes)

$0101

$0120

$0100Options register

Reserved

MC68HC05B32 Registers

RAMII

(352 bytes)

$0400

Bootloader ROMI

(80 bytes)

Bootloader ROM vectors

(16 bytes)

Bootloader ROMII

(80 bytes)

$7E00

$7FDE

User vectors

(14 bytes)

$7FF2–3 SCI

Timer overﬂow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$7FF4–5

$7FF6–7

$7FF8–9

$7FFA–B

$7FFC–D

$7FFE–F

TPG

241

05B6Book Page 3 Tuesday, April 6, 1999 8:24 am

MOTOROLA

G-4 MC68HC05B6

Rev. 4

MC68HC05B32

(1) This bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1 = watchdog enabled, 0 = watchdog disabled.

(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

(4) This register is implemented in ROM; therefore reset has no effect on the individual bits.

Table G-1 Register outline

reset

Port A data (PORTA) $0000 Undeﬁned

Port B data (PORTB) $0001 Undeﬁned

Port C data (PORTC) $0002 PC2/

ECLK Undeﬁned

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undeﬁned

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EEPROM/ECLK control $0007 0000ECLK E1ERA E1LAT E1PGM 0000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR (1) INTP INTN INTE SFA SFB SM WDOG (2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undeﬁned

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undeﬁned

Input capture high 1 $0014 Undeﬁned

Input capture low 1 $0015 Undeﬁned

Output compare high 1 $0016 Undeﬁned

Output compare low 1 $0017 Undeﬁned

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undeﬁned

Input capture low 2 $001D Undeﬁned

Output compare high 2 $001E Undeﬁned

Output compare low 2 $001F Undeﬁned

Options (OPTR)(3) $0100 EE1P SEC Not affected

Mask option register (MOR)(4) $7FDE RTIM RWAT WWAT PBPD PCPD Not affected

TPG

242

05B6Book Page 4 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-1

MC68HC705B32

Preliminary

MC68HC705B32

Maskset errata

This errata section outlines the diff erences between two previously available masksets

(D59J and D40J) and all other masksets. Unless otherwise stated, the main body of

Appendix G ref ers to all these other masksets with any differences being noted in this

errata section.

• For the D59J and D40J masksets, the MCU only requires that a logic zero is

applied to the RESET input for 1.5 tCYC.

• For D59J, 16 cycle POR delay option (tPORL) is not available

• For the D59J maskset, oscillator divide ratio DIV10 is forced in Bootstrap mode. On

all other revisions DIV2 is forced.

For the D59J:

The STOP Idd is greater than the expected value of 120µA at 5 volts Vdd at a

temperature of 20°C with the CAN module enab led and in SLEEP mode . Typically the

STOP Idd is in the region of 2.0 milliamps at 20°C.

The fault lies with the design of the EPROM array. When the STOP instruction is

e xecuted, the ne xt opcode in memory is present on the data bus. A f ault in the EPROM

write data latch circuitry causes a latch to be driven to logic 0 on both sides when the

data bus for that bit is logic 1. This results in increasing STOP Idd of 450µA per data

bus bit set to a logic 1. If all data bus bits are set to logic 1 (i.e. next opcode is $FF, STX

0,X) the STOP Idd shall be in the region of 3.6mA.

The minimum ST OP Idd is achie ved b y ensuring the opcode immediately f ollowing the

ST OP instruction is data $00. This corresponds to BRSET 0,ADDRESS,LABEL. If the

label points to the ne xt sequential instruction in memory then this has the effect of a 5

cycle NOP but note that the carry bit in the condition code register may be altered by

the BRSET instruction.

TPG

243

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-2 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

Example

STOP

BRSET 0,$00,NEXT

NEXT any CPU instruction

The address compared may be any address in the page zero memory and the only

restriction is that it should not be a register with ﬂags cleared by reading the register.

The example shows the address compared to be por t A data register and this should

not cause any problems in any applications.

High STOP Idd will be variable dependant upon the opcode following the STOP

instruction. The more bits set in the following opcode, the higher the STOP Idd. The

work around described above ma y be used on an y 68HC05B32 or corrected version of

the 68HC705B32 without problem. It simply adds a 5 cycle delay to the recovery from

ST OP and 3 bytes of additional code per ST OP instruction but may alter the state of the

carry bit in the CCR.

Also for the D59J:

The EEPROM programming circuit only fully supports 16-byte simultaneous

programming mode and does not support single byte programming correctly.

The f ault lies with the design of the EPROM arra y. A f ault in the EPROM write data latch

circuitry causes a latch to be driven to logic 0 on both sides when the data b us for that

bit is logic 1. When the ELAT signal is remov ed, there is a race condition with the EPBS

signal which results in the data bus value being copied to all the EPROM latches.

Since 16-byte simultaneous programming functions correctly, it is a relatively simple

matter to emulate single b yte programming b y ﬁrst initialising all 16 data latches to $00

and then writing the data to be written to the appropriate address.

This problem does not aff ect user application software in normally circumstances since

it only applies to programming the EPROM array. The serial programming software

should always simulate 16-b yte prog r amming. The Motorola software f or prog r amming

the 705B32 from an IBM compatible PC functions in 16 byte programming mode. This

program therefore correctly programs the EPROM.

In normal circumstances this errata does not affect the user application software. This

only affects software that programs the EPROM array. The parallel programming

bootloader software within the 705B32 ROM performs 16-byte programming and so

functions correctly.

TPG

244

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-3

MC68HC705B32

Preliminary

The MC68HC705B32 is an EPROM version of the MC68HC05B32, with the ROM replaced by a

similar amount of EPROM. The entire MC68HC05B6 data sheet applies to the MC68HC705B32,

with the exceptions outlined in this appendix.

H.1 Features

• 31246 bytes user EPROM

• No page zero EPROM at $20–$4F

• 528 bytes of RAM

• 638 bytes bootstrap ROM instead of 432 bytes of self-check ROM

• Simultaneous programming of EPROM with up to 16 bytes of different data

• -40 to +85°C operating temperature range (extended)

• 52-pin PLCC, 56-pin SDIP and 64-pin QFP packages

• High speed version not available

Note:

The electrical characteristics from the MC68HC05B6 data sheet should not be used for

the MC68HC705B32. Data speciﬁc to this device can be found in Section H.7 and

Section H.9.

TPG

245

05B6Book Page 3 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-4 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

Figure H-1 MC68HC705B32 block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP1

256 bytes

EEPROM

Charge pump

÷ 2 / ÷32

PLMA D/A

PLMB D/A

8-bit

32 kbytes

EPROM

528 bytes

static RAM

638 bytes

VPP6

bootstrap ROM

TPG

246

05B6Book Page 4 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-5

MC68HC705B32

Preliminary

Figure H-2 Memory map of the MC68HC705B32

Bootstrap ROM vectors

(16 bytes)

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000 I/O

(32 bytes)

$0020

$00C0

$0100

$7FDE

$7FF0–1

Stack

RAM1

(176 bytes)

$0250

$0200

$0050

Port A data direction register

Port B data direction register

Port C data direction register

E/EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Bootstrap ROMII

(80 bytes)

$03B0

$7FE0

Options register

Unprotected (31 bytes)

Protected (224 bytes)

EEPROM

(256 bytes)

$0101

$0120

$0100Options register

Reserved

MC68HC705B32 Registers

RAM11

(352 bytes)

$0400

Mask option register

Mask option register $7FDE

Bootstrap ROMI

(80 bytes)

User EPROM

(31232 bytes)

Bootstrap ROMIII

(478 bytes)

$7E00

User vectors

(14 bytes)

$7FF2–3 SCI

Timer overﬂow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$7FDF

$7FF4–5

$7FF6–7

$7FF8–9

$7FFA–B

$7FFC–D

$7FFE–F

TPG

247

05B6Book Page 5 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-6 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

(1) This bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

(4) This register is implemented in EPROM; therefore reset has no effect on the individual bits.

Table H-1 Register outline

reset

Port A data (PORTA) $0000 Undeﬁned

Port B data (PORTB) $0001 Undeﬁned

Port C data (PORTC) $0002 PC2/

ECLK Undeﬁned

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undeﬁned

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EPROM/EEPROM/ECLK control $0007 0 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM u000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR (1) INTP INTN INTE SFA SFB SM WDOG (2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undeﬁned

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undeﬁned

Input capture high 1 $0014 Undeﬁned

Input capture low 1 $0015 Undeﬁned

Output compare high 1 $0016 Undeﬁned

Output compare low 1 $0017 Undeﬁned

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undeﬁned

Input capture low 2 $001D Undeﬁned

Output compare high 2 $001E Undeﬁned

Output compare low 2 $001F Undeﬁned

Options (OPTR)(3) $0100 EE1P SEC Not affected

Mask option register (MOR)(4) $7FDE RTIM RWAT WWAT PBPD PCPD Not affected

TPG

248

05B6Book Page 6 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-7

MC68HC705B32

Preliminary

H.2 External clock

When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see

Figure D-2). The tOXOV or tILCH speciﬁcations (see Section H.9) do not apply when using an

exter nal clock input. The equivalent speciﬁcation of the external clock source should be used in

lieu of tOXOV or tILCH.

H.3 RESET pin

When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied

to the RESET input f or a minimum period of 3.0 machine cycles (tCYC). This differs from the 05B6,

05B4, 705B5, 05B8, 05B16, 705B16 and the 05B32, which require 1.5 tCYC. For more inf ormation

see Section 9.1.3.

H.4 EPROM

The MC68HC705B32 memor y map is given in Figure H-2. The device has a total of 31246 bytes

of EPROM. 14 bytes are used for the reset and interrupt vectors from address $7FF2 to $7FFF.

The main EPROM block of 31232 bytes is located from $0400 to $7DFF. One byte of EPROM is

used as an options register and is located at address $7FDE.

The EPROM array is supplied by the VPP6 pin in both read and program modes. Typically the

user’s software will be loaded into a programming board where VPP6 is controlled by one of the

bootstrap loader routines. It will then be placed in an application where no programming occurs.

In this case the VPP6 pin should be hardwired to VDD.

Warning: A minimum VDD voltage must be applied to the VPP6 pin at all times, including

power-on. Failure to do so could result in permanent damage to the device. Unless

otherwise stated, EPROM programming is guaranteed at ambient (25°C) temperature

only.

TPG

249

05B6Book Page 7 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-8 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

H.4.1 EPROM read operation

The execution of a program in the EPROM address range or a load from the EPROM are both read

operations. The E6LAT bit in the EPROM/EEPR OM control register should be cleared to ‘0’ which

automatically resets the E6PGM bit. In this way the EPROM is read like a normal ROM. Reading

the EPROM with the E6LAT bit set will give data that does not correspond to the actual memory

content. As interrupt vectors are in EPROM, they will not be loaded when E6LAT is set. Similarly,

the bootstrap ROM routines cannot be executed when E6LAT is set. In read mode, the VPP6 pin

must be at the VDD level. When entering the STOP mode, the EPROM is automatically set to the

read mode.

Note:

An erased byte reads as $00.

H.4.2 EPROM program operation

Typically, the EPROM will be programmed b y the bootstr ap routines resident in the on-chip R OM.

However, the user program can be used to program some EPROM locations if the proper

procedure is followed. In particular, the programming sequence must be running in RAM, as the

EPROM will not be a vailable f or code ex ecution while the E6LAT bit is set. The VPP6 switching must

occur e xternally after EPGM is set, for e xample under control of a signal generated on a pin b y the

programming routine.

Note:

Unless the part has a window for reprogramming, only the cumulative progr amming of

bits to logic ‘1’ is possible if multiple programming is made on the same byte.

To allow simultaneous programming of up to sixteen b ytes, these b ytes must be in the same group

of addresses which share the same most signiﬁcant address bits; only the four LSBs can change .

H.4.3 EPROM/EEPROM control register

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

EPROM/EEPROM/ECLK control $0007 0 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM u000 0000

TPG

250

05B6Book Page 8 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-9

MC68HC705B32

Preliminary

E6LAT — EPROM programming latch enable bit

1 (set) – Address and up to sixteen data bytes can be latched into the EPROM

for further programming providing the E6PGM bit is cleared. When

programming the EPROM, all other 15 addresses must be latched

with the erased state ($00) or corruption may occur.

0 (clear) – Data can be read from the EPROM or ﬁrmware R OM; the E6PGM bit

is reset to zero when E6LAT is ‘0’.

STOP, power-on and external reset clear the E6LAT bit.

Note:

After the tERA1 erase time or tPROG1 programming time, the E6LAT bit has to be reset

to zero in order to clear the E6PGM bit.

E6PGM — EPROM program enable bit

This bit is the EPROM program enable bit. It can be set to ‘1’ to enable programming only after

E6LAT is set and at least one byte is written to the EPROM. It is not possib le to clear this bit using

software but clearing E6LAT will always clear E6PGM.

Note:

All combinations are not shown in the above table, since the E6PGM bit is cleared when

the E6LAT bit is at zero, and will result in a read condition.

ECLK

See Section 4.3.

E1ERA — EEPROM erase/programming bit

Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the

EEPROM is for erasing or programming purposes.

1 (set) – An erase operation will take place.

0 (clear) – A programming operation will take place.

Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.

Table H-2 EPROM control bits description

E6LAT E6PGM Description

0 0 Read/execute in EPROM

1 0 Ready to write address/data to EPROM

1 1 programming in progress

TPG

251

05B6Book Page 9 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-10 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

E1LAT — EEPROM programming latch enable bit

1 (set) – Address and data can be latched into the EEPROM for further

program or erase operations, providing the E1PGM bit is cleared.

0 (clear) – Data can be read from the EEPROM. The E1ERA bit and the E1PGM

bit are reset to zero when E1LAT is ‘0’.

STOP, power-on and external reset clear the E1LAT bit.

Note:

After the tERA1 erase time or tPROG1 programming time, the E1LAT bit has to be reset

to zero in order to clear the E1ERA bit and the E1PGM bit.

E1PGM — EEPROM charge pump enable/disable

1 (set) – Internal charge pump generator switched on.

0 (clear) – Internal charge pump generator switched off.

When the charge pump generator is on, the resulting high voltage is applied to the EEPROM arra y .

This bit cannot be set before the data is selected, and once this bit has been set it can only be

cleared by clearing the E1LAT bit.

A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in Table H-3.

Note:

The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.

Table H-3 EEPROM control bits description

E1ERA E1LAT E1PGM Description

0 0 0 Read condition

0 1 0 Ready to load address/data for program/erase

0 1 1 Byte programming in progress

1 1 0 Ready for byte erase (load address)

1 1 1 Byte erase in progress

TPG

252

05B6Book Page 10 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-11

MC68HC705B32

Preliminary

H.4.4 Mask option register

RTIM

This bit can modify the time tPORL, where the RESET pin is kept low after a power-on reset.

1 (set) – tPORL = 16 cycles.

0 (clear) – tPORL = 4064 cycles.

RWAT

This bit can modify the status of the watchdog counter after reset. Usually, the watchdog system

is disabled after power-on or exter nal reset but when this bit is set, it will be active immediately

after the following resets (except in bootstrap mode).

WWAT

This bit can modify the status of the watchdog counter in WAIT mode. Normally, the watchdog

system is disabled in WAIT mode but when this bit is set, the watchdog will be active in WAIT mode.

PBPD

This bit, when programmed, connects a resistive pull-down on all 8 pins of port B. This pull-down,

RPD, is active on a given pin only while it is an input.

PCPD

This bit, when programmed, connects a resistiv e pull-do wn on all 8 pins of port C. This pull-do wn,

RPD, is active on a given pin only while it is an input.

(1) Because this register is implemented in EPROM, reset has no effect on the individual bits.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Mask option register (MOR)(1) $7FDE RTIM RWAT WWAT PBPD PCPD Not affected

TPG

253

05B6Book Page 11 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-12 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

H.4.5 Options register (OPTR)

EE1P – EEPROM protect bit

In order to achieve a higher degree of protection, the EEPROM is effectively split into two par ts,

both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to

$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected b y the EE1P bit

of the options register.

1 (set) – Part 2 of the EEPROM array is not protected; all 256 bytes of

EEPROM can be accessed for any read, erase or programming

operations.

0 (clear) – Part 2 of the EEPROM array is protected; any attempt to erase or

program a location will be unsuccessful.

When this bit is set to 1 (erased), the protection will remain until the next power-on or external

reset. EE1P can only be written to ‘0’ when the E1LAT bit in the EEPROM control register is set.

Note:

The EEPROM1 protect function is disabled while in bootstrap mode.

SEC — Secure bit

This bit allows the EPR OM and EEPROM1 to be secured from e xternal access. When this bit is in

the erased state (set), the EPR OM and EEPR OM1 content is not secured and the device may be

used in non user mode. When the SEC bit is programmed to ‘zero’, the EPROM and EEPROM1

content is secured by prohibiting entry to the non user mode. To deactivate the secure bit, the

EPROM has to be er ased by e xposure to a high density ultraviolet light, and the device has to be

entered into the EPROM erase veriﬁcation mode with PD1 set. When the SEC bit is changed, its

new value will have no effect until the next power-on or external reset.

1 (set) – EEPROM/EPROM not protected.

0 (clear) – EEPROM/EPROM protected.

(1) Because this register is implemented in EEPROM, reset has no effect on the individual bits.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Options (OPTR)(1) $0100 EE1P SEC Not affected

TPG

254

05B6Book Page 12 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-13

MC68HC705B32

Preliminary

H.5 Bootstrap mode

Oscillator divide-by-two is forced in bootstrap mode.

The 432 bytes of self-chec k ﬁrmware on the MC68HC05B6 are replaced by 654 b ytes of bootstrap

ﬁrmware. A detailed description of the modes of operation within bootstrap mode is given below.

The bootstrap progr am in mask R OM address locations $0200 to $024F, $03B0 to $3FFF, $7E00

to $7FDD and $7FE0 to $7FEF can be used to program the EPROM and the EEPROM, to check

if the EPROM is erased or to load and execute data in RAM.

After reset, while going to the bootstrap mode, the vector located at address $7FEE and $7FEF

(RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap

mode, the IRQ pin should be at 2xVDD with the TCAP1 pin ‘high’ during transition of the RESET

pin from low to high. The hold time on the IRQ and TCAP1 pins is two clock cycles after the external

RESET pin is brought high.

When the MC68HC705B32 is placed in the bootstrap mode, the bootstrap reset vector will be

fetched and the bootstrap ﬁrmware will start to execute. Table H-4 shows the conditions required

to enter each level of bootstrap mode on the rising edge of RESET.

The bootstrap program will ﬁrst copy part of itself in RAM (except ‘RAM parallel load’), as the

program cannot be executed in ROM during veriﬁcation/programming of the EPROM. It will then

set the TCMP1 output to a logic high le vel, unlike the MC68HC05B6 which k eeps TCMP1 low . This

can be used to distinguish between the two circuits and, in particular , for selection of the VPP le vel

and current capability.

Table H-4 Mode of operation selection

IRQ pin TCAP1 pin PD1 PD2 PD3 PD4 Mode

VSS to VDD VSS to VDD xxxxSingle chip

2xVDD VDD 0 0 0 x Erased EPROM veriﬁcation

2xVDD VDD 1000

EPROM veriﬁcation; erase EEPROM;

EPROM/EEPROM parallel program/verify

2xVDD VDD 0100

Erased EPROM veriﬁcation;

no EEPROM erase if SEC is zero (parallel mode)

2xVDD VDD 1100

Erased EPROM veriﬁcation; erase EEPROM;

EPROM parallel program/verify (no E2)

2xVDD VDD x 1 1 0 Jump to start of RAM ($0051); SEC bit = ACTIVE

2xVDD VDD 0 1 0 1 EPROM and EEPROM v eriﬁcation; SEC bit = ACTIVE (parallel mode)

2xVDD VDD xx11

Serial RAM load/ex ecute – similar to MC68HC05B6 but can ﬁll RAM I,

II and III

x = Don’t care

TPG

255

05B6Book Page 13 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-14 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

Figure H-3 Modes of operation ﬂow chart (1 of 2)

Red LED on

TCAP1=V DD?

SEC bit active?PD3 set?

Reset

User mode

Red LED on

Non-user mode

Bootstrap mode Parallel E/EEPROM bootstrap

PD4 set?

Erased EPROM veriﬁcation

Serial RAM

load/execute

PD2 set?

Jump to RAM

($0051)

PD2 set?

PD1 set?

SEC bit active? Red LED on

PD4 set? Y

EPROM erased?

Green LED on

PD1 set?

Erase EEPROM1

Red LED off

SEC bit active?

IRQ at 2xV DD?

TPG

256

05B6Book Page 14 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-15

MC68HC705B32

Preliminary

Figure H-4 Modes of operation ﬂow chart (2 of 2)

Data veriﬁed?

PD2 set?

Red LED on

ABase address = $400

(EPROM only)

Base address = $100

(EPROM and EEPROM)

Green LED on

PD2 set? NY

Base address = $400

(EPROM only)

Base address = $400

(EPROM only)

TPG

257

05B6Book Page 15 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-16 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

H.5.1 Erased EPROM veriﬁcation

If a non $00 byte is detected, the red LED will be turned on and the routine will stop (see Figure H-3

and Figure H-4). Only when the whole EPR OM content is veriﬁed as erased will the green LED be

turned on. PD1 is then check ed. If PD1=0, the bootstr ap program stops here and no progr amming

occurs until such time as a high level is sensed on PD1. If PD1 = 1, the bootstrap program

proceeds to erase the EEPR OM1 for a nominal 2.5 seconds (4.0 MHz crystal). It is then checked

f or complete erasure; if any EEPROM b yte is not erased, the prog r am will stop bef ore er asing the

SEC byte. When both EPROM and EEPROM1 are completely erased and the security bit is

cleared the programming oper ation can be performed. A schematic diagr am of the circuit required

for erased EPROM veriﬁcation is shown in Figure H-7.

H.5.2 EPROM/EEPROM parallel bootstrap

Within this mode there are various subsections which can be utilised by correctly conﬁguring the

port pins shown in Table H-4.

The erased EPROM veriﬁcation program will be executed ﬁrst as described in Section H.5.1.

When PD2=0, the programming time is set to 5 milliseconds with the bootstr ap program and verify

for the EPROM taking approximately 15 seconds. The EPROM will be loaded in increasing

address order with non EPROM segments being skipped by the loader. Simultaneous

programming is performed by reading sixteen bytes of data before actual programming is

perf ormed, thus dividing the loading time of the internal EPROM b y 16. If an y b loc k of 16 EPR OM

bytes or 1 EEPROM byte of data is in the erased state, no programming takes place, thus speeding

up the execution time.

Parallel data is entered through Port A, while the 15-bit address is output on port B, PC0 to PC4

and TCMP1 and TCMP2. If the data comes from an external EPROM, the handshake can be

disabled by connecting together PC5 and PC6. If the data is supplied by a parallel interface,

handshake will be provided by PC5 and PC6 according to the timing diagram of Figure H-5 (see

also Figure H-6).

During programming, the green LED will ﬂash at about 3 Hz.

Upon completion of the programming operation, the EPROM and EEPROM1 content will be

checked against the exter nal data source. If programming is veriﬁed the green LED will stay on,

while an error will cause the red LED to be turned on. Figure H-7 is a schematic diagram of a circuit

which can be used to program the EPROM or to load and execute data in the RAM.

Note:

The entire EPROM and EEPROM1 can be loaded from the external source; if it is

desired to leave a segment undisturbed, the data for this segment should be all $00s

for EPROM data and all $FFs for EEPROM1 data.

TPG

258

05B6Book Page 16 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-17

MC68HC705B32

Preliminary

Figure H-5 Timing diagram with handshake

Figure H-6 Parallel EPROM loader timing diagram

Data read Data read

Address

HDSK out

(PC5)

Data

HDSK in

(PC6)

F29

tCOOE

tADE tDHE

Address

Data

tADE tDHE

tCOOE tCOOE tCDDE

tADE max (address to data delay) 5 machine cycles

tDHA min (data hold time) 14 machine cycles

tCOOE (load cycle time) 117 machine cycles < tCOOE < 150 machine cycles

tCDDE (programming cycle time) tCOOE + tPROG (5ms nominal for EPROM; 10ms for EEPROM1))

1 machine cycle = 1/(2f0(Xtal))

TPG

259

05B6Book Page 17 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-18 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

Figure H-7 EPROM parallel bootstrap schematic diagram

VCC

281

VPP PGM

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

GND OE

14 22

+5V

P1 GND

+5V

100µF

22pF

4.0 MHz

1N914

1kΩ

1.0µF

22pF

100kΩ

1N914

RESET RUN

0.01µF

TDO

SCLK

RDI

VRL

TCAP2

PD7

PD6

PD5

PD3

PD2

PD1

PD0

PD4

+5V

3VPP

VPP6

PC7

PC5

PC4

PC3

PC2

PC1

PC0

PC6

A10

A12

A11

A12

A11

A10

HDSK out

HDSK in

Short circuit if

handshake not used

100 kΩ

TCMP1

TCMP2

PLMA

PLMB

470Ω

red LED

green LED

4k7Ω

12 kΩ

BC239C

BC309C

10k Ω

27C256

VRH

red LED — programming failed

green LED — programming OK

1nF

1N5819

1 kΩ

RAM

EPROM

green LED — EPROM erased

47µF+

Erase check & boot

EPROM erase

check

VPP1

red LED — EPROM not erased

Boot

Erase check

A13

MC68HC705B32

MCU

A14

Verify

Program

EPROM

Note:

This circuit is recommended for programming only at 25°C and not for use in the

end application, or at temperatures other than 25°C . If used in the end application,

VPP6 should be tied to VDD to avoid damaging the device.

TPG

260

05B6Book Page 18 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-19

MC68HC705B32

Preliminary

H.5.3 Serial RAM loader

This mode is similar to the RAM load/execute program for the MC68HC05B6 described in

Section 2.2, with the additional features listed below. Table H-4 shows the entry conditions

required for this mode.

If the ﬁrst byte is less than $B0, the bootloader behaves exactly as the MC68HC05B6, i.e. count

byte followed by data stored in $0050 to $00FF. If the count byte is larger than RAM I (176 bytes)

then the code continues to ﬁll RAM II then RAM III. In this case the count byte is ignored and the

program ex ecution begins at $0051 once the total RAM area is ﬁlled or if no data is received f or 5

milliseconds.

The user must tak e care when using branches or jumps as his code will be relocated in RAM I, II

and III. If the user intends to use the stac k in his progr am, he should send NOP’ s to ﬁll the desired

stack area.

In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see

Table H-5). This allows programmers to use their own service-routine addresses. Each

pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,

because an explicit jump (JMP) opcode is needed to cause the desired jump to the users

service-routine address.

H.5.3.1 Jump to start of RAM ($0051)

The Jump to start of RAM program will be executed when bring the device out of reset with PD2

and PD3 at ‘1’ and PD4 at ‘0’.

Table H-5 Bootstrap vector targets in RAM

Vector targets in RAM

SCI interrupt $0063

Timer overﬂow $0060

Timer output compare $005D

Timer input capture $005A

IRQ $0057

SWI $0054

TPG

261

05B6Book Page 19 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-20 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

Figure H-8 RAM load and execute schematic diagram

Green LED — programming ended

Flashing green LED — programming

VPP6

PC7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

P1 GND

+5V

1N914

1kΩ

1.0µF

100kΩ

1N914

RESET RUN

0.01µF

3VPP

PC5

PC4

PC3

PC2

PC1

PC0

PC6

PLMA

PLMB

470Ω

Red LED

Green LED

VRH

22µF

2 x 3KΩ1

1213

22µF

RS232

Connector MAX

232

+5V

9600 BD

8-bit

no parity

22 8 10

41 7

VRL

TCAP2

TCMP1

TCMP2

SCLK

10nF 47µF

PD0

PD4

PD1

PD2

PD5

PD6

PD7

22pF 4.0 MHz

22pF

4k7Ω

4k7Ω12 kΩ

BC239C

BC309C

10k Ω

1nF

1N5819

1 kΩ

Serial boot

Erase check

47µF+

PD3

RDI

TDO

Erase check

Red LED — EPROM not erased

Green LED — EPROM erased

Serial boot &

serial boot

Erase check and serial boot

EPROM erase check

VPP1

MC68HC705B32

MCU (socket)

Note:

A minimum VDD voltage must be applied to the VPP6 pin at all times,

including power-on, as a lower voltage could damage the device. Unless

otherwise stated, EPROM programming is guaranteed at ambient (25°C)

temperature only

TPG

262

05B6Book Page 20 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-21

MC68HC705B32

Preliminary

Figure H-9 Parallel RAM loader timing diagram

tADR tDHR

Address

Data

tCR

PD4 tEXR max

tHO

tHI max

PC5 out

PC6 in

tADR max (address to data delay; PC6=PC5) 16 machine cycles

tDHR min (data hold time) 4 machine cycles

tCR (load cycle time; PC6=PC5) 49 machine cycles

tHO (PC5 handshake out delay) 5 machine cycles

tHI max (PC6 handshake in, data hold time) 10 machine cycles

tEXR max (max delay for transition to be recognised during this cycle; PC6=PC5 30 machine cycles

1 machine cycle = 1/(2f0(Xtal))

TPG

263

05B6Book Page 21 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-22 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

H.6 Absolute maximum ratings

Note:

This device contains circuitry designed to protect against damage due to high

electrostatic voltages or electric ﬁelds. However, it is recommended that normal

precautions be taken to a void the application of an y voltages higher than those giv en in

the maximum ratings table to this high impedance circuit. For maximum reliability all

unused inputs should be tied to either VSS or VDD.

(1) All voltages are with respect to V

SS.

(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.

Table H-6 Absolute Maximum ratings

Rating Symbol Value Unit

Supply voltage(1) VDD – 0.5 to +7.0 V

Input voltage (Except VPP1 and VPP6)V

IN VSS – 0.5 to VDD + 0.5 V

Input voltage

– Self-check mode (IRQ pin only) VIN VSS – 0.5 to 2VDD + 0.5 V

Operating temperature range

– Standard (MC68HC705B32)

– Extended (MC68HC705B32C)

TATL to TH

0 to +70

–40 to +85 °C

Storage temperature range TSTG – 65 to +150 °C

Current drain per pin (excluding VDD and VSS)(2)

– Source

– Sink ID

45 mA

TPG

264

05B6Book Page 22 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-23

MC68HC705B32

Preliminary

H.7 DC electrical characteristics

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the tr ansient switching

currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0 MHz); all inputs 0.2 V from rail; no

DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports conﬁgured as inputs; V

IL = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

Table H-7 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, –40 to +85°C)

Characteristic(1) Symbol Min Typ (2) Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µAVOH

VOL VDD – 0.1

——

0.1 V

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

Output high voltage (ILOAD = -300µA)

OSC2

VOH

VDD – 0.8

VDD – 0.4

VDD – 0.3

—

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

Output low voltage (ILOAD = -100µA)

OSC2

VOL

—

0.1

0.4

TBD

0.4

—

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7,OSC1, IRQ ,

RESET, TCAP1, TCAP2, RDI VIL VSS — 0.2VDD V

Supply current(3) (For Guidance Only)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP 0 to 70 (standard)

– 40 to 85 (extended)

IDD

—

1.5

TBD

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK IIL —±0.2 ±1µA

Input current

Port B and port C pull-down (VIN=VIH)I

RPD 80 µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN —±0.2 ±1µA

Input current (– 40 to 85)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN ——±5µA

Capacitance

P orts (as input or output), RESET, TDO, SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

TPG

265

05B6Book Page 23 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-24 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the

transient switching currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

(3) RUN and W AIT IDD: measured using an external square-wa ve cloc k source (f OSC = 2.0 MHz); all inputs 0.2 V

from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).

ST OP /WAIT IDD: all ports conﬁgured as inputs; V

IL = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with

OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

Table H-8 DC electrical characteristics for 3.3V operation

(VDD = 3.3Vdc ± 10%, VSS = 0Vdc, TA = –40 to +85°C)

Characteristic(1) Symbol Min Typ (2) Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µAVOH

VOL VDD – 0.1

——

0.1 V

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.3

VDD – 0.1

—

—V

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

VOL

— 0.1

0.2

0.3

0.6 V

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ ,

RESET, TCAP1, TCAP2, RDI VIL VSS — 0.2VDD V

Supply current(3) (For Guidance Only)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP 0 to 70 (standard)

– 40 to 85 (extended)

IDD

—

1.5

0.5

TBD

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK IIL —±0.2 ±1µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN —±0.2 ±1µA

Input current (– 40 to 125)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN ——±5µA

Capacitance

P orts (as input or output), RESET, TDO, SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

TPG

266

05B6Book Page 24 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-25

MC68HC705B32

Preliminary

H.8 A/D converter characteristics

(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

(2) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

Table H-9 A/D characteristics for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V) —± 0.5 LSB

Quantization error Uncertainty due to converter resolution — ± 0.5 LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors —± 1 LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VRMinimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

a. External clock (OSC1, OSC2)

b. Internal RC oscillator —

—32

32 tCYC

µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

a. External clock (OSC1, OSC2)

b. Internal RC oscillator(1) —

—12

12 tCYC

µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(2) Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

TPG

267

05B6Book Page 25 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-26 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

(2) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

Table H-10 A/D characteristics for 3.3V operation

(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V) —± 1 LSB

Quantization error Uncertainty due to converter resolution — ± 1 LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors —± 2 LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VRMinimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

Internal RC oscillator — 32 µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

Internal RC oscillator(1) —12µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(2) Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

TPG

268

05B6Book Page 26 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-27

MC68HC705B32

Preliminary

H.9 Control timing

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

(2) Since a 2-bit prescaler in the timer must count four external cycles (t

CYC), this is the limiting factor

in determining the timer resolution.

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute

the capture interrupt service routine plus 24 t

CYC.

(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute

the interrupt service routine plus 21 t

CYC.

(5) tOH and tOL should not total less than 238ns.

(6) At a temperature of 85°C

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

Table H-11 Control timing for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option fOSC

fOSC

—

dc 4.2

4.2 MHz

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock fOP

fOP

—

dc 2.1

2.1 MHz

MHz

Cycle time (see Figure 9-1) tCYC 476 — ns

Crystal oscillator start-up time (see Figure 9-1) t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) t

ILCH 100 ms

RC oscillator stabilization time t

ADRC 5µs

A/D converter stabilization time t

ADON 500 µs

External RESET input pulse width tRL 3.0 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle tPORL

tPORL

4064

16 —

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended) tERA

tERA

10 —

—ms

EEPROM byte program time (1)

0 to 70 (standard)

– 40 to 85 (extended) tPROG

tPROG

10 —

—ms

Timer (see Figure H-10)

Resolution(2)

Input capture pulse width

Input capture pulse period

tRESL

tTH, tTL

tTLTL

125

—(3)

—

tCYC

Interrupt pulse width (edge-triggered) t

ILIH 125 — ns

Interrupt pulse period tILIL —(4) —t

CYC

OSC1 pulse width(5) tOH, tOL 90 — ns

Write/Erase endurance(6)(7) — 10000 cycles

Data retention(6)(7) — 10 years

TPG

269

05B6Book Page 27 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-28 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

(2) Since a 2-bit prescaler in the timer must count four external cycles (t

CYC), this is the limiting

factor in determining the timer resolution.

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to

execute the capture interrupt service routine plus 24 t

CYC.

(4) The minimum period tILIL should not be less than the number of cycle times it takes to

execute the interrupt service routine plus 21 t

CYC.

(5) tOH and tOL should not total less than 500ns.

(6) At a temperature of 85°C

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

Table H-12 Control timing for operation at 3.3V

(VDD = 3.3Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option fOSC

fOSC

—

dc 2.0

2.0 MHz

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock fOP

fOP

—

dc 1.0

1.0 MHz

MHz

Cycle time (see Figure 9-1) tCYC 1000 — ns

Crystal oscillator start-up time (see Figure 9-1) t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) t

ILCH 100 ms

RC oscillator stabilization time t

ADRC 5µs

A/D converter stabilization time t

ADON 500 µs

External RESET input pulse width tRL 3.0 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle tPORL

tPORL

4064

16 —

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended) tERA

tERA

30 —

—ms

EEPROM byte program time (1)

0 to 70 (standard)

– 40 to 85 (extended) tPROG

tPROG

30 —

—ms

Timer (see Figure H-10)

Resolution(2)

Input capture pulse width

Input capture pulse period

tRESL

tTH, tTL

tTLTL

250

—(3)

—

tCYC

Interrupt pulse width (edge-triggered) t

ILIH 250 — ns

Interrupt pulse period tILIL —(4) —t

CYC

OSC1 pulse width(5) tOH, tOL 100 — ns

Write/Erase endurance(6)(7) — 10000 cycles

Data retention(6)(7) — 10 years

TPG

270

05B6Book Page 28 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

H-29

MC68HC705B32

Preliminary

H.10 EPROM electrical characteristics

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the

transient switching currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

Figure H-10 Timer relationship

Table H-13 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic(1) Symbol Min Typ (2) Max Unit

EPROM

Absolute maximum voltage

Programming voltage

Programming current

Read voltage

VPP6 max

VPP6

IPP6

VPP6R

VDD

—

VDD

—

15.5

VDD

Table H-14 Control timing for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic Symbol Min Max Unit

EPROM programming time t PROG 520ms

Table H-15 Control timing for 3.3V operation

(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic Symbol Min Max Unit

EPROM programming time t PROG 520ms

External

signal

(TCAP1,

TCAP2)

tTLTL tTH tTL

05B6Book Page 29 Tuesday, April 6, 1999 8:24 am

MOTOROLA

H-30 MC68HC05B6

Rev. 4

MC68HC705B32

Preliminary

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MC68HC05B6

Rev. 4 MOTOROLA

I-1

HIGH SPEED OPERATION 15

TPG

271

HIGH SPEED OPERATION

This section contains the electrical speciﬁcations and associated timing information for high speed

versions of the MC68HC05B6, MC68HC05B8 and MC68HC05B16 (fOSC max = 8 MHz). The

ordering information for these devices is contained in Table I-1.

Note:

The high speed version has the same device title as the standard version. High speed

operation is selected via a check-box on the order form and will be conﬁr med on the

listing veriﬁcation form.

Table I-1 Ordering information

Device title Package Sufﬁx

0 to 70°CSufﬁx

-40 to +85°C

MC68HC05B6 52-pin PLCC FN CFN

64-pin QFP FU CFU

56-pin SDIP B CB

MC68HC05B8 52-pin PLCC FN CFN

64-pin QFP FU CFU

56-pin SDIP B CB

MC68HC05B16 52-pin PLCC FN CFN

64-pin QFP FU CFU

56-pin SDIP B CB

05B6Book Page 1 Tuesday, April 6, 1999 8:24 am

MOTOROLA

I-2 MC68HC05B6

Rev. 4

HIGH SPEED OPERATION

I.1 DC electrical characteristics

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient

switching currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 8.0MHz); all inputs 0.2 V from

rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports conﬁgured as inputs; V

IL = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with

OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

Table I-2 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)

Characteristic(1) Symbol Min Typ (2) Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µAVOH

VOL

VDD – 0.1

——

0.1 V

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.8

—

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

VOL

—

0.4

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ ,

RESET, TCAP1, TCAP2, RDI VIL VSS — 0.2VDD V

Supply current(3)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP 0 to 70 (standard)

– 40 to 85 (extended)

IDD

—

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK IIL ——±1µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected) IIN ——

—±5

±1µA

Capacitance

Ports (as input or output), RESET, TDO , SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

TPG

272

05B6Book Page 2 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

I-3

HIGH SPEED OPERATION 15

I.2 A/D converter characteristics

(1) Performance veriﬁed down to 2.5V ∆VR, but accuracy is tested and guaranteed at ∆VR = 5V±10%.

(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

(3) The external system error caused by input leakage current is approximately equal to the product of R

source and input current. Input current to A/D channel will be dependent on external source impedance

(see Figure 8-2).

Table I-3 A/D characteristics for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through

the A/D transfer characteristics

(VRH = VDD and VRL = 0V) —± 0.5 LSB

Quantization error Uncertainty due to converter resolution — ± 0.5 LSB

Absolute accuracy Diff erence between the actual input voltage and

the full-scale equivalent of the binary code

output code for all errors —± 1 LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VR(1) Minimum difference between VRH and VRL 3—V

Conversion time

Total time to perform a single analog to digital

conversion

a. External clock (OSC1, OSC2)

b. Internal RC oscillator —

—32

32 tCYC

µs

Monotonicity Conversion result never decreases with an

increase in input voltage and has no missing

codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition

time

Analog input acquisition sampling

a. External clock (OSC1, OSC2)

b. Internal RC oscillator(2) —

—12

12 tCYC

µs

Sample/hold

capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(3) Input leakage on A/D pins PD0/AN0–PD7/AN7

VRL, VRH —

—1

1µA

µA

TPG

273

05B6Book Page 3 Tuesday, April 6, 1999 8:24 am

MOTOROLA

I-4 MC68HC05B6

Rev. 4

HIGH SPEED OPERATION

I.3 Control timing for 5V operation

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

(2) Since a 2-bit prescaler in the timer must count four external cycles (t

CYC), this is the limiting

factor in determining the timer resolution.

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to

execute the capture interrupt service routine plus 24 t

CYC.

(4) The minimum period tILIL should not be less than the number of cycle times it takes to

execute the interrupt service routine plus 21 t

CYC.

(5) At a temperature of 85°C

(6) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate

information.

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option fOSC

fOSC

—

dc 8.0

8.0 MHz

MHz

Internal operating frequency (fOSC/2)

Crystal

External clock fOP

fOP

—

dc 4.0

4.0 MHz

MHz

Cycle time (see Figure 9-1) tCYC 250 — ns

Crystal oscillator start-up time (see Figure 9-1) t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) t

ILCH 100 ms

External RESET input pulse width tRL 1.5 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle tPORL

tPORL

4064

16 —

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended) tERA

tERA

10 —

—ms

EEPROM byte program time (1)

0 to 70 (standard)

– 40 to 85 (extended) tPROG

tPROG

10 —

—ms

Timer (see Figure I-1)

Resolution(2)

Input capture pulse width

Input capture pulse period

tRESL

tTH, tTL

tTLTL

125

—(3)

—

tCYC

Interrupt pulse width (edge-triggered) t

ILIH 125 — ns

Interrupt pulse period tILIL —(4) —t

CYC

OSC1 pulse width tOH, tOL 90 — ns

Write/Erase endurance(5)(6) — 10000 cycles

Data retention(5)(6) — 10 years

TPG

274

05B6Book Page 4 Tuesday, April 6, 1999 8:24 am

MC68HC05B6

Rev. 4 MOTOROLA

I-5

HIGH SPEED OPERATION 15

Figure I-1 Timer relationship

External

signal

(TCAP1,

TCAP2)

tTLTL tTH tTL

TPG

275

05B6Book Page 5 Tuesday, April 6, 1999 8:24 am

MOTOROLA

I-6 MC68HC05B6

Rev. 4

HIGH SPEED OPERATION

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TPG

276

05B6Book Page 6 Tuesday, April 6, 1999 8:24 am

MC68HC05B6 MOTOROLA

GLOSSARY

This section contains abbreviations and specialist words used in this data

sheet and throughout the industry. Further inf ormation on many of the terms

may be gleaned from Motorola’s

M68HC11 Reference Manual,

M68HC11RM/AD

, or from a variety of standard electronics text books.

$xxxx The digits following the ‘$’ are in hexadecimal format.

%xxxx The digits following the ‘%’ are in binary format.

A/D, ADC Analog-to-digital (converter).

Bootstrap mode In this mode the device automatically loads its internal memory from an

external source on reset and then allows this program to be executed.

Byte Eight bits.

CCR Condition codes register; an integral part of the CPU.

CERQUAD A cer amic package type , principally used for EPR OM and high temperature

devices.

Clear ‘0’ — the logic zero state; the opposite of ‘set’.

CMOS Complementary metal oxide semiconductor. A semiconductor technology

chosen for its low power consumption and good noise immunity.

COP Computer operating properly.

aka

‘watchdog’. This circuit is used to detect

device runaway and provide a means for restoring correct operation.

CPU Central processing unit.

D/A, DAC Digital-to-analog (converter).

EEPROM Electrically erasable programmable read only memory.

aka

‘EEROM’.

EPROM Erasable programmable read only memory. This type of memory requires

exposure to ultra-violet wavelengths in order to erase previous data.

aka

‘PROM’.

ESD Electrostatic discharge.

Expanded mode In this mode the internal address and data bus lines are connected to

external pins. This enables the device to be used in much more complex

systems, where there is a need for external memory for example.

TPG

277

05B6Book Page i Tuesday, April 6, 1999 8:24 am

MOTOROLA

ii MC68HC05B6GLOSSARY

EVS Evaluation system. One of the range of platforms provided by Motorola for

evaluation and emulation of their devices.

HCMOS High-density complementary metal oxide semiconductor. A semiconductor

technology chosen f or its low po w er consumption and good noise immunity.

I/O Input/output; used to describe a bidirectional pin or function.

Input capture (IC) This is a function provided by the timing system, whereby an external

event is ‘captured’ by storing the value of a counter at the instant the event

is detected.

Interrupt This refers to an asynchronous external event and the handling of it by the

MCU. The external event is detected by the MCU and causes a

predetermined action to occur.

IRQ Interrupt request. The overline indicates that this is an active-low signal

format.

K byte A kilo-byte (of memory); 1024 bytes.

LCD Liquid crystal display.

LSB Least signiﬁcant byte.

M68HC05 Motorola’s family of 8-bit MCUs.

MCU Microcontroller unit.

MI BUS Motorola interconnect bus. A single wire, medium speed serial

communications protocol.

MSB Most signiﬁcant byte.

Nibble Half a byte; four bits.

NRZ Non-return to zero.

Opcode The opcode is a byte which identiﬁes the particular instruction and operating

mode to the CPU. See also: prebyte, operand.

Operand The operand is a byte containing information the CPU needs to execute a

particular instruction. There ma y be from 0 to 3 operands associated with an

opcode. See also: opcode, prebyte.

Output compare (OC) This is a function provided by the timing system, whereby an external

event is generated when an internal counter value matches a predeﬁned

value.

PLCC Plastic leaded chip carrier package.

PLL Phase-locked loop circuit. This provides a method of frequency

multiplication, to enable the use of a low frequency crystal in a high

frequency circuit.

Prebyte This byte is sometimes required to qualify an opcode, in order to fully specify

a particular instruction. See also: opcode, operand.

TPG

278

05B6Book Page ii Tuesday, April 6, 1999 8:24 am

MC68HC05B6 MOTOROLA

iii

GLOSSARY

Pull-down, pull-up These terms refer to resistors, sometimes internal to the device, which are

permanently connected to either ground or VDD.

PWM Pulse width modulation. This term is used to describe a technique where the

width of the high and low periods of a wa v eform is varied, usually to enable

a representation of an analog value.

QFP Quad ﬂat pack package.

RAM Random access memory . Fast read and write, but contents are lost when the

power is removed.

RFI Radio frequency interference.

RTI Real-time interrupt.

ROM Read-only memory. This type of memory is programmed during device

manufacture and cannot subsequently be altered.

RS-232C A standard serial communications protocol.

SAR Successive approximation register.

SCI Serial communications interface.

Set ‘1’ — the logic one state; the opposite of ‘clear’.

Silicon glen An area in the central belt of Scotland, so called because of the

concentration of semiconductor manufacturers and users found there.

Single chip mode In this mode the de vice functions as a self contained unit, requiring only I/O

devices to complete a system.

SPI Serial peripheral interface.

Test mode This mode is intended for factory testing.

TTL Transistor-transistor logic.

UART Universal asynchronous receiver transmitter.

VCO Voltage controlled oscillator.

Watchdog

see

‘COP’.

Wired-OR A means of connecting outputs together such that the resulting composite

output state is the logical OR of the state of the individual outputs.

Word Two bytes; 16 bits.

XIRQ Non-maskable interrupt request. The overline indicates that this has an

active-low signal format.

TPG

279

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MOTOROLA

iv MC68HC05B6GLOSSARY

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TPG

280

05B6Book Page iv Tuesday, April 6, 1999 8:24 am

MC68HC05B6 MOTOROLA
v
INDEX
INDEX
In this inde x numeric entries are placed ﬁrst; page references in 
italics
 indicate that the ref erence
is to a ﬁgure.
A
A/D converter
block diagram  
8–2
during STOP mode  8–6
during WAIT mode  8–6
operation  8–1
registers
ADDATA  8–3
ADSTAT  8–4
PORTD  8–3
A/D converter characteristics  11–8, 11–9, E–24, E–25, 
F–22, F–23, H–25, H–26, I–3
A/D status/control register
ADON  4–5
absolute maximum ratings  11–1
ADDATA – A/D result data register  8–3
ADON – A/D converter on  8–5
ADON – A/D converter on bit  4–5
ADRC – A/D RC oscillator control  8–4
ADSTAT
ADON  8–5
ADRC  8–4
CH3-CH0  8–5
COCO  8–4
ADSTAT – A/D status/control register  8–4
alternate counter register  5–3
analog input  8–6
B
Baud rate register
SCP1, SCP0  6–18
SCR2, SCR1, SCR0  6–19
SCT2, SCT1, SCT0  6–18
block diagrams
MC68HC05B16  
D–3
MC68HC05B32  
G–2
MC68HC05B4  
A–2
MC68HC05B8  
B–2
MC68HC705B16  
E–2
MC68HC705B16N  
F–2
MC68HC705B32  
H–4
MC68HC705B5  
C–2
PLM system  
7–1
programmable timer  
5–2
SCI  
6–2
, 6–2
watchdog system  
9–3
bootstrap mode  C–8, E–10, H–12
C
ceramic resonator  2–11
CH3-CH0 – A/D channels 3, 2, 1 and 0  8–5
COCO – Conversion complete flag  8–4
control timing  11–10, 11–11, C–19, E–26, E–27, F–24, 
F–25, H–27, H–28, I–4
COP watchdog  9–3
during STOP mode  9–4
during WAIT mode  9–4
counter  5–1
counter register  5–3
CPHA – Clock phase  6–12
CPOL – Clock polarity  6–12
crystal  2–11
D
data direction registers
DDRA, DDRB, DDRC  4–5
data format  6–5
DC electrical characteristics  11–2, 11–5, C–19, E–22, 
E–23, F–20, F–21, H–23, H–24, I–2
E
E1ERA – EEPROM erase/programming bit  3–3, E–7, 
F–7, H–9
E1LAT – EEPROM programming latch enable  3–4
E1LAT – EEPROM programming latch enable bit  E–7, 
F–7, H–10
TPG
281
05B6Book  Page v  Tuesday, April 6, 1999  8:24 am

MOTOROLA
vi MC68HC05B6INDEX
E1PGM – EEPROM charge pump enable/disable  3–4, 
E–7, F–7, H–10
E6LAT – EPROM programming latch enable bit  E–6, F–6, 
H–9
E6PGM – EPROM program enable bit  E–6, F–6, H–9
ECLK – External clock output bit  4–3
EE1P – EEPROM protect bit  E–9, F–9
EE1P – EEPROM protection bit  H–12
EEPROM  3–1, 3–3
erase operation  3–5
programming operation  3–6
read operation  3–5
STOP mode  3–7
WAIT mode  3–7
EEPROM control register
E1ERA  3–3
E1LAT  3–4
E1PGM  3–4
ECLK  3–3
EEPROM options register
EE1P  E–9, F–9
SEC  E–9, F–9
EEPROM/ECLK control
ECLK  4–3
ELAT – EPROM programming latch enable bit  C–6
EPGM – EPROM programming bit  C–6
EPP – EPROM protect  C–7
EPPT – EPROM protect test bit  C–6
EPROM  13–2, C–5, E–5, F–5
control register  C–6, E–6, F–6
options register  C–7
program operation  E–5, F–6, H–8
programming operation  C–5
read operation  E–5, F–5, H–8
EPROM control register
ELAT  C–6
EPGM  C–6
EPPT  C–6
EPROM electrical characteristics  E–28, F–26, H–29
EPROM registers  C–6
EPROM/EEPROM/ECLK control register
E1ERA  E–7, F–7
E1LAT  E–7, F–7
E1PGM  E–7, F–7
E6LAT  E–6, F–6
E6PGM  E–6, F–6
external clock  2–12, D–4, E–5, F–5, G–2
external interrupt  9–7
F
FE – Framing error flag  6–17
H
high speed operation  I–1
I
I/O pin states  4–2
I/O port structure  
4–2
, 4–2
ICF1 – Input capture flag 1  5–6
ICF2 – Input capture flag 2  5–7
IDLE – Idle line detect flag  6–16
IEDG1 – Input edge 1  5–5
ILIE – Idle line interrupt enable  6–14
Input capture registers
ICR1  5–7
ICR2  5–8
input/output programming  4–1
INTE – External interrupt enable  3–9, 9–9
interrupts
priorities  9–6
SCI  9–10
SWI  9–6
INTP, INTN – External interrupt sensitivity options  3–9, 9–9
IRQ  9–7
IRQ sensitivity  9–9
L
LBCL – Last bit clock  6–13
low power modes
SLOW  2–9
STOP  2–6
WAIT  2–8
M
M – Mode  6–11
Mask option register
PBPD  E–8, F–8, H–11
PCPD  E–8, F–9, H–11
RTIM  E–8, F–8, H–11
RWAT  E–8, F–8, H–11
WWAT  E–8, F–8, H–11
mask options
MC68HC05B6  1–3
maskable hardware interrupts  9–7
maskset errata  D–1, H–1
MC68HC05B16  D–1
block diagram  
D–3
memory map  
D–5
MC68HC05B32  G–1
block diagram  
G–2
memory map  
G–3
MC68HC05B4
block diagram  
A–2
memory map  
A–3
MC68HC05B6
block diagram  1–3
mask options  1–3
memory map  
3–2
pinouts  12–1, 12–2, 12–3
TPG
282
05B6Book  Page vi  Tuesday, April 6, 1999  8:24 am

MC68HC05B6 MOTOROLA
vii
INDEX
MC68HC05B8  B–1
block diagram  
B–2
memory map  
B–3
MC68HC705B16  E–1
block diagram  
E–2
memory map  
E–3
MC68HC705B16N  F–1
block diagram  
F–2
memory map  
F–3
MC68HC705B32  H–3
block diagram  
H–4
memory map  
H–5
MC68HC705B5  C–1
block diagram  
C–2
memory map  
C–3
mechanical dimensions  12–4, 12–5, 12–6
memory map
MC68HC05B16  
D–5
MC68HC05B32  
G–3
MC68HC05B4  
A–3
MC68HC05B6  
3–2
MC68HC05B8  
B–3
MC68HC705B16  
E–3
MC68HC705B16N  
F–3
MC68HC705B32  
H–5
MC68HC705B5  
C–3
Miscellaneous register
INTE  3–9, 9–9
INTP, INTN  3–9, 9–9
POR  3–9, 9–2
SFA  3–10, 7–3
SFB  3–10, 7–3
SM  2–9, 3–10, 7–3
WDOG  3–10, 9–4
modes of operation
jump to any address  2–4
low power modes  2–6
single chip mode  2–1
N
NF – Noise error flag  6–17
nonmaskable software interrupt  9–6
O
OCF1 – Output compare flag 2  5–6
OCF2 – Output compare flag 2  5–7
OCIE – Output compares interrupt enable  5–4
OLV1 – Output level 1  5–5
OLV2 – Output level 2  5–5
Options register
SEC  H–12
options register
EE1P  H–12
EPP  C–7
PBPD  C–8
PCPD  C–8
RTIM  C–7
RWAT  C–7
WWAT  C–7
OPTR – options register  3–6, C–7
EE1P – EEPROM protection bit  3–7
SEC – Security bit  3–7
OR – Overrun error flag  6–17
oscillator connections  2–12, 
D–4
Output compare registers
OCR1  5–9
OCR2  5–10
P
parallel bootstrap  E–13, E–19, F–13, H–16
PBPD – Port B pull-down  E–8, F–8
PBPD – Port B pull-down resistors  C–8
PCPD – Port C pull-down  E–8, F–9
PCPD – Port C pull-down resistors  C–8
pin configurations  
12–1
pinsIRQ  2–10
OSC1, OSC2  2–11
PA0–PA7, PB0–PB7, PC0–PC7  2–13
PD0/AN0–PD7/AN7  2–13
PLMA, PLMB  2–13
RDI, TDO  2–13
RESET  2–10, 9–3
SCLK  2–13
TCAP1  2–10
TCAP2  2–11
TCMP1, TCMP2  2–11
VDD, VSS  2–10
VPP1  2–13
VRH, VRL  2–13
PLCC  12–1
PLM  5–11
block diagram  
7–1
clock selection  7–4
PLMA, PLMB  7–2
POR – Power-on reset bit  3–9, 9–2
port registers
PORTA, PORTB  4–4
PORTC  4–4
PORTD  4–5
PORTD – Port D data register  8–3
portsA and B  4–2
C  4–3
D  4–3
power-on reset  9–2
programmable timer
block diagram  
5–2
Pulse  5–11
pulse length modulation  5–11
registers
PLMA, PLMB  5–11
TPG
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05B6Book  Page vii  Tuesday, April 6, 1999  8:24 am

MOTOROLA
viii MC68HC05B6INDEX
pulse length modulation registers
PLMA, PLMB  5–11
Q
QFP  12–2
R
R8 – Receive data bit 8  6–11
RAM  3–1
RDI  6–6
RDRF – Receive data register full flag  6–16
RE – receiver enable  6–15
receive data in  6–6
receiver  6–3
register outline  3–8
registers  3–1
RESET  9–3, E–5, F–5
reset timing diagram  
9–1
resets  9–1
RIE – receiver interrupt enable  6–14
ROM  3–1
RTIM – Reset time  C–7, E–8, F–8
RVU  13–2
RWAT – Watchdog after reset  C–7, E–8, F–8
RWU – receiver wake-up  6–15
S
SBK – Send break  6–15
SCI block diagram  
6–2
receiver  6–3
sampling technique  6–7
synchronous transmission  6–9
transmitter  6–3
two-wire system  6–1
SCI interrupts  9–10
SCI registers
BAUD  6–18
SCCR1  6–10
SCCR2  6–14
SCDR  6–10
SCSR  6–16
SCP1, SCP0 – Serial prescaler select bits  6–18
SCR2, SCR1, SCR0 – SCI rate select bits  6–19
SCT2, SCT1, SCT0 – SCI rate select bits  6–18
SDIP  12–3
SEC – Secure bit  E–9, F–9, H–12
self-check mode  A–5
self-check ROM  3–2
serial bootstrap  E–16
Serial communications control register 1  6–10
CPHA  6–12
CPOL  6–12
LBCL  6–13
M  6–11
R8  6–11
T8  6–11
WAKE  6–11
Serial communications control register 2
ILIE  6–14
RE  6–15
RIE  6–14
RWU  6–15
SBK  6–15
TCIE  6–14
TE  6–14
TIE  6–14
Serial communications data register  6–10
Serial communications status register
FE  6–17
IDLE  6–16
NF  6–17
OR  6–17
RDRF  6–16
TC  6–16
TDRE  6–16
serial RAM loader  2–2, F–16, H–19
SFA – Slow or fast mode selection for PLMA  3–10, 7–3
SFB – Slow or fast mode selection for PLMB  3–10, 7–3
single chip mode  2–1
SLOW  2–9
SM – Slow mode  3–10, 7–3
SM – slow mode selection bit  2–9
start bit detection  6–6
STOP  2–6, 3–7, 5–12, 6–21, 7–4, 8–6, 9–4
T
T8 – transmit data bit 8  6–11
TC – Transmit complete flag  6–16
TCIE – Transmit complete interrupt enable  6–14
TDO  6–8
TDRE – Transmit data register empty flag  6–16
TE – Transmitter enable  6–14
TIE – Transmit interrupt enable  6–14
Timer control register
IEDG1  5–5
OCIE  5–4
OLV1  5–5
OLV2  5–5
TOIE  5–4
timer interrupts  9–10
timer state diagrams  5–12
Timer status register
ICF1  5–6
ICF2  5–7
OCF1  5–6
OCF2  5–7
TOF  5–6
TOF – Timer overflow status flag  5–6
TOIE – Timer overflow interrupt enable  5–4
transmit data out  6–8
TPG
284
05B6Book  Page viii  Tuesday, April 6, 1999  8:24 am

MC68HC05B6 MOTOROLA
ix
INDEX
transmitter  6–3
TSR – Timer status register  5–6
V
verification media  13–2
W
WAIT  2–8, 3–7, 5–12, 6–21, 7–4, 8–6, 9–4
WAKE – Wake-up mode select  6–11
wake-up
address mark  6–6
idle line  6–6
receiver  6–5
WDOG – Watchdog enable/disable  3–10, 9–4
WWAT – Watchdog during WAIT mode  C–7, E–8, F–8
TPG
285
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MOTOROLA

xMC68HC05B6INDEX

THIS PAGE LEFT BLANK INTENTIONALLY

TPG

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05B6Book Page x Tuesday, April 6, 1999 8:24 am

CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05B6/D rev. 4)

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SECTION 1 INTRODUCTION

SECTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS

SECTION 3 MEMORY AND REGISTERS

SECTION 4 INPUT/OUTPUT PORTS

SECTION 5 PROGRAMMABLE TIMER

SECTION 6 SERIAL COMMUNICATIONS INTERFACE

SECTION 7 PULSE LENGTH D/A CONVERTERS

SECTION 8 ANALOG TO DIGITAL CONVERTER

SECTION 9 RESETS AND INTERRUPTS

SECTION 10 CPU CORE AND INSTRUCTION SET

SECTION 11 ELECTRICAL SPECIFICATIONS

SECTION 12 MECHANICAL DATA

SECTION 13 ORDERING INFORMATION

SECTION 14 APPENDICES

SECTION 15 HIGH SPEED OPERATION

TPG

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05B6Book Page xi Tuesday, April 6, 1999 8:24 am

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05B6Book Page xii Tuesday, April 6, 1999 8:24 am

INTRODUCTION

MODES OF OPERATION AND PIN DESCRIPTIONS

MEMORY AND REGISTERS

INPUT/OUTPUT PORTS

PROGRAMMABLE TIMER

SERIAL COMMUNICATIONS INTERFACE

PULSE LENGTH D/A CONVERTERS

ANALOG TO DIGITAL CONVERTER

RESETS AND INTERRUPTS

CPU CORE AND INSTRUCTION SET

ELECTRICAL SPECIFICATIONS

MECHANICAL DATA

ORDERING INFORMATION

APPENDICES

HIGH SPEED OPERATION

TPG

289

05B6Book Page 13 Tuesday, April 6, 1999 8:24 am

INTRODUCTION

MODES OF OPERATION AND PIN DESCRIPTIONS

MEMORY AND REGISTERS

INPUT/OUTPUT PORTS

PROGRAMMABLE TIMER

SERIAL COMMUNICATIONS INTERFACE

PULSE LENGTH D/A CONVERTERS

ANALOG TO DIGITAL CONVERTER

RESETS AND INTERRUPTS

CPU CORE AND INSTRUCTION SET

ELECTRICAL SPECIFICATIONS

MECHANICAL DATA

ORDERING INFORMATION

APPENDICES

HIGH SPEED OPERATION

TPG

290

05B6Book Page 14 Tuesday, April 6, 1999 8:24 am

05B6Book Page 15 Tuesday, April 6, 1999 8:24 am

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