NS ESI G D N EW CT FO R P R O D U D E D E Single Volatile ME N 3511 I TU T COM SUBST 62, ISL2 E R 4 E T 0 L O N L9 SI B October 22, 2015 1, IS POS Data 46Sheet 0 9 L IS ISL90460 32-Tap XDCPTM FN8225.4 Digitally Controlled Potentiometer (XDCP) Features The Intersil ISL90460 is a digitally controlled potentiometer (XDCP). Configured as a variable resistor, the device consists of a resistor array, wiper switches, a control section, and volatile memory. The wiper position is controlled by a 2-pin Up/Down interface. * Volatile Solid-State Potentiometer The potentiometer is implemented by a resistor array composed of 31 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS and U/D inputs. * 32 Wiper Tap Points The device can be used in a wide variety of applications including: * Available RTOTAL Values = 10k50k100k * LCD contrast control * Parameter and bias adjustments * Packages - 5 Ld SC-70, SOT-23 * Industrial and automotive control * Pb-Free Plus Anneal Available (RoHS Compliant) * Transducer adjustment of pressure, temperature, position, chemical, and optical sensors Pinout * 2-pin UP/DN Interface * DCP Terminal Voltage, 2.7V to 5.5V * Tempco 35ppm/C Typical * Low Power CMOS - Active current 25A max. - Supply current 0.3A * Temp Range -40C to +85C ISL90460 (5 LD SOT-23, SC-70) TOP VIEW * Laser Diode driver biasing * Gain control and offset adjustment VDD RH GND U/D 1 CS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas LLC XDCP is a trademark of Intersil Americas LLC Copyright Intersil Americas LLC 2005, 2015. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL90460 Ordering Information PART NUMBER PART MARKING RTOTAL (K) TEMP RANGE (C) 10 -40 to +85 5 Ld SC-70 (Pb-free) P5.049 -40 to +85 5 Ld SOT-23 (Pb-free) P5.064 -40 to +85 5 Ld SC-70 (Pb-free) P5.049 -40 to +85 5 Ld SOT-23 (Pb-free) P5.064 -40 to +85 5 Ld SC-70 (Pb-free) P5.049 -40 to +85 5 Ld SOT-23 (Pb-free) P5.064 ISL90460WIE527Z-TK (See Note) DDY No longer available or supported, recommended replacement: ISL90460TIH527Z-TK ISL90460WIH527Z -TK (See Note) DDZ ISL90460UIE527Z-TK (See Note) DDW No longer available or supported, recommended replacement: ISL90460TIH527Z-TK 50 ISL90460UIH527Z -TK (See Note) DDX No longer available or supported, recommended replacement: ISL90460TIH527Z-TK ISL90460TIE527Z-TK (See Note) DDU No longer available or supported, recommended replacement: ISL90460TIH527Z-TK ISL90460TIH527Z-TK (See Note) 100 DDV PACKAGE (Tape and Reel) PKG. DWG. # NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Block Diagram Pin Descriptions VCC SOT-23/SC-70 5-PIN SYMBOL 1 VDD Supply voltage 2 GND Ground 3 U/D Up - Down AND 4 CS Chip select MEMORY 5 RH High terminal/Wiper terminal UP/DOWN RH (U/D) CONTROL DEVICE SELECT DESCRIPTION (CS) GND (GROUND) GENERAL 2 FN8225.4 October 22, 2015 ISL90460 Absolute Maximum Ratings Recommended Operating Conditions Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on CS, U/D and VCC with Respect to GND . . . . -1V to +7V Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . 300C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1mW Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40C to 85C Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Potentiometer SpecificationsOver recommended operating conditions unless otherwise stated SYMBOL RTOT VR MIN TYP (Note 4) MAX UNIT W version 8 10 12 k U version 40 50 60 k T version 80 100 120 k VCC V PARAMETER End to end resistance CONDITIONS RH, RL terminal voltages Noise 0 Ref: 1kHz RW Wiper Resistance IW Wiper Current Resolution dBV 600 1 Absolute linearity (Note 1) RH(n)(actual) - RH(n)(expected) Relative linearity (Note 2) RH(n+1) - [RH(n)+MI] RTOTAL temperature coefficient CH/CL/CW -120 Potentiometer capacitances See equivalent circuit 0.6 mA 32 Taps 1 MI (Note 3) 0.5 MI (Note 3) 35 ppm/C 10/10/25 pF NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (RH(n)(actual) - RH(n)(expected)) = 1 Ml Maximum. n = 1 .. 29 only. 2. Relative linearity is a measure of the error in step size between taps = RH(n+1) - [RH(n) + Ml] = 0.5 Ml, n = 1 .. 29 only. 3. 1 Ml = Minimum Increment = RTOT/31. 4. Typical values are for TA = 25C and nominal supply voltage. Equivalent Circuit RTOTAL RL RH CW CH CL RW 3 FN8225.4 October 22, 2015 ISL90460 DC Electrical Specifications SYMBOL Over recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP (Note 4) MAX UNIT 25 A 1 A ICC VCC active current (Increment) CS = 0V, U/D = fclock = 1MHz and VCC = 3V ISB Standby supply current CS = VCC, U/D = VSS or VCC = 3V ILI CS input leakage current VIN = VSS to VCC 1 A ILI U/D input leakage current VIN = VSS to VCC 1 A VIH CS, U/D input HIGH voltage VIL CS, U/D input LOW voltage CIN CS, U/D input capacitance Timing Specifications 0.3 VCC x 0.7 V VCC x 0.3 VCC = 3V, VIN = VSS, TA = 25C, f = 1MHz V 10 pF Over recommended operating conditions unless otherwise specified) (Figures 1 and 2) SYMBOL PARAMETER MIN TYP (Note 4) MAX UNIT tCU U/D to CS setup 25 ns tCI CS to U/D setup 50 ns tIC CS to U/D hold 25 ns tlL U/D LOW period 300 ns tlH U/D HIGH period 300 ns fTOGGLE Up/Down toggle rate 1 MHz tSETTLE Output settling time 1 s CS tCU tIC tIL U/D tCI tIH tSETTLE RH FIGURE 1. SERIAL INTERFACE TIMING DIAGRAM, INCREMENT 4 FN8225.4 October 22, 2015 ISL90460 CS tCU tIC tIH U/D tCI tIL tSETTLE RH FIGURE 2. SERIAL INTERFACE TIMING DIAGRAM, DECREMENT Pin Descriptions Principles of Operation RH The ISL90460 contains a digital potentiometer connected as a rheostat or variable resistor. The wiper and one terminal of the digital potentiometer is tied to the RH pin, and the other terminal of the potentiometer is tied to the ground pin (GND). The resistance from the RH pin to ground will vary with the potentiometer setting; at the highest setting, the resistance will be the maximum (Rtot), at the lowest setting it will be a minimum. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in volatile memory when CS is returned HIGH. When CS is high, the device is placed in low power standby mode. There are two sections of the ISL90460: the input control, counter and decode section; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. The resistor array is comprised of 31 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the connection at that point to the wiper. The wiper is connected to the RH terminal, forming a variable resistor from RH to GND. The direction of the wiper movement is defined when the device is selected. If during CS transition from High to Low the U/D input is LOW, the wiper will move down on each rising edge of U/D toggling. Similarly, the wiper will move up on each rising edge of U/D toggling if, during CS transition from High to Low, the U/D input is High. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. If the wiper is moved several positions, multiple taps are connected to the wiper for tSETTLE (U/D to RH change). The 2-terminal resistance value for the device can temporarily change by a significant amount if the wiper is moved several positions. 5 FN8225.4 October 22, 2015 ISL90460 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION October 22, 2015 FN8225.4 CHANGE Added Rev History and About Intersil Verbiage. Updated Ordering Information on page 2 Updated PODs to most recent revisions. Made correction to Pkg Dwg # in Ordering Information table "P5.046" to P5.064" About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6 FN8225.4 October 22, 2015 ISL90460 Package Outline Drawing P5.064 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev 3, 4/11 8 0 3.00 3 2.80 (1.90) 5 0.22 0.08 5 4 3.00 2.60 1.70 1.50 3 2 (0.95) SEE DETAIL X 0.50 0.30 0.20 (0.008) M C TOP VIEW END VIEW 0.25 0.10 0.10 MIN 1.30 0.90 1.45 SEATING 0.90 PLANE C GAUGE PLANE SEATING PLANE 4 0.55 0.35 C 0.15 0.00 0.10 (0.004) C (0.60) SIDE VIEW 8 0 (0.25) DETAIL "X" 5x (0.60) 5x (1.2) 5 4 (2.4) NOTES: 1. Dimensioning and tolerance per ASME Y14.5M-1994. 3 2. Package conforms to EIAJ SC-74 and JEDEC MO178AA. 3. Package length and width are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength measured at reference to gauge plane. 5. Lead thickness applies to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. (2x 0.95) 6. Controlling dimension: MILLIMETER. Dimensions in ( ) for reference only. (1.90) TYPICAL RECOMMENDED LAND PATTERN 7 FN8225.4 October 22, 2015 ISL90460 Small Outline Transistor Plastic Packages (SC70-5) P5.049 D VIEW C e1 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES 5 SYMBOL 4 E CL 1 2 CL 3 e E1 b CL 0.20 (0.008) M C C CL A A2 SEATING PLANE A1 -C- PLATING b1 0.043 0.80 1.10 - 0.004 0.00 0.10 - A2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 D 0.073 0.085 1.85 2.15 3 E 0.071 0.094 1.80 2.40 - E1 0.045 0.053 1.15 1.35 3 e 0.0256 Ref 0.65 Ref - e1 0.0512 Ref 1.30 Ref - L2 c1 NOTES 0.031 0.010 0.018 0.017 Ref. 0.26 0.46 4 0.420 Ref. 0.006 BSC 0o N c MAX 0.000 WITH MIN A L b MILLIMETERS MAX A1 L1 0.10 (0.004) C MIN - 0.15 BSC 8o 0o 5 8o - 5 5 R 0.004 - 0.10 - R1 0.004 0.010 0.15 0.25 Rev. 3 7/07 NOTES: BASE METAL 1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 4X 1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1 L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 4X 1 VIEW C 0.4mm 0.75mm 2.1mm 0.65mm TYPICAL RECOMMENDED LAND PATTERN 8 FN8225.4 October 22, 2015