CY7C027V/028V CY7C037V/038V 3.3V 32K/64K x 16/18 Dual-Port Static RAM Features + Fully asynchronous operation + Automatic power-down + Expandable data bus to 32/36 bits or more using Mas- ter/Slave chip select when using more than one device + On-chip arbitration logic + Semaphores included to permit software handshaking + True Dual-Ported memory cells which allow simulta- neous access of the same memory lIccation * 32K x 16 organization (CY7C027V) + 64K x 16 organization (CY7CO028V) * 32K x 18 organization (CY7CO037V) between ports + 64K x 18 organization (CY7CO38V) + INT flag for port-to-port communication + 0.35-micron CMOS for optimum speed/power + Separate upper-byte and lower-byte control + High-speed access: 15!'1/20/25 ns + Dual Chip Enables + Low operating power + Pin select for Master or Slave Active: log = 115 mA (typical) + Commercial and Industrial temperature ranges Standby: Igg3 = 10 LA (typical) + Available in 100-pin TQFP + Pin-compatible and functionallyequivalent toIDT70V27 Logic Block Diagram CEo- Eor CE Eqr cB, [Ba OE, OER [2] 2] VOgeVO15;4 70 WgeaVOisa7R 8/9 8/9 He Control 3] Vo i3] VOg.-VOs/aL Control Og_-VO7/aR 15/16 Address Decode Address Decode True Dual-Ported Agr-A RAM Array OR **14/15R (4) Aot-Atanse [4] iq Ao-Aran se Aor-Atasi5r CEL Interrupt CER OEL Semaphore OER RW, Arbitration RW, SEM, SEM BUSY, BUSYR RT, INT UBL UBR LBL LBr Notes: 1. Call for availability. 4. Ag-Ayy for 32K; Ap-Ays for 64K devices. 2. WO,-l/Oy5 for x16 devices; |/O,-V/O,; for x18 devices. 5. BUSY is an output in master mode and an inputin slave mode. 3. 49-10; for x16 devices: I/O,-1/O, for x18 devices. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation + 3901 North First Street + SanJose + CA 95134 + 408-943-2600 November 23, 1998SSELAINASY CY7C027V/028V CY7C037V/038V Functional Description The CY7CO27V/028V and CY7037V/038V are low-power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbi- tration schemes are included on the devices to handle situa- tions when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchro- nous access for reads and writes to any location in memory. The devices can be utilized as stand-alone 16/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate mas- ter and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, commu- Pin Configurations nications status buffering, and dual-port video/graphics mem- ory. Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT}. BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled indesendently on each port by a chip select (CE) pin. The GCY7C027V/028V and GY7037V/038V are available in 100-pin Thin Quad Plastic Flatpacks (TQFP). 100-Pin TQFP (Top View) I Si gdegzGzgga geek 8 a#e#ee 2 4 2 (2 la 9? 91 90 89 88 87 8&6 GND cc So w BESTEST ESES slaz ead ted fee 84 83 82 &1 80 AaL { AOR AIOL 2 Aton ALL 3 AIR AlaL 4 Aten AI3L 5 AI3R AMAL 6 A14R [Note 6] A1SL 7 AISR [Note 6] NC 8 NC NG 9 NC Tat TBR UBL 11 UBAR GEOL CY7CO028V (64K x 16) CEOR CEIL CEIR SEML CY7C027V (32K x 16) SEMA voc eND RAWL RAWA OEL OER GND ND GND cND VOTE VO1sR YO1aL Votan HOTSL VOI3R vor2L Vo12R WO1IL VOR WO1oL VO10R ao iw WN ~~ @ easeseses 8 & 885 8 2 Y geeee sg 2 Note: 6. This pin is NC for CY7CO27V. GND rrrrnrtnrenreoenretket oe SBsereN RABE BOR DB ReA SES sgsssEs soeCY7C027V/028V SSELAINASY CY7C037V/038V Pin Configurations (continued) 100-Pin TQFP (Top View) S zeazgdd = ee ee (a 9 9 g Iw (a aa rcrrere = ce te Fy & i} =o = Qz 9 Ww a2eeee 2 4 e@ Em oGbS Seezeet ee e2ted2e ASL 1 A8R A1OL 2 ASR AVIL 3 AIOR Ale2L 4 A11R A13L 5 A1I2R A14L 6 A13R [Note 7] A1SL 7 ALAR TBL 8 A15R [Note 7] UBL 9 CBR CEOL UBR CHIL 11 CEOR SEML CY7CO38V (64K x 18) CeIn RAW SEMA OEL CY7C037V (32K x 18) paw veo ND GND OER VO17L GND vO16L VO17R GND e@ND WO1sL O16R VO14_L VO1sR VO13L VO14R WO12L O13R VOL Vo12R 1O10L VO11R 41 42 43 ext oedHAstasaea At A oO HP HP ea tee ee conrnkckte: SSsSsSSSsssesses es SS SSESSESE Selection Guide CY7Co27V/02z8V CY7C027V/028V CY7C027V/028V CY7CO37V/028V CY7C037V/038V CY7C037V/038V -15"'] -20 -25 Maximum Access Time (ns) 15 20 25 Typical Operating Current (mA) 125 120 115 Typical Standby Current for lgg1 (mA) (Both ports 35 35 30 TTL level) Typical Standby Current for Isgg (uA) (Both ports 10 pA 10 nA 10 nA CMOS level} Shaded area contains advance information. Note: 7. This pinis NC for CY7CO37V.CY7C027V/028V BAESCIINA SY CY7C037V/038V Pin Definitions Left Port Right Port Description CEng, CEy CEor. CEiR Chip Enable (CE is LOW when CE, = Vip and CE, = Vip} RW RWe Read/Write Enable OE, OER Output Enable Aot-AisL Aor-Aisr Address (Ap-Aj4 for 32K; AgA;5 for 64K devices) VOg _-VO4- VOon-VO17R Data Bus Input/Output (l/Og-l/O15 for x16 devices; |/Qg-I/O17 for x18) SEM, SEM Semaphore Enable UB, UBa Upper Byte Select (I/Og-l/015 for x16 devices; l/Ogl/O,7 for x18 devices) LB, LBr Lower Byte Select (l/Og-VO; for x16 devices; I/Ogl/Og for x18 devices) INT, INT Interrupt Flag BUSY, BUSY, Busy Flag M/S Master or Slave Select Voc Power GND Ground NG No Connect Maximum Ratings Output Current into Cutputs (LOW) oo, 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge VoHage sess nseieen > 1100V lines, not tested.) Latch-Up Current... cece ceeeceeeeeeereeteeeteeeteenees >200 mA _mro o Storage Temperature ......000 ee 65C to +150C Operating Range Ambient Temperature with - Power Applied ......0..cccccccscsscscseestesteseeeseees -55C to +125C Ambient . Range Temperature Vec Supply Voltage to Ground Potential ............... 0.5V to +4.6V - . Commercial 0S to +70C 3.3V +300 mV DC Voltage Applied to - 5 5 Outputs in High Z State 0... eee cece. -0.5V to Veo+0.5V Industrial 40C to +85C 3.3V +300 mV pe Input Voltage!) -0.5V to Vogt 5V Shaded area contains advance information. Note: 8. Pulse width < 20 ns.CY7C027V/028V SSELAINASY CY7C037V/038V Electrical Characteristics Over the Operating Range CY7C027V/028V CY7C037V/038V -15H -20 -25 Symbol Parameter Min | Typ | Max | Min | Typ | Max | Min| Typ | Max | Units Vou Output HIGH Voltage (Vec=3.3V, loy=-4.0mA)] 2.4 24 24 Vv Voi Qutput LOW Voltage (lo.=4.0mA) 0.4 0.4 0.4 Vv Vin Input HIGH Voltage 22 2.2 22 V Vib Input LOW Voltage 0.8 0.8 0.8 V lix Input Leakage Current 5 5 5 5 | -5 5 LA loz Qutput Leakage Current -10 10 | -10 10 |-10 10 pA loc Operating Current (Vog=Max, Igy7=0 | Goml. 125 | 185 120 | 175 115 | 165 | mA mA) Outputs Disabled Indust. 140 | 195 135 | 185 | mA Ispy Standby Current (Both Ports TTL Com'l. 35 50 35 45 30 40 mA Level) CE, & CER 2 Vin, ffmax Indust. 45 | 55 40 | 50 | mA Ispo Standby Current (One Port TTL Level) | Goml. 80 | 120 75 110 65 95 mA CEL | GER? Vin. imax indust. @ | 120 75 | 105 | mA laps Standby Current (Both Ports CMOS = | Com! 10 | 106 10 | 100 10 | 100 | pA Level) CE, & CER > Vec0.2V, f=0 Indust. 10 100 10 100 WA Ispa Standby Current (One Port CMOS Com. 75 108 70 95 60 80 mA Level) CE, | CEp 2 Vin, fofuax! Indust. 80 | 105 70 | 90 | mA Shaded area contains advance information. Capacitance! Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f = 1 MHz, 10 pF - Voo = 3.3V Court Output Capacitance 10 pF AC Test Loads and Waveforms 3.3V 3.3V Ri= 5902 Rry= 2502 OUTPUT, OUTPUT Ri= 5900 C= 30pF R2= 4350 C= 90 eT om L C= 5pF = = = Vin= 14V R2= 4350 (a) Normal Load (Load 1) (b) Thvenin Equivalent (Load 1) (c) Three-State Delay (Load 2) (Used for tz, tyz, tuzwe, & trawe ALL INPUT PULSES including scope and jig) 3.0V GND <3ns <3ns Notes: 9. fax = Vac = All inputs cyding atf = 1/tac (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby Isp3. 10. Tested initially and after any design or process changes that may affect these parameters.CY7C027V/028V SSELAINASY CY7C037V/038V Switching Characteristics Over the Operating Range!" CY7C027V/028V CY7CO037V/038V -151] -20 -25 Parameter Description Min. Max. Min. Max. Min. Max. Unit READ CYCLE lac Read Cycle Time 15 20 25 ns taa Address to Data Valid 15 20 25 ns touHa Output Hold From Address Change 3 3 3 ns tace'4 CE LOW to Data Valid 15 20 25 ns tpoE OE LOW to Data Valid 10 12 13 ns trzoel!# 475 | OE LOW to Low Z 3 3 3 ns tuzogl 249 | OE HIGH to High Z 10 12 15 ns tice S411 | CE LOW to Low Z 3 3 3 ns tuzog' 3451 | GE HIGH to High Z 10 12 15 ns ipyt! CE LOW to Power-Up 0 0 0 ns ip! CE HIGH to Power-Down 15 20 25 ns tage? Byte Enable Access Time 15 20 25 ns WRITE CYCLE twe Write Cycle Time 15 20 25 ns iscel"4 CE LOW to Write End 12 16 20 ns taw Address Valid to Write End 12 16 20 ns tua Address Hold From Write End 0 0 0 ns teal! Address Set-Up to Write Start G 0 0 ns tpwe Write Pulse Width 12 17 22 ns tsp Data Set-Up to Write End 16 12 15 ns typ Data Hold From Write End G 0 0 ns tuzwel!* RW LOW to High Z 10 12 15 ns trawell4 9 R/W HIGH to Low Z 3 3 3 ns twoo'4 Write Pulse to Data Delay 30 40 50 ns topo! Write Data Valid to Read Data Valid 25 30 35 ns BUSY TIMING! BLA BUSY LOW from Address Match 15 20 20 ns taHA BUSY HIGH from Address Mismatch 15 20 20 ns tac BUSY LOW from CE LOW 15 20 20 ns tHe BUSY HIGH from CE HIGH 15 16 17 ns tps Port Set-Up for Priority 5 5 5 ns twe RW HIGH after BUSY (Slave) G 0 a) ns twH RAW HIGH after BUSY HIGH (Slave) 13 15 17 ns tap! BUSY HIGH to Data Valid 15 20 25 ns Shaded area contains advance information. Notes: 11. Test conditions assume signal transition time of 3ns or less, timing reference levels of 1.5V, input pulse levels of Oto 3.0, and output loading of the specified lovloy and 30-pF load capacitance. _ ae 12. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tzo time. 13. At any given temperature and voltage condition for any given device, tio is less thant, ge and tyz_ is less thant zoe. 14. Test conditions used are Load 2. 15. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 16. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 17. Test conditions used are Load 1. 18. tapp is a calculated parameter and is the greater of tywoo-tpwe_ (actual) or top ptsp (actual).CY7C027V/028V BARECMNA RY CY7C037V/038V Switching Characteristics Over the Operating Range!" (continued) CY7CO027V/028V CY7CO037V/038V ~15!4 -20 -25 Parameter Description Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING!" tins INT Set Time 15 20 20 ns tinr INT Reset Time 15 20 20 ns SEMAPHORE TIMING tsop SEM Flag Update Pulse (OE or SEM) 10 10 12 ns IswAD SEM Flag Write to Read Time 5 5 5 ns tsps SEM Flag Contention Window 5 5 5 ns saa SEM Address Access Time 15 20 25 ns Shaded area contains advance information. Data Retention Mode Timing The CY7CO027V/028V and CY7037V/O038V are designed with Data Retention Mode battery backup in mind. Data retention voltage and supply cur- rent are guaranteed over temperature. The following rules en- Veo 7 * a.0v 3.0V sure data retention: Voo22.0V tac 1. Chip enable (CE) must be held HIGH during data retention, with- Verto V 0.2V . _ Oo U. inVoc 10 Vog -0.2V. cE WD co to Voc Vi NX 2. GE must be kept between Voc 0.2V and 70% of Vee during the power-up and power-down transitions. 3. The RAM can begin operation >tpc after Voc reaches the Parameter Test Conditions! Max. Unit minimum operating voltage (3.0 volts). ICG DRI @ VCCopr =2V 50 HA Note: 19. CE=Vgq, V,, = GND to Vag, Ty = 25C. This parameter is guaranteed but not tec! tested.CY7C027V/028V SSELAINASY CY7C037V/038V Switching Waveforms Read Cycle No. 1 (Either Port Address Access)!?.21.221 at tre ADDRESS * * - tAA >| @$ tou, +a tona DATAOQUT _- PREVIOUS DATA VALID * x x DATA VALID x x Read Cycle No. 2 (Either Port CE/OE Access)!20:29.241 t TE and ACE LB or UB tzce tpoE OE tHZOE {LZ0E DATA OUT DATA VALID tLZCE teu loc CURRENT 7 Isp tpp Read Cycle No. 3 (Either Port)!?.22.23.24] at: trac > ADDRESS _ x j_ tra a ivy) 9 r oo DATA OUT Notes: 20. RAW is HIGH for read cycles. _ Le 21. Device is continuously selected CE =|_ and UB or LB = V. This waveform cannot be used for semaphore reacls. 22. OE=V/. 23. Address valid prior to or coincident with CE transition LOW. a 24. To access RAM, CE=V, UBorLB =V,, SEM =V\,. To access semaphore, CE = V|,,, SEM =V,.Switching Waveforms (continued) SSELAINASY CY7C027V/028V CY7C037V/038V Write Cycle No. 1: R/W Controlled Timing!*5227.28] nat twe ADDRESS * X $$ thyz0/3'] CLLMLLLLLELLLLLLLLLLLLLL LLL 2 Yo UL) na: cE [29,30] oo e ica se thazwel!] baw tp !?5). _o me ta DATA OUT ~< DATA IN 7 / / pa t_z~ve +| j._ tsp < kore 32 , _ ib Write Cycle No. 2: CE Controlled Timing!?5-76-27.331 < twe ADDRESS x > 4 < taw > [29,30] YJ cE! ] A < isa tgce | tua > RAW \ / tsp =e- ty DATA IN Notes: 25. RAW must be HIGH during all address transitions. _ ae 26. A write occurs during the overlap (tgo ortpyy-) ofa LOW CE or SEM and a LOW UB or LB. 27. ty, is measured from the earlier of CE or RAW or (GEM or RAW) going HIGH at the end of write cycle. 28. |f OEis LOW during a RAV controlled write aycle, the write pulse width must be the larger of tay_ or (tay + tsp) to allow the VO drivers to tum off and data to be placed on the bus for the required ts 5. f OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tryyc. 29. To access RAM, CE=V,,SEM=V/,.. 30. To access upper byte, CE = V. UB = V,, SEM=V),,. To access lower byte, CE = V, ,.LB=V,, SEM= V.,. 31. Transition is measured +500 mV trom steady state with a 5-pF load (induding scope and jig). This parameter is sampled and not 100% tested. 32. During this period, the I/O pins are in the output state, and input signals must not be applied. 33. If the CE or SEM LCW transition occurs simultaneously with or after the RW LCM] transition, the outputs remain in the high-impedance state.CY7C027V/028V SSELAINASY CY7C037V/038V Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side! L< tsaa>| t toya A rons KK eR KK KKK _vasononess XX XK +a tay m , ACE SEM ___ HA tsp VO 4 DATA 1 VALID -____________/\ DATA our VALID 7 ty tsa - tpwe RW Le y +| swap tboE _ iy EYL LLNLL LLL LA BL BEE f/f i tag WRITE CYCLE epege_-_ READ CYCLE + Timing Diagram of Semaphore Contention953697] AgiAar MATCH x RAW SEM, tspg * Aor-Agr MATCH x RW, 7 SE R x Notes: a4 . GE = HIGH for the duration of the above timing {both write and read cycle). 35. [/Ooq = 14Oy_ = LOW (request semaphore); CE, =CE =HIGH. 36. Semaphores are reset {available to both ports) at cycle start. 37. If tgpg is violated, the semaphore will definitely be obtained by one side or the other, but which side will getthe semaphore is unpredictable. 10CY7C027V/028V SSELAINASY CY7C037V/038V Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH)!*"l a twe > ADDRESSr * MATCH x RW I tpwe "LY N. / fe SD sepee fHD DATA INj x * VALID tps ia ADDRESS, * MATCH BLA =] 1 tapi L oa tgpp at: topp 7 DATA our. *K vaup oe twop ~ Write Timing with Busy Input (M/S=LOW) _ tpwE RAV a twe twH Note: 38. CE, = CE, =LOW. 11CY7C027V/028V SSELAINASY CY7C037V/038V Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration)!?*! CE, Valid First: ADDRESS, p x ADDRESS MATCH x CE, __ w- tpg CER tale be tBHc BUSY, CE, Valid First: ADDRESS, p x ADDRESS MATCH x fa f =e tps | rc tBLo le tpHo BUSY, Busy Timing Diagram No. 2 (Address Arbitration) 9 Left Address Valid First: tre or two _nr ADDRESS, ADDRESS MATCH * ADDRESS MISMATCH x ~t tps ADDRESS, x tBLa f tana BUSY, Right Address Valid First: tae oF twe 4 ADDRESS, ADDRESS MATCH * ADDRESS MISMATCH x tps ADDRESS, x tBLa pe BHA BUSY Note: 39. If tag is Violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.CY7C027V/028V SSELAINASY CY7C037V/038V Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTp - twe > ADDRESS, 4 WRITE 7FFF (FFFF for CY7Cazawisev) K > XX x a mS) Co iN __ N INT p [411 > + tins aN Right Side Clears INTR: ADDRESS tac READ 7FFF FFFF for CY7Coz28V/38V R a pa tiny 41] _ TZZDR =. SIAN / INTa a Right Side Sets INT, : fa mM w 2 nat two > ADDRESS x WRITE 7FFE (FFFE for CY7CGO28V/38V) KKK x CE, a \ RiWp, " __ N\ INT. pe ty") * Left Side Clears INT _: ' RC READ Tere SK ADDRESS FFFEF for CY7CO28V/38V L am AAA LK ra Mm a j Notes: 40. tua depends on which enable pin (CE_ or RAW) is deasserted first. 41. tyyg ortpy_ depends on which enable pin (CE, or RAV) is asserted last. 13SSELAINASY CY7C027V/028V CY7C037V/038V Architecture The CY7C027V/028V and CY7037V/038V consist of an array of 32K and 64K words of 16 and 18 bits each of dual-port RAM cells, /O and address lines, and control signals (CE, OE, RAW). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port-to-port communication. Two sema- phore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. Functional Description Write Operation Data must be set up for a duration of tgp before the rising edge of R/W in order to guarantee a valid write. A write operation is con- trolled by either the RAW pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 7. lf a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; other- wise the data read is not deterministic. Data willbe valid on the port tppp alter the data is presented on the other port. Read Operation When reading the device, the user must_assert both the OE and CE pins. Data will be available tace after CE or togg after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE mustalso be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (7FFF for the CY7C027V/37V, FFFF for the CY7CO28V/38V) is the mailbox for the right port and the second-highest memory location (7FFE for the CY7C027V/37V, FFFE for the CY7CO28V/38V} is the mailbox for the left port. When one port writes to the other ports mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port's mailbox without resetting the interrupt. The active state of the busy signal (to a port} prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. lf an application does not require message passing, do not connect the interrupt pin to the processor's interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C027V/028V and CY7037V/038V provide on-chip ar- bitration to resolve simultaneous memory lIccation access 14 (contention). If both ports CEs are asserted and an address match occurs within tpg of each other, the busy logic will determine which port has access. If tpg is violated, one port will definitely gain permission to the location, but tt is not predictable which port will get that permission. BUSY will be asserted tp. after an address match oF taic after CE is taken LOW. Master/Slave A M/S pinis provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (ta_c Or tp_a), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin al- lows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used tosend the arbitration outcome to a slave. Semaphore Operation The CY7C027V/028V and CY7037V/038V provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the sema- phore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then ver- ifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tggp before attempting to read the semaphore. The semaphore value will be available tgyrp + tpoe after the rising edge of the semaphore write. If the left port was successful (reads a zero}, it assumes control of the shared resource, ctherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one}, the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its re- quest. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). Ag_> represents the semaphore address. OE and RW are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/Qq is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sam- ple semaphore operations. When reading a semaphore, all sixteen/eighteen data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to ac- cess the semaphore within tgpg of each other, the semaphore will definitely be obtained by one side or the other, but there is no guaran- tee which side will control the semaphore.CY7C027V/028V PSELE MUSA RY CY7C037V/038V Table 1. Non-Contending Read/Write Inputs Outputs CE RW OE UB LB SEM VOgH/047 VOo4/Og Operation H x x x x H High 7 High 7 Deselected: Power-Down x X x H H H High 2 High Z Deselected: Power-Down L L x L H H Data In High 2 Write to Upper Byte Only L L x H L H High Z Data In Write to Lower Byte Only L L 4 L L H Data In Data In Write to Both Bytes L H L L H H Data Out High 2 Read Upper Byte Only L H L H L H High 2 Data Out Read Lower Byte Only L H L L L H Data Out Data Out Read Both Bytes x xX H x Xx x High Z High Z Outputs Disabled H H L Xx Xx L Data Out Data Out Read Data in Semaphore Flag x H L H H L Data Out Data Out Read Data in Semaphore Flag H ir X X xX L Data In Data In Write Dijg into Semaphore Flag x cr xX H H L Data In Data In Write Diyg into Semaphore Flag L x x L X Not Allowed L X x X L L Not Allowed Table 2. Interrupt Operation Example (assumes BUSY, =BUSY,-HIGH) 7! Left Port Right Port Fu nctio n RAW CE, OE, Ao. INT, RW, CER OER Aor-1 4R INTR Set Right INT, Flag L L X 7FFF X X x x x Li44] Reset Right INTp Flag x x x x x Xx L L 7 FFF Hi43] Set Left INT, Flag X X Xx Xx Ls} L X 7FFE Xx Reset Left INT, Flag X L L 7FFE H41 | x x x x x Table 3. Semaphore Operation Example Function VO pV0,; Lett | VO g4/0,7 Right Status No action 1 Semaphore free Left port writes 0 to semaphore Left Port has semaphore token Right port writes 0 to semaphore No change. Right side has no write access to semaphore Left port writes 1 to semaphore Right port obtains semaphore token Left port writes 0 to semaphore No change. Left port has no write access to semaphore Right port writes 1 to semaphore Left port obtains semaphore token Left port writes 1 to semaphore Semaphore free Right port writes 0 to semaphore Right port has semaphore token Right port writes 1 to semaphore Semaphore free Left port writes 0 to semaphore Left port has semaphore token Left port writes 1 to semaphore =/o} =} =| =| of = | = | co] s/o} =] oa] =] =P o!] oo] =| =] = Semaphore free Notes: 42. Ag is 43. If BUSYp_=L thenno change. 44. If BUSY, =L, then no change. and Ap. jsq/FFFF/FFFE for the CY7CozavioseV, 15CY7C027V/028V BPSEs ina sy CY7C037V/038V Ordering Information 32K x16 3.3V Asynchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 15H | G7C027V-15AC A100 160-Pin Thin Quad Flat Pack Commercial 20 CY7C027V-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7G027V-20Al A106 100-Pin Thin Quad Flat Pack Industrial 25 CY7C027V-25AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C027V-25Al A100 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 64K x16 3.3V Asynchronous Dual-Port SRAM Speed Package Operating ns) Ordering Code Name Package Type ange q5U CY7C028V-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C028V-20AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C028V-20Al A100 100-Pin Thin Quad Flat Pack Industrial 25 CY7C028V-25AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C02Z8V-25Al A100 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 32K x18 3.3V Asynchronous Dual-Port SRAM Speed Package Operating Ins) Ordering Code Name Package Type ange 15] CY7C037V-15AC A100 100-Pin Thin Quad Flat Pack Commereial 20 CY7C037V-20ACG A100 100-Pin Thin Quad Flat Pack Commercial CY7C037V-20Al A100 100-Pin Thin Quad Flat Pack Industrial 25 CY7C037V-25AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C037V-25Al A100 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 64K x18 3.3V Asynchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range isl] GY7C038V-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C038V-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7CO38V-20Al A100 100-Pin Thin Quad Flat Pack Industrial 25 CY7C038V-25ACG A100 100-Pin Thin Quad Flat Pack Commercial CY7CO38V-25Al A108 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. Document #: 38-00670-C 16CY7C027V/028V PRECIMINASY CY7C037V/038V Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 16001025 SO DIMENSIONS ARE IN MILLIMETERS. R 008 MIN. oO MIN. MAX. a | a ats max | allali f R O08 NIN, 020 WAX o-7 E oso 020 WIN TYP. asor01s 100 REF. 51-85048-A ma SEATING PLANE 12*s1* pi MAX. -~ 0 020 MAx SEE DETAIL A Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use ofany circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical componenis in life-support systems where a maliunction or failure may reasonably be expecied to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that ine manutacturer assumes all risk of Such Use and in doing so indemnifies Cypress Semiconductor against all charges.