OM13006,598 - NXP Semiconductors

1. General description

The EM773 is an ARM Cortex-M0 based , low-cost 32-bit energy metering IC, designed for

8/16-bit smart metering applications. The EM773 offers programmability and on-chip

metrology functionality combined with a low power, simple instruction set and memory

addressing with reduced code size compared to existing 8/16-bit architectures.

The EM773 operates at CPU frequencies of up to 48 MHz.

The peripheral complement of the EM773 includes up to 32 kB of flash memory, up to

8 kB of dat a memo ry, on e Fa st-mode Plus I2C- bu s in te rface, on e RS-4 85/EIA- 485 UART,

one SPI interface with SSP features, three general purpose counter/timers, up to 25

general purpose I/O pins, and a metrology engine for energy measurement.

2. Features and benefits

System:

ARM Cortex-M0 processor, running at frequencies of up to 48 MHz.

ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

Serial Wire Debug.

System tick timer.

Memory:

32 kB on-chip flash programming memory.

8 kB SRAM.

In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

Digital peripherals:

Up to 25 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors, and a configurable open-drain mode.

GPIO pins can be used as edge and level sensitive interrupt sources.

High-current output driver (20 mA) on one pin.

High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.

Three general purpose counter/timers with a total of two capture inputs and 10

match outpu ts.

Programmable Windowed W atchDog Timer (WWDT).

Analog peripherals:

Metrology Engine for Smart Metering with two current inputs and a voltage input.

EM773

Energy metering IC; up to 32 kB flash and 8 kB SRAM

Rev. 2 — 3 January 2012 Product data sheet

Product data sheet Rev. 2 — 3 January 2012 2 of 51

NXP Semiconductors EM773

Energy metering IC

Serial interfaces:

UART with fractional baud rate generation, internal FIFO, and RS-485 support.

One SPI controller with SSP features and with FIFO and multi-protocol capabilities.

I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a

data rate of 1 Mbit/s with multiple address recognition and monitor mode.

Clock generation :

12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used

as a system clock.

Crystal oscillator with an operating range of 1 MHz to 25 MHz.

Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.

PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator or the internal RC

oscillator.

Clock output function with divider that can reflect the system oscillator clock, IRC

clock, CPU clock, and the Watchdog clock.

Power control:

Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, and Deep power-down modes.

Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

Processor wake-up from Deep-sleep mode via a dedicated star t logic using up to

13 of the functional pins.

Power-On Reset (POR).

Brownout detect with four separate thresholds for interrupt and forced reset.

Unique device serial number for identification.

Single 3.3 V power supply (1.8 V to 3.6 V).

Available as 33-pin HVQFN33 package.

3. Applications

Smart Metering

Product data sheet Rev. 2 — 3 January 2012 3 of 51

NXP Semiconductors EM773

Energy metering IC

4. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

EM773FHN33 HVQFN33 HVQFN: plastic thermal enhanced ve ry thin quad flat package; no

leads; 33 terminals; body 7  7  0.85 mm n/a

Product data sheet Rev. 2 — 3 January 2012 4 of 51

NXP Semiconductors EM773

Energy metering IC

5. Block diagram

Fig 1. EM773 block di agram

SRAM

8 kB

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

FLASH

32 kB

HIGH-SPEED

GPIO

AHB TO APB

BRIDGE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

XTALIN

XTALOUT RESET

clocks and

controls

SWD

EM773

002aag726

slave

slave slave

ROM

slave

AHB-LITE BUS

GPIO ports

PIO0/1/2/3

CLKOUT

IRC

POR

SPI0

METROLOGY ENGINE

UART

32-bit COUNTER/TIMER 0

I2C-BUS

WDT

IOCONFIG

CT32B0_MAT[2:0]

I_LOWGAIN

I_HIGHGAIN

VOLTAGE

CT32B0_CAP0

SDA

SCL

RXD

TXD

DTR, CTS, RTS

SYSTEM CONTROL

PMU

32-bit COUNTER/TIMER 1

CT32B1_MAT[3:0]

16-bit COUNTER/TIMER 0

CT16B0_MAT[2:0]

CT16B0_CAP0

SCK0, SSEL0

MISO0, MOSI0

system bus

Product data sheet Rev. 2 — 3 January 2012 5 of 51

NXP Semiconductors EM773

Energy metering IC

6. Pinning information

6.1 Pinning

Fig 2. Pin configuration HVQFN 33 package

002aag727

Transparent top view

PIO0_8/MISO0/CT16B0_MAT0

PIO1_8

PIO0_2/SSEL0/CT16B0_CAP0

PIO0_9/MOSI0/CT16B0_MAT1

VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2

XTALOUT I_LOWGAIN

XTALIN I_HIGHGAIN

PIO0_1/CLKOUT/CT32B0_MAT2 VOLTAGE

RESET/PIO0_0 R/PIO1_1/CT32B1_MAT0

PIO2_0/DTR R/PIO1_2/CT32B1_MAT1

PIO0_3

PIO0_4/SCL

PIO0_5/SDA

PIO1_9

PIO3_4

PIO3_5

PIO0_6/SCK0

PIO0_7/CTS

PIO1_7/TXD/CT32B0_MAT1

PIO1_6/RXD/CT32B0_MAT0

PIO1_5/RTS/CT32B0_CAP0

VDD

PIO3_2

PIO1_11

PIO1_4/CT32B1_MAT3/WAKEUP

SWDIO/PIO1_3/CT32B1_MAT2

817

718

619

520

421

322

223

124

terminal 1

index area

33 VSS

Product data sheet Rev. 2 — 3 January 2012 6 of 51

NXP Semiconductors EM773

Energy metering IC

6.2 Pin description

Table 2. EM773 pin descripti on table

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

PIO0_0 to PIO0_10 I/O Port 0 — Port 0 is a 12-bit I/O port with individual

direction and function controls for each bit. The

operation of port 0 pins dep ends on the function

selected through the IOCONFIG register block. Pin

PIO0_11 is not available.

RESET/PIO0_0 2[2] yes I I;PU RESET — External reset input with 20 ns glitch filter. A

LOW-going pulse as short as 50 ns on this pin resets

the device, causing I/O ports and peripherals to take on

their default states, and processor execution to begin at

address 0.

I/O - PIO0_0 — General purpose digital input/output pin.

PIO0_1/CLKOUT/

CT32B0_MAT2 3[3] yes I/O I;PU PIO0_1 — General purpose digital input/output pin. A

LOW level on this pin during reset starts the ISP

command handler .

O- CLKOUT — Clock out pin.

O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

PIO0_2/SSEL0/

CT16B0_CAP0 8[3] yes I/O I;PU PIO0_2 — General purpose digital input/output pin.

I/O - SSEL0 — Slave select for SPI0.

I-CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO0_3 9[3] yes I/O I;PU PIO0_3 — General purpose digital input/output pin.

PIO0_4/SCL 10[4] yes I/O IA PIO0_4 — General purpose digital input/output pin

(open-drain).

I/O - SCL — I2C-bus, open-drain clock input/output.

High-current sink only if I2C Fast-mode Plus is selected

in the I/O configuration register.

PIO0_5/SDA 11[4] yes I/O IA PIO0_5 — General purpose digital input/output pin

(open-drain).

I/O - SDA — I2C-bus, open-drain data input/output.

High-current sink only if I2C Fast-mode Plus is selected

in the I/O configuration register.

PIO0_6/SCK0 15[3] yes I/O I;PU PIO0_6 — General purpose digital input/output pin.

I/O - SCK0 — Serial clock for SPI0.

PIO0_7/CTS 16[3] yes I/O I;PU PIO0_7 — General purpose digital input/output pin

(high-current output driver).

I-CTS — Clear To Send input for UART.

PIO0_8/MISO0/

CT16B0_MAT0 17[3] yes I/O I;PU PIO0_8 — General purpose digital input/output pin.

I/O - MISO0 — Master In Slave Out for SPI0.

O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

PIO0_9/MOSI0/

CT16B0_MAT1 18[3] yes I/O I;PU PIO0_9 — General purpose digital input/output pin.

I/O - MOSI0 — Master Out Slave In for SPI0.

O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

Product data sheet Rev. 2 — 3 January 2012 7 of 51

NXP Semiconductors EM773

Energy metering IC

SWCLK/PIO0_10/SCK0/

CT16B0_MAT2 19[3] yes I I;PU SWCLK — Serial wire clock.

I/O - PIO0_10 — General purpose digital input/output pi n.

I/O - SCK0 — Serial clock for SPI0.

O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

I_HIGHGAIN 21[5] no I I;PU I_HIGHGAIN — High gain current input for metrology

engine.

PIO1_1 to PIO1_9;

PIO1_11 I/O Port 1 — Port 1 is a 12-bit I/O port with individual

direction and function controls for each bit. The

operation of port 1 pins dep ends on the function

selected through the IOCONFIG register block. Pins

PIO1_0 and PIO1_10 are not available.

VOLTAGE 22[5] no I I;PU VOLTAGE — Voltage input for the metrology engine.

R/PIO1_1/

CT32B1_MAT0 23[5] no O I;PU R — Reserved. Configure for an alternate functi on in

the IOCONFIG block.

I/O - PIO1_1 — General purpose digital input/output pin.

O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

R/PIO1_2/

CT32B1_MAT1 24[5] no I I;PU R — Reserved. Configure for an alternate function in

the IOCONFIG block.

I/O - PIO1_2 — General purpose digital input/output pin.

O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

SWDIO/PIO1_3/

CT32B1_MAT2 25[5] no I/O I;PU SWDIO — Serial wire debug inpu t/output.

I/O - PIO1_3 — General purpose digital input/output pin.

O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

PIO1_4/

CT32B1_MAT3/WAKEUP 26 no I/O I;PU PIO1_4 — General purpose digital input/output pin.

O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

I-WAKEUP — Deep power-down mode wake-up pin with

20 ns glitch filter . This pin must be pulled HIGH

externally to enter Deep power-down mode and pulled

LOW to exit Deep power-down mode. A LOW-going

pulse as short as 50 ns wakes up the part.

PIO1_5/RTS/

CT32B0_CAP0 30[3] no I/O I;PU PIO1_5 — General purpose digital input/output pin.

O- RTS — Request To Send output for UART.

I-CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

PIO1_6/RXD/

CT32B0_MAT0 31[3] no I/O I;PU PIO1_6 — General purpose digital input/output pin.

I-RXD — Receiver input for UART.

O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

PIO1_7/TXD/

CT32B0_MAT1 32[3] no I/O I;PU PIO1_7 — General purpose digital input/output pin.

O- TXD — Transmitter output for UART.

O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO1_8 7[3] no I/O I;PU PIO1_8 — General purpose digital input/output pin.

PIO1_9 12[3] no I/O I;PU PIO1_9 — General purpose digital input/output pin.

I_LOWGAIN 20 no I I;PU I_LOWGAIN — Low gain current input for metrology

engine.

Table 2. EM773 pin descripti on table …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 2 — 3 January 2012 8 of 51

NXP Semiconductors EM773

Energy metering IC

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; (pins pulled up to full VDD level ); IA = inactive,

no pull-up/down enabled.

[2] See Figure 25 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to

reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down

mode. Pin is 5 V tolerant.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 24).

[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a analog input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 24).

[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

PIO1_11 27 no I/O I;PU PIO1_11 — General purpose digital input/output pin.

PIO2_0 I/O Port 2 — Port 2 is a 12-bit I/O port with individual

direction and function controls for each bit. The

operation of port 2 pins dep ends on the function

selected through the IOCONFIG register block. Pins

PIO2_1 to PIO2_11 are not available.

PIO2_0/DTR 1[3] no I/O I;PU PIO2_0 — General purpose digital input/output pin.

O- DTR — Data Terminal Ready output for UART.

PIO3_0 to PIO3_5 no I/O Port 3 — Port 3 is a 12-bit I/O port with individual

direction and function controls for each bit. The

operation of port 3 pins dep ends on the function

selected through the IOCONFIG register block. Pins

PIO3_0, PIO3_1, PIO3_3 and PIO3_6 to PIO3_11 are

not available.

PIO3_2 28[3] no I/O I;PU PIO3_2 — General purpose digital input/output pin.

PIO3_4 13[3] no I/O I;PU PIO3_4 — General purpose digital input/output pin.

PIO3_5 14[3] no I/O I;PU PIO3_5 — General purpose digital input/output pin.

VDD 6; 29 - I - 3.3 V supply voltage to the internal regulator, the

external rail, and the metrology engine .

XTALIN 4[6] - I - Input to the oscillator circuit and internal clock generator

circuits. Input voltage must not exceed 1.8 V.

XTALOUT 5[6] - O - Output from the oscillator amplifier.

VSS 33 - - - Thermal pad. Connect to ground.

Table 2. EM773 pin descripti on table …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 2 — 3 January 2012 9 of 51

NXP Semiconductors EM773

Energy metering IC

7. Functional description

7.1 ARM Cortex-M0 processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption.

7.2 On-chip flash program memory

The EM773 contains 32 kB of on-chip flash memory.

7.3 On-chip SRAM

The EM773 contains a total of 8 kB on-chip static RAM memory.

7.4 Memory map

The EM773 incorporates several distinct memory regions, shown in the following figure.

Figure 3 shows the overall map of the entire address space from the user program

viewpoint following reset. The interrupt vector area supports address remapp ing.

The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128

peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32

peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows

simplifying the address decoding for each peripheral.

Product data sheet Rev. 2 — 3 January 2012 10 of 51

NXP Semiconductors EM773

Energy metering IC

7.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

7.5.1 Features

•Controls system exceptions and peripheral interrupts.

•In the EM773, the NVIC supports 32 vectored interrupts including up to 13 inputs to

the start logic from individual GPIO pins.

Fig 3. EM773 memory map

0x5000 0000

0x5001 0000

0x5002 0000

0x5020 0000

AHB peripherals

16-127 reserved

GPIO PIO1

4-7

0x5003 0000

0x5004 0000

GPIO PIO2

GPIO PIO3

8-11

12-15

GPIO PIO0

0-3

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4008 0000

0x4001 C000

0x4001 4000

0x4000 0000

WDT

32-bit counter/timer 0

32-bit counter/timer 1

UART

PMU

I2C-bus

13 - 7 reserved

31 - 19 reserved

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x1000 2000

0x1FFF 0000

0x1FFF 4000

0x2000 0000

0x4000 0000

0x4008 0000

0x5000 0000

0x5020 0000

0xFFFF FFFF

reserved

APB peripherals

AHB peripherals

8 kB SRAM 0x1000 0000

EM773

0x0000 8000

32 kB on-chip flash

16 kB boot ROM

0x0000 0000

0x0000 00C0

active interrupt vectors

002aag728

SPI0

reserved

16-bit counter/timer 0

IOCONFIG

system control

flash controller

Product data sheet Rev. 2 — 3 January 2012 11 of 51

NXP Semiconductors EM773

Energy metering IC

•Four programmable interrupt priority levels with hardware priority level masking.

•Software interrupt generation.

7.5.2 Interrupt sources

Each peripheral devi ce has one interrupt line con nected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any GPIO pin (total of up to 25 pins) regardless of the selected function, can be

programmed to generate an interrupt on a level, or rising edge or falling edge, or both.

7.6 IOCONFIG block

The IOCONFIG block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be conn ected to the appro priate pins prior to being activated and pr ior

to any related interrup t(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.7 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamica lly configured as input s or output s. Multiple output s

can be set or cleared in on e wr ite op e ratio n.

The EM773 uses accelerated GPIO functions:

•GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing

can be achieved .

•Entire port value can be written in one instruction.

Additionally, any GPIO pin (total of up to 25 pins) providing a digital function can be

programmed to generate an interrupt on a level, a rising or falling edge, or both.

7.7.1 Features

•Bit level port registers allow a single instruction to set or clear any number of bits in

one write operation.

•Direction control of individual bits.

•All I/O default to inputs with pull-ups enabled after reset with the exception of the

I2C-bus pins PIO0_4 and PIO0_5.

•Pull-up/pull-down resistor configuration can be programm ed through the IOCONFIG

block for each GPIO pin (except for pins PIO0_4 and PIO0_5).

•All GPIO pins (except PIO0_4 and PIO0_5) are pulle d up to 3.3 V (VDD = 3.3 V) if their

pull-up resistor is enabled in the IOCONFIG block.

•Programmable open-drain mode.

Product data sheet Rev. 2 — 3 January 2012 12 of 51

NXP Semiconductors EM773

Energy metering IC

7.8 UART

The EM773 contains one UART.

Support for RS-4 85 /9 -b it mo d e allo ws bo th software addr ess detection and auto m at ic

address detection using 9-bit mode.

The UART includes a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.8.1 Features

•Maximum UART data bit rate of 3.125 MBit/s.

•16 Byte Receive and Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

•FIFO control mechanism that enables software flow control implementation.

•Support for RS-4 85 /9 -b it mo d e.

•Support for modem control.

7.9 SPI serial I/O controller

The SPI controller is capable of operation on a SSP, 4-wir e SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bu s. Only a sing le mas te r an d a sing le

slave can communicate on the bus during a given data transfer. The SPI supports full

duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. In practice, often only one of these data flows

carries meaningful data.

7.9.1 Features

•Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)

•Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

•Synchronous serial communication

•Master or slave operation

•8-frame FIFOs for both transmit and receive

•4-bit to 16-bit frame

7.10 I2C-bus serial I/O controller

The EM773 contains one I2C-bus controller.

The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line

(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and

can operate as either a r eceiver-o nly device ( e.g., an LCD driver) or a tra nsmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

Product data sheet Rev. 2 — 3 January 2012 13 of 51

NXP Semiconductors EM773

Energy metering IC

receivers can oper ate in eithe r master or sl ave mo de, dependin g on wheth er the chip has

to initiate a data transfer or is only addressed. The I2C is a multi-m a ste r bu s an d ca n be

controlled by more than one bus master connected to it.

7.10.1 Features

•The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The

I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.

•Easy to configure as master, slave, or master/slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake mech anism to suspend and

resume serial transfer.

•The I2C-bus can be used for test and diagnostic purposes.

•The I2C-bus controller sup port s m ultiple addr ess recognition a nd a bus monitor m ode.

7.11 Metrology engine

The EM773 contains a metrology engine d esigned to co llect voltage and current in puts to

calculate the active power, reactive power, apparent power and power factor of a load.

The purpose of the metrology engine is for non-billing applications such as plug meters,

smart appliances, industrial and consumer sub-meters, etc.

7.11.1 Features

•1 % accurate for scalable input sources up to 230 V/50 Hz/16 A and

110 V/60 Hz/20 A while maintaining this accuracy with a factor of 1 to 400 down from

this maximum current.

•Automatically calculates active power in W, reactive power in VAr, apparent power in

VA, power factor ratio, Vrms and Irms without ARM CPU intervention.

•Standard API for initializing, starting, stopping and reading data from the metrology

engine using the ARM Cortex M0.

7.12 General purpose external event counter/timers

The EM773 includes two 32-bit counter/timers and one 16-bit counter/timer. The

counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. Each counter/timer also includes one capture input to tr ap the timer value

when an input signal transitions, optionally generating an interrupt.

7.12.1 Features

•A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

Product data sheet Rev. 2 — 3 January 2012 14 of 51

NXP Semiconductors EM773

Energy metering IC

•Counter or timer op er a tion .

•One capture channel per timer, that can take a snapshot of the timer value when an

input signal transitions. A capture event may also generate an interrupt.

•Four match registers per timer that allow :

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Up to four external outputs corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

7.13 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exc ep tion at a fixed time interval (typically 10 ms).

7.14 Windowed WatchDog Timer

The purpose of the watchdog is to reset the controller if software fails to periodically

service it within a programmable time window.

7.14.1 Features

•Internally resets chip if not periodically reloaded during the p rogrammable time-out

period.

•Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

•Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

•Enabled by soft ware but requires a har dware reset or a watchdog reset/interrupt to be

disabled.

•Incorrect feed sequence causes reset or interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 24-bit timer with internal prescaler.

•Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in

multiples of Tcy(WDCLK) 4.

•The W atchdog Clock (WDCLK) source can be selected from the IRC or the dedica ted

watchdog oscillator (WDO). This gives a wide range of potential timing choices of

watchdog operation under different power conditions.

Product data sheet Rev. 2 — 3 January 2012 15 of 51

NXP Semiconductors EM773

Energy metering IC

7.15 Clocking and power control

7.15.1 Crystal oscillators

The EM773 includes three independent oscillators. These are the system oscillator, the

Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for

more than one purpose as required in a particular application.

Following reset, the EM773 will operate from the Internal RC oscillator until switched by

software. This allows systems to operate without any external crystal and the bootloader

code to operate at a known frequency.

See Figure 4 for an overview of the EM773 clock generation.

7.15.1.1 Internal RC oscillator

The IRC may be used as the clock so urce for th e WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the EM773 uses th e IRC as the clock source. Software

may later switch to one of the other available clock sources.

Fig 4. EM773 clock gen eration block diagram

SYSTEM PLL

IRC oscillator

system oscillator

watchdog oscillator

IRC oscillator

watchdog oscillator

MAINCLKSEL

(main clock select)

SYSPLLCLKSEL

(system PLL clock select)

SYSTEM CLOCK

DIVIDER

AHB clock 0

(system)

SYSAHBCLKCTRL[1:18]

(AHB clock enable)

AHB clocks 1 to 18

(memories

and peripherals)

SPI0 PERIPHERAL

CLOCK DIVIDER SPI0

UART PERIPHERAL

CLOCK DIVIDER UART

WDT CLOCK

DIVIDER WDT

WDTUEN

(WDT clock update enable)

watchdog oscillator

IRC oscillator

system oscillator CLKOUT PIN CLOCK

DIVIDER CLKOUT pin

CLKOUTUEN

(CLKOUT update enable) 002aag729

main clock

system clock

IRC oscillator

Product data sheet Rev. 2 — 3 January 2012 16 of 51

NXP Semiconductors EM773

Energy metering IC

7.15.1.2 System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using

the PLL.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL.

7.15.1.3 Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the

watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is

programmable betwee n 7.8 kHz and 1.7 MHz. The frequency spread over p rocessing and

temperature is 40 %.

7.15.2 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desir ed output frequency. The PLL

output frequency must be lower tha n 100 MHz. The output divider may be set to divide by

2, 4, 8, or 16 to prod uce the output clock. Si nce the minimum outp ut divider value is 2 , it is

insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed

following a chip reset and may be enabled by software. The program must configure and

activate the PLL, wait for the PLL to lock, and then connect to th e PLL as a clock source.

The PLL settling time is 100 s.

7.15.3 Clock output

The EM773 features a clock output function that routes the IRC oscillator, the system

oscillator, the watchdog oscillator, or the main clock to an output pin.

7.15.4 Wake-up process

The EM773 begin operation at power-up and when awakened from Deep power-down

mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation

to resume quickly. If the system oscillator or the PLL is needed by the application,

software will need to enable these features and wait for them to stabilize before they are

used as a clock source.

7.15.5 Power control

The EM773 support a varie ty of powe r con trol featu res. Th ere ar e three spe cial mod es of

processor power r eduction: Sleep mode, Deep-sleep mode, and Deep power-down mode.

The CPU clock rate may also be controlled as needed by changing clock sources,

reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a

trade-off of power versus processing speed based on application requirements. In

addition, a register is provided for shutting down the clocks to individual on-chip

peripherals, allowing fine tuning of power consumption by eliminating all dynamic power

use in any periph era ls th at ar e no t req uired for the a pplica tion. Selected per ipher als have

their own clock divide r wh ich pr ovides even better power control.

Product data sheet Rev. 2 — 3 January 2012 17 of 51

NXP Semiconductors EM773

Energy metering IC

7.15.5.1 Power profiles

The power consumption in Active and Sleep modes can be optimized for the application

through simple calls to the power profile. The power configuration routine configures the

EM773 for one of the following power modes:

•Default mode corresponding to power configuration after reset.

•CPU performance mode corresponding to optimized processing capability.

•Efficie ncy mode corresponding to optimi zed balance of current consumption and CPU

performance.

•Low-current mode corresponding to lowest power consumption.

In addition, the power profile includes routines to select the optimal PLL settings for a

given system clock and PLL input clock.

7.15.5.2 Sleep mode

When Sleep mode is entered, the clock to the core is stoppe d. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.15.5.3 Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition all a nalog blo cks are shut

down. As an exception, the user has the option to keep the watchdog oscillator and the

BOD circuit running for se lf-timed wake-up and BOD pr otection. Deep- sleep mod e allows

for additiona l powe r sa vin gs.

Up to 13 pins total serve as external wake-up pins to the start logic to wake up the chip

from Deep-sleep mode.

Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source

should be switched to IRC before entering Deep-sleep mode, because the IRC can be

switched on and off glitch-free.

7.15.5.4 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

WAKEUP pin. The EM773 can wake up from Deep power-down mode via the WAKEUP

pin.

A LOW-going pulse as short as 50 ns wakes up the part from Deep power- down mode.

When entering Deep power-down mode, an external pull-up resistor is required on the

WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from

floating while in Deep power-down mode.

Product data sheet Rev. 2 — 3 January 2012 18 of 51

NXP Semiconductors EM773

Energy metering IC

7.16 System control

7.16.1 Start logic

The start logic connects external pins to corresponding interrupts in the NVIC. Each pin

shown in Table 2 as input to the start logic has an individual interrupt in the NVIC interrupt

vector table. The start logic pins can serve as external interrupt pins when the chip is

running. In addition, an input signal on the start logic pins can wake up the chip from

Deep-sleep mode when all clocks are shut down.

The start logic must be configured in the system configuration block and in the NVIC

before being used.

7.16.2 Reset

Reset has four sources on the EM773: the RESET pin, the Watchdog reset, Power-On

Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip re set by a ny source, on ce the ope ratin g voltage attain s

a usable level, starts the IRC and initializes the flash controller.

A LOW-going pulse as short as 50 ns resets the part.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

An external pull-up resistor is required on the RESET pin if Deep power-down mode is

used.

7.16.3 Brownout detection

The EM773 includes four levels for monitoring the voltage on the VDD pin. If this voltage

falls below one of the four selected levels, the BOD asse rts an interrupt signal to the

NVIC. This signal can be enabled fo r interrupt in the In terrupt Enable Registe r in the NVIC

in order to cause a CPU interrupt; if not, software can monito r the signal by reading a

dedicated status register. Four additional threshold levels can be selected to cause a

forced reset of the chip.

7.16.4 Code security (Code Read Protection - CRP)

This feature of the EM773 allows user to enable different levels of security in the system

so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and

In-System Programming (ISP) can be restricted. When needed, CRP is invoked by

programming a specific pattern into a dedicated flash location. IAP commands are not

affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For

details see the EM773 user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and flash field updates are needed but all sectors can

not be erased.

Product data sheet Rev. 2 — 3 January 2012 19 of 51

NXP Semiconductors EM773

Energy metering IC

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to the ch ip

via the SWD pins and the ISP. This mode effectively disables ISP override using

PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update

mechanism using IAP calls or call reinvoke ISP command to enable flash update via

the UART.

In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be

disabled. For details see the EM773 user manual.

7.16.5 APB interface

The APB peripherals are located on one APB bus.

7.16.6 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main

static RAM, and the Boot ROM.

7.16.7 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs

serve as exte rnal interrupts (see Section 7.16.1).

7.17 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four

breakpoints and two watchpoint s is supported.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Product data sheet Rev. 2 — 3 January 2012 20 of 51

NXP Semiconductors EM773

Energy metering IC

8. Limiting values

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined

based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.

[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD supply voltage (core and external rail) 1.8 3.6 V

VIinput voltage 5 V tolerant I/O

pins; only valid

when the VDD

supply voltage is

present

[2] 0.5 +5.5 V

IDD supply current per supply pin [3] - 100 mA

ISS ground current per ground pin [3] - 100 mA

Ilatch I/O latch-up cu rrent (0.5VDD) < VI <

(1.5VDD);

Tj < 125 C

- 100 mA

Tstg storage temperature non-operating [4] 65 +150 C

Tj(max) maximum junction temperature - 150 C

Ptot(pack) total power dissipation (per package) based on package

heat transfer, not

device power

consumption

-1.5W

VESD electrostatic discharge voltage human body

model; all pins [5] 6500 +6500 V

Product data sheet Rev. 2 — 3 January 2012 21 of 51

NXP Semiconductors EM773

Energy metering IC

9. Static characteristics

Table 4. Static characteristics

Tamb =40 C to +85 C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD supply voltage (core

and external rail) 1.8 3.3 3.6 V

Power consumption in low-current mode [10]

IDD supply current Active mode; code

while(1){}

executed from flash

system clock = 12 MHz

VDD = 3.3 V

[2][3][4]

[5][6] -2-mA

system clock = 50 MHz

VDD = 3.3 V

[2][3][5]

[6][7] -7-mA

Sleep mode;

system clock = 12 MHz

VDD = 3.3 V

[2][3][4]

[5][6] -1-mA

Deep-sleep mode;

VDD = 3.3 V [2][3][8] -2-A

Deep power-down mode;

VDD = 3.3 V [2][9] -220-nA

Standard port pins, RESET

IIL LOW-level input current VI= 0 V; on-chi p pull-up

resistor disabled - 0.5 10 nA

IIH HIGH-level input

current VI=V

DD; on-chip

pull-down resistor

disabled

- 0.5 10 nA

IOZ OFF-state output

current VO=0V; V

O=V

DD;

on-chip pull-up/down

resistors disabled

- 0.5 10 nA

VIinput voltage pin configured to provide

a digital function [11][12]

[13] 0- 5.0V

VOoutput voltage output ac tive 0 - VDD V

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage - 0.4 - V

VOH HIGH-level output

voltage 2.0 V  VDD  3.6 V;

IOH =4 mA VDD  0.4 - - V

1.8 V  VDD < 2.0 V ;

IOH =3 mA VDD  0.4 - - V

VOL LOW-level output

voltage 2.0 V  VDD  3.6 V;

IOL =4 mA --0.4V

1.8 V  VDD < 2.0 V ;

IOL =3 mA --0.4V

Product data sheet Rev. 2 — 3 January 2012 22 of 51

NXP Semiconductors EM773

Energy metering IC

IOH HIGH-level output

current VOH =V

DD 0.4 V;

2.0 V  VDD  3.6 V

4- - mA

1.8 V  VDD < 2.0 V 3- - mA

IOL LOW-level output

current VOL =0.4V

2.0 V  VDD  3.6 V 4- - mA

1.8 V  VDD < 2.0 V 3 - - mA

IOHS HIGH-level short-circuit

output current VOH =0V [14] --45 mA

IOLS LOW-level short-circuit

output current VOL =V

DD [14] --50mA

Ipd pull-down current VI=5V 10 50 150 A

Ipu pull-up current VI=0V;

2.0 V  VDD  3.6 V

15 50 85 A

1.8 V  VDD < 2.0 V 10 50 85 A

VDD <V

I<5V 0 0 0 A

High-drive output pin (PIO0_7)

IIL LOW-level input current VI= 0 V; on-chi p pull-up

resistor disabled - 0.5 10 nA

IIH HIGH-level input

current VI=V

DD; on-chip

pull-down resistor

disabled

- 0.5 10 nA

IOZ OFF-state output

current VO=0V; V

O=V

DD;

on-chip pull-up/down

resistors disabled

- 0.5 10 nA

VIinput voltage pin configured to provide

a digital function [11][12]

[13] 0- 5.0V

VOoutput voltage output ac tive 0 - VDD V

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage 0.4 - - V

VOH HIGH-level output

voltage 2.5 V VDD 3.6 V;

IOH =20 mA VDD  0.4 - - V

1.8 V VDD < 2.5 V;

IOH =12 mA VDD  0.4 - - V

VOL LOW-level output

voltage 2.0 V VDD 3.6 V;

IOL =4 mA --0.4V

1.8 V VDD < 2.0 V;

IOL =3 mA --0.4V

IOH HIGH-level output

current VOH =V

DD 0.4 V;

2.5 V  VDD  3.6 V 20 - - mA

1.8 V  VDD < 2.5 V 12 - - mA

Table 4. Static characteristics …continued

Tamb =40 C to +85 C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 2 — 3 January 2012 23 of 51

NXP Semiconductors EM773

Energy metering IC

IOL LOW-level output

current VOL =0.4V

2.0 V  VDD  3.6 V 4- - mA

1.8 V  VDD < 2.0 V 3 - - mA

IOLS LOW-level short-circuit

output current VOL =V

DD [14] --50mA

Ipd pull-down current VI=5V 10 50 150 A

Ipu pull-up current VI=0V

2.0 V  VDD  3.6 V

15 50 85 A

1.8 V  VDD < 2.0 V 10 50 85 A

VDD <V

I<5V 0 0 0 A

I2C-bus pins (PIO0_4 and PIO0_5)

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage - 0.05VDD -V

IOL LOW-level output

current VOL =0.4V; I

2C-bus pins

configured as standard

mode pins

2.0 V  VDD  3.6 V

3.5 - - mA

1.8 V  VDD < 2.0 V 3 - -

IOL LOW-level output

current VOL =0.4V; I

2C-bus pins

configure d as Fast -mode

Plus pins

2.0 V  VDD  3.6 V

20 - - mA

1.8 V  VDD < 2.0 V 16 - -

ILI input leakage current VI=V

DD [15] -24A

VI=5V - 10 22 A

Table 4. Static characteristics …continued

Tamb =40 C to +85 C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 2 — 3 January 2012 24 of 51

NXP Semiconductors EM773

Energy metering IC

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[2] Tamb =25C.

[3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[4] IRC enabled; system oscillator disabled; system PLL disabled.

[5] BOD disabled.

[6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0 disabled in system configuration block.

[7] IRC disabled; system oscillator enabled; system PLL enabled.

[8] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.

[9] WAKEUP pin pulled HIGH externally.

[10] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.

[11] Including voltage on outputs in 3-state mode.

[12] VDD supply voltage must be present.

[13] 3-state outputs go into 3-state mode in Deep power-down mode.

[14] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[15] To VSS.

Oscillator pins

Vi(xtal) crystal input voltage 0.5 1.8 1.95 V

Vo(xtal) crystal output voltage 0.5 1.8 1.95 V

Table 4. Static characteristics …continued

Tamb =40 C to +85 C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 2 — 3 January 2012 25 of 51

NXP Semiconductors EM773

Energy metering IC

9.1 BOD static characteristics

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCT RL, see EM773

user manual.

9.2 Power consumption

Power measurement s in Active, Sleep , and Deep-sleep mod es were performed under the

following conditions (see EM77 3 us er man u al ):

•Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.

•Configure GPIO pins as outputs using the GPIOnDIR registers.

•Write 0 to all GPIOnDATA registers to drive the outputs LOW.

Table 5. BOD static characteristics[1]

Tamb =25C.

Symbol Parameter Conditions Min Typ Max Unit

Vth threshold voltage interrupt level 0

assertion - 1.65 - V

de-assertion - 1.80 - V

interrupt level 1

assertion - 2.22 - V

de-assertion - 2.35 - V

interrupt level 2

assertion - 2.52 - V

de-assertion - 2.66 - V

interrupt level 3

assertion - 2.80 - V

de-assertion - 2.90 - V

reset level 0

assertion - 1.46 - V

de-assertion - 1.63 - V

reset level 1

assertion - 2.06 - V

de-assertion - 2.15 - V

reset level 2

assertion - 2.35 - V

de-assertion - 2.43 - V

reset level 3

assertion - 2.63 - V

de-assertion - 2.71 - V

Product data sheet Rev. 2 — 3 January 2012 26 of 51

NXP Semiconductors EM773

Energy metering IC

Conditions: Tamb = 25 C; active mode entered executing code

while(1){}

from flash; all peripherals

disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks

disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 5. Active mode : Typical supply current IDD versus supply voltage VDD for different

system clock frequencies

Conditions: VDD = 3.3 V; active mode entered executing code

while(1){}

from flash; all peripherals

disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks

disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 6. Active mode : Typical supply current IDD versus temperatur e for different system

clock frequencies

VDD (V)

1.8 3.63.02.4

002aaf980

IDD

(mA)

12 MHz(1)

24 MHz(2)

36 MHz(2)

48 MHz(2)

002aaf981

temperature (°C)

−40 853510 60−15

IDD

(mA)

12 MHz(1)

24 MHz(2)

36 MHz(2)

48 MHz(2)

Product data sheet Rev. 2 — 3 January 2012 27 of 51

NXP Semiconductors EM773

Energy metering IC

Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled; low-current mode.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

Fig 7. Sleep mode: Typical supply current IDD versus temperature for different system

clock frequencies

temperature (°C)

−40 853510 60−15

002aaf982

IDD

(mA)

12 MHz(1)

24 MHz(2)

36 MHz(2)

48 MHz(2)

Product data sheet Rev. 2 — 3 January 2012 28 of 51

NXP Semiconductors EM773

Energy metering IC

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0x0000 18FF).

Fig 8. Deep-sleep mode: Typical supply current IDD versus temperature for different

supply vo ltages VDD

Fig 9. Deep power-down mode: Typical supply current IDD versu s temp erature for

different supply voltages VDD

002aaf977

temperature (°C)

−40 853510 60−15

2.5

4.5

3.5

5.5

IDD

(μA)

1.5

VDD = 3.3 V, 3.6 V

1.8 V

002aaf978

0.2

0.6

0.4

0.8

IDD

(μA)

temperature (°C)

−40 853510 60−15

VDD = 3.6 V

3.3 V

1.8 V

Product data sheet Rev. 2 — 3 January 2012 29 of 51

NXP Semiconductors EM773

Energy metering IC

9.3 Peripheral power consumption

The supply current p er peripheral is measured as the differ ence in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG

and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both

registers and no code is executed. Mea sured on a typical sample at Tamb =25 C. Unless

noted otherwise, the system oscillator and PLL are running in both measurements.

The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.

Table 6. Power consumption for individual analog and digital blocks

Peripheral Typical supply current in

mA Notes

n/a 12 MHz 48 MHz

IRC 0.27 - - System oscillator running; PLL off; independent

of main clock frequency.

System oscillator

at 12 MHz 0.22 - - IRC running; PLL off; independent of main clock

frequency.

Watchdog

oscillator at

500 kHz/2

0.004 - - System oscillator running; PLL off; independent

of main clock frequency.

BOD 0.051 - - Independent of main clock frequency.

Main PLL - 0.21 -

CLKOUT - 0.12 0.47 Main clock divided by 4 in the CLKOUTDIV

CT16B0 - 0.02 0.06

CT16B1 - 0.02 0.06

CT32B0 - 0.02 0.07

CT32B1 - 0.02 0.06

GPIO - 0.23 0.88 G PIO pins configured as outputs and set to

LOW. Direction and pin state are maintained if

the GPIO is disabled in the SYSAHBCLKCFG

IOCONFIG - 0.03 0.10

I2C - 0.04 0.13

ROM - 0.04 0.15

SPI0 - 0.12 0.45

UART - 0.22 0.82

WDT - 0.02 0.06 Ma in clock selected as clock source for the

WDT.

Product data sheet Rev. 2 — 3 January 2012 30 of 51

NXP Semiconductors EM773

Energy metering IC

9.4 Electrical pin characteristics

Conditions: VDD = 3.3 V; on pin PIO0_7.

Fig 10. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level

output current IOH.

Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.

Fig 11. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus

LOW-level output voltage VOL

IOH (mA)

0 60402010 5030

002aae990

2.8

2.4

3.2

3.6

VOH

(V)

T = 85 °C

25 °C

−40 °C

VOL (V)

0 0.60.40.2

002aaf019

IOL

(mA)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 2 — 3 January 2012 31 of 51

NXP Semiconductors EM773

Energy metering IC

Conditions: VDD = 3.3 V; standard port pins and PIO0_7.

Fig 12. Typical LOW-level output current IOL versus LOW-level output voltage VOL

Conditions: VDD = 3.3 V; standard port pins.

Fig 13. Typical HIGH-level output voltage VOH versus HIGH-level output source current

IOH

VOL (V)

0 0.60.40.2

002aae991

IOL

(mA)

T = 85 °C

25 °C

−40 °C

IOH (mA)

0 24168

002aae992

2.8

2.4

3.2

3.6

VOH

(V)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 2 — 3 January 2012 32 of 51

NXP Semiconductors EM773

Energy metering IC

Conditions: VDD = 3.3 V; standard port pins.

Fig 14. Typical pull-up current Ipu versus input voltage VI

Conditions: VDD = 3.3 V; standard port pins.

Fig 15. Typical pull-down current Ipd versus input voltage VI

VI (V)

0 54231

002aae988

−30

−50

−10

Ipu

(μA)

−70

T = 85 °C

25 °C

−40 °C

VI (V)

0 54231

002aae989

Ipd

(μA)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 2 — 3 January 2012 33 of 51

NXP Semiconductors EM773

Energy metering IC

10. Dynamic characteristics

10.1 Power-up ramp conditions

[1] See Figure 16.

[2] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up.

10.2 Flash memory

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash

in blocks of 256 bytes.

Table 7. Power-up characteristics

Tamb =40 C to +85 C.

Symbol Parameter Conditions Min Typ Max Unit

trrise time at t = t1: 0 < VI 400 mV [1] 0- 500 ms

twait wait time [1][2] 12 - - s

VIinput voltage at t = t1 on pin VDD 0 - 400 mV

Condition: 0 < VI 400 mV at start of power-up (t = t1)

Fig 16. Power-up ramp

400 mV

wait

t = t

1002aag001

Table 8. Flash characteristics

Tamb =40 C to +85 C, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance [1] 10000 100000 - cycles

tret retention time powered 10 - - years

unpowered 20 - - years

ter erase time sector or multiple

consecutive

sectors

95 100 105 ms

tprog programming

time [2] 0.95 1 1.05 ms

Product data sheet Rev. 2 — 3 January 2012 34 of 51

NXP Semiconductors EM773

Energy metering IC

10.3 External clock

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

Table 9. Dynamic characteristic: external clock

Tamb =40 C to +85 C; VDD over specified ranges.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc oscillator frequency 1 - 25 MHz

Tcy(clk) clock cycle time 40 - 1000 ns

tCHCX clock HIGH time Tcy(clk) 0.4--ns

tCLCX clock LOW time Tcy(clk) 0.4--ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Fig 17. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)

tCHCL tCLCX tCHCX

Tcy(clk)

tCLCH

002aaa907

Product data sheet Rev. 2 — 3 January 2012 35 of 51

NXP Semiconductors EM773

Energy metering IC

10.4 Internal oscillators

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %.

[3] See the EM773 user manual.

Table 10. Dynamic characteristic: internal oscillators

Tamb =40 C to +85 C; 2.7 V  VDD  3.6 V.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc(RC) internal RC oscillator frequency - 11.88 12 12.12 MHz

Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for

2.7 V  VDD  3.6 V and Tamb =40 C to +85 C. Variations between parts may cause the IRC to

fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V.

Fig 18. Internal RC oscillator frequency ver sus temperature

Table 11. Dynamic characteristics: Watchdog oscillator

Symbol Parameter Conditions Min Typ[1] Max Unit

fosc(int) internal oscillator

frequency DIVSEL = 0x1F, FREQSEL = 0x1

in the WDTOSCCTRL register; [2][3] -7.8 - kHz

DIVSEL = 0x00, FREQSEL = 0xF

in the WDTOSCCTRL register [2][3] - 1700 - kHz

002aaf403

11.95

12.05

12.15

(MHz)

11.85

temperature (°C)

−40 853510 60−15

VDD = 3.6 V

3.3 V

3.0 V

2.7 V

2.4 V

2.0 V

Product data sheet Rev. 2 — 3 January 2012 36 of 51

NXP Semiconductors EM773

Energy metering IC

10.5 I/O pins

[1] Applies to standard port pins and RESET pin.

10.6 I2C-bus

[1] See the I2C-bus specification UM10204 for details.

[2] Parameters are valid over operating temperature range unless otherwise specified.

[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission

and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[5] Cb = total capacitance of one bus line in pF.

Table 12. Dynamic characteristic: I/O pins[1]

Tamb =40 C to +85 C; 3.0 V  VDD  3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

trrise time pin

configured as

output

3.0 - 5.0 ns

tffall time pin

configured as

output

2.5 - 5.0 ns

Table 13. Dynamic characteristic: I2C-bus pins[1]

Tamb =40 C to +85 C.[2]

Symbol Parameter Conditions Min Max Unit

fSCL SCL clock

frequency Standard-mode 0 100 kHz

Fast-mode 0 400 kHz

Fast-mode Plus 0 1 MHz

tffall time [4][5][6][7] of both SDA and

SCL signals

Standard-mode

- 300 ns

Fast-mode 20 + 0.1  Cb300 ns

Fast-mode Plus - 120 ns

tLOW LOW period of

the SCL clock Standard-mode 4.7 - s

Fast-mode 1.3 - s

Fast-mode Plus 0.5 - s

tHIGH HIGH period of

the SCL clock Standard-mode 4.0 - s

Fast-mode 0.6 - s

Fast-mode Plus 0.26 - s

tHD;DAT dat a ho l d time [3][4][8] Standard-mode 0 - s

Fast-mode 0 - s

Fast-mode Plus 0 - s

tSU;DAT data set-up

time

[9][10] Standard-mode 250 - ns

Fast-mode 100 - ns

Fast-mode Plus 50 - ns

Product data sheet Rev. 2 — 3 January 2012 37 of 51

NXP Semiconductors EM773

Energy metering IC

[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for St andard-mode and Fast-mode but must be less than

the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement

tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must

meet this set-up time.

10.7 SPI interface

Fig 19. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

HD;DAT

SCL

1 / f

SCL

70 %

30 % 70 %

30 %

VD;DAT

HIGH

LOW

SU;DAT

Table 14. Dynamic characteristics of SPI pins in SPI mode

Symbol Parameter Conditions Min Typ Max Unit

SPI master (in SPI mode)

Tcy(clk) clock cycle time full-duplex mode [1] 50 - - ns

when only transmitting [1] 40 ns

tDS data set-up time in SPI mode

2.4 V  VDD  3.6 V

[2] 15 - - ns

2.0 V  VDD < 2.4 V [2] 20 ns

1.8 V  VDD < 2.0 V [2] 24 - - ns

tDH data hold time in SPI mode [2] 0-- ns

tv(Q) data output valid time in SPI mode [2] --10 ns

th(Q) data output hold time in SPI mode [2] 0-- ns

Product data sheet Rev. 2 — 3 January 2012 38 of 51

NXP Semiconductors EM773

Energy metering IC

[1] Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR p arameter (specified in the SSP0CR0 register),

and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).

[2] Tamb = 40 C to 85 C.

[3] Tcy(clk) = 12  Tcy(PCLK).

[4] Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V.

SPI slave (in SPI mode)

Tcy(PCLK) PCLK cycle time 20 - - ns

tDS data set-up time in SPI mode [3][4] 0-- ns

tDH data hold time in SPI mode [3][4] 3  Tcy(PCLK) + 4 - - ns

tv(Q) data output valid time in SPI mode [3][4] --3  Tcy(PCLK) + 11 ns

th(Q) data output hold time in SPI mode [3][4] --2  Tcy(PCLK) + 5 ns

Table 14. Dynamic characteristics of SPI pins in SPI mode

Symbol Parameter Conditions Min Typ Max Unit

Fig 20. SPI master timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk) tclk(H) tclk(L)

tDS tDH

tv(Q)

D ATA V ALID D AT A VALID

th(Q)

SCK (CPOL = 1)

D ATA V ALID D ATA V ALID

MOSI

MISO

tDS tDH

D ATA V ALID D AT A VALID

th(Q)

D ATA V ALID D ATA V ALID

tv(Q)

CPHA = 1

CPHA = 0

002aae829

Product data sheet Rev. 2 — 3 January 2012 39 of 51

NXP Semiconductors EM773

Energy metering IC

Fig 21. SPI slave timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

cy(clk)

clk(H)

clk(L)

v(Q)

D ATA V ALID D AT A VALID

h(Q)

SCK (CPOL = 1)

D ATA V ALID D ATA V ALID

MOSI

MISO

v(Q)

D ATA V ALID D AT A VALID

h(Q)

D ATA V ALID D ATA V ALID

CPHA = 1

CPHA = 0

002aae830

Product data sheet Rev. 2 — 3 January 2012 40 of 51

NXP Semiconductors EM773

Energy metering IC

11. Application information

11.1 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommende d that the inpu t be coupled throug h a cap acitor with

Ci = 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground Cg which attenuates the inpu t volt age by a factor C i/(Ci + Cg). In slave

mode, a minimum of 200 mV (RMS) is needed.

In slave mode the input clock signal should be coup led by means of a cap acitor of 100 pF

(Figure 22), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 23 and in

Table 15 and Table 16. Since the feedback resistance is integrated on chip, only a crystal

and the capacitances CX1 and CX2 need to be connected externally in case of

fundamental mode oscillation (the fundamental frequency is represented by L, CL and

RS). Capacitance CP in Figure 23 represen ts the p arallel p ackage cap acitance and sho uld

not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by th e crystal

manufacturer (see Table 15).

Fig 22. Slave mode operation of the on-chip oscillator

EM773

XTALIN

100 pF Cg

002aag730

Product data sheet Rev. 2 — 3 January 2012 41 of 51

NXP Semiconductors EM773

Energy metering IC

11.2 XTAL Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors CX1, CX2, and CX3 in case

of third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loop s must be made as small as possible in

Fig 23. Oscillator modes and models: os cillation mode of operation and external crystal

model used for CX1/CX2 evaluation

Table 15. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

1 MHz - 5 MHz 10 pF < 300 18 pF, 18 pF

20 pF < 300 39 pF, 39 pF

30 pF < 300 57 pF, 57 pF

5 MHz - 10 MHz 10 pF < 300 18 pF, 18 pF

20 pF < 200 39 pF, 39 pF

30 pF < 100 57 pF, 57 pF

10 MHz - 15 MHz 10 pF < 160 18 pF, 18 pF

20 pF < 60 39 pF, 39 pF

15 MHz - 20 MHz 10 pF < 80 18 pF, 18 pF

Table 16. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) high frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

15 MHz - 20 MHz 10 pF < 180 18 pF, 18 pF

20 pF < 100 39 pF, 39 pF

20 MHz - 25 MHz 10 pF < 160 18 pF, 18 pF

20 pF < 80 39 pF, 39 pF

002aag731

EM773

XTALIN XTALOUT

CX2

CX1

XTAL

CLCP

Product data sheet Rev. 2 — 3 January 2012 42 of 51

NXP Semiconductors EM773

Energy metering IC

order to keep the no ise couple d in via th e PCB as sm all as po ss ible . A lso parasitic s

should stay as small as possible. Values of CX1 and CX2 should be cho se n sm alle r

accordingly to the increase in parasitics of the PCB layout.

11.3 Standard I/O pad configuration

Figure 24 shows the possible pin modes for standard I/O pins with analog input function:

•Digital output driver

•Digital input: Pull-up enabled/disabled

•Digital input: Pull-down enabled/disabled

•Digital input: Repeater mode enabled/disabled

•Analog input

Fig 24. Standard I/O pad configuration

VDD

ESD

VSS

ESD

VDD

weak

pull-up

weak

pull-down

output enable

repeater mode

enable

output

pull-up enable

pull-down enable

data input

analog input

select analog input

002aaf304

pin configured

as digital output

driver

pin configured

as digital input

pin configured

as analog input

Product data sheet Rev. 2 — 3 January 2012 43 of 51

NXP Semiconductors EM773

Energy metering IC

11.4 Reset pad configuration

11.5 ElectroMagnetic Compatibility (EMC)

Radiated emission measurements according to the IEC61967 -2 standard using the

TEM-cell method are shown in Table 17.

[1] IEC levels refer to Appendix D in the IEC61967-2 Specification.

Fig 25. Reset pad configuration

VSS

reset

002aaf274

VDD

Rpu ESD

ESD

20 ns RC

GLITCH FILTER PIN

Table 17. ElectroMagnetic Compatibility (EMC) (TEM-cell method)

VDD = 3.3 V; Tamb = 25



Parameter Frequency band System clock = Unit

12 MHz 24 MHz 48 MHz

Input clock: IRC (12 MHz)

maximum

peak level 150 kHz - 30 MHz 757dBV

30 MHz - 150 MHz 21 10dBV

150 MHz - 1 GHz 4 8 16 dBV

IEC level[1] -ONM-

Input clock: crystal oscillator (12 MHz)

maximum

peak level 150 kHz - 30 MHz 777dBV

30 MHz - 150 MHz 218dBV

150 MHz - 1 GHz 4 7 14 dBV

IEC level[1] -ONM-

Product data sheet Rev. 2 — 3 January 2012 44 of 51

NXP Semiconductors EM773

Energy metering IC

12. Package outline

Fig 26. Package outline (HVQFN33 5x5)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

MO-220

hvqfn33f_po

11-10-11

11-10-17

Unit(1)

mm max

nom

min 0.85 0.05

0.00 0.2 5.1

4.9

3.75

3.45

5.1

4.9

3.75

3.45 0.5 3.5

Dimensions (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

0.30

0.18

D(1)

A(1) DhE(1) Ehee

1e2L

3.5

0.1 0.1

0.05

0.5

0.3

0.05

0 2.5 5 mm

scale

1/2 e

AC B

vCw

terminal 1

index area

AA1c

detail X

y1C

916

32 25

terminal 1

index area

1/2 e

Product data sheet Rev. 2 — 3 January 2012 45 of 51

NXP Semiconductors EM773

Energy metering IC

Fig 27. Package outline (HVQFN33 7x7)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

- - -

hvqfn33_po

09-03-17

09-03-23

Unit

mm max

nom

min

1.00

0.85

0.80

0.05

0.02

0.00 0.2 7.1

7.0

6.9

4.85

4.70

4.55

7.1

7.0

6.9 0.65 4.55 0.75

0.60

0.45 0.1

A(1)

Dimensions

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;

33 terminals; body 7 x 7 x 0.85 mm

A1b

0.35

0.28

0.23

(1) DhE(1) Eh

4.85

4.70

4.55

1e2

4.55

0.1

0.05

0.08

0 2.5 5 mm

scale

terminal 1

index area

detail X

AC B

vCw

terminal 1

index area Dh

L9 16

Product data sheet Rev. 2 — 3 January 2012 46 of 51

NXP Semiconductors EM773

Energy metering IC

13. Soldering

Fig 28. Reflow soldering of the HVQFN33 package

Footprint information for reflow soldering of HVQFN33 package

001aao134

occupied area

solder land

solder resist

solder land plus solder paste

solder paste deposit

Dimensions in mm Remark:

Stencil thickness: 0.125 mm

e = 0.65

evia = 4.25

OwDtot = 5.10 OA

PID = 7.25 PA+OA

OID = 8.20 OA

0.20 SR

chamfer (4×)

0.45 DM

evia = 1.05

W = 0.30 CU

evia = 4.25

evia = 2.40

LbE = 5.80 CU

LbD = 5.80 CU

PIE = 7.25 PA+OA

LaE = 7.95 CU

LaD = 7.95 CU

OIE = 8.20 OA

OwEtot = 5.10 OA

EHS = 4.85 CU

DHS = 4.85 CU

4.55 SR

B-side

(A-side fully covered)

number of vias: 20

Solder resist

covered via

0.30 PH

0.60 SR cover

0.60 CU

SEhtot = 2.70 SP

SDhtot = 2.70 SP

GapE = 0.70 SP

SPE = 1.00 SP

0.45 DM

SPD = 1.00 SP

GapD = 0.70 SP

Product data sheet Rev. 2 — 3 January 2012 47 of 51

NXP Semiconductors EM773

Energy metering IC

14. Abbreviations

Table 18. Abbreviations

Acronym Description

AHB Advanced High-performance Bus

APB Advanced Peripheral Bus

BOD BrownOut Detection

GPIO General Purpose Input/Output

PLL Phase-Locked Loop

RC Resistor-Capacitor

SPI Seri al Peripheral Interface

SSI Serial Synchronous Interface

SSP Synchronous Serial Port

TEM Transverse ElectroMagnetic

UART Universal Asynchronous Receiver/Transmitter

Product data sheet Rev. 2 — 3 January 2012 48 of 51

NXP Semiconductors EM773

Energy metering IC

15. Revision history

Table 19. Revision history

Document ID Release date Data sheet status Change notice Supersedes

EM773 v.2 20120103 Product data sheet - EM773 v.1

Modifications: •Updated Section 7.7.1 “Features”.

•Updated Section 7.14 “Windowed WatchDog Timer”.

•Updated Section 7.15.2 “System PLL”.

•Added Section 7.15.5.1 “Power profiles”.

•Updated Section 7.15.5.4 “Deep power-down mode”.

•Updated Section 7.16.2 “Reset”.

•Updated Section 7.16.7 “External interrupt inputs”.

•Updated Section 9.2 “Power consumption”.

•Added Section 9.3 “Peripheral power consum ption”.

•Updated Section 10 “Dynamic characteri stics”.

•Added Section 11.5 “ElectroMagne tic Compatibility (EMC)”.

•Table 2 “EM773 pin description table”:

–Updated descriptions for WAKEUP and RESET.

–Updated Table note [1] , Table note 2, and Tabl e no te 5.

•Table 3 “Limiting values”:

–Added “non-operating” to Tstg conditions.

–Updated Table note [4] .

•Table 4 “Static characteristics”:

–Added/updated power consumption information.

–Updated I2C-bus Vhys typical to 0.05VDD.

–Updated Table note [6] and Table note [8].

–Added Table note [10].

EM773 v.1 20100901 Product data sheet - -

Product data sheet Rev. 2 — 3 January 2012 49 of 51

NXP Semiconductors EM773

Energy metering IC

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short dat a sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

16.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be lia ble for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability t owards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where f ailure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default ,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third part y

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Not hing in this document may be interpret ed or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyri ghts, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 2 — 3 January 2012 50 of 51

NXP Semiconductors EM773

Energy metering IC

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting f rom customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

16.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors EM773

Energy metering IC

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 January 2012

Document identifier: EM773

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7 Functional description . . . . . . . . . . . . . . . . . . . 9

7.1 ARM Cortex-M0 processor. . . . . . . . . . . . . . . . 9

7.2 On-chip flash program memory . . . . . . . . . . . . 9

7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.5 Nested Vectored Interrupt Controller (NVIC) . 10

7.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.5.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 11

7.6 IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 11

7.7 Fast general purpose parallel I/O . . . . . . . . . . 11

7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.8 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.9 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 12

7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.10 I2C-bus serial I/O controller . . . . . . . . . . . . . . 12

7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.11 Metrology engine . . . . . . . . . . . . . . . . . . . . . . 13

7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.12 General purpose external event

counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 13

7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.13 System tick timer . . . . . . . . . . . . . . . . . . . . . . 14

7.14 Windowed WatchDog Timer. . . . . . . . . . . . . . 14

7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.15 Clocking and power control . . . . . . . . . . . . . . 15

7.15.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 15

7.15.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 15

7.15.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 16

7.15.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 16

7.15.2 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.15.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.15.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 16

7.15.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.15.5.1 Power profiles. . . . . . . . . . . . . . . . . . . . . . . . . 17

7.15.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.15.5.3 Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 17

7.15.5.4 Deep power-down mode . . . . . . . . . . . . . . . . 17

7.16 System control . . . . . . . . . . . . . . . . . . . . . . . . 18

7.16.1 Start logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.16.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.16.3 Brownout detection . . . . . . . . . . . . . . . . . . . . 18

7.16.4 Code security (Code Read Protection - CRP) 18

7.16.5 APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 19

7.16.6 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.16.7 External interrupt inputs. . . . . . . . . . . . . . . . . 19

7.17 Emulation and debugging . . . . . . . . . . . . . . . 19

8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 20

9 Static characteristics . . . . . . . . . . . . . . . . . . . 21

9.1 BOD static characteristics . . . . . . . . . . . . . . . 25

9.2 Power consumption . . . . . . . . . . . . . . . . . . . 25

9.3 Peripheral power consumption . . . . . . . . . . . 29

9.4 Electrical pin characteristics. . . . . . . . . . . . . . 30

10 Dynamic characteristics. . . . . . . . . . . . . . . . . 33

10.1 Power-up ramp conditions. . . . . . . . . . . . . . . 33

10.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 33

10.3 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 34

10.4 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 35

10.5 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.6 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.7 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . 37

11 Application information . . . . . . . . . . . . . . . . . 40

11.1 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11.2 XTAL Printed Circuit Board (PCB) layout

guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11.3 Standard I/O pad configuration . . . . . . . . . . . 42

11.4 Reset pad configuration. . . . . . . . . . . . . . . . . 43

11.5 ElectroMagnetic Compatibility (EMC) . . . . . . 43

12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 44

13 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 47

15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 48

16 Legal information . . . . . . . . . . . . . . . . . . . . . . 49

16.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 49

16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 49

16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 50

17 Contact information . . . . . . . . . . . . . . . . . . . . 50

18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51