ESMT SDRAM M12L128168A 2M x 16 Bit x 4 Banks Synchronous DRAM FEATURES y y y y y y y y y JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read single write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) PRODUCT NO. MAX PACKAGE COMMENTS M12L128168A-5TG 200MHz 54 Pin TSOP II Pb-free M12L128168A-5BG 200MHz 54 Ball FBGA Pb-free M12L128168A-6TG 166MHz 54 Pin TSOP II Pb-free M12L128168A-6BG 166MHz 54 Ball FBGA Pb-free M12L128168A-7TG 143MHz 54 Pin TSOP II Pb-free M12L128168A-7BG 143MHz 54 Ball FBGA Pb-free FREQ. ORDERING INFORMATION GENERAL DESCRIPTION The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Pin Arrangement Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 1/45 ESMT M12L128168A BLOCK DIAGRAM CKE Clock Generator Bank D Bank C Bank B Address Mode Register Row Address Buffer & Refresh Counter Row Decoder CLK Bank A CAS WE Address L(U)DQM Column Decoder Buffer & Counter Data Control Circuit Input & Output Buffer RAS Column Latch Circuit CS Control Logic Command Decoder Sense Amplifier DQ PIN DESCRIPTION PIN NAME INPUT FUNCTION CLK System Clock CS Chip Select CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior new command. Disable input buffers for power down in standby. A0 ~ A11 Address Row / column address are multiplexed on the same pins. Row address : RA0~RA11, column address : CA0~CA8 BA0 , BA1 Bank Select Address Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with CAS Column Address Strobe WE Write Enable L(U)DQM Data Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins. VDD / VSS Power Supply / Ground Power and ground for the input buffers and the core logic. VDDQ / VSSQ Data Output Power / Ground Isolated power supply and ground for the output buffers to provide improved noise immunity. N.C No Connection This pin is recommended to be left No Connection on the device. Elite Semiconductor Memory Technology Inc. Active on the positive going edge to sample all inputs Disables or enables device operation by masking or enabling all inputs except CLK , CKE and L(U)DQM RAS low. (Enables row access & precharge.) Latches column address on the positive going edge of the CLK with CAS low. (Enables column access.) Enables write operation and row precharge. Latches data in starting from CAS , WE active. Publication Date: Oct. 2009 Revision: 2.4 2/45 ESMT M12L128168A ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITION Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 C ) Parameter Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA Input leakage current IIL -5 - 5 A 3 Output leakage current IOL -5 - 5 A 4 Supply voltage Note: Note 1. VIH(max) = 4.6V AC for pulse width 10ns acceptable. 2. VIL(min) = -1.5V AC for pulse width 10ns acceptable. 3. Any input 0V VIN VDD, all other pins are not under test = 0V. 4. Dout is disabled, 0V VOUT VDD. CAPACITANCE (VDD = 3.3V, TA = 25 C , f = 1MHz) Parameter Input capacitance (A0 ~ A11, BA0 ~ BA1) Input capacitance Symbol Min Max Unit CIN1 2.5 4 pF CIN2 2.5 4 pF COUT 2 6.5 pF (CLK, CKE, CS , RAS , CAS , WE & L(U)DQM) Data input/output capacitance (DQ0 ~ DQ15) Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 3/45 ESMT M12L128168A DC CHARACTERISTICS Recommended operating condition unless otherwise notedTA = 0 to 70 C Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode Precharge Standby Current in non power-down mode Active Standby Current in power-down mode Symbol Version Test Condition -5 -6 -7 170 160 140 ICC1 Burst Length = 1, tRC tRC(min), IOL = 0 mA ICC2P CKE VIL(max), tCC = tCC(min) 2 ICC2PS CKE & CLK VIL (max), tCC = 2 ICC2N CKE VIH(min), CS VIH(min), tCC = tCC(min) Input signals are changed one time during 2tCC 45 ICC2NS CKE VIH(min), CLK VIL(max), tCC = input signals are stable 25 ICC3P CKE VIL(max), tCC = tCC(min) 6 ICC3PS CKE & CLK VIL(max), tCC = 6 Unit Note mA 1,2 mA mA mA CKE VIH(min), CS VIH(min), tCC=15ns Active Standby Current in non power-down mode (One Bank Active) ICC3N Input signals are changed one time during 2clks 55 mA 35 mA All other pins VDD-0.2V or 0.2V ICC3NS CKE VIH(min), CLK VIL(max), tCC = input signals are stable Operating Current (Burst Mode) ICC4 IOL = 0 mA, Page Burst, 2 Banks activated 280 210 180 mA Refresh Current ICC5 tRFC tRFC(min) 280 210 180 mA Self Refresh Current ICC6 CKE 0.2V Note: 2 1,2 mA 1. Measured with outputs open. 2. Input signals are changed one time during 2 CLKS. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 4/45 ESMT M12L128168A AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V TA = 0 to 70 C ) Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall-time Output timing measurement reference level Output load condition Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 Vtt = 1.4V 3.3V 1200 50 VOH (DC) =2.4V , IOH = -2 mA Output VOL (DC) =0.4V , IOL = 2 mA Output Z0 =50 50pF 50pF 870 (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol -5 -6 -7 Unit Note Row active to row active delay tRRD(min) 10 12 14 ns 1 RAS to CAS delay tRCD(min) 15 18 20 ns 1 Row precharge time tRP(min) 15 18 20 ns 1 tRAS(min) 38 40 42 ns 1 Row active time Row cycle time tRAS(max) 100 us @ Operating tRC(min) 53 58 63 ns 1 @ Auto refresh tRFC(min) 55 60 70 ns 1,5 Last data in to col. address delay tCDL(min) 1 CLK 2 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Refresh period (4,096 rows) tREF(max) 64 ms 6 Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 5/45 ESMT M12L128168A Parameter Version Symbol -5 Col. address to col. address delay Number of valid Output data -6 tCCD(min) 1 CAS latency = 3 2 CAS latency = 2 1 Unit Note CLK 3 ea 4 -7 Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. A new command may be given tRFC after self refresh exit. 6. A maximum of eight consecutive AUTO REFRESH commands (with tRFC(min)) can be posted to any given SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8x15.6 s.) AC CHARACTERISTICS (AC operating condition unless otherwise noted) Parameter -5 Symbol MIN CLK cycle time CAS latency = 3 CAS latency = 2 CLK to valid output delay CAS latency = 3 Output data hold time CAS latency = 3 CAS latency = 2 CAS latency = 2 tCC tSAC tOH 5 10 -6 MAX 1000 MIN 6 10 -7 MAX 1000 MIN 7 10 Unit Note ns 1 ns 1,2 ns 2 MAX 1000 - 4.5 - 5.4 - 5.4 - 6 - 6 - 6 2 - 2.5 - 2.5 - 2 - 2.5 - 2.5 - CLK high pulse width tCH 2 - 2.5 - 2.5 - ns 3 CLK low pulse width tCL 2 - 2.5 - 2.5 - ns 3 Input setup time tSS 1.5 - 1.5 - 1.5 - ns 3 Input hold time tSH 1 - 1 - 1 - ns 3 CLK to output in Low-Z tSLZ 1 - 1 - 1 - ns 2 - 5.0 - 5.4 - 5.4 ns - 6 - 6 - 6 - CLK to output in Hi-Z Note: CAS latency = 3 CAS latency = 2 tSHZ 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered. 3. Assumed input rise and fall time (tr & tf) =1ns. If tr & tf is longer than 1ns. transient time compensation should be considered. i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 6/45 ESMT M12L128168A SIMPLIFIED TRUTH TABLE COMMAND Register CKEn-1 CKEn H X H L Mode Register set Auto Refresh Entry Self Refresh Exit Refresh Write & Column Address L X L L L H X X H X L H X H H X H X X X V H X L H L H X L H L H X V H X L H L L X V H X L H H L X H X L L H L X Entry H L H X X X L V V V Exit L H X X X X Entry H L H X X X L H H H Exit L H H X X X L V V V Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Bank Selection All Banks Clock Suspend or Active Power Down L DQM H Burst Stop Precharge L WE L Bank Active & Row Addr. Read & Column Address H L A11, BA0 A10/AP A9~A0 BA1 OP CODE CS RAS CAS Precharge Power Down Mode DQM H No Operating Command H X X H X X X L H H H X X Row Address Column L Address H (A0~A8) Column L Address H (A0~A8) X V L X H Note 1,2 3 3 3 3 4 4,5 4 4,5 6 X X X X X X V X X X 7 (V = Valid, X = Don't Care. H = Logic High, L = Logic Low) Note: 1.OP Code: Operating Code A0~A11 & BA0~BA1: Program keys. (@ MRS) 2.MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3.Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge of command is meant by "Auto". Auto/self refresh can be issued only at all banks idle state. 4.BA0~BA1: Bank select addresses. If BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected If A10/AP is "High" at row precharge , BA0 and BA1 is ignored and all banks are selected. 5.During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6.Burst stop command is valid at every burst length. 7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2) Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 7/45 ESMT M12L128168A MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address BA0~BA1 A11~A10/AP A9 Function RFU RFU W.B.L. Test Mode A8 A7 A6 TM CAS Latency A5 A4 A3 CAS Latency A2 BT A1 A0 Burst Length Burst Type Burst Length A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT = 0 BT = 1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 0 0 1 Reserved 1 Interleave 0 0 1 2 2 1 0 Reserved 0 1 0 2 0 1 0 4 4 1 1 Reserved 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved Write Burst Length A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved 0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved 1 Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved Full Page Length: 512 Note: 1. RFU (Reserved for future use) should stay "0" during MRS cycle. 2. If A9 is high during MRS cycle, "Burst Read single write" function will be enabled. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 8/45 ESMT M12L128168A BURST SEQUENCE (BURST LENGTH = 4) Initial Address Sequential Interleave A1 A0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 BURST SEQUENCE (BURST LENGTH = 8) Initial Address Sequential Interleave A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 9/45 ESMT M12L128168A DEVICE OPERATIONS CLOCK (CLK) POWER-UP The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time around positive edge of the clock for proper functionality and ICC specifications. 1.Apply power and start clock, Attempt to maintain CKE = "H", DQM = "H" and the other pins are NOP condition at the inputs. 2.Maintain stable power, stable clock and NOP input condition for minimum of 200us. 3.Issue precharge commands for all banks of the devices. 4.Issue 2 or more auto-refresh commands. 5.Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order. CLOCK ENABLE(CKE) The clock enable (CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + tSS" before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands. BANK ADDRESSES (BA0~BA1) This SDRAM is organized as four independent banks of 2,097,152 words x 16 bits memory arrays. The BA0~BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The banks addressed BA0~BA1 are latched at bank active, read, write, mode register set and precharge operations. ADDRESS INPUTS (A0~A11) The 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 12 address input pins (A0~A11). The 12 row addresses are latched along with RAS and BA0~BA1 during bank active command. The 9 bit column addresses are latched along with CAS , WE and BA0~BA1 during read or with command. NOP and DEVICE DESELECT CS high. CS MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS , RAS , CAS and WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0~A11 and BA0~BA1 in the same cycle as CS , RAS , CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields into depending on functionality. The burst length field uses A0~A2, burst type uses A3, CAS latency (read latency from column address) use A4~A6, vendor specific options or test mode use A7~A8, A10/AP~A11 and BA0~BA1. The write burst length is programmed using A9. A7~A8, A10/AP~A11 and BA0~BA1 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies. BANK ACTIVATE The bank activate command is used to select a random When RAS , CAS and WE are high , The SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting The device is now ready for normal operation. high disables the command decoder so that RAS , CAS , WE and all the address inputs are ignored. Elite Semiconductor Memory Technology Inc. row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of tRCD(min) from the time of bank activation. tRCD is the internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD(min) with cycle time of the clock and then Publication Date: Oct. 2009 Revision: 2.4 10/45 ESMT M12L128168A DEVICE OPERATIONS (Continued) rounding of the result to the next higher integer. The SDRAM has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high requiring some time for power supplies to recover before another bank can be sensed reliably. tRRD(min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS(min). Every SDRAM bank activate command must satisfy tRAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS(max) and tRAS(max) can be calculated similar to tRCD specification. BURST READ The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and RAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD(min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length. BURST WRITE The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS , CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be complete by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and precharge the bank tRDL after the last data input to be written into the active row. See DQM OPERATION also. Elite Semiconductor Memory Technology Inc. DQM OPERATION The DQM is used mask input and output operations. It works similar to OE during operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interrupts of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is required. Please refer to DQM timing diagram also. PRECHARGE The precharge is performed on an active bank by asserting low on clock cycles required between bank activate and clock cycles required between bank activate and CS , RAS , WE and A10/AP with valid BA0~BA1 of the bank to be procharged. The precharge command can be asserted anytime after tRAS(min) is satisfy from the bank active command in the desired bank. tRP is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing tRP with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tRAS(max). Therefore, each bank has to be precharge with tRAS(max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to power-down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state. AUTO PRECHARGE The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy tRAS(min) and "tRP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst write by asserting high on A10/AP, the bank is precharge command is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state. FOUR BANKS PRECHARGE Four banks can be precharged at the same time by using Precharge all command. Asserting low on CS , RAS , and WE with high on A10/AP after all banks have satisfied tRAS(min) requirement, performs precharge on all banks. At the end of tRP after performing precharge all, all banks are in idle state. Publication Date: Oct. 2009 Revision: 2.4 11/45 ESMT M12L128168A DEVICE OPERATIONS (Continued) AUTO REFRESH SELF REFRESH The storage cells of SDRAM need to be refreshed every 64ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on The self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state CS , RAS and CAS with high on CKE and WE . The auto refresh command can only be asserted with all banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by tRFC(min). The minimum number of clock cycles required can be calculated by driving tRFC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOP's until the auto refresh operation is completed. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us. Elite Semiconductor Memory Technology Inc. by asserting low on CS , RAS , CAS and CKE with high on WE . Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the refresh. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of tRFC before the SDRAM reaches idle state to begin normal operation. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit. Publication Date: Oct. 2009 Revision: 2.4 12/45 ESMT M12L128168A COMMANDS Mode register set command ( CS , RAS , CAS , WE = Low) The M12L128168A has a mode register that defines how the device operates. In this command, A0~A11 and BA0~BA1 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During 2CLK following this command, the M12L128168A cannot accept any other commands. Activate command ( CS , RAS = Low, CAS , WE = High) The M12L128168A has four banks, each with 4,096 rows. This command activates the bank selected by BA1 and BA0 (BS) and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's RAS falling. Precharge command ( CS , RAS , WE = Low, CAS = High ) This command begins precharge operation of the bank selected by BA1 and BA0 (BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0. When A10 is Low, only the bank selected by BA1 and BA0 is precharged. After this command, the M12L128168A can't accept the activate command to the precharging bank during tRP (precharge to activate command period). This command corresponds to a conventional DRAM's RAS rising. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 13/45 ESMT M12L128168A Write command ( CS , CAS , WE = Low, RAS = High) If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst can be input with this command with subsequent data on following clocks. Read command ( CS , CAS = Low, RAS , WE = High) Read data is available after CAS latency requirements have been met. This command sets the burst start address given by the column address. CBR (auto) refresh command ( CS , RAS , CAS = Low, WE , CKE = High) This command is a request to begin the CBR refresh operation. The refresh address is generated internally. Before executing CBR refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During tRFC period (from refresh command to refresh or activate command), the M12L128168A cannot accept any other command. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 14/45 ESMT M12L128168A Self refresh entry command ( CS , RAS , CAS , CKE = Low , WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes to high, the M12L128168A exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged. Burst stop command ( CS , WE = Low, RAS , CAS = High) This command terminates the current burst operation. Burst stop is valid at every burst length. No operation ( CS = Low , RAS , CAS , WE = High) This command is not a execution command. No operations begin or terminate by this command. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 15/45 ESMT M12L128168A BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 1) Clock Suspended During W rite (BL=4) 2) Clock Suspended During Read (BL=4) CLK CMD WR RD CKE Masked by CKE Internal CLK DQ(CL2) D0 D1 D2 D3 DQ(CL3) D0 D1 D2 D3 Q0 Q1 Q2 Q3 Q1 Q2 Q3 Not W ritten Q0 Suspe nded Dout 2. DQM Operation 2)Read Mask (BL=4) 1)Write Mask (BL=4) CLK CMD RD WR DQM Ma s k e d b y D Q M Ma s k e d b y D Q M DQ(CL2) D0 D1 D3 DQ(CL3) D0 D1 D3 Q0 Hi-Z Hi-Z DQ M t o D at a- i n M as k = 0 Q2 Q3 Q1 Q2 Q3 DQ M to D at a- ou t M ask = 2 *Note2 3)DQM with clcok su sp end ed (F ull Page Read ) CLK CMD RD CKE Internal CLK DQM DQ( CL2 ) DQ(CL3) Q0 Hi- Z Hi-Z Q2 Q1 Hi- Z Hi-Z Q4 Q3 Hi- Z Hi-Z Q6 Q7 Q8 Q5 Q6 Q7 *Note: 1. CKE to CLK disable/enable = 1CLK. 2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE "L". 3. DQM masks both data-in and data-out. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 16/45 ESMT M12L128168A 3. CAS Interrupt (I) *N ote1 1)R ea d i nt er ru pt ed by R ead (B L =4) CL K C MD RD RD ADD A B DQ ( C L 2 ) QA0 D Q ( CL 3 ) QB0 QB1 QB2 QB3 QA0 QB0 QB1 QB2 QB3 t C CD *N ot e 2 2) Wr i t e i n t er ru pt e d b y W ri t e (B L= 2) 3 )W ri t e in t er rup t ed b y R e ad (B L=2 ) CLK C MD WR WR t CC D A DD DQ WR tC CD * No t e 2 A B DA0 DB 0 A D B1 tC D L * No t e 3 DQ ( C L 2 ) DA0 D Q ( CL 3 ) DA 0 RD *N ote 2 B DB0 DB1 DB 0 DB1 tC D L * No t e 3 *Note: 1. By "interrupt" is meant to stop burst read/write by external before the end of burst. By " CAS interrupt ", to stop burst read/write by CAS access ; read and write. 2. tCCD: CAS to CAS delay. (=1CLK) 3. tCDL: Last data in to new column address delay. (=1CLK) Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 17/45 ESMT M12L128168A 4. CAS Interrupt (II): Read Interrupted by Write & DQM ( a) CL =2 , B L= 4 CLK i)CMD RD WR DQM DQ ii)CMD D0 RD D1 D2 D3 D1 D2 D3 D1 D2 D3 D1 D2 WR DQM Hi-Z DQ iii)CMD D0 WR RD DQM Hi-Z DQ iv)CMD D0 WR RD DQM DQ Q0 HHi -i -ZZ D0 D3 *Note1 Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 18/45 ESMT M12L128168A (b) CL =3 ,B L= 4 CLK i)CMD RD WR DQM DQ D0 ii)CMD RD D1 D2 D3 D1 D2 D3 D1 D2 D3 D1 D2 D3 D1 D2 WR DQM DQ D0 iii)CMD RD WR DQM D0 DQ iv)CMD WR RD DQM Hi-Z DQ v)CM D D0 RD WR DQM DQ Q0 Hi-Z D0 D3 *Note1 *Note: 1. To prevent bus contention, there should be at least one gap between data in and data out. 5. Write Interrupted by Precharge & DQM CLK CMD WR PRE *Note2 DQM DQ D0 D1 D3 tRDL(min) *Note: *Note3 Masked by DQM 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out. 2. To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 19/45 ESMT M12L128168A 6. Precharge 1) Nor mal W rit e (B L=4) 2) Norm al Read (B L= 4) CLK CLK CMD WR DQ D0 PRE CMD RD PRE CL=2 Q2 Q3 *Note2 D1 D2 DQ( CL2) D3 tRDL Q0 Q1 PRE CL= 3 CMD *Note1 *Note2 DQ ( CL 3 ) Q0 Q1 Q2 Q3 . 7. Auto Precharge 1)Normal W rit e (BL=4) 2)Normal Read (BL=4) CLK CMD DQ CLK CMD WR D0 D1 D2 D3 DQ( CL 2) tRDL RD D0 D1 D2 D3 D0 D1 D2 (min ) DQ(CL3) D3 *Note3 Auto Pr ech arge st art s *Note3 Auto Pr ech arge st art s *Note: 1. tRDL: Last data in to row precharge delay. 2. Number of valid output data after row precharge: 1, 2 for CAS Latency = 2, 3 respectively. 3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 20/45 ESMT M12L128168A 8. Burst Stop & Interrupted by Precharge 1)W rite Bu rst St op (BL=8) 1)W rite interrupted by precharge ( BL=4) CLK CMD CLK CMD STOP WR DQM DQ tRDL PRE *Note4 DQM D0 D1 D2 D3 D5 D4 tBDL DQ D0 D1 Mask Mask *Note1 2)Read Burst Stop (BL=4) 2)Read interrupted by precharge (BL=4) CLK CMD * Note3 WR C LK RD CMD STOP RD PRE *Note5 *Note2 DQ(CL2) Q0 DQ (CL2) Q1 Q0 Q1 Q2 Q3 Q0 Q1 Q2 *Note2 DQ(CL3) Q0 Q1 DQ(CL3) Q3 9. MRS 1) Mo d e Re g is te r S e t CLK *Note4 CMD PRE tRP *Note: ACT MRS 2CLK 1. tBDL: 1 CLK; Last data in to burst stop delay. Read or write burst stop command is valid at every burst length. 2. Number of valid output data after burst stop: 1, 2 for CAS latency = 2, 3 respectiviely. 3. Write burst is terminated. tBDL determinates the last data write. 4. DQM asserted to prevent corruption of locations D2 and D3. 5. Precharge can be issued here or earlier (satisfying tRAS min delay) with DQM. 6. PRE: All banks precharge, if necessary. MRS can be issued only at all banks precharge state. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 21/45 ESMT M12L128168A 10. Clock Suspend Exit & Power Down Exit 1) Cl o ck S u sp en d (= Ac t ive P ow er Do wn ) Exi t CLK CLK CKE Inter nal CLK 2)P ower Down (= Pr ec ha rg e Power Down ) tSS CKE tSS Internal CLK *Note1 CMD *Note2 CMD RD NOP AC T 11. Auto Refresh & Self Refresh 1)Auto Refresh & Self Refresh *Note3 CLK *Note4 CMD *Note5 PRE AR CMD CKE tRP 2)Self Refresh tRFC *Note6 CLK *Note4 CMD SR PRE CMD CKE tRP *Note: tRFC 1. Active power down : one or more banks active state. 2. Precharge power down: all banks precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after auto refresh command. During tRFC from auto refresh command, any other command can not be accepted. 4. Before executing auto/self refresh command, all banks must be idle state. 5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh entry, refresh interval and refresh operation are performed internally. After self refresh entry, self refresh mode is kept while CKE is low. During self refresh entry, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state. For the time interval of tRFC from self refresh exit command, any other command can not be accepted. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 22/45 ESMT M12L128168A 12. About Burst Type Control Sequential Counting At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL = 4,8) BL = 1, 2, 4, 8 and full page. Interleave Counting At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL = 4,8) BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting Basic MODE Random Random Column Access MODE tCCD = 1 CLK Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM. 13. About Burst Length Control Basic MODE 1 At MRS A210 = "000" At auto precharge. tRAS should not be violated. 2 At MRS A210 = "001" At auto precharge. tRAS should not be violated. 4 At MRS A210 = "010" 8 At MRS A210 = "011" Full Page Special MODE BRSW Random MODE Burst Stop Interrupt MODE RAS Interrupt (Interrupted by Precharge) CAS Interrupt At MRS A210 = "111" At the end of the burst length, burst is warp-around. At MRS A9 = "1" Read burst = 1,2,4,8, full page write burst =1 At auto precharge of write, tRAS should not be violated. tBDL = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively. Using burst stop command, any burst length control is possible. Before the end of burst. Row precharge command of the same bank stops read /write burst with auto precharge. tRDL = 1 with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively. During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 23/45 ESMT M12L128168A FUNCTION TRUTH TABLE (TABLE 1) Current State IDLE Row Active Read Write Read with Auto Precharge Write with Auto Precharge CS RAS CAS WE BA ADDR H L L L L L L L H L L L L L L L H L L L L L L L H L L L L L L L H L L L L L H L L L L L X H H H L L L L X H H H H L L L X H H H H L L L X H H H H L L L X H H H L L X H H H L L X H H L H H L L X H H L L H H L X H H L L H H L X H H L L H H L X H H L H L X H H L H L X H L X H L H L X H L H L H L X X H L H L H L X X H L H L H L X X H L X X X X H L X X X X X X BA BA BA X OP code X X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA X X X X BA BA X X X X CA, A10/AP RA A10/AP X OP code X X X CA, A10/AP CA, A10/AP RA A10/AP X X X X CA, A10/AP CA, A10/AP RA A10/AP X X X X CA, A10/AP CA, A10/AP RA A10/AP X X X X CA, A10/AP RA, RA10 X X X X CA, A10/AP RA, RA10 X Elite Semiconductor Memory Technology Inc. ACTION NOP NOP ILLEGAL ILLEGAL Row (&Bank) Active ; Latch RA NOP Auto Refresh or Self Refresh Mode Register Access NOP NOP ILLEGAL Begin Read ; latch CA ; determine AP Begin Write ; latch CA ; determine AP ILLEGAL Precharge ILLEGAL NOP (Continue Burst to End AE Row Active) NOP (Continue Burst to End AE Row Active) Term burst AE Row active Term burst, New Read, Determine AP Term burst, New Write, Determine AP ILLEGAL Term burst, Precharge timing for Reads ILLEGAL NOP (Continue Burst to End AE Row Active) NOP (Continue Burst to End AE Row Active) Term burst AE Row active Term burst, New Read, Determine AP Term burst, New Write, Determine AP ILLEGAL Term burst, Precharge timing for Writes ILLEGAL NOP (Continue Burst to End AE Row Active) NOP (Continue Burst to End AE Row Active) ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to End AE Row Active) NOP (Continue Burst to End AE Row Active) ILLEGAL ILLEGAL ILLEGAL ILLEGAL Note 2 2 4 5 5 2 2 3 2 3 3 2 3 2 2 Publication Date: Oct. 2009 Revision: 2.4 24/45 ESMT Current State Read with Auto Precharge Row Activating Refreshing Mode Register Accessing Abbreviations: *Note: M12L128168A CS RAS CAS WE BA ADDR ACTION H L L L L L L H L L L L L L H L L L L H L L L L X H H H L L L X H H H L L L X H H L L X H H H L X H H L H H L X H H L H H L X H L H L X H H L X X H L X H L X X H L X H L X X X X X X X H L X X X X X BA BA BA X X X X BA BA BA X X X X X X X X X X X X X X CA RA A10/AP X X X X CA RA A10/AP X X X X X X X X X X X NOP AE Idle after tRP NOP AE Idle after tRP ILLEGAL ILLEGAL ILLEGAL NOP AE Idle after tRP ILLEGAL NOP AE Row Active after tRCD NOP AE Row Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP AE Idle after tRFC NOP AE Idle after tRFC ILLEGAL ILLEGAL ILLEGAL NOP AE Idle after 2clocks NOP AE Idle after 2clocks ILLEGAL ILLEGAL ILLEGAL RA = Row Address NOP = No Operation Command BA = Bank Address CA = Column Address Note 2 2 2 4 2 2 2 2 AP = Auto Precharge 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle. 2. Illegal to bank in specified state; Function may be legal in the bank indicated by BA, depending on the state of the bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP). 5. Illegal if any bank is not idle. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 25/45 ESMT M12L128168A FUNCTION TRUTH TABLE (TABLE2) Current State Self Refresh All Banks Precharge Power Down All Banks Idle Any State other than Listed above CKE ( n-1 ) H L L L L L L H L L L L L L H H H H H H H H H L H H L L CKE n X H H H H H L X H H H H H L H L L L L L L L L L H L H L CS RAS CAS X H L L L L X X H L L L L X X H L L L L L L L X X X X X X X H H H L X X X H H H L X X X H H H L L L L X X X X X X X H H L X X X X H H L X X X X H H L H H L L X X X X X WE ADDR X X H L X X X X X H L X X X X X H L X H H H L X X X X X X X X X X X X X X X X X X X X X X X X RA X X OP Code X X X X X ACTION INVALID Exit Self Refresh AE Idle after tRFC (ABI) Exit Self Refresh AE Idle after tRFC (ABI) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Self Refresh AE ABI Exit Self Refresh AE ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Low Power Mode) Refer to Table1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL Row (& Bank) Active NOP Enter Self Refresh Mode Register Access NOP Refer to Operations in Table 1 Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend Note 6 6 7 7 8 8 8 9 9 Abbreviations: ABI = All Banks Idle, RA = Row Address *Note: 6.CKE low to high transition is asynchronous. 7.CKE low to high transition is asynchronous if restart internal clock. A minimum setup time 1CLK + tSS must be satisfy before any command other than exit. 8.Power down and self refresh can be entered only from the all banks idle state. 9.Must be a legal command. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 26/45 ESMT M12L128168A Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3, Burst Length = 1 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK tCL tCC HIGH tRAS CKE tRC tSH *Note1 CS tRP tRCD tSS tSH RAS tSS tCCD tSH CAS tSS tSH ADDR Ra Ca Cb Cc Rb tSS *Note2,3 *Note2,3 *Note4 BA0, BA1 BS BS BS BS BS BS A10/AP Ra *Note 2 *Note 2 *Note 2 *Note4 Rb *Note2 *Note2,3 tSAC tSH DQ Qa tSLZ *Note2 Db Qc tSS tOH tSH WE tSS tSS tSH DQM Row Active Read W rite Read Row Active Pre ch arge :Don't Care Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 27/45 ESMT Note: M12L128168A 1. All input expect CKE & DQM can be don't care when CS is high at the CLK high going edge. 2. Bank active @ read/write are controlled by BA0~BA1. BA0 BA1 Active & Read/Write 0 0 Bank A 0 1 Bank B 1 0 Bank C 1 1 Bank D 3. Enable and disable auto precharge function are controlled by A10/AP in read/write command A10/AP 0 1 BA0 BA1 Operating 0 0 Disable auto precharge, leave A bank active at end of burst. 0 1 Disable auto precharge, leave B bank active at end of burst. 1 0 Disable auto precharge, leave C bank active at end of burst. 1 1 Disable auto precharge, leave D bank active at end of burst. 0 0 Enable auto precharge, precharge bank A at end of burst. 0 1 Enable auto precharge, precharge bank B at end of burst. 1 0 Enable auto precharge, precharge bank C at end of burst. 1 1 Enable auto precharge, precharge bank D at end of burst. 4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted. A10/AP BA0 BA1 Precharge 0 0 0 Bank A 0 0 1 Bank B 0 1 0 Bank C 0 1 1 Bank D 1 X X All Banks Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 28/45 ESMT M12L128168A Power Up Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 29/45 ESMT M12L128168A Read & Write Cycle at Same Bank @ Burst Length = 4 *Note: 1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ) after the clock. 3. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst) Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 30/45 ESMT M12L128168A Page Read & Write Cycle at Same Bank @ Burst Length = 4 Note: 1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 31/45 ESMT M12L128168A Page Read Cycle at Different Bank @ Burst Length = 4 Note: 1. CS can be don't cared when RAS , CAS and WE are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 32/45 ESMT M12L128168A Page Write Cycle at Different Bank @ Burst Length = 4 *Note: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 33/45 ESMT M12L128168A Read & Write Cycle at Different Bank @ Burst Length = 4 *Note: 1. tCDL should be met to complete write. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 34/45 ESMT M12L128168A Read & Write cycle with Auto Precharge @ Burst Length = 4 Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 35/45 ESMT M12L128168A Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4 *Note: 1. DQM is needed to prevent bus contention Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 36/45 ESMT M12L128168A Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page *Note: 1. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of "Full page write burst stop cycles". 2. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 37/45 ESMT M12L128168A Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page *Note: 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 2. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 38/45 ESMT M12L128168A Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4 *Note: 1. All banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + tSS prior to Row active command. 3. Can not violate minimum refresh specification. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 39/45 ESMT M12L128168A Self Refresh Entry & Exit Cycle *Note: TO ENTER SELF REFRESH MODE 1. CS , RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low". cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tRFC is required after CKE going high to complete self refresh exit. 7. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 40/45 ESMT M12L128168A Mode Register Set Cycle 0 1 2 Auto Refresh Cycle 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 CLOCK HIG H HIGH CKE CS tRFC *Note2 RAS *Note1 CAS *Note3 ADDR Key Ra HI-Z HI-Z DQ WE DQM MRS New Command New Command Auto Refresh :Don't Care All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note: 1. CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 41/45 ESMT M12L128168A PACKING DIMENSIONS 54-LEAD TSOP(II) SDRAM (400mil) SEE DETAIL "A" Symbol A A1 A2 b b1 c c1 D ZD E E1 L L1 e R1 R2 Dimension in mm Min Norm Max 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.30 0.35 0.40 0.12 0.21 0.10 0.127 0.16 22.22 BSC 0.71 REF 11.76 BSC 10.16 BSC 0.40 0.50 0.60 0.80 REF 0.80 BSC 0.12 0.12 0.25 1 2 0 0 10 3 10 y Elite Semiconductor Memory Technology Inc. Dimension in inch Min Norm Max 0.047 0.002 0.004 0.006 0.037 0.039 0.041 0.012 0.018 0.012 0.014 0.016 0.005 0.008 0.004 0.005 0.006 0.875 BSC 0.028 REF 0.463 BSC 0.400 BSC 0.016 0.020 0.024 0.031 REF 0.031 BSC 0.005 0.005 0.010 8 0 0 15 20 10 15 15 20 10 15 0.100 8 20 20 0.004 Publication Date: Oct. 2009 Revision: 2.4 42/45 ESMT M12L128168A PACKING DIMENSIONS 54-BALL SDRAM ( 8x8 mm ) Symbol Dimension in mm Min Norm Max A 1.00 A1 0.20 0.25 0.30 A2 0.61 0.66 0.71 b 0.30 0.35 0.40 D 7.90 8.00 8.10 E 7.90 8.00 8.10 D1 6.40 E1 6.40 e 0.80 Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Dimension in inch Min Norm Max 0.039 0.008 0.010 0.012 0.024 0.026 0.028 0.012 0.014 0.016 0.311 0.315 0.319 0.311 0.315 0.319 0.252 0.252 0.031 Publication Date: Oct. 2009 Revision: 2.4 43/45 ESMT M12L128168A Revision History Revision Date 1.0 2002.10.31 Original 1.1 2003.03.25 Modify die from 0.165mm to 0.15mm 1.2 2003.09.02 Delete speed distribution -5 to prevent confusion of customers 1.3 2004.08.23 Correct typing error 1.4 2005.03.17 1.Add Pb-free to ordering information 2.Modify P8 from bank precharge state to ldle state 1.5 2005.04.22 Modify refresh spec 1.6 2005.06.07 1.Modify tREF spec 2.Modify tRFC spec 1.7 2005.09.02 Add revision history 1.8 2006.09.08 Add -5T to ordering information 1.9 2006.10.11 1.Modify AC parameter (tCH, tCL, tRP, tRAS, tRC) 2.Modify tSAC, tOH timing 2.0 2006.10.24 Modify tRFC , tSHZ timing 2.1 2007.07.18 2.2 2009.02.23 2.3 2009.03.05 2.4 2009.10.02 Elite Semiconductor Memory Technology Inc. Description Add BGA package 1.Rename A13,A12 to BA0,BA1 2.Modify the specification of tOH for -6 and -7 3.Modify the test condition of lIL and ICC3N 4.Modify the description about self refresh operation Chang back to the specification of tOH of the previous version 1. Add the description about A9 bit of MRS 2. Delete the unnecessary description about self refresh Publication Date: Oct. 2009 Revision: 2.4 44/45 ESMT M12L128168A Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2009 Revision: 2.4 45/45